U.S. patent application number 14/323732 was filed with the patent office on 2014-10-30 for solid-state imaging device.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. The applicant listed for this patent is KABUSHIKI KAISHA TOSHIBA. Invention is credited to Yoshitaka Egawa.
Application Number | 20140320713 14/323732 |
Document ID | / |
Family ID | 45095956 |
Filed Date | 2014-10-30 |
United States Patent
Application |
20140320713 |
Kind Code |
A1 |
Egawa; Yoshitaka |
October 30, 2014 |
SOLID-STATE IMAGING DEVICE
Abstract
According to one embodiment, a solid-state imaging device
includes a pixel array unit where pixels are disposed in a matrix
and a column amplifying circuit that is disposed at an end of the
pixel array unit and amplifies a unit signal of a unit pixel read
from each pixel with at least first and second amplification
factors, and outputs a plurality of amplified signals.
Inventors: |
Egawa; Yoshitaka; (Kanagawa,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
KABUSHIKI KAISHA TOSHIBA |
Minato-ku |
|
JP |
|
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Minato-ku
JP
|
Family ID: |
45095956 |
Appl. No.: |
14/323732 |
Filed: |
July 3, 2014 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
13107255 |
May 13, 2011 |
|
|
|
14323732 |
|
|
|
|
Current U.S.
Class: |
348/301 |
Current CPC
Class: |
H04N 5/3742 20130101;
H04N 5/355 20130101; H04N 5/378 20130101; H04N 5/3575 20130101 |
Class at
Publication: |
348/301 |
International
Class: |
H04N 5/378 20060101
H04N005/378 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 10, 2010 |
JP |
2010-133156 |
Claims
1. A solid-state imaging device, comprising: a pixel array unit in
which pixels are disposed in a matrix; and first and second a
column amplifying circuits that is are disposed at an end of the
pixel array unit and amplifies amplify a unit signal of a unit
pixel read from each pixel with at least first and second
amplification factors, wherein a plurality of amplified signals are
simultaneously output in parallel.
2. The solid-state imaging device of claim 1, further comprising: a
synthesizing unit that synthesizes the plurality of output
signals.
3. The solid-state imaging device of claim 2, wherein the
synthesizing unit includes an amplifying circuit that amplifies the
output signal having the small amplification factor.
4. A solid-state imaging device, comprising: a pixel array unit
where pixels are disposed in a matrix; a column amplifying circuit
that is disposed at an end of the pixel array unit and amplifies a
signal read from each pixel; an amplification factor switching
circuit that switches an amplification factor of at least a unit
signal of unit pixel to first and second amplification factors; a
comparator circuit that executes A/D conversion on the signals
amplified by the column amplifying circuit; a signal level
determining circuit that determines the magnitude of levels of a
plurality of amplified signals; an amplifying factor storing
circuit that determines the first and second amplification factors
which are valid for the comparator circuit and holds a
determination result; a comparator circuit that executes A/D
conversion on the signals amplified by the column amplifying
circuit; and an operation circuit that adds or subtracts a digital
signal of a comparator output.
5. The solid-state imaging device of claim 4, wherein the operation
circuit includes anyone of a counter circuit that executes
subtraction processing based on n up/down counting operation, a
counter circuit that inverts bits of digital data by a
predetermined control signal and executes the subtraction
processing, and an operation circuit that adds or subtracts a
plurality of signals read from a plurality of line memories storing
two kinds of signals.
6. The solid-state imaging device of claim 4, further comprising: a
memory that stores an output value of the operation circuit.
7. The solid-state imaging device of claim 4, further comprising: a
plurality of storing circuits that store a plurality of signals of
reference levels having different amplification factors.
8. The solid-state imaging device of claim 7, further comprising: a
signal synthesizing unit that switches the amplification factors of
the output signals according to the according to data stored in the
amplification factor storing circuit and outputs the output
signals.
9. The solid-state imaging device of claim 8, wherein the signal
synthesizing unit includes a synthesizing circuit that switches the
amplification factors of the signals such that the signal having
the small amplification factor is amplified with the amplification
factor larger than the amplification factor of the signal having
the large amplification factor.
10. The solid-state imaging device of claim 9, wherein the
amplification factor switching circuit includes a control circuit
that switches the amplification factors according to the
determination result.
11. The solid-state imaging device of claim 8, wherein the signal
synthesizing unit includes a switching circuit that subtracts black
levels of the output signals, according to the determination
result.
12. A solid-state imaging device, comprising: a pixel array unit
where pixels are disposed in a matrix; a column amplifying circuit
that amplifies a signal read from each pixel with first and second
amplification factors; and a sample and hold signal converting
circuit that samples a first reference level and a first signal
level from the signal amplified with the first amplification
factor, samples a second reference level and a second signal level
from the signal amplified with the second amplification factor, and
detects a plurality of signal components of each pixel by
correlated double sampling, amplification factors of the signal
components being different from each other, wherein both the first
signal level and the second signal level are sampled after both the
first reference level and the second reference level are sampled in
the correlated double sampling.
13. The solid-state imaging device of claim 12, wherein the column
amplifying circuit includes a switched capacitor type amplifying
circuit that adjusts a capacitance value of a capacitor and adjusts
the amplification factor.
14. The solid-state imaging device of claim 12, wherein the column
amplifying circuit includes a first amplification transistor that
configures a differential pair with the second amplification
transistor that amplifies photoelectrically converted signals in
the pixels.
15. The solid-state imaging device of claim 12, further comprising:
a linearization amplifying circuit that amplifies the signals such
that a signal component of each pixel detected from the signal
level of the different amplification factor by the correlated
double sampling becomes 1 with respect to the amount of light; and
a linearization synthesizing circuit that synthesizes the signals
amplified by the linearization amplifying circuit and makes the
signal component of each pixel become linear with respect to the
amount of light.
16. The solid-state imaging device of claim 15, wherein the
linearization amplifying circuit includes a black level adjusting
unit that adjusts a black level with respect to the signal
component of each pixel.
17. The solid-state imaging device of claim 15, wherein the sample
and hold signal converting circuit includes a gain selecting unit
that switches the signals synthesized by the linearization
synthesizing circuit, on the basis of the switching result of the
first amplification factor and the second amplification factor.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This divisional application claims the benefit of priority
under 35 U.S.C. .sctn.120 from prior U.S. patent application Ser.
No. 13/107,255, filed on Mar. 13, 2011. This application is also
based upon and claims the benefit of priority under 35 U.S.C.
.sctn.119 from prior Japanese Patent Application No. 2010-133156,
filed on Jun. 10, 2010; the entire contents of each of which are
incorporated herein by reference.
FIELD
[0002] Embodiments described herein relate generally to a
solid-state imaging device.
BACKGROUND
[0003] With regard to a solid state imaging device, a method that
provides a signal processing circuit to execute A/D conversion or
correlated double sampling (CDS) for each column and amplifies a
signal read from each pixel on a column basis is known.
[0004] For example, there is a method that provides a function of
detecting the magnitude of each pixel signal independently and
setting gain independently of the magnitude of each pixel signal in
a column region portion of an image sensor.
[0005] In this method, an amplification factor is switched with
respect to a signal component detected by the CDS. For this reason,
at the time of the CDS, a reference level is sampled from a signal
before switching the amplification factor and a signal level is
sampled from a signal after switching the amplification factor.
Therefore, an effect of suppressing noise based on the CDS is
insufficient.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a block diagram of a schematic configuration of a
solid-state imaging device according to a first embodiment;
[0007] FIG. 2 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a second
embodiment;
[0008] FIG. 3 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 2;
[0009] FIG. 4 is a diagram illustrating a dynamic range of the
solid-state imaging device of FIG. 2 in comparison with a dynamic
range according to the related art;
[0010] FIG. 5 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a third
embodiment;
[0011] FIG. 6 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 5;
[0012] FIG. 7 is a block diagram of a schematic configuration of a
solid-state imaging device according to a fourth embodiment;
[0013] FIG. 8 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a fifth
embodiment;
[0014] FIG. 9 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 8;
[0015] FIG. 10 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a sixth
embodiment;
[0016] FIG. 11 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 10;
[0017] FIG. 12 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a seventh
embodiment;
[0018] FIG. 13 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 12;
[0019] FIG. 14 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to an eighth
embodiment;
[0020] FIG. 15 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 14;
[0021] FIG. 16 is a block diagram of a schematic configuration of a
solid-state imaging device according to a ninth embodiment;
[0022] FIG. 17 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a tenth
embodiment;
[0023] FIG. 18 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 17;
[0024] FIG. 19 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to an eleventh
embodiment;
[0025] FIG. 20 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 19;
[0026] FIG. 21 is a block diagram of a schematic configuration of a
solid-state imaging device according to a twelfth embodiment;
[0027] FIG. 22 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a
thirteenth embodiment;
[0028] FIG. 23 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 22;
[0029] FIG. 24 is a schematic circuit diagram of the configuration
of one column of a solid-state imaging device according to a
fourteenth embodiment;
[0030] FIG. 25 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 24;
[0031] FIG. 26 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a fifteenth
embodiment;
[0032] FIG. 27 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 26;
[0033] FIG. 28 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a sixteenth
embodiment;
[0034] FIG. 29 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 28;
[0035] FIG. 30 is a block diagram of a schematic configuration of a
solid-state imaging device according to a seventeenth
embodiment;
[0036] FIG. 31 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to an
eighteenth embodiment; and
[0037] FIG. 32 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 31.
DETAILED DESCRIPTION
[0038] In general, according to one embodiment, a solid-state
imaging device includes a pixel array unit and a column amplifying
circuit. In the pixel array unit, pixels are disposed in a matrix.
The column amplifying circuit is disposed at an end of the pixel
array unit, amplifies a unit signal of a unit pixel read from each
pixel with at least first and second amplification factors, and
outputs the plural amplified signals.
[0039] Exemplary embodiments of the solid-state imaging device will
be explained below in detail with reference to the accompanying
drawings. The present invention is not limited to the following
embodiments.
First Embodiment
[0040] FIG. 1 is a block diagram of a schematic configuration of a
solid-state imaging device according to a first embodiment.
[0041] In FIG. 1, the solid-state imaging device includes a pixel
array unit 1 where pixels PC to accumulate photoelectrically
converted charges are disposed in a matrix in row and column
directions, a row scanning circuit 2 that scans each pixel PC to be
read in a vertical direction, a column amplifying circuit 3-1 that
amplifies a signal read from each pixel PC with an amplification
factor A1 for each column, a column amplifying circuit 3-2 that
amplifies a signal read from each pixel PC with an amplification
factor A2 for each column, a sample and hold signal converting
circuit 4-1 that detects a signal component of each pixel PC
amplified with the amplification factor A1 by CDS, a sample and
hold signal converting circuit 4-2 that detects a signal component
of each pixel PC amplified with the amplification factor A2 by the
CDS, a column scanning circuit 7-1 that reads a signal stored in a
line memory of the sample and hold signal converting circuit 4-1 in
a horizontal direction, a column scanning circuit 7-2 that reads a
signal stored in a line memory of the sample and hold signal
converting circuit 4-2 in a horizontal direction, a timing control
circuit 8 that controls the timing for read or accumulation of each
pixel PC, a D/A converter 9-1 that outputs a reference voltage
VREF1 to the sample and hold signal converting circuit 4-1, and a
D/A converter 9-2 that outputs a reference voltage VREF2 to the
sample and hold signal converting circuit 4-2. To the timing
control circuit 8, a master clock MCK is input.
[0042] In this case, the sample and hold signal converting circuit
4-1 can sample a first reference level and a first signal level
from the signal of each pixel PC amplified with the amplification
factor A1 and detect a signal component of each pixel PC by the
CDS. The sample and hold signal converting circuit 4-2 can sample a
second reference level and a second signal level from the signal of
each pixel PC amplified with the amplification factor A2 and detect
a signal component of each pixel PC by the CDS.
[0043] The D/A converters 9-1 and 9-2 can output triangular waves
as the reference voltages VREF1 and VREF2, when executing an
up-counting operation and a down-counting operation by the column
ADC circuits 5-1 and 5-2. For example, when a subject is bright,
the amplification factor A1 can be set to 1.times. and the
amplification A2 can be set to 4.times.. When the subject is dark,
the amplification factor A1 can be set to 1.times. and the
amplification factor A2 can be set to 4.times.. However, the
amplification factor A2 is not limited to 4.times. and may be set
to 2.times., 8.times. or 16.times..
[0044] In the pixel array unit 1, horizontal control lines Hlin
that perform read control of the pixels PC are provided in a row
direction and vertical signal lines Vlin that transmit signals read
from the pixels PC are provided in a column direction.
[0045] In the sample and hold signal converting circuit 4-1, a
column ADC circuit 5-1 that executes an up-counting operation and a
down-counting operation on the basis of the comparison result of
the read signal from the pixel PC amplified with the amplification
factor A1 and the reference voltage VREF1 and calculates the
difference between a reference level and a signal level of the CDS
and a line memory 6-1 that stores a count value of the column ADC
circuit 5-1 by the amount of horizontal pixels are provided. In the
sample and hold signal converting circuit 4-2, a column ADC circuit
5-2 that executes an up-counting operation and a down-counting
operation on the basis of the comparison result of the read signal
from the pixel PC amplified with the amplification factor A2 and
the reference voltage VREF1 and calculates the difference between
the reference level and the signal level of the CDS and a line
memory 6-2 that stores a count value of the column ADC circuit 5-2
by the amount of horizontal pixels are provided.
[0046] In the solid-state imaging device, a multiplier 10 that
multiplies an output signal Vout6 from the sample and hold signal
converting circuit 4-1 with the amplification factor A2, a
comparator 11 that compares an output signal Vout7 from the sample
and hold signal converting circuit 4-2 and a reference level VSL,
and a switch 12 that switches an output signal Vout8 to the L side
or the H side on the basis of the comparison result of the
comparator 11 are provided. When the amplification factor of the
column amplifying circuit 3-1 is not 1.times., the amplification
factor A2 of the multiplier 10 can be changed such that a
photoelectric conversion characteristic of the output signal Vout8
becomes linear with respect to an optical signal amount.
[0047] If the pixels PC are scanned in a vertical direction by the
row scanning circuit 2, the pixels PC of a row direction are
selected and the signals that are output from the pixels PC are
transmitted to the column amplifying circuits 3-1 and 3-2 through
the vertical signal lines Vlin. After the signals read from the
pixels PC are amplified with the amplification factor A1 by the
column amplifying circuit 3-1, the signals are transmitted to the
sample and hold signal converting circuit 4-1. After the signals
read from the pixels PC are amplified with the amplification factor
A2 by the column amplifying circuit 3-2, the signals are
transmitted to the sample and hold signal converting circuit
4-2.
[0048] In the sample and hold signal converting circuit 4-1, a
first reference level and a first signal level are sampled from the
signal of each pixel PC amplified with the amplification factor A1,
the difference between the first signal level and the first
reference level is taken, and a signal component of each pixel PC
is detected by the CDS and is output as the output signal
Vout6.
[0049] In this case, in the column ADC circuit 5-1, after a
down-counting operation is executed until the first reference level
sampled from the signal of each pixel PC amplified with the
amplification factor A1 is matched with the level of the reference
voltage VREF1, an up-counting operation is executed until the first
signal level sampled from the signal of each pixel PC amplified
with the amplification factor A1 is matched with the level of the
reference voltage VREF1, and the signal component that is detected
by the CDS is converted into a digital value and is stored in the
line memory 6-1 by the amount of horizontal pixels.
[0050] In the sample and hold signal converting circuit 4-2, a
second reference level and a second signal level are sampled from
the signal of each pixel PC amplified with the amplification factor
A2, the difference between the second signal level and the second
reference level is taken, and a signal component of each pixel PC
is detected by the CDS and is output as the output signal
Vout7.
[0051] In this case, in the column ADC circuit 5-2, after a
down-counting operation is executed until the second reference
level sampled from the signal of each pixel PC amplified with the
amplification factor A2 is matched with the level of the reference
voltage VREF2, an up-counting operation is executed until the
second signal level sampled from the signal of each pixel PC
amplified with the amplification factor A2 is matched with the
level of the reference voltage VREF2, and the signal component that
is detected by the CDS is converted into a digital value and is
stored in the line memory 6-2 by the amount of horizontal
pixels.
[0052] In the comparator 11, when the output signal Vout7 from the
sample and hold signal converting circuit 4-2 is compared with the
reference level VSL, if the level of the output signal Vout7 is
lower than the reference level VSL, the switch 12 is switched to
the L side and the output signal Vout7 is output as the output
signal Vout8.
[0053] Meanwhile, when the level of the output signal Vout7 is
equal to or higher than the reference level VSL, the switch 12 is
switched to the H side. In the multiplier 10, the output signal
Vout6 from the sample and hold signal converting circuit 4-1 is
multiplied with the amplification factor A2, a signal component of
the output signal Vout6 amplified with the amplification factor A1
becomes linear with respect to the amount of light, and the output
signal Vout6 multiplied with the amplification factor A2 is output
as the output signal Vout8. With respect to the reference level
VSL, at the time of the A/D conversion of 10 bits, 1023 levels that
are a maximum value can be set. That is, at the time of the 1023
levels where the output signal Vout2 is saturated, the output
signal Vout6 that is multiplied with the amplification factor A2
can be selected.
[0054] For example, when the subject is bright, both the
amplification factors A1 and A2 are set as 1.times. and the output
signal Vout7 that is not saturated is output as the output signal
Vout8. Since the saturated signal have a digital value of 1023, the
switch 12 is switched to the H side and a signal that is obtained
by amplifying the output signal Vout6 with 1.times. equal to the
amplification factor A2 is output as the output signal Vout8.
However, since the amplification factor A1 is 1.times., a signal
with a digital value of 1023 is output. When the amplification
factor A2 is 1.times., the switch 12 can be fixed to the L
side.
[0055] Meanwhile, when the subject is dark, the amplification
factor A1 is set as 1.times. and the amplification factor A2 is set
as 4.times. and the output signal Vout7 that is not saturated is
output as the output signal Vout8. When the signal Vout7 is
saturated and has a digital value of 1023, the switch 12 is
switched to the H side and a signal that is obtained by amplifying
the output signal Vout6 with the amplification factor 4.times. is
output as the output signal Vout8. That is, a digital value of 4095
that is approximately the quadruple of 1023 to be the maximum value
of the ADC is obtained from the output signal Vout8. A signal whose
dynamic range is quadrupled is obtained.
[0056] In this case, when the signal component of each pixel PC
amplified with the amplification factor A1 is detected by the CDS,
an effect of canceling noise based on the CDS in the amplification
factor A1 can be improved by sampling the first reference level
from the signal of each pixel PC amplified with the amplification
factor A1. When the signal component of each pixel PC amplified
with the amplification factor A2 is detected by the CDS, an effect
of canceling noise based on the CDS in the amplification factor A2
can be improved by sampling the second reference level from the
signal of each pixel PC amplified with the amplification factor A2.
For this reason, the amplification factor of the signal level can
be switched while an effect of suppressing the noise based on the
CDS is improved. Therefore, a dynamic range can be enlarged while
an S/N ratio is increased.
Second Embodiment
[0057] FIG. 2 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a second
embodiment.
[0058] In FIG. 2, the solid-state imaging device includes a pixel
array unit 1, column amplifying circuits 3-1a and 3-2a, and sample
and hold signal converting circuits 4-1a and 4-2a.
[0059] In the pixel array unit 1, pixels PCn and PCn+1 are
provided. In each of the pixels PCn and PCn+1, a photodiode PD, a
row selection transistor Ta, an amplification transistor Tb, a
reset transistor Tc, and a read transistor Td are provided. At a
connection point of the amplification transistor Tb, the reset
transistor Tc, and the read transistor Td, floating diffusion FD
that functions as a detection node is formed.
[0060] In the pixels PCn and PCn+1, sources of the read transistors
Td are connected to the photodiodes PD and read signals READn and
READn+1 are input to gates of the read transistors Td. Sources of
the reset transistors Tc are connected to drains of the read
transistors Td and reset signals RESETn and RESETn+1 are input to
gates of the reset transistors Tc, and drains of the reset
transistors Tc are connected to a power supply VDD. Row selection
signals ADRESn and ADRSn+1 are input to gates of the row selection
transistors Ta and drains of the row selection transistors Ta are
connected to the power supply VDD. Sources of the amplification
transistors Tb are connected to the vertical signal line Vlin,
gates of the amplification transistors Tb are connected to drains
of the read transistors Td, and drains of the amplification
transistors Tb are connected to sources of the row selection
transistors Ta.
[0061] The horizontal control line Hlin of FIG. 1 can transmit the
read signals READn and READn+1, the reset signals RESETn and
RESETn+1, and the row selection signals ADRESn and ADRESn+1 to the
pixels PC for each row.
[0062] A drain of a constant current transistor TL is connected to
the vertical signal line Vlin and a gate of the constant current
transistor TL is connected to a bias power supply VTL. The constant
current transistor TL and the amplification transistor Tb are
combined and configure a source follower and can execute a constant
current operation.
[0063] In the column amplifying circuit 3-1a, capacitors C11 and
C12, an operational amplifier OP1, and a switch transistor Tsc1 are
provided for each column. The vertical signal line Vlin is
connected to an input terminal of the operational amplifier OP1
through the capacitor C11 and the capacitor C12 is connected
between the input terminal and an output terminal of the
operational amplifier OP1. The switch transistor Tsc1 is connected
in parallel to the capacitor C12.
[0064] In the column amplifying circuit 3-2a, capacitors C21 and
C22, an operational amplifier OP2, and a switch transistor Tsc2 are
provided for each column. The vertical signal line Vlin is
connected to an input terminal of the operational amplifier OP2
through the capacitor C21 and the capacitor C22 is connected
between the input terminal and an output terminal of the
operational amplifier OP2. The switch transistor Tsc2 is connected
in parallel to the capacitor C22.
[0065] As the column amplifying circuits 3-1a and 3-2a, a switched
capacitor type inverting amplifier that can control each of the
amplification factors A1 and A2 with a capacitance ratio can be
used. The amplification factors A1 and A2 can be calculated by
C11/C12 and C21/C22, respectively. For example, in the case of
C11=0.05 pF and C12=0.05 pF, 1.times. is obtained as the
amplification factor A1, and in the case of C21=0.05 pF and C22=0.2
pF, 4.times. is obtained as the amplification factor A2.
[0066] In the sample and hold signal converting circuit 4-1a, a
comparator PA1, a switch transistor Tcp1, an inverter V1, an
up-down counter UD1, and a line memory LM1 are provided for each
column. In the up-down counter UD1, an AND circuit N1 is
provided.
[0067] An output terminal of the operational amplifier OP1 is
connected to an inverting input terminal of the comparator PA1
through a capacitor C13 and the reference voltage VREF1 is input to
a non-inverting input terminal of the comparator PA1. The switch
transistor Tcp1 is connected between the inverting input terminal
and the output terminal of the comparator PA1. The output terminal
of the comparator PA1 is connected to one input terminal of the AND
circuit N1 through the inverter V1 and a reference clock CKC1 is
input to the other input terminal of the AND circuit N1. An output
terminal of the up-down counter UD1 is connected to the line memory
LM1.
[0068] In the sample and hold signal converting circuit 4-2a, a
comparator PA2, a switch transistor Tcp2, an inverter V2, an
up-down counter UD2, and a line memory LM2 are provided for each
column. In the up-down counter UD2, an AND circuit N2 is
provided.
[0069] An output terminal of the operational amplifier OP2 is
connected to an inverting input terminal of the comparator PA2
through a capacitor C23 and the reference voltage VREF2 is input to
a non-inverting input terminal of the comparator PA2. The switch
transistor Tcp2 is connected between the inverting input terminal
and the output terminal of the comparator PA2. The output terminal
of the comparator PA2 is connected to one input terminal of the AND
circuit N2 through the inverter V2 and a reference clock CKC2 is
input to the other input terminal of the AND circuit N2. An output
terminal of the up-down counter UD2 is connected to the line memory
LM2.
[0070] FIG. 3 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 2.
[0071] In FIG. 3, when a level of the row selection signal ADRESn
is a low level, the row selection transistor Ta is turned off and
the source follower operation is not executed. For this reason, a
signal is not output to the vertical signal line Vlin. At this
time, if a level of each of the read signal READn and the reset
signal RESETn become a high level, the read transistor Td is turned
on and charges that are accumulated in the photodiode PD are
discharged to the floating diffusion FD. The charges are discharged
to the power supply VDD through the reset transistor Tc.
[0072] After the charges accumulated in the photodiode PD are
discharged to the power supply VDD, if the level of the read signal
READn becomes a low level, charges of valid signals start to be
accumulated in the photodiode PD.
[0073] Next, if the level of the row selection signal ADRESn
becomes a high level, the row selection transistor Ta of the pixels
PC is turned on, the power supply potential VDD is applied to the
drain of the amplification transistor Tb, and a source follower is
configured by the amplification transistor Tb and the constant
current transistor TL.
[0074] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta being turned on, the reset
transistor Tc is turned on and the extra charges that are generated
in the leak current are reset to the floating diffusion FD. A
voltage according to a reference level of the floating diffusion FD
is applied to the gate of the amplification transistor Tb. In this
case, since the source follower is configured by the amplification
transistor Tb and the constant current transistor TL, the voltage
of the vertical signal line Vlin follows the voltage applied to the
gate of the amplification transistor Tb and is output as the output
voltage Vout1 of the reference level to the vertical signal line
Vlin.
[0075] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if a reset pulse Psc1 is
applied to the gate of the switch transistor Tsc1, the input
voltage of the operational amplifier OP1 is clamped with the output
voltage and an operation point is set. At this time, the voltage
difference with respect to the vertical signal line Vlin is held in
the capacitor C11 and the input voltage of the operational
amplifier OP1 is set to zero.
[0076] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if the reset pulse Psc1 is
applied to the gate of the switch transistor Tcp1, the input
voltage of the inverting input terminal of the comparator RA1 is
clamped with the output voltage and an operation point is set. At
this time, the voltage difference with respect to the output
voltage Vout2 from the operational amplifier OP1 is held in the
capacitor C13 and the input voltage of the operational amplifier
OP1 is set to zero.
[0077] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if a reset pulse Psc2 is
applied to the gate of the switch transistor Tsc2, the input
voltage of the operational amplifier OP2 is clamped with the output
voltage and an operation point is set. At this time, the voltage
difference with respect to the vertical signal line Vlin is held in
the capacitor C21 and the input voltage of the operational
amplifier OP2 is set to zero.
[0078] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if the reset pulse Pcp2 is
applied to the gate of the switch transistor Tcp2, the input
voltage of the inverting input terminal of the comparator PA2 is
clamped with the output voltage and an operation point is set. At
this time, the voltage difference with respect to the output
voltage Vout3 from the operational amplifier OP2 is held in the
capacitor C23 and the input voltage of the comparator PA2 is set to
zero.
[0079] After the switch transistor Tsc1 is turned off, if the input
voltage of the operational amplifier OP1 is changed, the voltage is
fed back from the capacitor C12, such that the input voltage
becomes the zero voltage. As a result, the output voltage Vout2
that is inverted and amplified with the capacitance ratio
C.sub.11/C.sub.12 (=amplification factor A1) is output from the
operational amplifier OP1 and is applied to the inverting input
terminal of the comparator PA1 through the capacitor C13. In this
case, a capacitance value of the capacitor C11 is set as C.sub.11
and a capacitance value of the capacitor C12 is set as
C.sub.12.
[0080] After the switch transistor Tsc2 is turned off, if the input
voltage of the operational amplifier OP2 is changed, the voltage is
fed back from the capacitor C22, such that the input voltage
becomes the zero voltage. As a result, the output voltage Vout3
that is inverted and amplified with the capacitance ratio
C.sub.21/C.sub.22 (=amplification factor A2) is output from the
operational amplifier OP2 and is applied to the inverting input
terminal of the comparator PA2 through the capacitor C23. In this
case, a capacitance value of the capacitor C21 is set as C.sub.21
and a capacitance value of the capacitor C22 is set as
C.sub.22.
[0081] With the output voltage Vout2 of the reference level being
input to the comparator PA1 through the capacitor C13 after the
switch transistor Tcp1 is turned off, a triangular wave is applied
as the reference voltage VREF1 and the output voltage Vout2 of the
reference level and the reference voltage VREF1 are compared with
each other. After the output voltage of the comparator PA1 is
inverted by the inverter V1, the output voltage is input as the
output voltage Vout4 to one input terminal of the AND circuit
N1.
[0082] The reference clock CKC1 is input to the other input
terminal of the AND circuit N1. When the level of the output
voltage Vout2 of the reference level is lower than the level of the
reference voltage VREF1, the level of the output voltage Vout4
becomes a high level. For this reason, the reference clock CKC1
passes through the AND circuit N1 and a reference clock CKCi1 after
the passage is down-counted by the up-down counter UD1. If the
level of the output voltage Vout2 of the reference level is matched
with the level of the reference voltage VREF1, the output voltage
of the comparator PA1 falls and the level of the output voltage
Vout4 becomes a low level. For this reason, the reference clock
CKC1 is intercepted by the AND circuit N1 and the down-counting
operation is stopped by the up-down counter UD1. As a result, the
output voltage Vout2 of the reference level is converted into a
digital value D and is held as the first reference level of the
signal amplified with the amplification factor A1 in the up-down
counter UD1.
[0083] With the output voltage Vout3 of the reference level being
input to the comparator PA2 through the capacitor C23 after the
switch transistor Tcp2 is turned off, a triangular wave is applied
as the reference voltage VREF2 and the output voltage Vout3 of the
reference level and the reference voltage VREF2 are compared with
each other. After the output voltage of the comparator PA2 is
inverted by the inverter V2, the output voltage is input as the
output voltage Vout5 to one input terminal of the AND circuit
N2.
[0084] The reference clock CKC2 is input to the other input
terminal of the AND circuit N2. When the level of the output
voltage Vout3 of the reference level is lower than the level of the
reference voltage VREF2, the level of the output voltage Vout5
becomes a high level. For this reason, the reference clock CKC2
passes through the AND circuit N2 and a reference clock CKCi2 after
the passage is down-counted by the up-down counter UD2. If the
level of the output voltage Vout3 of the reference level is matched
with the level of the reference voltage VREF2, the output voltage
of the comparator PA2 falls and the level of the output voltage
Vout5 becomes a low level. For this reason, the reference clock
CKC2 is intercepted by the AND circuit N1 and the down-counting
operation is stopped by the up-down counter UD2. As a result, the
output voltage Vout3 of the reference level is converted into a
digital value D and is held as the first reference level of the
signal amplified with the amplification factor A2 in the up-down
counter UD2.
[0085] Next, if the level of the read signal READn becomes a high
level with the row selection transistor Ta of the pixel PCn being
turned on, the read transistor Td is turned on, the charges that
are accumulated in the photodiode PD are transmitted to the
floating diffusion FD, a voltage according to a signal level of the
floating diffusion FD is applied to the gate of the amplification
transistor Tb. In this case, since the source follower is
configured by the amplification transistor Tb and the constant
current transistor TL, the voltage of the vertical signal line Vlin
follows the voltage applied to the gate of the amplification
transistor Tb and is output as the output voltage Vout1 of the
signal level to the vertical signal line Vlin.
[0086] If the output voltage Vout1 of the signal level is applied
to the input terminal of the operational amplifier OP1 through the
capacitor C11 and the input voltage of the operational amplifier
OP1 is changed, the voltage is fed back from the capacitor C12 such
that the input voltage becomes a zero voltage. As a result, the
output voltage Vout2 of the signal level that is inverted and
amplified with the capacitance ratio C.sub.11/C.sub.12
(=amplification factor A1) is output from the operational amplifier
OP1 and is applied to the inverting input terminal of the
comparator PA1 through the capacitor C13.
[0087] If the output voltage Vout1 of the signal level is applied
to the input terminal of the operational amplifier OP2 through the
capacitor C21 and the input voltage of the operational amplifier
OP2 is changed, the voltage is fed back from the capacitor C22 such
that the input voltage becomes a zero voltage. As a result, the
output voltage Vout3 of the signal level that is inverted and
amplified with the capacitance ratio C.sub.21/C.sub.22
(=amplification factor A2) is output from the operational amplifier
OP2 and is applied to the inverting input terminal of the
comparator PA2 through the capacitor C23.
[0088] With the output voltage Vout2 of the signal level being
input to the comparator PA1 through the capacitor C13, a triangular
wave is applied as the reference voltage VREF1 and the output
voltage Vout2 of the signal level and the reference voltage VREF1
are compared with each other. After the output voltage of the
comparator PA1 is inverted by the inverter V1, the output voltage
is input as the output voltage Vout4 to one input terminal of the
AND circuit N1.
[0089] When the level of the output voltage Vout2 of the signal
level is lower than the level of the reference voltage VREF1, the
level of the output voltage Vout4 becomes a high level. For this
reason, the reference clock CKC1 passes through the AND circuit N1
and a reference clock CKCi1 after the passage is up-counted by the
up-down counter UD1. If the level of the output voltage Vout2 of
the signal level is matched with the level of the reference voltage
VREF1, the output voltage of the comparator PA1 falls and the level
of the output voltage Vout4 becomes a low level. For this reason,
the reference clock CKC1 is intercepted by the AND circuit N1, the
up-counting operation is stopped by the up-down counter UD1, and
the difference between the output voltage Vout2 of the signal level
and the output voltage Vout2 of the reference level is converted
into a digital value D and is transmitted to the line memory LM1.
As a result, in the line memory LM1, the difference between the
first signal level and the first reference level that are sampled
from the signal amplified with the amplification factor A1 is held
as a signal component of the amplification factor A1 detected by
the CDS.
[0090] With the output voltage Vout3 of the signal level being
input to the comparator PA2 through the capacitor C23, a triangular
wave is applied as the reference voltage VREF2 and the output
voltage Vout3 of the signal level and the reference voltage VREF2
are compared with each other. After the output voltage of the
comparator PA2 is inverted by the inverter V2, the output voltage
is input as the output voltage Vout4 to one input terminal of the
AND circuit N2.
[0091] When the level of the output voltage Vout3 of the signal
level is lower than the level of the reference voltage VREF2, the
level of the output voltage Vout5 becomes a high level. For this
reason, the reference clock CKC2 passes through the AND circuit N2
and a reference clock CKCi2 after the passage is up-counted by the
up-down counter UD2. If the level of the output voltage Vout3 of
the signal level is matched with the level of the reference voltage
VREF2, the output voltage of the comparator PA2 falls and the level
of the output voltage Vout5 becomes a low level. For this reason,
the reference clock CKC2 is intercepted by the AND circuit N2, the
up-counting operation is stopped by the up-down counter UD2, and
the difference between the output voltage Vout3 of the signal level
and the output voltage Vout3 of the reference level is converted
into a digital value D and is transmitted to the line memory LM2.
As a result, in the line memory LM2, the difference between the
second signal level and the second reference level that are sampled
from the signal amplified with the amplification factor A2 is held
as a signal component of the amplification factor A2 detected by
the CDS.
[0092] In this case, even when the up-counting operation is
executed on the basis of the output voltage Vout2 of the signal
level of the amplification factor A1 after the down-counting
operation is executed on the basis of the output voltage Vout2 of
the reference level of the amplification factor A1 and the
reference level is overlapped when reading the signal level, the
overlapped reference level can be cancelled and the signal
component of the amplification factor A1 can be effectively
detected by the CDS.
[0093] Even when the up-counting operation is executed on the basis
of the output voltage Vout3 of the signal level of the
amplification factor A2 after the down-counting operation is
executed on the basis of the output voltage Vout3 of the reference
level of the amplification factor A2 and the reference level is
overlapped when reading the signal level, the overlapped reference
level can be cancelled and the signal component of the
amplification factor A2 can be effectively detected by the CDS.
[0094] In an example of FIG. 3, since an average value of an
imaging area when imaging the dark subject is small, the
amplification factor A2 is set to 4.times.. However, since the
signal of the subject is different for each pixel, in a certain
pixel, the output signal Vout4 of the amplification factor A1 of
1.times. that has a digital value of 364 and the output signal
Vout5 of the amplification factor A2 of 4.times. that has a digital
value of 1264 are output. By the operation of the up-down counter
UD1 at the rear stage, the output signal Vout6 has a digital value
of 300 from which a digital value of 64 of the black level is
subtracted. By the operation of the up-down counter UD2, the output
signal Vout7 has a digital value of 1200 from which a digital value
of 64 of the black level is subtracted. However, the output signal
Vout7 has a digital value of 1023 by a clip operation to clip an
output of the up-down counter, for an operation of 10 bits. At this
time, by setting the VSL level to 1023, an output of the comparator
C becomes H. The output signal Vout8 has a digital value of 1200
where the digital value of the output signal Vout6 to be 300 is
amplified to the quadruple of the digital value of 300. The signal
that is saturated with the digital value of 1023 in the related art
is obtained without being saturated, and a signal where a dynamic
range is enlarged can be obtained. When the down-counter executes a
down-counting operation of a maximum of 255, the up-counter
executes an up-counting operation of a maximum of
1024+255=1279.
[0095] FIG. 4 is a diagram comparing a dynamic range of the
solid-state imaging device of FIG. 2 and a dynamic range according
to the related art.
[0096] In FIG. 4, the level of the output signal Vout6 of when the
amplification factor A1 is 1.times. becomes a level of 1023 to be a
saturation level, in the case in which the light intensity is 1.
Meanwhile, the level of the output signal Vout7 of when the
amplification factor A2 is 4.times. becomes a level of 1023 to be a
maximum value of the A/D conversion, in the case in which the light
intensity is 0.25.
[0097] When the light intensity is 0.25 or less, the output signal
Vout8 that is obtained by synthesizing the output signals Vout6 and
Vout7 becomes the output signal Vout7. When the light intensity is
more than 0.25, the output signal Vout8 becomes a signal that has a
digital value to be the quadruple of a digital value of the output
signal Vout6.
[0098] For this reason, the output signal Vout8 becomes a signal
where a signal component becomes linear with respect to the light
intensity of a level of a maximum of 4095. In a low-illumination
region (light intensity is 0.25 or less) where noise is observed,
by amplifying the signal to the quadruple by the column amplifying
circuit 3-2a, a signal having a high S/N ratio where circuit noise
of the column ADC circuit 5-2 is reduced to 1/4 of the original
noise can be obtained. By changing the amplification factor, a
low-illumination level can be changed. As the output signal Vout8,
a signal that corresponds to 12 bits of the A/D conversion is
obtained. In the low-illumination region, a signal having a high
S/N ratio can be obtained, and a dynamic range can be enlarged by
reducing the low-illumination noise. By making a signal component
of the output signal Vout8 linear with respect to the amount of
light, even when the amplification factor is switched, signal
processing of a rear stage can be executed without changing the
circuit configuration of the rear stage.
Third Embodiment
[0099] FIG. 5 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a third
embodiment.
[0100] In FIG. 5, the solid-state imaging device includes column
amplifying circuits 3-1b and 3-2b, instead of the column amplifying
circuits 3-1a and 3-2a of FIG. 2.
[0101] In the column amplifying circuit 3-1b, an amplification
transistor Tf1 and a load transistor Te1 are provided for each
column. A source of the amplification transistor Tf1 is connected
to the vertical signal line Vlin, a gate of the amplification
transistor Tf1 is connected to a bias power supply Vg1, and a drain
of the amplification transistor Tf1 is connected to a source of the
load transistor Te1. A drain of the load transistor Te1 is
connected to the power supply VDD and a gate of the load transistor
Te1 is connected to a switch SWsf1.
[0102] In this case, the amplification transistors Tb and Tf1, the
row selection transistor Ta, the load transistor Te1, and the
constant current transistor TL configure a differential amplifying
circuit. The switch SWsf1 can switch the connection destination of
the gate of the load transistor Te1 between the power supply VDD
and the ground.
[0103] In the column amplifying circuit 3-2b, an amplification
transistor Tf2 and a load transistor Te2 are provided for each
column. A source of the amplification transistor Tf2 is connected
to the vertical signal line Vlin and a gate of the amplification
transistor Tf2 is connected to a bias power supply Vg2, and a drain
of the amplification transistor Tf2 is connected to a source of the
load transistor Te2. A drain of the load transistor Te2 is
connected to the power supply VDD and a gate of the load transistor
Te2 is connected to a switch SWsf2.
[0104] In this case, the amplification transistors Tb and Tf2, the
row selection transistor Ta, the load transistor Te2, and the
constant current transistor TL configure a differential amplifying
circuit. The switch SWsf2 can switch the connection destination of
the gate of the load transistor Te2 between the power supply VDD
and the ground.
[0105] If the switch SWsf1 is switched to the H side, the gate
potential of the load transistor Te1 is set to the power supply
potential VDD and a differential operation can be executed by the
amplification transistors Tb and Tf1. Meanwhile, if the switch
SWsf1 is switched to the L side, the load transistor Te1 is turned
off and the output voltage Vout1 is output as the output voltage
Vout2 through the amplification transistor Tf1.
[0106] If the switch SWsf2 is switched to the H side, the gate
potential of the load transistor Te2 is set to the power supply
potential VDD and a differential operation can be executed by the
amplification transistors Tb and Tf2. Meanwhile, if the switch
SWsf2 is switched to the L side, the load transistor Te2 is turned
off and the output voltage Vout2 is output as the output voltage
Vout3 through the amplification transistor Tf2.
[0107] FIG. 6 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 5.
[0108] In FIG. 6, if the level of the row selection signal ADRESn
becomes a high level, the row selection transistor Ta of the pixel
PC is turned on, the power supply potential VDD is applied to the
drain of the amplification transistor Tb, and a source follower is
configured by the amplification transistor Tb and the constant
current transistor TL.
[0109] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta being turned on, the reset
transistor Tc is turned on and a voltage according to the reference
level of the floating diffusion FD is applied to the gate of the
amplification transistor Tb. In this case, since the source
follower is configured by the amplification transistor Tb and the
constant current transistor TL, the voltage of the vertical signal
line Vlin follows the voltage that is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the reference level to the vertical signal line Vlin.
[0110] If the output voltage Vout1 of the reference level is
applied to the source of the amplification transistor Tf1 with the
switch SWsf1 being switched to the H side, the output voltage Vout2
of the reference level is output from the drain of the
amplification transistor Tf1. In this case, the polarity of the
signal that is input to the gate of the amplification transistor Tb
becomes equal to the polarity of the output voltage Vout2 and the
polarity of the signal that is input to the gate of the
amplification transistor Tf1 becomes opposite to the polarity of
the output voltage Vout2.
[0111] Since the gate of the load transistor Te1 is connected to
the power supply VDD, the load transistor Te1 operates as a
resistor. When a signal is read from the pixel PCn, the row
selection transistor Ta is turned on and the gate of the row
selection transistor Ta is substantially connected to the power
supply VDD and the row selection transistor Ta operates as a
resistor. The constant current transistor TL executes an operation
to flow a constant current determined by a transistor size and a
gate voltage.
[0112] For this reason, the current that flows to the constant
current transistor TL becomes a sum of a source current of the
amplification transistor Tb and a source current of the
amplification transistor Tf1. If the source current of the
amplification transistor Tb increases, the source current of the
amplification transistor Tf1 decreases. If the source current of
the amplification transistor Tb decreases, the source current of
the amplification transistor Tf1 increases. For this reason, a
differential pair is configured by the amplification transistor Tb
and the amplification transistor Tf1 and the column amplifying
circuit 3-1b can execute a differential operation.
[0113] By changing the sizes of the amplification transistor Tf1
and the load transistor Te1, the amplification factor A1 of the
column amplifying circuit 3-1b can be set to 1 or less, or 1 or
more. For example, by setting a resistance value of the load
transistor Te1 to be larger than a resistance value of the
amplification transistor Tf1, the amplification factor A1 can be
increased.
[0114] When the signal of the reference level is output to the
vertical signal line Vlin, if the reset pulse Pcp1 is input to the
gate of the switch transistor Tcp1, the input voltage of the
comparator PA1 is clamped with the output voltage and an operation
point is set.
[0115] Then, with the output voltage Vout2 of the reference level
being input to the comparator PA1 through the capacitor C13, a
triangular wave is applied as the reference voltage VREF1 and the
output voltage Vout2 of the reference level and the reference
voltage VREF1 are compared with each other. The high level of the
output voltage Vout4 is maintained until the output voltage Vout2
of the reference level is matched with the level of the reference
voltage VREF1, the up-down counter UD1 executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the reference
level is converted into a digital value D and is held as the first
level of the signal amplified with the amplification factor A1 in
the up-down counter UD1.
[0116] If the output voltage Vout1 of the reference level is
applied to the source of the amplification transistor Tf2 with the
switch SWsf2 being switched to the H side, the output voltage Vout3
of the reference level is output from the drain of the
amplification transistor Tf2. In this case, the polarity of the
signal that is input to the gate of the amplification transistor Tb
becomes equal to the polarity of the output voltage Vout3 and the
polarity of the signal that is input to the gate of the
amplification transistor Tf2 becomes opposite to the polarity of
the output voltage Vout3.
[0117] Since the gate of the load transistor Te2 is connected to
the power supply VDD, the load transistor Te2 operates as a
resistor. When a signal is read from the pixel PCn, the row
selection transistor Ta is turned on, the gate of the row selection
transistor Ta is substantially connected to the power supply VDD,
and the row selection transistor Ta operates as a resistor.
[0118] For this reason, the current that flows to the constant
current transistor TL becomes a sum of a source current of the
amplification transistor Tb and a source current of the
amplification transistor Tf2. If the source current of the
amplification transistor Tb increases, the source current of the
amplification transistor Tf2 decreases. If the source current of
the amplification transistor Tb decreases, the source current of
the amplification transistor Tf2 increases. For this reason, a
differential pair is configured by the amplification transistor Tb
and the amplification transistor Tf2 and the column amplifying
circuit 3-2b can execute a differential operation.
[0119] By changing the sizes of the amplification transistor Tf2
and the load transistor Te2, the amplification factor A2 of the
column amplifying circuit 3-2b can be set to 1 or less, or 1 or
more. For example, by setting a resistance value of the load
transistor Te2 to be larger than a resistance value of the
amplification transistor Tf2, the amplification factor A2 can be
increased.
[0120] When the signal of the reference level is output to the
vertical signal line Vlin, if the reset pulse Pcp2 is input to the
gate of the switch transistor Tcp2, the input voltage of the
comparator PA2 is clamped with the output voltage and an operation
point is set.
[0121] Then, with the output voltage Vout3 of the reference level
being input to the comparator PA2 through the capacitor C23, a
triangular wave is applied as the reference voltage VREF2 and the
output voltage Vout3 of the reference level and the reference
voltage VREF2 are compared with each other. The high level of the
output voltage Vout5 is maintained until the output voltage Vout3
of the reference level is matched with the level of the reference
voltage VREF2, the up-down counter UD2 executes the down-counting
operation until the level of the output voltage Vout5 is inverted
into a low level, and the output voltage Vout3 of the reference
level is converted into a digital value D and is held as the second
level of the signal amplified with the amplification factor A2 in
the up-down counter UD2.
[0122] Next, if the level of the read signal READn becomes a high
level with the row selection transistor Ta of the pixel PCn being
turned on, the read transistor Td is turned on, the charges that
are accumulated in the photodiode PD are transmitted to the
floating diffusion FD, and a voltage according to the reference
level of the floating diffusion FD is applied to the gate of the
amplification transistor Tb. In this case, since the source
follower is configured by the amplification transistor Tb and the
constant current transistor TL, the voltage of the vertical signal
line Vlin follows the voltage that is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the signal level to the vertical signal line Vlin.
[0123] The output voltage Vout1 of the signal level is applied to
the source of the amplification transistor Tf1 and the output
voltage Vout2 of the signal level is output from the drain of the
amplification transistor Tf1.
[0124] Then, with the output voltage Vout2 of the signal level
being input to the comparator PA1 through the capacitor C13, a
triangular wave is applied as the reference voltage VREF1 and the
output voltage Vout2 of the signal level and the reference voltage
VREF1 are compared with each other. The high level of the output
voltage Vout4 is maintained until the level of the output voltage
Vout2 of the signal level is matched with the level of the
reference voltage VREF1, the up-down counter UD1 executes the
up-counting operation until the level of the output voltage Vout4
is inverted into a low level, and a differential voltage of the
output voltage Vout2 of the signal level and the output voltage
Vout2 of the reference level is converted into a digital value D
and is transmitted to the line memory LM1. As a result, in the line
memory LM1, the difference between the first signal level and the
first reference level that are sampled from the signal amplified
with the amplification factor A1 is held as the signal component of
the amplification factor A1 detected by the CDS.
[0125] With the output voltage Vout3 of the signal level being
input to the comparator PA2 through the capacitor C23, a triangular
wave is applied as the reference voltage VREF2 and the output
voltage Vout3 of the signal level and the reference voltage VREF2
are compared with each other. The high level of the output voltage
Vout5 is maintained until the level of the output voltage Vout3 of
the signal level is matched with the level of the reference voltage
VREF2, the up-down counter UD2 executes the up-counting operation
until the level of the output voltage Vout5 is inverted into a low
level, and the difference between the output voltage Vout3 of the
signal level and the output voltage Vout3 of the reference level is
converted into a digital value D and is transmitted to the line
memory LM2. As a result, in the line memory LM2, the difference
between the second signal level and the second reference level that
are sampled from the signal amplified with the amplification factor
A2 is held as the signal component of the amplification factor A2
detected by the CDS.
[0126] In this case, even when the up-counting operation is
executed on the basis of the output voltage Vout2 of the signal
level of the amplification factor A1 after the down-counting
operation is executed on the basis of the output voltage Vout2 of
the reference level of the amplification factor A1 and the
reference level is overlapped when reading the signal level, the
overlapped reference level can be cancelled and the signal
component of the amplification factor A1 can be effectively
detected by the CDS.
[0127] Even when the up-counting operation is executed on the basis
of the output voltage Vout3 of the signal level of the
amplification factor A2 after the down-counting operation is
executed on the basis of the output voltage Vout3 of the reference
level of the amplification factor A2 and the reference level is
overlapped when reading the signal level, the overlapped reference
level can be cancelled and the signal component of the
amplification factor A2 can be effectively detected by the CDS.
[0128] Since the amplification factors A1 and A2 are adjusted by
configuring the differential amplifying circuit by the column
amplifying circuits 3-1b and 3-2b, the capacitor does not need to
be used. As compared with the case in which the switched capacity
type amplifying circuits are used as the column amplifying circuits
3-1a and 3-2a of FIG. 2, an area can be reduced.
[0129] By configuring the differential amplifying circuit by the
column amplifying circuits 3-1b and 3-2b, the current that flows to
the constant current transistor TL can be used as the bias current
of the column amplifying circuits 3-1b and 3-2b, and the bias
current of the column amplifying circuits 3-1b and 3-2b does not
need to be set independently from the source follower circuit
configured by the amplification transistor Tb and the constant
current transistor TL. Therefore, power consumption can be
reduced.
[0130] By configuring the differential amplifying circuit by the
column amplifying circuits 3-1b and 3-2b, the same-phase component
of the differential input can be cancelled. Therefore, an S/N ratio
of each column can be improved.
[0131] If the amplification factor A2 is set to be larger than the
amplification factor A1, preferably, sampling is executed in the
order of sampling of the reference level of the amplification
factor A1->sampling of the reference level of the amplification
factor A2->sampling of the signal level of the amplification
factor A2->sampling of the signal level of the amplification
factor A1 and the sampling of the reference level of the
amplification factor A2 and the sampling of the signal level of the
amplification factor A2 are continuously executed.
[0132] Thereby, as compared with the case in which sampling is
executed in the order of sampling of the reference level of the
amplification factor A1->sampling of the reference level of the
amplification factor A2->sampling of the signal level of the
amplification factor A1->sampling of the signal level of the
amplification factor A2, a digital CDS time TD with respect to a
signal having the low signal level can be reduced. For this reason,
1/f noise or RTS noise with respect to the signal having the low
signal level can be reduced and an image quality can be
improved.
Fourth Embodiment
[0133] FIG. 7 a block diagram of a schematic configuration of a
solid-state imaging device according to a fourth embodiment.
[0134] In FIG. 7, the solid-state imaging device includes a column
amplifying circuit 3, a sample and hold signal converting circuit
4, a column scanning circuit 7, and a D/A converter 9, instead of
the column amplifying circuits 3-1 and 3-2, the sample and hold
signal converting circuits 4-1 and 4-2, the column scanning
circuits 7-1 and 7-2, and the D/A converters 9-1 and 9-2 of FIG. 1.
In the solid-state imaging device, a subtractor 13 that adjusts a
black level with respect to a signal component of each pixel PCn
may be provided.
[0135] The column amplifying circuit 3 can switch the amplification
factors of the signals read from each pixel PC with the
amplification factors A1 and A1 and amplify the signals for each
column. The sample and hold signal converting circuit 4 can detect
the signal component of each pixel PC amplified with the
amplification factors A1 and A2 by the CDS. The column scanning
circuit 7 can execute a scanning operation in a horizontal
direction to read the signals stored in the line memories 6-1 and
6-1 of the sample and hold signal converting circuit 4. The D/A
converter 9 can output the reference voltage VREF to the sample and
hold signal converting circuit 4.
[0136] The sample and hold signal converting circuit 4 can sample
the first reference level and the first signal level from the
signal of each pixel PC amplified with the amplification factor A1
and can detect the signal component of each pixel PC by the CDS.
The sample and hold signal converting circuit 4 can sample the
second reference level and the second signal level from the signal
of each pixel PC amplified with the amplification factor A2 and can
detect the signal component of each pixel PC by the CDS.
[0137] The sample and hold signal converting circuit 4 includes a
column ADC circuit 5 that executes the up-counting operation and
the down-counting operation on the basis of the comparison result
of the read signal from the pixel PC amplified with the
amplification factors A1 and A2 and the reference voltage VREF and
calculates the difference between the reference level and the
signal level of the CDS, a line memory 6-1 that stores a count
value of the column ADC circuit 5 with respect to the signal
amplified with the amplification factor A1 by the amount of
horizontal pixels, and a line memory 6-2 that stores a count value
of the column ADC circuit 5 with respect to the signal amplified
with the amplification factor A2 by the amount of horizontal
pixels.
[0138] If the pixels PC are scanned in a vertical direction by the
row scanning circuit 2, the pixels PC of the row direction are
selected and the signals that are read from the pixels PC are
transmitted to the column amplifying circuit 3 through the vertical
signal line Vlin. After the signals read from the pixels PC are
amplified with the amplification factors A1 and A2 by the column
amplifying circuit 3, the signals are transmitted to the sample and
hold signal converting circuit 4.
[0139] In the sample and hold signal converting circuit 4, the
first reference level and the first signal level are sampled from
the signal of each pixel PC amplified with the amplification factor
A1, the difference between the first signal level and the first
reference level is taken, and the signal component of each pixel PC
is detected by the CDS and is output as the output signal
Vout6.
[0140] In the sample and hold signal converting circuit 4, the
second reference level and the second signal level are sampled from
the signal of each pixel PC amplified with the amplification factor
A2, the difference between the second signal level and the second
reference level is taken, and the signal component of each pixel PC
is detected by the CDS and is output as the output signal
Vout7.
[0141] In this case, in the column ADC circuit 5, after the
down-counting operation is executed until the first reference level
sampled from the signal of each pixel PC amplified with the
amplification factor A1 is matched with the level of the reference
voltage VREF, the up-counting operation is executed until the first
signal level sampled from the signal of each pixel PC amplified
with the amplification factor A1 is matched with the level of the
reference voltage VREF, and the signal component of the
amplification factor A1 that is detected by the CDS is converted
into a digital value and is held in the line memory 6-1 by the
amount of horizontal pixels.
[0142] In the column ADC circuit 5, after the down-counting
operation is executed until the second reference level sampled from
the signal of each pixel PC amplified with the amplification factor
A2 is matched with the level of the reference voltage VREF, the
up-counting operation is executed until the second signal level
sampled from the signal of each pixel PC amplified with the
amplification factor A2 is matched with the level of the reference
voltage VREF, and the signal component of the amplification factor
A2 that is detected by the CDS is converted into a digital value
and is held in the line memory 6-2 by the amount of horizontal
pixels.
[0143] In the subtractor 13, the black level SB is subtracted from
the output signal Vout6 according to necessity, the black level of
the output signal Vout6 is adjusted, and the output signal is
output to the multiplier 10.
[0144] In this case, even when the reference level is sampled for
each of the amplification factors A1 and A2 by the sample and hold
signal converting circuit 4 and the amplification factors A1 and A2
are switched, the noise can be effectively suppressed by the
CDS.
[0145] By switching the amplification factors A1 and A2 by the
column amplifying circuit 3, the column amplifying circuits 3-1 and
3-2 and the sample and hold signal converting circuits 4-1 and 4-2
of FIG. 1 do not need to be provided for each of the amplification
factors A1 and A2, and a circuit scale can be suppressed from
increasing.
Fifth Embodiment
[0146] FIG. 8 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a fifth
embodiment.
[0147] In FIG. 8, the solid-state imaging device includes a column
amplifying circuit 3a and a sample and hold signal converting
circuit 4a, instead of the column amplifying circuits 3-1a and 3-2a
and the sample and hold signal converting circuits 4-1a and 4-2a of
FIG. 2.
[0148] In the column amplifying circuit 3a, capacitors C1, C2-1,
C2-2, and C3, an operational amplifier OP, an inverter V4, and
switch transistors Tsc1-1 and Tsc2-1 are provided for each column.
The vertical signal line Vlin is connected to an input terminal of
the operational amplifier OP through the capacitor C1 and the
capacitor C2-1 is connected between the input terminal and an
output terminal of the operational amplifier OP. The switch
transistor Tsc1-1 is connected in parallel to the capacitor C2-1. A
series circuit of the switch transistor Tsc2-1 and the capacitor
C2-2 is connected in parallel to the capacitor C2-1. The reset
pulse Psc is input to the gate of the switch transistor Tsc1-1 and
a switching signal SET-A is input to the gate of the switch
transistor Tsc2-1 through an inverter V4.
[0149] In the column amplifying circuit 3a, the amplification
factors A1 and A2 can be switched by turning on/off the switch
transistor Tsc2-l. For example, when the switch transistor Tsc2-1
is turned on, the amplification factor A1 of the column amplifying
circuit 3a is applied as C.sub.1/(C.sub.2-1+C.sub.2-2). When the
switch transistor Tsc2-1 is turned off, the amplification factor A2
of the column amplifying circuit 3a is applied as
C.sub.1/C.sub.2-1. In this case, a capacitance value of the
capacitor C1 is set as C.sub.1, a capacitance value of the
capacitor C2-1 is set as C.sub.2-1, and a capacitance value of the
capacitor C2-2 is set as C.sub.2-2.
[0150] In the sample and hold signal converting circuit 4a, a
comparator PA, a switch transistor Tcp, an inverter V, a switch
SW1, up-counters UD1 and UD2, and line memories LM1 and LM2 are
provided for each column.
[0151] An output terminal of the operational amplifier OP is
connected to an inverting input terminal of the comparator PA
through a capacitor C3 and the reference voltage VREF is input to a
non-inverting input terminal of the comparator PA. The switch
transistor Tcp is connected between the inverting input terminal
and the output terminal of the comparator PA. The output terminal
of the comparator PA is connected to the switch SW1 through the
inverter V, and the L side of the switch SW1 is connected to the
up-down counter UD1 and the H side thereof is connected to the
up-down counter UD2.
[0152] FIG. 9 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 8.
[0153] In FIG. 9, when a level of the switching signal SET-A is set
to a low level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a high level. If the
switch transistor Tsc2-1 is turned on, the amplification factor of
the column amplifying circuit 3a is set to A1. When the level of
the switching signal SET-A is set to a low level, the switch SW1 is
switched to the L side.
[0154] If a level of the row selection signal ADRESn becomes a high
level, the row selection transistor Ta of the pixel PCn is turned
on, the power supply potential VDD is applied to the drain of the
amplification transistor Tb, and a source follower is configured by
the amplification transistor Tb and the constant current transistor
TL.
[0155] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta being turned on, the reset
transistor Tc is turned on, and a voltage according to a reference
level of the floating diffusion FD is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the reference level to the vertical signal line Vlin.
[0156] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if the reset pulse Psc is
applied to the gate of the switch transistor Tsc1-1, the input
voltage of the operational amplifier OP is clamped with the output
voltage and an operation point is set. At this time, the voltage
difference with respect to the vertical signal line Vlin is held in
the capacitor C1 and an input voltage of the operational amplifier
OP is set to zero.
[0157] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if the reset pulse Pep is
applied to the gate of the switch transistor Tcp, the input voltage
of the inverting input terminal of the comparator PA is clamped
with the output voltage and an operation point is set. At this
time, the voltage difference with respect to the output voltage
Vout2 from the operational amplifier OP is held in the capacitor C3
and an input voltage of the comparator PA is set to zero.
[0158] After the switch transistor Tsc1-1 is turned off, if the
input voltage of the operational amplifier OP is changed, the
voltage is fed back from the capacitors C2-1 and C2-2, such that
the input voltage becomes the zero voltage. As a result, the output
voltage Vout2 that is inverted and amplified with the amplification
factor A1 is output from the operational amplifier OP and is
applied to the inverting input terminal of the comparator PA
through the capacitor C3.
[0159] With the output voltage Vout2 of the reference level of the
amplification factor A1 being input to the comparator PA through
the capacitor C3 after the switch transistor Tcp is turned off, a
triangular wave is applied as the reference voltage VREF and the
output voltage Vout2 of the reference level of the amplification
factor A1 and the reference voltage VREF are compared with each
other. After the output voltage of the comparator PA is inverted by
the inverter V, the output voltage is input as the output voltage
Vout4 to the up-down counter UD1 through the switch SW1.
[0160] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the reference level of the
amplification factor A1 is matched with the level of the reference
voltage VREF, the up-down counter UD1 executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the reference
level of the amplification factor A1 is converted into a digital
value D and is held as the first reference level of the signal
amplified with the amplification factor A1 in the up-down counter
UD1.
[0161] Next, if the level of the switching signal SET-A changes to
a high level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a low level. If the
switch transistor Tsc2-1 is turned off, the amplification factor of
the column amplifying circuit 3a is set to A2. When the level of
the switching signal SET-A is set to a high level, the switch SW1
is switched to the H side.
[0162] After the level of the switching signal SET-A changes to a
high level, if the input voltage of the operational amplifier OP
changes, the voltage is fed back from the capacitor C2-1, such that
the input voltage becomes the zero voltage. As a result, the output
voltage Vout2 that is inverted and amplified with the amplification
factor A2 is output from the operational amplifier OP and is
applied to the inverting input terminal of the comparator PA
through the capacitor C3.
[0163] With the output voltage Vout2 of the reference level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the reference level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to the up-down counter UD2
through the switch SW1.
[0164] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the reference level of the
amplification factor A2 is matched with the level of the reference
voltage VREF, the up-down counter UD2 executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the reference
level of the amplification factor A2 is converted into a digital
value D and is held as the second reference level of the signal
amplified with the amplification factor A2 in the up-down counter
UD2.
[0165] Next, if the level of the read signal READn becomes a high
level with the row selection transistor Ta of the pixel PCn being
turned on, the read transistor Td is turned on, the charges that
are accumulated in the photodiode PD are transmitted to the
floating diffusion FD. A voltage according to a signal level of the
floating diffusion FD is applied to the gate of the amplification
transistor Tb and is output as the output voltage Vout1 of the
signal level to the vertical signal line Vlin.
[0166] If the output voltage Vout1 of the signal level is applied
to the input terminal of the operational amplifier OP through the
capacitor C1 and the input voltage of the operational amplifier OP
changes, the voltage is fed back from the capacitor C2-1 such that
the input voltage becomes a zero voltage. As a result, the output
voltage Vout2 of the signal level that is inverted and amplified
with the amplification factor A2 is output from the operational
amplifier OP and is applied to the inverting input terminal of the
comparator PA through the capacitor C3.
[0167] With the output voltage Vout2 of the signal level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the signal level and
the output voltage Vout2 of the signal level of the amplification
factor A2 and the reference voltage VREF are compared with each
other. After the output voltage of the capacitor PA is inverted by
the inverter V, the output voltage is input as the output voltage
Vout4 to the up-down counter UD2 through the switch SW1.
[0168] The high level of the output voltage Vout4 is maintained
until the level of the output voltage Vout2 of the signal level of
the amplification factor A2 is matched with the level of the
reference voltage VREF, the up-down counter UD2 executes the
up-counting operation until the level of the output voltage Vout4
is inverted into a low level, and the difference between the output
voltage Vout2 of the signal level of the amplification factor A2
and the output voltage Vout2 of the reference level is converted
into a digital value D and is transmitted to the line memory LM2.
As a result, in the line memory LM2, the difference between the
second signal level and the second reference level that are sampled
from the signal amplified with the amplification factor A2 is held
as the signal component of the amplification factor A2 detected by
the CDS.
[0169] Next, if the level of the switching signal SET-A changes to
a low level, the switching signal SET-A is inverted by the inverter
V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor of the
column amplifying circuit 3a is set to A1. If the level of the
switching signal SET-A changes to a low level, the switch SW1 is
switched to the L side.
[0170] With the output voltage Vout2 of the signal level of the
amplification factor A1 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the signal level of
the amplification factor A1 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to the up-down counter UD1
through the switch SW1.
[0171] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the signal level of the
amplification factor A1 is matched with the level of the reference
voltage VREF, the up-down counter UD1 executes the up-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the difference between the output voltage
Vout2 of the signal level of the amplification factor A1 and the
output voltage Vout2 of the reference voltage is converted into a
digital value D and is transmitted to the line memory LM1. As a
result, in the line memory LM1, the difference between the first
signal level and the first reference level that are sampled from
the signal amplified with the amplification factor A1 is held as
the signal component of the amplification factor A1 detected by the
CDS.
[0172] In this case, even when the first reference level and the
first signal level are sampled before the amplification factor of
the signal read from the pixel PCn is switched and the second
reference level and the second signal level are sampled after the
amplification factor of the signal read from the pixel PCn is
switched and the amplification factor of the signal read from the
pixel PCn is switched, the reference level according to the
amplification factor can be cancelled and an effect of suppressing
noise based on the CDS can be improved.
[0173] In the fifth embodiment, since the black level is cancelled
in both the signal component of the amplification factor A1 and the
signal component of the amplification factor A2, the black level
does not need to be adjusted by the subtractor 13 of FIG. 7.
Sixth Embodiment
[0174] FIG. 10 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a sixth
embodiment.
[0175] In FIG. 10, the solid-state imaging device includes a column
amplifying circuit 3b and a sample and hold signal converting
circuit 4b, instead of the column amplifying circuit 3a and the
sample and hold signal converting circuit 4a of FIG. 8.
[0176] In the column amplifying circuit 3b, column amplifying
circuits 3-1b' and 3-2b', a switch SW2, and an inverter V3 are
provided. In this case, the amplification factor of the column
amplifying circuit 3-1b' is set to A1 and the amplification factor
of the column amplifying circuit 3b-2' is set to A2.
[0177] In the column amplifying circuit 3-1b', an amplification
transistor Tf1 and a load transistor Te1 are provided for each
column. A source of the amplification transistor Tf1 is connected
to the vertical signal line Vlin and a drain thereof is connected
to a source of the load transistor Te1. A gate of the amplification
transistor Tf1 is connected to the ground through the capacitor C31
and is connected to an output terminal of a comparator PA3 through
the switch transistor Tcp11. A drain of the load transistor Te1 is
connected to the power supply VDD and a gate thereof is connected
to a switch SWsf1.
[0178] In the column amplifying circuit 3-2b', an amplification
transistor Tf2 and a load transistor Te2 are provided for each
column. A source of the amplification transistor Tf2 is connected
to the vertical signal line Vlin and a drain thereof is connected
to a source of the load transistor Te2. A gate of the amplification
transistor Tf2 is connected to the ground through the capacitor C32
and is connected to the output terminal of the comparator PA3
through the switch transistor Tcp12. A drain of the load transistor
Te2 is connected to the power supply VDD and a gate thereof is
connected to a switch SWsf2.
[0179] The switch SWsf1 is switched by a signal obtained by
inverting the switching signal SET-A by the inverter V3 and the
switch SWsf2 is switched by the switching signal SET-A. The L side
of the switch SW2 is connected to the drain of the amplification
transistor Tf1 and the H side thereof is connected to the drain of
the amplification transistor Tf2. The reset pulse Pcp1 is input to
the gate of the switch transistor Tcp11 and the reset pulse Pcp2 is
input to the gate of the switch transistor Tcp12.
[0180] In the sample and hold signal converting circuit 4b, instead
of the comparator PA, the switch transistor Tcp, and the inverter V
of the sample and hold signal converting circuit 4a of FIG. 8, the
comparator PA3 is provided.
[0181] In this case, a non-inverting terminal of the comparator PA3
is connected to the switch SW2, a reference voltage VREF is applied
to an inverting input terminal of the comparator PA3, and an output
terminal of the comparator PA3 is connected to the switch SW1.
[0182] FIG. 11 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 10.
[0183] In FIG. 11, when the level of the switching signal SET-A is
set to a low level, the switch SWsf2 is switched to the L side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a high level, and the switch SWsf1 is switched to
the H side. When the level of the switching signal SET-A is set to
a low level, the switches SW1 and SW2 are switched to the L
side.
[0184] If the level of the row selection signal ADRESn becomes a
high level, the row selection transistor Ta of the pixel PC is
turned on, the power supply potential VDD is applied to the drain
of the amplification transistor Tb, and a source follower is
configured by the amplification transistor Tb and the constant
current transistor TL.
[0185] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta being turned on, the reset
transistor Tc is turned on and a voltage according to the reference
level of the floating diffusion FD is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the reference level to the vertical signal line Vlin.
[0186] If the output voltage Vout1 of the reference level is
applied to the source of the amplification transistor Tf1 with the
switch SWsf1 being switched to the H side, the output voltage Vout2
of the reference level of the amplification factor A1 is output
from the drain of the amplification transistor Tf1.
[0187] When the signal of the reference level is output to the
vertical signal line Vlin, if the reset pulse Pcp1 is input to the
gate of the switch transistor Tcp11, the output voltage Vout4 of
the comparator PA3 is held in the capacitor C31 and is applied to
the gate of the amplification transistor Tf1, and a bias voltage is
applied.
[0188] Next, if the level of the switching signal SET-A changes to
a high level, the switch SWsf2 is switched to the H side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a low level, and the switch SWsf1 is switched to
the L side. If the level of the switching signal SET-A changes to a
high level, the switches SW1 and SW2 are switched to the H
side.
[0189] If the output voltage Vout1 of the reference level is
applied to the source of the amplification transistor Tf2 with the
switch SWsf2 being switched to the H side, the output voltage Vout3
of the reference level of the amplification factor A2 is output
from the drain of the amplification transistor Tf2.
[0190] When the signal of the reference level is output to the
vertical signal line Vlin, if the reset pulse Pcp2 is input to the
gate of the switch transistor Tcp12, the output voltage Vout4 of
the comparator PA3 is held in the capacitor C32 and is applied to
the gate of the amplification transistor Tf2, and a bias voltage is
applied.
[0191] Next, if the level of the switching signal SET-A changes to
a low level, the switch SWsf2 is switched to the L side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a high level, and the switch SWsf1 is switched to
the H side. If the level of the switching signal SET-A changes to a
low level, the switches SW1 and SW2 are switched to the L side.
[0192] Then, with the output voltage Vout2 of the reference level
of the amplification factor A1 being input to the comparator PA3
through the switch SW2, a triangular wave is applied as the
reference voltage VREF and the output voltage Vout2 of the
reference level of the amplification factor A1 and the reference
voltage VREF are compared with each other. The high level of the
output voltage Vout4 is maintained until the level of the output
voltage Vout2 of the reference level of the amplification factor A1
is matched with the level of the reference voltage VREF, the
up-down counter UD1 executes the down-counting operation until the
level of the output voltage Vout4 is inverted into a low level, and
the output voltage Vout2 of the reference level of the
amplification factor A1 is converted into a digital value D and is
held as the first reference level of the signal amplified with the
amplification factor A1 in the up-down counter UD1.
[0193] Next, if the level of the switching signal SET-A changes to
the high level, the switch SWsf2 is switched to the H side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a low level, and the switch SWsf1 is switched to
the L side. If the level of the switching signal SET-A changes to a
high level, the switches SW1 and SW2 are switched to the H
side.
[0194] Then, with the output voltage Vout3 of the reference level
of the amplification factor A2 being input to the comparator PA3
through the switch SW2, a triangular wave is applied as the
reference voltage VREF and the output voltage Vout3 of the
reference level of the amplification factor A2 and the reference
voltage VREF are compared with each other. The high level of the
output voltage Vout4 is maintained until the output voltage Vout3
of the reference level of the amplification factor A2 is matched
with the level of the reference voltage VREF, the up-down counter
UD2 executes the down-counting operation until the level of the
output voltage Vout4 is inverted into a low level, and the output
voltage Vout3 of the reference level of the amplification factor A2
is converted into a digital value D and is held as the second
reference level of the signal amplified with the amplification
factor A2 in the up-down counter UD2.
[0195] If the level of the read signal READn becomes a high level
with the row selection transistor Ta of the pixel PCn being turned
on, the read transistor Td is turned on and the charges that are
accumulated in the photodiode PD are transmitted to the floating
diffusion FD. In addition, a voltage according to the signal level
of the floating diffusion FD is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the signal level to the vertical signal line Vlin.
[0196] If the output voltage Vout1 of the signal level is applied
to the source of the amplification transistor Tf1, the output
voltage Vout2 of the signal level of the amplification factor A2 is
output from the drain of the amplification transistor Tf1.
[0197] Then, with the output voltage Vout3 of the signal level of
the amplification factor A2 being input to the comparator PA
through the switch SW2, a triangular wave is applied as the
reference voltage VREF and the output voltage Vout3 of the signal
level of the amplification factor A2 and the reference voltage VREF
are compared with each other. The high level of the output voltage
Vout4 is maintained until the level of the output voltage Vout3 of
the signal level of the amplification factor A2 is matched with the
level of the reference voltage VREF, the up-down counter UD2
executes the up-counting operation until the level of the output
voltage Vout4 is inverted into a low level, and the difference
between the output voltage Vout3 of the signal level of the
amplification factor A2 and the output voltage Vout3 of the
reference level is converted into a digital value D and is
transmitted to the line memory LM2. As a result, in the line memory
LM2, the difference between the second signal level and the second
reference level that are sampled from the signal amplified with the
amplification factor A2 is held as the signal component of the
amplification factor A2 detected by the CDS.
[0198] Next, if the level of the switching signal SET-A changes to
a low level, the switch SWsf2 is switched to the L side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a high level, and the switch SWsf1 is switched to
the H side. If the level of the switching signal SET-A changes to a
low level, the switches SW1 and SW2 are switched to the L side.
[0199] Then, with the output voltage Vout2 of the reference level
of the amplification factor A1 being input to the comparator PA
through the switch SW2, a triangular wave is applied as the
reference voltage VREF and the output voltage Vout2 of the signal
level of the amplification factor A1 and the reference voltage VREF
are compared with each other. The high level of the output voltage
Vout4 is maintained until the level of the output voltage Vout2 of
the signal level of the amplification factor A1 is matched with the
level of the reference voltage VREF, the up-down counter UD1
executes the up-counting operation until the level of the output
voltage Vout4 is inverted into a low level, and the difference
between the output voltage Vout2 of the signal level of the
amplification factor A1 and the output voltage Vout2 of the
reference level is converted into a digital value D and is
transmitted to the line memory LM1. As a result, in the line memory
LM1, the difference between the first signal level and the first
reference level that are sampled from the signal amplified with the
amplification factor A1 is held as the signal component of the
amplification factor A1 detected by the CDS.
[0200] In this case, even when the first reference level and the
first signal level of the amplification factor A1 of the signal
read from the pixel PCn are sampled and the second reference level
and the second signal level of the amplification factor A2 of the
signal read from the pixel PCn are sampled and the amplification
factor of the signal read from the pixel PCn is switched, the
reference level according to the amplification factor can be
cancelled and an effect of suppressing noise based on the CDS can
be improved.
[0201] In the sixth embodiment, since the black level is cancelled
in both the signal component of the amplification factor A1 and the
signal component of the amplification factor A2, the black level
does not need to be adjusted by the subtractor 13 of FIG. 7.
Seventh Embodiment
[0202] FIG. 12 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a seventh
embodiment.
[0203] In FIG. 12, a solid-state imaging device includes a sample
and hold signal converting circuit 4c, instead of the sample and
hold signal converting circuit 4a of FIG. 8.
[0204] In this case, in the sample and hold signal converting
circuit 4c, instead of the switch SW1, the up-down counters UD1 and
UD2, and the line memories LM1 and LM2 of FIG. 8, an up-down
counter UD and line memories LM11 and LM12 are provided.
[0205] FIG. 13 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 12.
[0206] In FIG. 13, when the level of the switching signal SET-A is
set to a high level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a low level. The switch
transistor Tsc2-1 is turned off and the amplification factor of the
column amplifying circuit 3a is set to A2.
[0207] If the level of the row selection signal ADRESn becomes a
high level, the row selection transistor Ta of the pixel PCn is
turned on, the power supply potential VDD is applied to the drain
of the amplification transistor Tb, and a source follower is
configured by the amplification transistor Tb and the constant
current transistor TL.
[0208] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta being turned on, the reset
transistor Tc is turned on and a voltage according to the reference
level of the floating diffusion FD is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the reference level to the vertical signal line Vlin.
[0209] When the output voltage Vout1 of the reference level of the
amplification factor A2 is output to the vertical signal line Vlin,
if the reset pulse Psc is applied to the gate of the switch
transistor Tsc1-1, the input voltage of the operational amplifier
OP is clamped with the output voltage and an operation point is
set. At this time, the voltage difference with respect to the
vertical signal line Vlin is held in the capacitor C1 and the input
voltage of the operational amplifier OP is set to zero.
[0210] Next, if the level of the switching signal SET-A changes to
a low level, the switching signal SET-A is inverted by the inverter
V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor of the
column amplifying circuit 3a is set to A1.
[0211] When the output voltage Vout1 of the reference level of the
amplification factor A1 is output to the vertical signal line Vlin,
if the reset pulse Pcp is input to the gate of the switch
transistor Tcp, the input voltage of the inverting input terminal
of the comparator PA is clamped with the output voltage and an
operation point is set. At this time, the voltage difference with
respect to the output voltage Vout2 from the operational amplifier
OP is held in the capacitor C3 and the input voltage of the
comparator PA is set to zero. At this time, in the capacitors C1
and C3, a reference level at the time of an analog CDS operation is
held.
[0212] Next, if the level of the switching signal SET-A changes to
a high level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a low level. The switch
transistor Tsc2-1 is turned off and the amplification factor of the
column amplifying circuit 3a is set to A2.
[0213] With the output voltage Vout2 of the reference level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the reference level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to the up-down counter UD.
[0214] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the reference level of the
amplification factor A2 is matched with the level of the reference
voltage VREF, the up-down counter UD executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the reference
level of the amplification factor A2 is converted into a digital
value D and is held as the second reference level of the signal
amplified with the amplification factor A2 in the up-down counter
UD.
[0215] Next, if the level of the read signal READn becomes a high
level with the row selection transistor Ta of the pixel PCn being
turned on, the read transistor Td is turned on and the charges that
are accumulated in the photodiode PD are transmitted to the
floating diffusion FD. In addition, a voltage according to the
signal level of the floating diffusion FD is applied to the gate of
the amplification transistor Tb and is output as the output voltage
Vout1 of the signal level to the vertical signal line Vlin.
[0216] If the output voltage Vout1 of the signal level is applied
to the input terminal of the operational amplifier OP through the
capacitor C1 and the input voltage of the operational amplifier OP
changes, the voltage is fed back from the capacitor C2-1, such that
the input voltage becomes the zero voltage. As a result, the output
voltage Vout2 of the signal level that is inverted and amplified
with the amplification factor A2 is output from the operational
amplifier OP and is applied to the inverting input terminal of the
comparator PA through the capacitor C3.
[0217] With the output voltage Vout2 of the reference level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the reference level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to the up-down counter UD.
[0218] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the signal level of the
amplification factor A2 is matched with the level of the reference
voltage VREF, the up-down counter UD executes the up-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the difference between the output voltage
Vout2 of the signal level of the amplification factor A2 and the
output voltage Vout2 of the reference level is converted into a
digital value D and is transmitted to the line memory LM12. As a
result, in the line memory LM12, the difference between the second
signal level and the second reference level that are sampled from
the signal amplified with the amplification factor A2 is stored as
the signal component of the amplification factor A2 detected by the
CDS. If the signal component of the amplification factor A2
detected by the CDS is held in the line memory LM12, the up-down
counter UD is reset.
[0219] Next, if the level of the switching signal SET-A changes to
a low level, the switching signal SET-A is inverted by the inverter
V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor of the
column amplifying circuit 3a is set to A1.
[0220] With the output voltage Vout2 of the signal level of the
amplification factor A1 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the signal level of
the amplification factor A1 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to the up-down counter UD.
[0221] The high level of the output voltage Vout4 is maintained
until the level of the output voltage Vout2 of the signal level of
the amplification factor A1 is matched with the level of the
reference voltage VREF, the up-down counter UD executes the
up-counting operation until the level of the output voltage Vout4
is inverted into a low level, and the output voltage Vout2 of the
signal level of the amplification factor A1 is converted into a
digital value D and is transmitted to the line memory LM11. As a
result, in the line memory LM11, the analog CDS processed
difference between the first signal level and the first reference
level stored in the capacitors C1 and C3 is stored.
[0222] In this case, even when the first reference level and the
first signal level of the amplification factor A1 of the signal
read from the pixel PCn are sampled and the second reference level
and the second signal level of the amplification factor A2 of the
signal read from the pixel PCn are sampled and the amplification
factor of the signal read from the pixel PCn is switched, the
reference level according to the amplification factor can be
cancelled and an effect of suppressing noise based on the CDS can
be improved.
[0223] By stopping the count operation by the up-down counter UD
when sampling the first reference level, the number of up-down
counters UD can be reduced and a circuit scale can be reduced.
[0224] In the seventh embodiment, since the black level of the
signal component of the amplification factor A1 and the black level
of the signal component of the amplification factor A2 are matched
with each other, the black level is preferably adjusted by the
subtractor 13 of FIG. 7.
[0225] When the signal level is low (amplification factor=A2), an
output of the comparator PA is changed due to the change of the
threshold value Vth of the comparator PA disposed for each vertical
signal line Vlin or the coupling change when turning off the switch
transistor Tcp. For this reason, vertical stripe noise is
generated.
[0226] In order to suppress the vertical stripe noise from being
generated, if the reference level is obtained by down-counting and
the signal level is obtained by up-counting, the vertical stripe
noise can be cancelled. At this time, the black level becomes 0.
This processing is called a digital CDS operation, because the
noise (change) of the reference level is stored by the up-down
counter UD in a digital manner and the noise is suppressed.
[0227] Meanwhile, when the signal level is high (amplification
factor=A1), the reference level is held in the capacitors C1 and
C3. In the reference level, the reset noise of when the floating
diffusion FD is reset or the change of the output of the column
amplifying circuit 3a is included. At this time, the reference
level of the reference voltage VREF can be set to become 64
levels.
[0228] Next, if the signal charges are read from the photodiode PD,
the charges are converted into a voltage by the floating diffusion
FD and the signal level changes. The output signal Vout2 of the
column amplifying circuit 3a also changes in the same way. The
change amount is A/D converted as the signal level. As a result,
only a signal component where the noise of the reference level is
suppressed can be obtained. This processing is called an analog CDS
operation, because the noise (change) of the reference level is
stored in the capacitors C1 and C3 in an analog manner and the
noise is suppressed. During this operation, the black level becomes
64 levels.
[0229] When the signal level is high (amplification factor=A1), the
noise is not displayed in an image, even though the noise is
slightly increased. Therefore, when the signal level is high, by
executing only the analog CDS operation, an operation time of the
A/D conversion can be reduced, and a high-speed operation can be
realized.
[0230] When the signal level is high, the analog CDS operation is
executed and when the signal level is low, the digital CDS
operation is executed. In this case, in order to match the black
levels of the output signals Vout6 and Vout7, by setting the black
level SB of FIG. 7 to 64 levels, the 64 levels can be subtracted
from the output signal Vout6.
Eighth Embodiment
[0231] FIG. 14 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to an eighth
embodiment.
[0232] In FIG. 14, the solid-state imaging device includes a sample
and hold signal converting circuit 4d, instead of the sample and
hold signal converting circuit 4b of FIG. 10.
[0233] In this case, in the sample and hold signal converting
circuit 4d, instead of the switch SW1, the up-down counters UD1 and
UD2, and the line memories LM1 and LM2 of FIG. 10, an up-down
counter UD and line memories LM11 and LM12 are provided.
[0234] FIG. 15 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 14.
[0235] In FIG. 15, when the level of the switching signal SET-A is
set to a low level, the switch SWsf2 is switched to the L side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a high level, and the switch SWsf1 is switched to
the H side. When the level of the switching signal SET-A is set to
a low level, the switch SW2 is switched to the L side.
[0236] If the level of the row selection signal ADRESn becomes a
high level, the row selection transistor Ta of the pixel PC is
turned on, the power supply potential VDD is applied to the drain
of the amplification transistor Tb, and a source follower is
configured by the amplification transistor Tb and the constant
current transistor TL.
[0237] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta being turned on, the reset
transistor Tc is turned on and a voltage according to the reference
level of the floating diffusion FD is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the reference level to the vertical signal line Vlin.
[0238] If the output voltage Vout1 of the reference level is
applied to the source of the amplification transistor Tf1 with the
switch SWsf1 being switched to the H side, the output voltage Vout2
of the reference level of the amplification factor A1 is output
from the drain of the amplification transistor Tf1.
[0239] When the signal of the reference level is output to the
vertical signal line Vlin, if the reset pulse Pcp' is input to the
gate of the switch transistor Tcp11, the output voltage Vout4 of
the comparator PA3 is held in the capacitor C31 and is applied to
the gate of the amplification transistor Tf1, and a bias voltage is
applied.
[0240] If the switch transistor Tcp11 is turned off, the output
voltage Vout4 of the comparator PA3 is held as the first reference
level of the signal amplified with the amplification factor A1 in
the capacitor C31. In this case, when the output voltage Vout2 of
the reference level of the amplification factor A1 is output, the
reference voltage VREF is maintained to have a constant value. The
up-down counter UD is reset.
[0241] Next, if the level of the switching signal SET-A changes to
a high level, the switch SWsf2 is switched to the H side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a low level, and the switch SWsf1 is switched to
the L side. When the level of the switching signal SET-A changes to
a high level, the switch SW2 is switched to the H side.
[0242] If the output voltage Vout1 of the reference level is
applied to the source of the amplification transistor Tf2 with the
switch SWsf2 being switched to the H side, the output voltage Vout3
of the reference level of the amplification factor A2 is output
from the drain of the amplification transistor Tf2.
[0243] When the signal of the reference level is output to the
vertical signal line Vlin, if the reset pulse Pcp2 is input to the
gate of the switch transistor Tcp12, the output voltage Vout4 of
the comparator PA3 is held in the capacitor C32 and is applied to
the gate of the amplification transistor Tf2, and a bias voltage is
applied.
[0244] With the output voltage Vout3 of the reference level of the
amplification factor A2 being input to the comparator PA3 through
the switch SW2, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout3 of the reference level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. The high level of the output voltage
Vout4 is maintained until the output voltage Vout3 of the reference
level of the amplification factor A2 is matched with the level of
the reference voltage VREF, the up-down counter UD executes the
down-counting operation until the level of the output voltage Vout4
is inverted into a low level, and the output voltage Vout3 of the
reference level of the amplification factor A2 is converted into a
digital value D and is held as the second reference level of the
signal amplified with the amplification factor A2 in the up-down
counter UD.
[0245] Next, if the level of the read signal READn becomes a high
level with the row selection transistor Ta of the pixel PCn being
turned on, the read transistor Td is turned on and the charges that
are accumulated in the photodiode PD are transmitted to the
floating diffusion FD. In addition, a voltage according to the
signal level of the floating diffusion FD is applied to the gate of
the amplification transistor Tb and is output as the output voltage
Vout1 of the signal level to the vertical signal line Vlin.
[0246] If the output voltage Vout1 of the signal level is applied
to the source of the amplification transistor Tf2, the output
voltage Vout3 of the signal level of the amplification factor A2 is
output from the drain of the amplification transistor Tf2.
[0247] Then, with the output voltage Vout3 of the signal level of
the amplification factor A2 being input to the comparator PA
through the switch SW2, a triangular wave is applied as the
reference voltage VREF and the output voltage Vout3 of the
reference level of the amplification factor A2 and the reference
voltage VREF are compared with each other. The high level of the
output voltage Vout4 is maintained until the level of the output
voltage Vout3 of the signal level of the amplification factor A2 is
matched with the level of the reference voltage VREF, the up-down
counter UD executes the up-counting operation until the level of
the output voltage Vout4 is inverted into a low level, and the
difference between the output voltage Vout3 of the signal level of
the amplification factor A2 and the output voltage Vout3 of the
reference level is converted into a digital value D and is
transmitted to the line memory LM12. As a result, in the line
memory LM12, the difference between the second signal level and the
second reference level that are sampled from the signal amplified
with the amplification factor A2 is held as the signal component of
the amplification factor A2 detected by the CDS. If the signal
component of the amplification factor A2 detected by the CDS is
held in the line memory LM12, the up-down counter UD is reset.
[0248] Next, if the level of the switching signal SET-A changes to
a low level, the switch SWsf2 is switched to the L side, the
switching signal SET-A is inverted by the inverter V3 and the level
thereof becomes a high level, and the switch SWsf1 is switched to
the H side. If the level of the switching signal SET-A changes to a
low level, the switch SW2 is switched to the L side.
[0249] Then, with the output voltage Vout2 of the signal level of
the amplification factor A1 being input to the comparator PA
through the switch SW2, a triangular wave is applied as the
reference voltage VREF and the output voltage Vout2 of the signal
level of the amplification factor A1 and the reference voltage VREF
are compared with each other. The high level of the output voltage
Vout4 is maintained until the level of the output voltage Vout2 of
the signal level of the amplification factor A1 is matched with the
level of the reference voltage VREF, the up-down counter UD
executes the up-counting operation until the level of the output
voltage Vout4 is inverted into a low level, and the output voltage
Vout2 of the signal level of the amplification factor A1 is
converted into a digital value D and is transmitted to the line
memory LM11. As a result, in the line memory LM11, the analog CDS
processed difference between the first signal level and the first
reference level stored in the capacitors C1 and C3 is held.
[0250] In this case, even when the first reference level and the
first signal level of the amplification factor A1 of the signal
read from the pixel PCn are sampled and the second reference level
and the second signal level of the amplification factor A2 of the
signal read from the pixel PCn are sampled and the amplification
factor of the signal read from the pixel PCn is switched, the
reference level according to the amplification factor can be
cancelled and an effect of suppressing noise based on the CDS can
be improved.
[0251] By stopping the count operation by the up-down counter UD
when sampling the first reference level, the number of up-down
counters UD can be reduced and a circuit scale can be reduced.
[0252] In the eighth embodiment, since the black level of the
signal component of the amplification factor A1 and the black level
of the signal component of the amplification factor A2 are matched
with each other, the black level is preferably adjusted by the
subtractor 13 of FIG. 7.
Ninth Embodiment
[0253] FIG. 16 is a block diagram of a schematic configuration of a
solid-state imaging device according to a ninth embodiment.
[0254] In FIG. 16, the solid-state imaging device includes a sample
and hold signal converting circuit 31, instead of the sample and
hold signal converting circuit 4 of FIG. 7. Further, the
solid-state imaging device includes a multiplier 35 and a switch
36, instead of the multiplier 10, the comparator 11, the switch 12,
and the subtractor 13 of FIG. 7.
[0255] After the sample and hold signal converting circuit 31
samples the first reference level from the signal amplified with
the amplification factor A1 and samples the second reference level
from the signal amplified with the amplification factor A2, the
sample and hold signal converting circuit 31 samples the signal
level from the signal amplified with the amplification factors A1
and A2, on the basis of the signal level of the signal read from
each pixel PCn, and can detect the signal component of each pixel
PC by the CDS.
[0256] In this case, the sample and hold signal converting circuit
31 includes a column ADC circuit 32 that executes the up-counting
operation and the down-counting operation on the basis of the
comparison result of the read signal from the pixel PC amplified
with the amplification factors A1 and A2 and the reference voltage
VREF and calculates the difference between the reference level and
the signal level of the CDS, a line memory 33 that stores a count
value of the column ADC circuit 32 with respect to the signal
amplified with the amplification factors A1 and A2 by the amount of
horizontal pixels, and a gain selecting unit 34 that selects one of
the amplification factors A1 and A2 to amplify the signal read from
each pixel PC.
[0257] The multiplier 35 can multiply the output signal Vout11 from
the sample and hold signal converting circuit 31 with the
amplification factor A2. The switch 36 can switch the output signal
Vout8 to the L side or the H side, on the basis of the selection
result obtained by the gain selecting unit 34.
[0258] If the pixels PC are scanned in a vertical direction by the
row scanning circuit 2, the pixels PC of the row direction are
selected and the signals that are read from the pixels PC are
transmitted to the column amplifying circuit 3 through the vertical
signal line Vlin. After the signals read from the pixels PC are
amplified with the amplification factors A1 and A2 by the column
amplifying circuit 3, the signals are transmitted to the sample and
hold signal converting circuit 31.
[0259] In the sample and hold signal converting circuit 31, the
first reference level is sampled from the signal of each pixel PC
amplified with the amplification factor A1 and the second reference
level is sampled from the signal of each pixel PC amplified with
the amplification factor A2. On the basis of the signal level of
the signal read from each pixel PC, it is determined whether the
amplification factor of the signal level is the amplification
factor A1 or the amplification factor A2. On the determination
result, the difference between the first signal level and the first
reference level or the difference between the second signal level
and the second reference level is taken and are output as the
output signal Vout11.
[0260] In this case, in the column ADC circuit 32, the
down-counting operation is executed until the first reference level
sampled from the signal of each pixel PC amplified with the
amplification factor A1 is matched with the level of the reference
voltage VREF, and the count value with respect to the first
reference level is held. In the column ADC circuit 32, the
down-counting operation is executed until the second signal level
sampled from the signal of each pixel PC amplified with the
amplification factor A2 is matched with the level of the reference
voltage VREF, and the count value with respect to the second
reference level is held.
[0261] When A1 is selected as the amplification factor of the
signal level of the signal read from each pixel PC, the up-counting
operation is executed with respect to the count value of the first
reference level until the first signal level sampled from the
signal of each pixel PC amplified with the amplification factor A1
is matched with the level of the reference voltage VREF, and the
signal component of the amplification factor A1 that is detected by
the CDS is converted into a digital value and is held in the line
memory 33 by the amount of horizontal pixels.
[0262] Meanwhile, when A2 is selected as the amplification factor
of the signal level of the signal read from each pixel PC, the
up-counting operation is executed with respect to the count value
of the second reference level until the second signal level sampled
from the signal of each pixel PC amplified with the amplification
factor A2 is matched with the level of the reference voltage VREF,
and the signal component of the amplification factor A2 that is
detected by the CDS is converted into the digital value and is held
in the line memory 33 by the amount of horizontal pixels.
[0263] When A2 is selected as the amplification factor of the
signal level of the signal read from each pixel PC, the switch 36
is switched to the H side and the output signal Vout11 is output as
the output signal Vout8.
[0264] Meanwhile, when A1 is selected as the amplification factor
of the signal level of the signal read from each pixel PC, the
switch 36 is switched to the L side. The multiplier 35 multiplies
the output signal Vout1 from the sample and hold signal converting
circuit 31 with the amplification factor A2, the a signal component
of the output signal Vout11 that is amplified with the
amplification factor A1 becomes linear with respect to the amount
of light, and the output signal Vout11 that is multiplied with the
amplification factor A2 is output as the output signal Vout8.
[0265] In this case, by sampling the reference level by the sample
and hold signal converting circuit 31 for each of the amplification
factors A1 and A2, even when the amplification factors A1 and A2
are switched, the noise can be effectively suppressed by the
CDS.
[0266] By sampling the signal level from the signal amplified with
the amplification factor A1 and the amplification factor A2 on the
basis of the signal level of the signal read from each pixel PC,
the signal level does not need to be held simultaneously for each
of the amplification factors A1 and A2, and the line memory 33 does
not need to be provided individually for each of the amplification
factors A1 and A2. Therefore a circuit scale can be suppressed from
increasing.
Tenth Embodiment
[0267] FIG. 17 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a tenth
embodiment.
[0268] In FIG. 17, the solid-state imaging device includes a sample
and hold signal converting circuit 31a and a flip-flop F1, instead
of the sample and hold signal converting circuit 4a of FIG. 8.
[0269] In this case, in the sample and hold signal converting
circuit 31a, a comparator PA, a switch transistor Tcp, an inverter
V, switches SW11, SW12, and SW15, up-down counters UD11 and UD12, a
line memory LM21, a gain selecting unit SE1, and an AND circuit N11
are provided for each column. The bit number of the up-down
counters UD11 and UD12 may be smaller than the bit number of the
up-down counters UD1 and UD2 of FIG. 8. For example, if the up-down
counters UD1 and UD2 of FIG. 8 need the bit number of 10 bits, the
bit number of the up-down counters UD11 and UD12 may be set to 5
bits. If the bit number of the up-down counters UD11 and UD12 is
set to 5 bits, the change of the reference level until a maximum of
32 levels can be cancelled. When the change of the reference level
is large, if the bit number of the up-down counters UD11 and UD12
is set to 7 bits, the change of the reference level until a maximum
of 128 levels can be cancelled.
[0270] In the sample and hold signal converting circuit 31a, a
counter coupling unit 61 that couples the up-down counters UD11 and
UD12 and a reset circuit 62 that resets the up-down counters UD11
and UD12 are provided.
[0271] In the counter coupling unit 61, OR circuits N12 and N13 and
switches SW13 and SW14 are provided. In the reset circuit 62, AND
circuits N14 and N15 and OR circuits N16 and N17 are provided.
[0272] An one input terminal of the AND circuit N11 is connected to
an output terminal of the inverter V and a reference clock CKC is
input to the other input terminal of the AND circuit N11. The H
side of the switch SW11 is connected to the ground and the L side
of the switch SW11 is connected to an output terminal of the AND
circuit N11. The H side of the switch SW12 is connected to an
output terminal of the AND circuit N11 and the L side of the switch
SW12 is connected to the ground. The switches SW11 and SW12 are
switched by a switching signal SET-A.
[0273] One input terminal of the OR circuit N12 is connected to an
output terminal Q of a flip-flop F1 and a switching signal SET-PG
is input to the other input terminal of the OR circuit N12. One
input terminal of the OR circuit N13 is connected to an inverting
output terminal NQ of the flip-flop F1 and the switching signal
SET-PG is input to the other input terminal of the OR circuit
N13.
[0274] The L side of the switch SW13 is connected to an output
terminal of the switch SW11 and the H side of the switch SW13 is
connected to an output terminal of the up-down counter UD12. The H
side of the switch SW14 is connected to an output terminal of the
switch SW12 and the L side of the switch SW14 is connected to an
output terminal of the up-down counter UD11. An output terminal of
the switch SW13 is connected to an input terminal of the up-down
counter UD11 and an output terminal of the switch SW14 is connected
to an input terminal of the up-down counter UD12. The switch SW13
is switched by an output of the OR circuit N13 and the switch SW14
is switched by an output of the OR circuit N12.
[0275] A reset pulse R-BC is input to one input terminal of the AND
circuit N14 and the other input terminal of the AND circuit N14 is
connected to an inverting output terminal NQ of the flip-flop F1.
The reset pulse R-BC is input to one input terminal of the AND
circuit N15 and the other input terminal of the AND circuit N14 is
connected to an output terminal Q of the flip-flop F1.
[0276] One input terminal of the OR circuit N16 is connected to an
output terminal of the AND circuit N14 and a reset pulse AR-C is
input to the other input terminal of the AND circuit N16. One input
terminal of the OR circuit N17 is connected to an output terminal
of the AND circuit 15 and the reset pulse AR-C is input to the
other input terminal of the OR circuit N17. An output terminal of
the OR circuit N16 is connected to a reset terminal of the up-down
counter UD12 and an output terminal of the OR circuit N17 is
connected to a reset terminal of the up-down counter UD11.
[0277] The H side of the switch SW15 is connected to the output
terminal of the up-down counter UD11 and the L side of the switch
SW15 is connected to an output terminal of the up-down counter
UD12. The switch SW15 is switched by an output from the output
terminal Q of the flip-flop F1.
[0278] The gain selecting unit SE1 is connected to the output
terminal Q of the flip-flop F1. An input terminal D of the
flip-flop F1 is connected to the output terminal of the inverter V,
a reset signal R-FF is input to the reset terminal R of the
flip-flop F1, and a set pulse SET-G is input to a set terminal of
the flip-flop F1.
[0279] FIG. 18 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 17.
[0280] In FIG. 18, when a level of the switching signal SET-A is
set to a low level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor of the
column amplifying circuit 3a is set to A1.
[0281] If the level of the row selection signal ADRESn becomes a
high level, the row selection transistor Ta of the pixel PCn is
turned on, the power supply potential VDD is applied to the rain of
the amplification transistor Tb, and a source follower is
configured by the amplification transistor Tb and the constant
current transistor TL.
[0282] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta is turned on, the reset
transistor Tc being turned on and a voltage according to the
reference level of the floating diffusion FD is applied to the gate
of the amplification transistor Tb and is output as the output
voltage Vout1 of the reference level to the vertical signal line
Vlin.
[0283] In this case, if the level of the switching signal SET-A
changes to a high level with the reset pulses Psc and Pcp being
applied, the switch transistor Tsc2-1 is turned off and the
amplification factor of the column amplifying circuit 3a is set to
A2.
[0284] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if the reset pulse Psc is
applied to the gate of the switch transistor Tsc1-1, the input
voltage of the operational amplifier OP is clamped with the output
voltage and an operation point is set. At this time, the voltage
difference with respect to the vertical signal line Vlin is held in
the capacitor C1 and the input voltage of the operational amplifier
OP is set to zero.
[0285] When the output voltage Vout1 of the reference level is
output to the vertical signal line Vlin, if the reset pulse Pcp is
applied to the gate of the switch transistor Tcp, the input voltage
of the inverting input terminal of the comparator PA is clamped
with the output voltage and an operation point is set. At this
time, the voltage difference with respect to the output voltage
Vout2 from the operational amplifier OP is held in the capacitor C3
and the input voltage of the comparator PA is set to zero.
[0286] If the reset pulses AR-C are input to the reset terminals of
the up-down counters UD11 and UD12 through the OR circuits N15 and
N14, respectively, the up-down counters UD11 and UD12 are
reset.
[0287] Next, if the level of the switching signal SET-A changes to
a low level, the switching signal SET-A is inverted by the inverter
V and the level thereof becomes a high level. The switch transistor
Tsc2-1 is turned on and the amplification factor of the column
amplifying circuit 3a is set to A1.
[0288] If the level of the switching signal SET-A changes to a low
level, the switches SW11 and SW12 are switched to the L side. A
level of the switching signal SET-PG is set to a high level and the
switches SW13 and SW14 are switched to the H side. As a result, an
output terminal of the AND circuit N11 is connected to an input
terminal of the up-down counter UD11 though the switches SW11 and
SW13. At this time, the level of the reset signal R-FF is set to a
high level and the potential level of the output terminal Q of the
flip-flop F1 becomes a low level.
[0289] With the output voltage Vout2 of the reference level of the
amplification factor A1 being input to the comparator PA through
the capacitor C3 after the switch transistor Tcp is turned off, a
triangular wave is applied as the reference voltage VREF and the
output voltage Vout2 of the reference level of the amplification
factor A1 and the reference voltage VREF1 are compared with each
other. After the output voltage of the comparator PA is inverted by
the inverter V, the output voltage is input as the output voltage
Vout4 to one input terminal of the AND circuit N11, the reference
clock CKC passes through the AND circuit N11, and a reference clock
CKCi after the passage is down-counted by the up-down counter
UD11.
[0290] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the reference level of the
amplification factor A1 is matched with the level of the reference
voltage VREF, the up-down counter UD11 executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the reference
level of the amplification factor A1 is converted into a digital
value D and is held as the first level of the signal amplified with
the amplification factor A1 in the up-down counter UD11.
[0291] Next, if the level of the switching signal SET-A changes to
a high level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a low level. The switch
transistor Tsc2-1 is turned off and the amplification factor of the
column amplifying circuit 3a is set to A2.
[0292] If the level of the switching signal SET-A changes to a high
level, the switches SW11 and SW12 are switched to the H side. A
level of the switching signal SET-PG is set to a high level and the
switches SW13 and SW14 are switched to the H side. As a result, an
output terminal of the AND circuit N11 is connected to an input
terminal of the up-down counter UD12 though the switches SW12 and
SW14.
[0293] With the output voltage Vout2 of the reference level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the reference level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to one input terminal of the AND
circuit N11, the reference clock CKC passes through the AND circuit
N11, and a reference clock CKCi after the passage is down-counted
by the up-down counter UD12.
[0294] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the reference level of the
amplification factor A2 is matched with the level of the reference
voltage VREF, the up-down counter UD12 executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the reference
level of the amplification factor A2 is converted into a digital
value D and is held as the second reference level of the signal
amplified with the amplification factor A2 in the up-down counter
UD12.
[0295] Next, if the level of the read signal READn becomes a high
level with the row selection transistor Ta of the pixel PCn being
turned on, the read transistor Td is turned on and the charges that
are accumulated in the photodiode PD are transmitted to the
floating diffusion FD. In addition, a voltage according to the
signal level of the floating diffusion FD is applied to the gate of
the amplification transistor Tb and is output as the output voltage
Vout1 of the signal level to the vertical signal line Vlin.
[0296] If the output voltage Vout1 of the signal level is applied
to the input terminal of the operational amplifier OP through the
capacitor C1 and the input voltage of the operational amplifier OP
changes, the voltage is fed back from the capacitor C2-1, such that
the input voltage becomes the zero voltage. As a result, the output
voltage Vout2 of the signal level that is inverted and amplified
with the amplification factor A2 is output from the operational
amplifier OP and is applied to the inverting input terminal of the
comparator PA through the capacitor C3.
[0297] The level of the reference voltage VREF is set to a level
slightly lower than a saturation level of the A/D conversion (for
example, 1023 in the case of 10 bits). In order to change the level
of the reference voltage VREF to the above level at a high speed, a
different power supply that sets the level of the reference voltage
VREF to the above level may be provided in the column ADC circuit
32 of FIG. 16.
[0298] After the level of the reset signal R-FF changes to a low
level, if the set pulse SET-G is applied to a set terminal of the
flip-flop F1, the output voltage Vout4 is input to the flip-flop
F1.
[0299] In this case, since the level of the reference voltage VREF
is set to a level slightly lower than the saturation level of the
A/D conversion, if the output voltage Vout2 of the signal level of
the amplification factor A2 is saturated, the level of the output
voltage Vout3 becomes a low level and a logical value `0` is input
to the flip-flop F1. Meanwhile, if the output voltage Vout2 of the
signal level of the amplification factor A2 is not saturated, the
level of the output voltage Vout4 becomes a high level and a
logical value `1` is input to the flip-flop F1.
[0300] When the logical value `0` is input to the flip-flop F1, the
output voltage Vout2 of the signal level of the amplification
factor A2 is saturated. Therefore, it can be assumed that the
signal level is high and the amplification factor of the signal
level can be determined as A1. When the logical value `1` is input
to the flip-flop F1, the output voltage Vout2 of the signal level
of the amplification factor A2 is not saturated. Therefore, it can
be assumed that the signal level is low and the amplification
factor of the signal level can be determined as A2.
[0301] Next, if the reset pulse R-BC is input to one input terminal
of the AND circuit N14 and one input terminal of the AND circuit
N15, any one of the up-down counters UD1 and UD2 is reset.
[0302] Hereinafter, each of the case which the logical value `1` is
input to the flip-flop F1 and the case which the logical value `0`
is input to the flip-flop F1 will be described.
(Case in which the Logical Value `1` is Input to the Flip-Flop
F1)
[0303] Since the potential level of the output terminal Q of the
flip-flop F1 becomes a high level, the reset pulse R-BC is applied
to the reset terminal of the up-down counter UD1 through the AND
circuit N15 and a count value that is held in the up-down counter
UD1 and corresponds to the first reference level of the
amplification factor A1 is deleted.
[0304] Next, if the level of the switching signal SET-PG changes to
a low level, the switch SW13 is switched by the OR circuit N13 and
the switch SW14 is switched by the OR circuit N12. As a result, the
up-down counter UD11 is coupled to the rear stage of the up-down
counter UD12 and the output terminal of the AND circuit N11 is
connected to the input terminal of the up-down counter UD12 through
the switches SW12 and SW14. When the potential level of the output
terminal Q of the flip-flop F1 is a high level, the switch SW15 is
switched to the H side and the output terminal of the up-down
counter UD11 is connected to the line memory LM21.
[0305] With the output voltage Vout2 of the signal level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the signal level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to one input terminal to one
input terminal of the AND circuit N11, the reference clock CKC
passes through the AND circuit N11, and a reference clock CKCi
after the passage is up-counted by the up-down counters UD11 and
UD12.
[0306] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the signal level of the
amplification factor A2 is matched with the level of the reference
voltage VREF, the up-counters UD11 and UD12 execute the
down-counting operation until the level of the output voltage Vout4
is inverted into a low level, and the difference between the output
voltage Vout2 of the signal level of the amplification factor A2
and the output voltage Vout2 of the reference level is converted
into a digital value D and is transmitted to the line memory LM21
through the switch SW15. As a result, in the line memory LM21, the
difference between the second signal level and the second reference
level that are sampled from the signal amplified with the
amplification factor A2 is held as the signal component of the
amplification factor A2 detected by the CDS.
[0307] When the potential level of the output terminal Q of the
flip-flop F1 is a high level, a value of a gain selection signal
GSEL is set to `H` by the gain selecting unit 34 of FIG. 16. If the
value of the gain selection signal GSEL is set to `H`, the switch
36 is switched to the H side and the output signal Vout11 is output
as the output signal Vout8.
[0308] Next, if the level of the switching signal SET-A changes to
a low level, the switches SW11 and SW12 are switched to the L side.
However, since the switch SW13 is set to the L side, the output
terminal of the AND circuit N11 is not connected to the input
terminals of the up-down counters UD11 and UD12 and the up-down
counters UD11 and UD12 do not operate.
(Case in which the Logical Value `0` is Input to the Flip-Flop
F1)
[0309] Since the potential level of the inverting output terminal
NQ of the flip-flop F1 becomes a high level, the reset pulse R-BC
is applied to the reset terminal of the up-down counter UD2 through
the AND circuit N14 and a count value that is held in the up-down
counter UD2 and corresponds to the second reference level of the
amplification factor A2 is deleted.
[0310] At this time, since the level of the switching signal SET-A
is set to a high level, the switches SW11 and SW12 are switched to
the H side. However, since the switch SW14 is set to the L side,
the output terminal of the AND circuit N11 is not connected to the
input terminals of the up-down counters UD11 and UD12 and the
up-down counters UD11 and UD12 do not operate.
[0311] Next, if the level of the switching signal SET-A changes to
a low level, the switching signal SET-A is inverted by the inverter
V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor of the
column amplifying circuit 3a is set to A1.
[0312] If the level of the switching signal SET-A changes to a low
level, the switches SW11 and SW12 are switched to the L side. Since
the level of the switching signal SET-PG is set to a low level, if
the potential level of the inverting output terminal NQ of the
flip-flop F1 becomes a high level, the switch SW13 is switched to
the H side by the OR circuit N13 and the switch SW14 is switched to
the L side by the OR circuit N12. As a result, the up-down counter
UD12 is coupled to the rear stage of the up-down counter UD11 and
the output terminal of the AND circuit N11 is connected to the
input terminal of the up-down counter UD11 through the switches
SW11 and SW13. When the potential level of the inverting output
terminal NQ of the flip-flop F1 is a high level, the switch SW15 is
switched to the L side and the output terminal of the up-down
counter UD12 is connected to the line memory LM21.
[0313] With the output voltage Vout2 of the signal level of the
amplification factor A1 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the signal level of
the amplification factor A1 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to one input terminal of the AND
circuit N11, the reference clock CKC passes through the AND circuit
N11, and a reference clock CKCi after the passage is up-counted by
the up-down counters UD11 and UD12.
[0314] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the signal level of the
amplification factor A1 is matched with the level of the reference
voltage VREF, the up-counters UD11 and UD12 execute the up-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the difference between the output voltage
Vout2 of the signal level of the amplification factor A1 and the
output voltage Vout2 of the reference level is converted into a
digital value D and is transmitted to the line memory LM21 through
the switch SW15. As a result, in the line memory LM21, the
difference between the first signal level and the first reference
level that are sampled from the signal amplified with the
amplification factor A1 is held as the signal component of the
amplification factor A1 detected by the CDS.
[0315] When the potential level of the output terminal Q of the
flip-flop F1 is a low level, a value of a gain selection signal
GSEL is set to `L` by the gain selecting unit 34 of FIG. 16. If the
value of the gain selection signal GSEL is set to `L`, the switch
36 is switched to the H side and the output signal Vout11 that is
amplified with the amplification factor A2 is output as the output
signal Vout8.
[0316] In this case, even when the first reference level and the
second reference level are sampled before the amplification factors
A1 and A2 of the signals read from the pixels PCn are switched and
the first signal level and the second signal level are sampled
after the amplification factors A1 and A2 of the signals read from
the pixels PCn are switched and the amplification factors A1 and A2
of the signals read from the pixels PCn are switched, the reference
levels according to the amplification factors A1 and A2 can be
cancelled and an effect of suppressing noise based on the CDS can
be improved. Since the line memory LM21 does not need to be
provided individually for each of the amplification factors A1 and
A2, a circuit scale can be reduced.
Eleventh Embodiment
[0317] FIG. 19 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to an eleventh
embodiment.
[0318] In FIG. 19, in the solid-state imaging device, the sample
and hold signal converting circuit 31a of FIG. 17 is connected to
the rear stage of the column amplifying circuit 3b of FIG. 10.
[0319] FIG. 20 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 19.
[0320] In FIG. 20, the operations of FIGS. 11 and 18 are combined,
and the switched capacitor type amplifying circuit is not used and
a differential amplifying circuit is used as the column amplifying
circuit 3b.
Twelfth Embodiment
[0321] FIG. 21 is a block diagram of a schematic configuration of a
solid-state imaging device according to a twelfth embodiment.
[0322] In FIG. 21, the solid-state imaging device includes a sample
and hold signal converting circuit 41, instead of the sample and
hold signal converting circuit 31 of FIG. 16. The solid-state
imaging device includes a subtractor 43 that adjusts a black level
with respect to a signal component of each pixel PCn and a switch
44 that supplies a black level SB to the subtractor 43, on the
basis of a gain selection signal GSEL.
[0323] The sample and hold signal converting circuit 41 samples a
first reference level from a signal amplified with the
amplification factor A1, samples a second reference level from a
signal amplified with the amplification factor A2, and samples a
signal level from a signal amplified with the amplification factor
A1 or A2 on the basis of the signal level of the signal read from
each pixel PC, and can detects a signal component of each pixel PC
by the CDS. In this case, a signal component of the signal that is
amplified with the amplification factor A1 can be detected by the
analog CDS and a signal component of the signal that is amplified
with the amplification factor A2 can be detected by the digital
CDS.
[0324] In the sample and hold signal converting circuit 41, a
column ADC circuit 42 is provided. The column ADC circuit 42 can
execute the up-counting operation on the basis of the comparison
result of the signal of the signal level amplified with the
amplification factor A1 and read from the pixel PC and the
reference voltage VREF and calculate the difference between the
reference level and the signal level of the analog CDS. The column
ADC circuit 42 can execute the up-counting operation and the
down-counting operation on the basis of the comparison result of
the signal of the signal level amplified with the amplification
factor A2 and read from the pixel PC and the reference voltage VREF
and calculate the difference between the reference level and the
signal level of the digital CDS.
[0325] When A1 is selected as the amplification factor of the
signal level of the signal read from each pixel PC, the switches 36
and 44 are switched to the L side. In the sample and hold signal
converting circuit 41, the signal component is detected from the
signal read from each pixel PC by the analog CDS and is output as
the output voltage Vout11. The subtractor 43 subtracts the black
level SB from the output signal, the multiplier 35 multiplies the
output signal with the amplification factor A2, and the output
signal is output as the output signal Vout8.
[0326] Meanwhile, when A2 is selected as the amplification factor
of the signal level of the signal read from each pixel PC, the
switches 36 and 44 are switched to the H side. In the sample and
hold signal converting circuit 41, the signal component is detected
from the signal read from each pixel PC by the digital CDS and the
output signal Vout11 is output as the output signal Vout8.
[0327] In this case, even when the first reference level and the
second reference level are sampled before the amplification factors
A1 and A2 of the signals read from the pixels PCn are switched and
the first signal level and the second signal level are sampled
after the amplification factors A1 and A2 of the signals read from
the pixels PCn are switched and the amplification factors A1 and A2
of the signals read from the pixels PCn are switched, the reference
levels according to the amplification factors A1 and A2 can be
cancelled and an effect of suppressing noise based on the CDS can
be improved. Since the line memory 33 does not need to be provided
individually for each of the amplification factors A1 and A2, a
circuit scale can be reduced.
[0328] The signal component of the signal that is amplified with
the amplification factor A1 is detected by the analog CDS and the
signal component of the signal that is amplified with the
amplification factor A2 is detected by the digital CDS, and the
up-down counter does not need to be provided individually for each
of the amplification factors A1 and A2. Therefore, a circuit scale
can be reduced.
Thirteenth Embodiment
[0329] FIG. 22 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a
thirteenth embodiment.
[0330] In FIG. 22, the solid-state imaging device includes a sample
and hold signal converting circuit 41a and a flip-flop F2, instead
of the sample and hold signal converting circuit 31a and the
flip-flop F1 of FIG. 17.
[0331] In this case, in the sample and hold signal converting
circuit 41a, a comparator PA, a switch transistor Tcp, an inverter
V, an up-down counter UD21, a line memory LM21, a gain selecting
unit SE1, AND circuits N11 and N25, and an OR circuit N26 are
provided for each column.
[0332] In the sample and hold signal converting circuit 41a, a
counter input intercepting circuit 63 that intercepts an input of
the up-down counter UD21 on the basis of a value held in the
flip-flop F2 is provided. In the counter input intercepting circuit
63, an inverter V11, AND circuits N21, N22, and N24, and an OR
circuit N23 are provided.
[0333] One input terminal of the AND circuit N22 is connected to an
output terminal Q of the flip-flop F2 and a switching signal SET-A
is input to the other input terminal of the AND circuit N22 through
the inverter V11. One input terminal of the AND circuit N21 is
connected to an inverting output terminal NQ of the flip-flop F2
and the switching signal SET-A is input to the other input terminal
of the AND circuit N21.
[0334] One input terminal of the OR circuit N23 is connected to an
output terminal of the AND circuit N21 and the other input terminal
thereof is connected to an output terminal of the AND circuit N22.
One input terminal of the AND circuit 24 is connected to an output
terminal of the OR circuit N23 and the other input terminal thereof
is connected to an output terminal of the AND circuit N11. An
output terminal of the AND circuit N24 is connected to an input
terminal of the up-down counter UD21.
[0335] One input terminal of the AND circuit N25 is connected to an
output terminal Q of the flip-flop F1 and a reset pulse R-BC is
input to the other input terminal of the AND circuit N25. One input
terminal of the OR circuit N26 is connected to an output terminal
of the AND circuit N25 and a reset pulse AR-C is input to the other
input terminal of the OR circuit N26. An output terminal of the OR
circuit N26 is connected to a reset terminal of the up-down counter
UD21.
[0336] The gain selecting unit SE1 is connected to an inverting
output terminal NQ of the flip-flop F2. An input terminal D of the
flip-flop F2 is connected to an output terminal of the comparator
PA, a reset signal R-FF is input to a reset terminal R of the
flip-flop F2, and a set pulse SET-G is input to a set terminal of
the flip-flop F2.
[0337] FIG. 23 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 22.
[0338] In FIG. 23, when a level of the switching signal SET-A is
set to a high level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a low level. The switch
transistor Tsc2-1 is turned off and the amplification factor of the
column amplifying circuit 3a is set to A2.
[0339] If the level of the row selection signal ADRESn becomes a
high level, the row selection transistor Ta of the pixel PCn is
turned on, the power supply potential VDD is applied to a drain of
the amplification transistor Tb, and a source follower is
configured by the amplification transistor Tb and the constant
current transistor TL.
[0340] If the level of the reset signal RESETn becomes a high level
with the row selection transistor Ta being turned on, the reset
transistor Tc is turned on and a voltage according to the reference
level of the floating diffusion FD is applied to the gate of the
amplification transistor Tb and is output as the output voltage
Vout1 of the reference level to the vertical signal line Vlin.
[0341] When the output voltage Vout1 of the reference level of the
amplification factor A2 is output to the vertical signal line Vlin,
if the reset pulse Psc is applied to the gate of the switch
transistor Tsc1-1, the input voltage of the operational amplifier
OP is clamped with the output voltage and an operation point is
set. At this time, the voltage difference with respect to the
vertical signal line Vlin is held in the capacitor C1 and the input
voltage of the operational amplifier OP is set to zero.
[0342] Next, if the level of the switching signal SET-A changes to
a low level, the switching signal SET-A is inverted by the inverter
V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor of the
column amplifying circuit 3a is set to A1.
[0343] When the output voltage Vout1 of the reference level of the
amplification factor A1 is output to the vertical signal line Vlin,
if the reset pulse Pcp is applied to the gate of the switch
transistor Tcp, the input voltage of the inverting input terminal
of the comparator PA is clamped with the output voltage and an
operation point is set. At this time, the voltage difference with
respect to the output voltage Vout2 from the operational amplifier
OP is held in the capacitor C3 and the input voltage of the
comparator PA is set to zero.
[0344] The reference voltage VREF is maintained to have a constant
value. The up-down counter UD is reset.
[0345] Next, if the level of the switching signal SET-A changes to
a high level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a low level. The switch
transistor Tsc2-1 is turned off and the amplification factor of the
column amplifying circuit 3a is set to A2.
[0346] If the reset pulse AR-C is input to the reset terminal of
the up-down counter UD21 through the OR circuit 26, the up-down
counter UD21 is reset.
[0347] With the output voltage Vout2 of the reference level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the reference level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to one input terminal of the AND
circuit N11 and the reference clock CKC passes through the AND
circuit N11 and is input to the other input terminal of the AND
circuit N24.
[0348] At this time, the level of the reset signal R-FF is set to a
high level and the potential level of the output terminal Q of the
flip-flop F2 becomes a low level. For this reason, if the level of
the switching signal SET-A changes to a high level, an output of
the AND circuit N21 becomes a high level and is input to one input
terminal of the AND circuit N24 through the OR circuit N23. For
this reason, a reference clock CKCi passes through the AND circuit
N24 and is input to the up-down counter UD21, and the up-down
counter 21 executes the down-counting operation.
[0349] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the reference level of the
amplification factor A2 is matched with the level of the reference
voltage VREF, the up-down counter UD21 executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the reference
level of the amplification factor A2 is converted into a digital
value D and is held as the second reference level of the signal
amplified with the amplification factor A2 in the up-down counter
UD21.
[0350] Next, if the level of the read signal READn becomes a high
level with the row selection transistor Ta of the pixel PCn being
turned on, the read transistor Td is turned on and the charges that
are accumulated in the photodiode PD are transmitted to the
floating diffusion FD. In addition, a voltage according to the
signal level of the floating diffusion FD is applied to the gate of
the amplification transistor Tb and is output as the output voltage
Vout1 of the signal level to the vertical signal line Vlin.
[0351] The level of the reference voltage VREF is set to a level
slightly lower than a saturation level of the A/D conversion. After
the level of the reset signal R-FF changes to a low level, if the
set pulse SET-G is applied to a set terminal of the flip-flop F2,
the output level of the comparator PA is input to the flip-flop
F2.
[0352] In this case, when the logical value `1` is input to the
flip-flop F2, the amplification factor of the output voltage Vout2
of the signal level can be determined as A1. When the logical value
`0` is input to the flip-flop F2, the amplification factor of the
output voltage Vout2 of the signal level can be determined as
A2.
[0353] Hereinafter, each of the case which the logical value `1` is
input to the flip-flop F2 and the case which the logical value `0`
is input to the flip-flop F2 will be described.
(Case in which the Logical Value `0` is Input to the Flip-Flop
F2)
[0354] After the logical value `0` is input to the flip-flop F2,
the reset pulse R-BC is applied to the other input terminal of the
AND circuit N25. In this case, when the logical value `0` is input
to the flip-flop F2, the potential level of the output terminal Q
of the flip-flop F1 becomes a low level. For this reason, the reset
pulse R-BC is intercepted by the AND circuit 25 and the up-down
counter UD21 is not reset.
[0355] With the output voltage Vout2 of the signal level of the
amplification factor A2 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the signal level of
the amplification factor A2 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input to the output voltage Vout4 to one input terminal to one
input terminal of the AND circuit N11 and the reference clock CKC
passes through the AND circuit N11 and is input to the other input
terminal of the AND circuit N24.
[0356] At this time, the potential level of the inverting output
terminal NQ of the flip-flop F2 becomes a high level. For this
reason, if the level of the switching signal SET-A is set to a high
level, an output of the AND circuit N21 becomes a high level and is
input to one input terminal of the AND circuit N24 through the OR
circuit N23. For this reason, the reference clock CKCi passes
through the AND circuit N24 and is input to the up-down counter
UD21, and the up-down counter UD21 executes the up-counting
operation.
[0357] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the reference level of the
amplification factor A2 is matched with the level of the reference
voltage VREF, the up-down counter UD21 executes the down-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the difference between the output voltage
Vout2 of the signal level of the amplification factor A2 and the
output voltage Vout2 of the reference level is converted into a
digital value D and is transmitted to the line memory LM21. As a
result, in the line memory LM21, the difference between the second
signal level and the second reference level that are sampled from
the signal amplified with the amplification factor A2 is held as
the signal component of the amplification factor A2 detected by the
digital CDS.
[0358] Next, if the level of the switching signal SET-A changes to
a low level, the switching signal SET-A is inverted by the inverter
V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor A1 of
the column amplifying circuit 3a is set to A1.
[0359] At this time, since the potential level of the output
terminal Q of the flip-flop F2 becomes a low level, both outputs of
the AND circuits N21 and N22 become a low level, a reference clock
CKCi after passing through the AND circuit N11 is intercepted by
the AND circuit N24 and the up-down counter UD21 does not
operate.
[0360] When the potential level of the output terminal NQ of the
flip-flop F2 is a high level, the value of the gain selection
signal GSEL is set to `H` by the gain selecting unit 34 of FIG. 21.
If the value of the gain selection signal GSEL is set to `H`, the
switches 36 and 44 are switched to the H side and the output signal
Vout11 is output as the output signal Vout8.
(Case in which the Logical Value `1` is Input to the Flip-Flop
F2)
[0361] After the logical value `1` is input to the flip-flop F2,
the reset pulse R-BC is applied to the other input terminal of the
AND circuit N25. In this case, when the logical value `1` is input
to the flip-flop F2, the potential level of the output terminal Q
of the flip-flop F2 becomes a high level. Therefore, the reset
pulse R-BC passes through the AND circuit N25 and the up-down
counter UD21 is reset.
[0362] When the level of the switching signal SET-A is set to a
high level, the potential level of the inverting output terminal NQ
of the flip-flop F2 becomes a low level. Therefore, both outputs of
the AND circuits N21 and N22 become a low level, a reference clock
CKCi after passing through the AND circuit N11 is intercepted by
the AND circuit N24, and the up-down counter UD21 does not
operate.
[0363] Next, when the level of the switching signal SET-A changes
to a low level, the switching signal SET-A is inverted by the
inverter V4 and the level thereof becomes a high level. The switch
transistor Tsc2-1 is turned on and the amplification factor of the
column amplifying circuit 3a is set to A1.
[0364] With the output voltage Vout2 of the signal level of the
amplification factor A1 being input to the comparator PA through
the capacitor C3, a triangular wave is applied as the reference
voltage VREF and the output voltage Vout2 of the signal level of
the amplification factor A1 and the reference voltage VREF are
compared with each other. After the output voltage of the
comparator PA is inverted by the inverter V, the output voltage is
input as the output voltage Vout4 to one input terminal of the AND
circuit N11, and the reference clock CKC passes through the AND
circuit N11 and is input to the other input terminal of the AND
circuit N24.
[0365] At this time, the potential level of the output terminal Q
of the flip-flop F2 becomes a high level. For this reason, if the
level of the switching signal SET-A is set to a low level, an
output of the AND circuit N22 becomes a high level and is input to
one input terminal of the AND circuit N24 through the OR circuit
N23. For this reason, the reference clock CKCi passes through the
AND circuit N24 and is input to the up-down counter UD21, and the
up-down counter UD21 executes the up-counting operation.
[0366] The high level of the output voltage Vout4 is maintained
until the output voltage Vout2 of the signal level of the
amplification factor A1 is matched with the level of the reference
voltage VREF, the up-down counter UD21 executes the up-counting
operation until the level of the output voltage Vout4 is inverted
into a low level, and the output voltage Vout2 of the signal level
of the amplification factor A1 is converted into a digital value D
and is transmitted to the line memory LM21. As a result, in the
line memory LM21, the difference between the first signal level and
the first reference level that are sampled from the signal
amplified with the amplification factor A1 is held as the signal
component of the amplification factor A1 detected by the analog
CDS.
[0367] When the potential level of the output terminal Q of the
flip-flop F2 is a high level, a value of a gain selection signal
GSEL is set to `L` by the gain selecting unit 34 of FIG. 21. If the
value of the gain selection signal GSEL is set to `L`, the switches
36 and 44 are switched to the L side. After the output signal
Vout11 is subtracted by the black level SB, the output signal is
amplified with the amplification factor A2 and the output signal is
output as the output signal Vout8.
[0368] In this case, even when the first reference level and the
second reference level are sampled before the amplification factors
A1 and A2 of the signals read from the pixels PCn are switched and
the first signal level and the second signal level are sampled
after the amplification factors A1 and A2 of the signals read from
the pixels PCn are switched and the amplification factors A1 and A2
of the signals read from the pixels PCn is switched, the reference
levels according to the amplification factors A1 and A2 can be
cancelled and an effect of suppressing noise based on the CDS can
be improved. Since the line memory LM21 does not need to be
provided individually for each of the amplification factors A1 and
A2, a circuit scale can be reduced.
[0369] The signal component of the signal that is amplified with
the amplification factor A1 is detected by the analog CDS and the
signal component of the signal that is amplified with the
amplification factor A2 is detected by the digital CDS, and the
up-down counter UD21 does not need to be provided individually for
each of the amplification factors A1 and A2. Therefore, a circuit
scale can be reduced.
Fourteenth Embodiment
[0370] FIG. 24 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a
fourteenth embodiment.
[0371] In FIG. 24, in the solid-state imaging device, the sample
and hold signal converting circuit 41a of FIG. 22 is connected to
the rear stage of the column amplifying circuit 3b of FIG. 10.
[0372] FIG. 25 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 24.
[0373] In FIG. 25, the operations of FIGS. 11 and 23 are combined,
and the switched capacitor type amplifying circuit is not used and
a differential amplifying circuit is used as the column amplifying
circuit 3b.
Fifteenth Embodiment
[0374] FIG. 26 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a fifteenth
embodiment.
[0375] In FIG. 26, the solid-state imaging device includes a sample
and hold signal converting circuit 41b and a gain switching control
unit 45, instead of the sample and hold signal converting circuit
41a and the flip-flop F2 of FIG. 22.
[0376] In the sample and hold signal converting circuit 41b, the
counter input intercepting circuit 63 of the sample and hold signal
converting circuit 41a of FIG. 22 is omitted and the output
terminal of the AND circuit N11 is connected directly to the input
terminal of the up-down counter UD21 without using the counter
input intercepting circuit 63.
[0377] The gain switching control unit 45 can switch the
amplification factor of the signal read from each pixel PCn into A1
or A2, on the basis of the signal level of the signal read from
each pixel PCn. The gain switching control unit 45 can determine
the signal level of the signal that is read from each pixel PCn, on
the basis of the output from the comparator PA.
[0378] In this case, in the gain switching control unit 45, a
flip-flop F3 that stores values to specify the amplification
factors A1 and A2 of the signals read from each pixel PCn and a NOR
circuit N31 that switches the amplification factors A1 and A2 of
the column amplifying circuit 3a on the basis of the values stored
in the flip-flop F3 are provided.
[0379] The flip-flop F3 of FIG. 26 is different from the flip-flop
F2 of FIG. 22 in that an inverting output terminal NQ of the
flip-flop F2 is connected to the counter input intercepting circuit
63 and an inverting output terminal NQ of the flip-flop F3 is
connected to one input terminal of the NOR circuit N31.
[0380] The switching signal SET-A is input to the other input
terminal of the NOR circuit N31 and an output terminal of the NOR
circuit N31 is connected to the gate of the switch transistor
Tsc2-1.
[0381] FIG. 27 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 26.
[0382] In FIG. 27, the solid-state imaging device is the same as
the solid-state imaging device of FIG. 22 in that the output
voltage Vout2 of the reference level of the amplification factor A2
is held as the second reference level of the signal amplified with
the amplification factor A2 in the up-down counter UD21.
[0383] The flip-flop F3 is the same as the flip-flop F2 in that the
logical value `0` or `1` is input to the flip-flop F3 according to
the signal level of the signal read from each pixel PCn.
[0384] Meanwhile, in the solid-state imaging device of FIG. 22, by
switching the switching signal SET-A when detecting the signal
level, the up-counting operation of the signal level of the
amplification factor A1 or the up-counting of the signal level of
the amplification factor A2 is executed by the up-down counter
UD21. In this case, when the up-counting operation of the signal
level of the amplification factor A2 is executed by the up-down
counter UD21, the reference clock CKCi that is generated according
to the signal level of the amplification factor A2 is not input to
the up-down counter UD21 by the counter input intercepting circuit
63, in order to make the up-counting operation of the signal level
of the amplification factor A2 not executed by the up-down counter
UD21. When the up-counting operation of the signal level of the
amplification factor A2 is executed by the up-down counter UD21,
the reference clock CKCi that is generated according to the signal
level of the amplification factor A1 is not input to the up-down
counter UD21 by the counter input intercepting circuit 63, in order
to make the up-counting operation of the signal level of the
amplification factor A1 not executed by the up-down counter
UD21.
[0385] Meanwhile, in the solid-state imaging device of FIG. 27, the
up-counting operation of the signal level of the amplification
factor A1 or the up-counting operation of the signal level of the
amplification factor A2 is executed by the up-down counter UD21, on
the basis of the value stored in the flip-flop F3 when detecting
the signal level. In this case, the amplification factors A1 and A2
of the column amplifying circuit 3a are switched on the basis of
the value stored in the flip-flop F3 when detecting the signal
level, only the comparison operation with the output voltage Vout2
of the signal level of one of the amplification factors A1 and A2
is executed by the comparator PA, and an A/D conversion operation
of the signal level of each pixel PCn is executed only once. For
this reason, in the solid-state imaging device of FIG. 27, the
counter input intercepting circuit 63 of FIG. 22 is not needed.
[0386] In this case, the amplification factor of the signal that is
read from each pixel PCn is switched to A1 or A2 on the basis of
the signal level of the signal read from each pixel PCn, the A/D
conversion operation of the signal level of each pixel PCn is
executed only once, and a reading process of the solid-state
imaging device can be executed at a high speed.
Sixteenth Embodiment
[0387] FIG. 28 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to a sixteenth
embodiment.
[0388] In FIG. 28, the solid-state imaging device includes a sample
and hold signal converting circuit 41b and a gain switching control
unit 46, instead of the sample and hold signal converting circuit
41a, the inverter V3, and the flip-flop F2 of FIG. 24.
[0389] The gain switching control unit 46 can switch the
amplification factor of the signal read from each pixel PCn into A1
or A2, on the basis of the signal level of the signal read from
each pixel PCn. The gain switching control unit 46 can determine
the signal level of the signal that is read from each pixel PCn, on
the basis of the output of the comparator PA.
[0390] In this case, in the gain switching control unit 46, a
flip-flop F4 that stores values to specify the amplification
factors A1 and A2 of the signals read from each pixel PCn, a NOR
circuit N41 that switches the amplification factors A1 and A2 of
the column amplifying circuit 3b on the basis of the values stored
in the flip-flop F4, and an inverter V21 are provided.
[0391] The flip-flop F4 of FIG. 28 is different from the flip-flop
F2 of FIG. 24 in that an output terminal Q of the flip-flop F2 is
connected to the counter input intercepting circuit 63 and an
output terminal Q of the flip-flop F4 is connected to one input
terminal of the NOR circuit N41.
[0392] The switching signal SET-A is input to the other input
terminal of the NOR circuit N41 and an output terminal of the NOR
circuit N41 is connected to an input terminal of the inverter V21.
The switches SW2 and SWsf2 are switched on the basis of an output
of the inverter V21. The switch SWsf1 is switched on the basis of
an output of the NOR circuit N41.
[0393] FIG. 29 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 28.
[0394] In FIG. 29, the solid-state imaging device is the same as
the solid-state imaging device of FIG. 24 in that the output
voltage Vout2 of the reference level of the amplification factor A2
is held as the second reference level of the signal amplified with
the amplification factor A2 in the up-down counter UD21.
[0395] The flip-flop F4 is the same as the flip-flop F2 of FIG. 24
in that the logical value `0` or `1` is input to the flip-flop F4
according to the signal level of the signal read from each pixel
PCn.
[0396] Meanwhile, in the solid-state imaging device of FIG. 24, by
switching the switching signal SET-A when detecting the signal
level, the up-counting operation of the signal level of the
amplification factor A1 or the up-counting of the signal level of
the amplification factor A2 is executed by the up-down counter
UD21. In this case, when the up-counting operation of the signal
level of the amplification factor A1 is executed by the up-down
counter UD21, the reference clock CKCi that is generated according
to the signal level of the amplification factor A2 is not input to
the up-down counter UD21 by the counter input intercepting circuit
63, in order to make the up-counting operation of the signal level
of the amplification factor A2 not executed by the up-down counter
UD21. When the up-counting operation of the signal level of the
amplification factor A2 is executed by the up-down counter UD21,
the reference clock CKCi that is generated according to the signal
level of the amplification factor A1 is not input to the up-down
counter UD21 by the counter input intercepting circuit 63, in order
to make the up-counting operation of the signal level of the
amplification factor A1 not executed by the up-down counter
UD21.
[0397] Meanwhile, in the solid-state imaging device of FIG. 28, the
up-counting operation of the signal level of the amplification
factor A1 or the up-counting operation of the signal level of the
amplification factor A2 is executed by the up-down counter UD21, on
the basis of the value stored in the flip-flop F4 when detecting
the signal level. In this case, the amplification factors A1 and A2
of the column amplifying circuit 3b are switched on the basis of
the value stored in the flip-flop F4 when detecting the signal
level, only the comparison operation with the output voltage Vout2
of the signal level of one of the amplification factors A1 and A2
is executed by the comparator PA, and an A/D conversion operation
of the signal level of each pixel PCn is executed only once. For
this reason, in the solid-state imaging device of FIG. 28, the
counter input intercepting circuit 63 of FIG. 24 is not needed.
[0398] In this case, the amplification factor of the signal that is
read from each pixel PCn is switched to A1 or A2 on the basis of
the signal level of the signal read from each pixel PCn, the A/D
conversion operation of the signal level of each pixel PCn is
executed only once, and a reading process of the solid-state
imaging device can be executed at a high speed.
Seventeenth Embodiment
[0399] FIG. 30 is a block diagram of a schematic configuration of a
solid-state imaging device according to a seventeenth
embodiment.
[0400] In FIG. 30, the solid-state imaging device includes a column
amplifying circuit 50, a sample and hold signal converting circuit
51, multipliers 57 to 59, and a selector 60, instead of the column
amplifying circuit 3, the sample and hold signal converting circuit
31, the multiplier 35, and the switch 36 of FIG. 16. Further, the
solid-state imaging device includes a subtractor 55 that adjusts a
black level with respect to a signal component of each pixel PCn
and a switch 56 that supplies a black level SB to the subtractor 55
on the basis of a gain selection signal GSEL.
[0401] In this case, the column amplifying circuit 50 can switch
the amplification factors A1 to A4 (A1<A2<A3<A4) of the
signals read from each pixel PCn and amplify the signals for each
column. In the description below, in order to simplify the
description, it is assumed that A1 is 1, A2 is 2, A3 is 4, and A4
is 8.
[0402] The sample and hold signal converting circuit 51 samples
first to fourth reference levels from the signals amplified with
the amplification factors A1 to A4 and samples signal level from
the signal amplified with any one of the amplification factors A1
to A4, on the basis of the signal level of the signal read from
each pixel PC, and can detects a signal component of each pixel PC
by the CDS. For example, signal components of the signals that are
amplified with the amplification factors A1 and A2 can be detected
by the analog CDS and signal components of the signals that are
amplified with the amplification factors A3 and A4 can be detected
by the digital CDS.
[0403] In the sample and hold signal converting circuit 51, a
column ADC circuit 52 is provided. The column ADC circuit 52 can
execute the up-counting operation on the basis of the comparison
result of the signals of the signal levels amplified with the
amplification factors A1 and A2 and read from the pixels PC and the
reference voltage VREF and calculate the difference between the
reference level and the signal level of the analog CDS. The column
ADC circuit 52 can execute the up-counting operation and the
down-counting operation on the basis of the comparison result of
the signals of the signal levels amplified with the amplification
factors A3 and A4 and read from the pixels PC and the reference
voltage VREF and calculate the difference between the reference
level and the signal level of the digital CDS.
[0404] In the sample and hold signal converting circuit 51, a line
memory 53 that stores a count value of the column ADC circuit 52
with respect to the signal amplified with any one of the
amplification factors A1 to A4 by the amount of amount of
horizontal pixels and a gain selecting unit 54 that selects the
amplification factor from the amplification factors A1 to A4 to
amplify the signal from each pixel PC are provided.
[0405] The multipliers 57 to 59 can multiply the output signals
Vout21 from the sample and hold signal converting circuit 51 with
the amplification factors A2 to A4. The selector 60 can switch the
output signal Vout22 to any one of the terminals M1 to M4, on the
basis of the selection result obtained by the gain selecting unit
54.
[0406] When A1 is selected as the amplification factor of the
signal level of the signal read from each pixel PC, the switch 56
is switched to the L side and the selector 60 is switched to the
terminal M4. In the sample and hold signal converting circuit 51,
the signal component is detected from the signal read from each
pixel PC by the analog CDS and is output as the output voltage
Vout21. The subtractor 55 subtracts the black level SB from the
output signal, the multiplier 59 multiplies the output signal with
the amplification factor A4, and the output signal is output as the
output signal Vout22.
[0407] Meanwhile, when A2 is selected as the amplification factor
of the signal level of the signal read from each pixel PC, the
switch 56 is switched to the L side and the selector 60 is switched
to the terminal M3. In the sample and hold signal converting
circuit 51, the signal component is detected from the signal read
from each pixel PC by the digital CDS and the output signal is
output as the output signal Vout21. The subtractor 55 subtracts the
black level SB from the output signal, the multiplier 58 multiplies
the output signal with the amplification factor A3, and the output
signal is output as the output signal Vout22.
[0408] Meanwhile, when A3 is selected as the amplification factor
of the signal level of the signal read from each pixel PC, the
switch 56 is switched to the H side and the selector 60 is switched
to the terminal M2. In the sample and hold signal converting
circuit 51, the signal component is detected from the signal read
from each pixel PC by the digital CDS and the output signal is
output as the output signal Vout21. The subtractor 58 multiplies
the output signal with the amplification factor A2, and the output
signal is output as the output signal Vout22.
[0409] Meanwhile, when A4 is selected as the amplification factor
of the signal level of the signal read from each pixel PC, the
switch 56 is switched to the H side and the selector 60 is switched
to the terminal M1. In the sample and hold signal converting
circuit 51, the signal component is detected from the signal read
from each pixel PC by the digital CDS and the output signal Vout21
is output as the output signal Vout22.
[0410] In this case, even when the first to fourth reference levels
are sampled whenever the amplification factors A1 to A4 of the
signals read from the pixel PCn are switched and the signal level
of any one of the amplification factors A1 to A4 is sampled
according to the signal levels of the signals read from the pixels
PCn and the amplification factors A1 to A4 of the signals read from
the pixels PCn are switched, the reference levels according to the
amplification factors A1 to A4 can be cancelled and an effect of
suppressing noise based on the CDS can be improved. Since the line
memory LM21 does not need to be provided individually for each of
the amplification factors A1 to A4, a circuit scale can be
reduced.
[0411] The signal components of the signals that are amplified with
the amplification factors A1 and A2 are detected by the analog CDS
and the signal components of the signals that are amplified with
the amplification factors A3 and A4 are detected by the digital
CDS, and the up-down counter does not need to be provided
individually for each of the amplification factors A1 to A4.
Therefore, a circuit scale can be reduced.
Eighteenth Embodiment
[0412] FIG. 31 is a circuit diagram of a schematic configuration of
one column of a solid-state imaging device according to an
eighteenth embodiment.
[0413] In FIG. 31, the solid-state imaging device includes a column
amplifying circuit 50a, a sample and hold signal converting circuit
51a, and a gain switching control unit 47, instead of the column
amplifying circuit 3a, the sample and hold signal converting
circuit 41b, and the gain switching control unit 45 of FIG. 26.
[0414] The column amplifying circuit 50a can switch the
amplification factors A1 to A4 of the signals read from each pixel
PCn in four steps and amplify the signals for each column.
[0415] In this case, in the column amplifying circuit 50a, in order
to switch the amplification factors A1 to A4 in the four steps,
capacitors C2-4 and C2-8 and switch transistors Tsc4-1 and Tsc8-1
are added to the column amplifying circuit 3a of FIG. 26.
[0416] The sample and hold signal converting circuit 51a has almost
the same configuration as that of the sample and hold signal
converting circuit 31a of FIG. 17. However, the gain selecting unit
SE1 of FIG. 17 selects the amplification factors A1 and A2 on the
basis of a value stored in the flip-flop F1 and the gain selecting
unit SE2 of FIG. 31 selects the amplification factors A1 to A4 on
the basis of values stored in the flip-flops F1-2, F1-4, and F1-8.
In the sample and hold signal converting circuit 51a, an AND
circuit N52 and an OR circuit N53 are additionally provided to
reset the up-down counter UD11 on the basis of the values stored in
the flip-flops F1-4 and F1-8, when the reset pulse R-BC is
input.
[0417] The gain switching control unit 47 can switch the
amplification factors of the signals read from each pixel PCn into
A1 to A4, on the basis of the signal levels of the signals read
from each pixel PCn. The gain switching control unit 47 can switch
the signal level of the signal read from each pixel PCn, on the
basis of the output of the comparator PA.
[0418] In this case, in the gain switching control unit 47,
flip-flops F1-2, F1-4, and F1-8 that stores values to specify the
amplification factors A1 to A4 of the signals read from each pixel
PCn and NOR circuits N1-2, N1-4, and N1-8 that switch the
amplification factors A1 to A4 of the column amplifying circuit 3a
on the basis of the values stored in the flip-flops F1-2, F1-4, and
F1-8 are provided.
[0419] In this case, a set pulse SET-G2 is input to a set terminal
of the flip-flop F1-2, a set pulse SET-G4 is input to a set
terminal of the flip-flop F1-4, and a set pulse SET-G8 is input to
a set terminal of the flip-flop F1-8.
[0420] An inverting output terminal NQ of the flip-flop F1-2 is
connected to one input terminal of the NOR circuit N1-2, an
inverting input terminal NQ of the flip-flop F1-4 is connected to
one input terminal of the NOR circuit N1-4, and an inverting output
terminal NQ of the flip-flop F1-8 is connected to one input
terminal of the NOR circuit N1-8.
[0421] A switching signal SET-A2 is input to the other input
terminal of the NOR circuit N1-2, a switching signal SET-A4 is
input to the other input terminal of the NOR circuit N1-4, and a
switching signal SET-A8 is input to the other input terminal of the
NOR circuit N1-8.
[0422] An output terminal of the NOR circuit N1-2 is connected to a
gate of the switch transistor Tsc2-1, an output terminal of the NOR
circuit N1-4 is connected to a gate of the switch transistor
Tsc4-1, and an output terminal of the NOR circuit N1-8 is connected
to a gate of the switch transistor Tsc8-1.
[0423] FIG. 32 is a timing chart illustrating a read operation of
one pixel of the solid-state imaging device of FIG. 31.
[0424] In FIG. 32, after the reset signal RESETn is applied, the
switching signals SET-A2, SET-A4, and SET-A8 sequentially rise and
the amplification factor of the column amplifying circuit 50a is
switched in the order of A1->A2->A3->A4.
[0425] The reference level is sampled for each of the amplification
factors A1 to A4 of the column amplifying circuit 50a, and the
first reference level of the amplification factor A1, the second
level of the amplification factor A2, the third reference level of
the amplification factor A3, and the fourth reference level of the
amplification facto A4 are held in the sample and hold signal
converting circuit 51a.
[0426] In this case, in order to decrease the number of up-down
counters UD11 and UD12, when the amplification factors are A1 and
A2, the signal component is detected by the analog CDS, and when
the first reference level of the amplification factor A1 and the
second reference level of the amplification factor A2 are sampled,
the up-down counters UD11 and UD12 are not operated.
[0427] Since the signal level is low when the amplification factors
A3 and A4, the down-counting operation is executed by the up-down
counters UD11 and UD12 when sampling the third reference level of
the amplification factor A3 and the fourth reference level of the
amplification factor A4, and the signal component is detected by
the digital CDS.
[0428] Next, after the read signal READn is applied, the switching
signals SET-A8, SET-A4, and SET-A2 sequentially fall and the
amplification factor of the column amplifying circuit 50a is
switched in the order of A4->A3->A2->A1.
[0429] At this time, the level of the reference level VERF is set
to a level slightly lower than the saturation level of the A/D
conversion. When the amplification factor of the column amplifying
circuit 50a is A4, the set pulse SET-G8 is applied to the set
terminal of the flip-flop F1-8. When the amplification factor of
the column amplifying circuit 50a is A3, the set pulse SET-G4 is
applied to the set terminal of the flip-flop F1-4. When the
amplification factor A2 of the column amplifying circuit 50a is A2,
the set pulse SET-G2 is applied to the set terminal of the
flip-flop F1-2.
[0430] In this case, since the level of the reference level VERF is
set to a level slightly lower than the saturation level of the A/D
conversion, if the output voltage Vout2 of the signal level of the
amplification factor A4 is saturated, the level of the output
voltage of the comparator PA becomes a high level and a logical
value `1` is input to the flip-flop F1-8. Meanwhile, if the output
voltage Vout2 of the signal level of the amplification factor A4 is
not saturated, the level of the output voltage of the comparator PA
becomes a low level and a logical value `0` is input to the
flip-flop F1-8.
[0431] If the output voltage Vout2 of the signal level of the
amplification factor A3 is saturated, the level of the output
voltage of the comparator PA becomes a high level and a logical
value `1` is input to the flip-flop F1-4. Meanwhile, if the output
voltage Vout2 of the signal level of the amplification factor A3 is
not saturated, the level of the output voltage of the comparator PA
becomes a low level and a logical value `0` is input to the
flip-flop F1-4.
[0432] If the output voltage Vout2 of the signal level of the
amplification factor A2 is saturated, the level of the output
voltage of the comparator PA becomes a high level and a logical
value `1` is input to the flip-flop F1-2. Meanwhile, if the output
voltage Vout2 of the signal level of the amplification factor A2 is
not saturated, the level of the output voltage of the comparator PA
becomes a low level and a logical value `0` is input to the
flip-flop F1-2.
[0433] When the logical value `1` is input to the flip-flops F1-2,
F1-4, and F1-8, the output voltage Vout2 of the signal level of the
amplification factor A2 is saturated. Therefore, the amplification
factor of the signal level can be determined as A1. When the
logical value `0` is input to the flip-flop F1-2, the output
voltage Vout2 of the signal level of the amplification factor A3 is
saturated and the output voltage Vout2 of the signal level of the
amplification factor A2 is not saturated. Therefore, the
amplification factor of the signal level can be determined as A2.
When the logical value `0` is input to the flip-flop F1-4, the
output voltage Vout2 of the signal level of the amplification
factor A2 is saturated and the output voltage Vout2 of the signal
level of the amplification factor A3 is not saturated. Therefore,
the amplification factor of the signal level can be determined as
A3. When the logical value `0 is input to the flip-flop F1-8, the
output voltage Vout2 of the signal level of the amplification
factor A4 is not saturated. Therefore, the amplification factor of
the signal level can be determined as A4.
[0434] When the amplification factor of the signal level is
determined as A1, the amplification factor of the column amplifying
circuit 50a is switched to A1. When the amplification factor of the
signal level is determined as A2, the amplification factor of the
column amplifying circuit 50a is switched to A2. When the
amplification factor of the signal level is determined as A3, the
amplification factor of the column amplifying circuit 50a is
switched to A3. When the amplification factor of the signal level
is determined as A4, the amplification factor of the column
amplifying circuit 50a is switched to A4.
[0435] If the output voltage Vout1 of the signal level is amplified
with the amplification of any one of A1 to A4, the output voltage
Vout2 of the signal level is generated and is input to the
comparator PA. The up-down counters UD11 and UD12 execute the
up-counting operation on the basis of the comparison result of the
comparator PA and the signal component is detected by the CDS.
[0436] In this case, even when the amplification factors A1 to A4
of the column amplifying circuit 50a are switched on the basis of
the values stored in the flip-flops F1-2, F1-4, and F1-8 when
detecting the signal level and only the comparison operation with
the output voltage Vout2 of the signal level of any one of the
amplification factors A1 to A4 is executed by the comparator PA and
the amplification factors A1 to A4 are switched in the four steps,
an A/D conversion operation of the signal level of each pixel PCn
can be executed only once.
[0437] In the eighteenth embodiment described above, the signal
components of the signals that are amplified with the amplification
factors A1 and A2 are detected by the analog CDS and the signal
components of the signals that are amplified with the amplification
factors A3 and A4 are detected by the digital CDS. However, the
signal components of the signals that are amplified with the
amplification factor A1 may be detected by the analog CDS and the
signal components of the signals that are amplified with the
amplification factors A2 to A4 may be detected by the digital CDS.
Alternatively, the signal components of the signals that are
amplified with the amplification factors A1 to A3 may be detected
by the analog CDS and the signal components of the signals that are
amplified with the amplification factor A4 may be detected by the
digital CDS. Alternatively, the signal components of the signals
that are amplified with the amplification factors A1 to A4 may be
detected by the digital CDS.
[0438] In the eighteenth embodiment described above, the
configuration of the solid-state imaging device of FIG. 26 where
the amplification factors are switched in the two steps of A1 and
A2 is changed to the configuration where the amplification factors
are switched in the four steps of A1 to A4. However, the
configuration of the solid-state imaging device of FIG. 28 where
the amplification factors are switched in the two steps of A1 and
A2 may be changed to the configuration where the amplification
factors may be switched in the four steps of A1 to A4.
[0439] In the embodiments described above, the up-down counter is
used in the circuit that operates the difference between the
reference level and the signal level of the signal as the digital
CDS processing. Alternatively, a circuit that holds the reference
level and the signal level in different line memories,
respectively, and operates the difference between the read output
signals may be provided. Alternatively, a counter type operation
processing circuit that counts the reference level by the up-down
counter, inverts a count value by an inversion control signal, up
counts the signal level, and uses the two's complement may be
provided.
[0440] In the embodiments described above, the amplification
factors are switched in the two steps of A1 and A2 or the four
steps of A1 to A4. However, a method that switches the
amplification factors in two or more steps may be applied.
[0441] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions.
* * * * *