U.S. patent application number 13/864868 was filed with the patent office on 2014-10-23 for charge pump phase-locked loop circuits.
This patent application is currently assigned to MStar Semiconductor, Inc.. The applicant listed for this patent is MSTAR SEMICONDUCTOR, INC.. Invention is credited to Ryan Lee Bunch, Walter H. Prada.
Application Number | 20140312944 13/864868 |
Document ID | / |
Family ID | 51588162 |
Filed Date | 2014-10-23 |
United States Patent
Application |
20140312944 |
Kind Code |
A1 |
Bunch; Ryan Lee ; et
al. |
October 23, 2014 |
CHARGE PUMP PHASE-LOCKED LOOP CIRCUITS
Abstract
A charge pump phase-locked loop circuit includes an active loop
filter, an adjustable reference voltage source, and a charge pump.
The active loop filter includes an amplifier that has a negative
input node, a positive input node, and an output node. The
adjustable reference voltage source is coupled to the positive
input node to provide an adjustable reference voltage. The charge
pump is coupled to the negative input node to provide a current to
or draw a current from the active loop filter in response to a
signal from a phase detector. The charge pump includes a first
current source coupled to a first voltage and a second current
source electrically coupled to a second voltage, the second current
source including a resistor. The second current source is
configured such that a current provided by the second current
source depends on a resistance value of the resistor and a
difference between the reference voltage and the second
voltage.
Inventors: |
Bunch; Ryan Lee;
(Greensboro, NC) ; Prada; Walter H.; (Winston
Salem, NC) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MSTAR SEMICONDUCTOR, INC. |
ChuPei |
|
TW |
|
|
Assignee: |
MStar Semiconductor, Inc.
ChuPei
TW
|
Family ID: |
51588162 |
Appl. No.: |
13/864868 |
Filed: |
April 17, 2013 |
Current U.S.
Class: |
327/157 |
Current CPC
Class: |
H03L 7/093 20130101;
H03L 7/0898 20130101 |
Class at
Publication: |
327/157 |
International
Class: |
H03L 7/089 20060101
H03L007/089 |
Claims
1. An apparatus comprising: a charge pump phase-locked loop circuit
comprising: an active loop filter comprising an amplifier that has
a negative input node, a positive input node, and an output node,
in which a feedback path is provided between the output node and
the negative input node, the feedback path including a capacitor;
an adjustable reference voltage source that is electrically coupled
to the positive input node of the amplifier to provide a reference
voltage that is adjustable; and a charge pump electrically coupled
to the negative input node of the amplifier to provide a current to
or sink a current from the active loop filter in response to a
signal from a phase detector, the charge pump comprising a first
current source electrically coupled to a first voltage and a second
current source electrically coupled to a second voltage, the second
current source comprising a resistor, and the second current source
is configured such that a current provided by the second current
source depends on a resistance value of the resistor and a
difference between the reference voltage and the second voltage,
wherein the adjustable reference voltage source comprises a
digital-to-analog converter to receive a digital input signal and
output the reference voltage provided to the positive input node of
the amplifier.
2. The apparatus of claim 1 in which the second voltage is lower
than the first voltage, the first current source comprises a PMOS
transistor operating in an active region to provide an offset
current to the active loop filter, and the second current source
comprises an NMOS transistor that is turned on or off by the signal
from the phase detector.
3. The apparatus of claim 1, comprising a control circuit to
control the adjustable reference voltage source to adjust the
reference voltage to control a magnitude of the current flowing
from the active loop filter to the second current source.
4. (canceled)
5. The apparatus of claim 1 in which the resistor in the second
current source comprises a variable resistor, and the apparatus
further comprising a control circuit to control the variable
resistor to adjust the resistance value of the resistor to control
a magnitude of the current flowing between the active loop filter
and the second current source.
6. The apparatus of claim 5 in which the control circuit is
configured to control a magnitude of the current flowing between
the active loop filter and the second current source by also
controlling the adjustable reference voltage source to adjust the
reference voltage.
7. The apparatus of claim 6 in which the control circuit is
configured to set the current flowing between the active loop
filter and the second current source to a minimum value by setting
the resistance of the resistor to a maximum value among a plurality
of possible values for the resistance and setting the reference
voltage to a minimum value among a plurality of possible values for
the reference voltage.
8. The apparatus of claim 1 in which the first current source
comprises a transistor that is configured to operate in an active
region and provide an offset current to the active loop filter.
9. The apparatus of claim 1 in which the first current source is
configured to provide an offset current to the active loop filter
that is independent of the signal from the phase detector, and the
second current source is configured to switch on or off in response
to the signal from the phase detector.
10. The apparatus of claim 1 in which the charge pump phase-locked
loop circuit comprises a fractional-N phase-locked loop
circuit.
11. An apparatus comprising: a phase-locked loop circuit
comprising: an adjustable voltage reference source to output a
reference voltage that is adjustable; an active loop filter having
a first node, a second node, and third node, in which the first
node is configured to receive the reference voltage from the
adjustable voltage reference source, the second node has a voltage
that is configured to track the reference voltage, and the third
node provides a signal to an oscillator; a charge pump circuit
electrically coupled to the second node of the active loop filter
to pump current to or draw current from the active loop filter, in
which the current drawn from the active loop filter is configured
to be dependent on the reference voltage, and an operation of the
charge pump circuit is dependent on a signal received from a phase
detector; and a control circuit to control the reference voltage to
control a magnitude of the current drawn from the active loop
filter by the charge pump circuit, wherein the charge pump circuit
comprises a variable resistor, and the control circuit also
controls a resistance value of the variable resistor to control the
magnitude of the current drawn from the active loop filter by the
charge pump circuit.
12. (canceled)
13. The apparatus of claim 11 in which the control circuit is
configured to set the current flowing from the active loop filter
to the second current source to a minimum value by setting the
resistance of the resistor to a maximum value among a plurality of
possible values for the resistance and setting the reference
voltage to a minimum value among a plurality of possible values for
the reference voltage.
14. A method of operating a charge pump phase-locked loop circuit,
the method comprising: providing an adjustable reference voltage to
a first node of an active loop filter; pumping current to or
drawing current from a second node of the active loop filter in
response to a signal from a phase detector; providing a signal from
the active loop filter to an oscillator; and modifying a level of
the reference voltage to adjust an amplitude of the current drawn
from or pumped to the active loop filter, wherein drawing current
from the active loop filter comprises passing at least a portion of
the current through a variable resistor, and the method comprises
modifying a resistance value of the variable resistor to adjust the
amplitude of the current drawn from the active loop filter.
15. (canceled)
16. The method of claim 14, comprising setting the current drawn
from the active loop filter to a minimum value by setting the
resistance of the variable resistor to a maximum value among a
plurality of possible values for the resistance and setting the
reference voltage to a minimum value among a plurality of possible
values for the reference voltage.
17. The method of claim 14, comprising generating the reference
voltage using a digital-to-analog converter, and controlling a
digital signal provided to the digital-to-analog converter to
modify the reference voltage.
18. The method of claim 14 in which pumping current to the active
loop filter comprise providing an offset current from a transistor
operating in an active region.
19. The method of claim 14 in which pumping current to or drawing
current from the active loop filter comprises operating a P-type
transistor in an active region to provide an offset current to the
active loop filter, and operating an N-type transistor as a switch
to turn on or off the current drawn from the active loop filter in
response to the signal from the phase detector.
20. The method of claim 14, comprising modifying a level of the
reference voltage to adjust an amplitude of the current drawn from
the active loop filter.
Description
TECHNICAL FIELD
[0001] The present disclosure relates generally to charge pump
phase-locked loop circuits.
BACKGROUND
[0002] A phase-locked loop (PLL) circuit includes a reference
source to provide a reference signal, a phase frequency detector, a
charge pump, a loop filter, a voltage controlled oscillator (VCO),
and a feedback divider. The output of the voltage controlled
oscillator is sent to the feedback divider, which divides the
output frequency by an integer. The output of the feedback divider
is compared with the reference signal at the phase frequency
detector, and the phase difference is used to control a pump-up or
pump-down current source in the charge pump to charge or discharge
an integrating capacitor in the loop filter. The output voltage of
the loop filter is provided to the voltage controlled oscillator to
adjust its frequency and phase. The phase-locked loop is a negative
feedback loop that is designed so that the frequency of the output
of the voltage controlled oscillator is a multiple of that of the
reference signal.
[0003] A phase-locked loop circuit can track an input frequency or
generate a frequency that is a multiple of the input frequency.
Phase-locked loop circuits can be used to recover a signal from a
noisy communication channel or distribute clock timing pulses in
digital circuits.
SUMMARY
[0004] In one aspect, an apparatus includes a charge pump
phase-locked loop circuit having an active loop filter, an
adjustable reference voltage source, and a charge pump. The active
loop filter includes an amplifier that has a negative input node, a
positive input node, and an output node, in which a feedback path
is provided between the output node and the negative input node,
the feedback path including a capacitor. The adjustable reference
voltage source is electrically coupled to the positive input node
of the amplifier to provide a reference voltage that is adjustable.
The charge pump is electrically coupled to the negative input node
of the amplifier to provide a current to or sink a current from the
active loop filter in response to a signal from a phase detector.
The charge pump includes a first current source electrically
coupled to a first voltage and a second current source electrically
coupled to a second voltage, the second current source including a
resistor, and the second current source is configured such that a
current provided by the second current source depends on a
resistance value of the resistor and a difference between the
reference voltage and the second voltage.
[0005] Implementations of the apparatus can include one or more of
the following features. The second voltage can be lower or higher
than the first voltage. The apparatus can include a control circuit
to control the adjustable reference voltage source to adjust the
reference voltage to control a magnitude of the current flowing
from the active loop filter to the second current source. The
adjustable reference voltage source can include a digital-to-analog
converter to receive a digital input signal and output the
reference voltage provided to the positive input node of the
amplifier. The second current source can include a transistor
having a gate node that is configured to receive the signal from
the phase detector. The resistor in the second current source can
include a variable resistor.
[0006] In some examples, the apparatus can include a control
circuit to control the variable resistor to adjust the resistance
value of the resistor to control a magnitude of the current flowing
from the active loop filter to the second current source. The
control circuit can be configured to control a magnitude of the
current flowing from the active loop filter to the second current
source by also controlling the adjustable reference voltage source
to adjust the reference voltage. The control circuit can be
configured to set the current flowing from the active loop filter
to the second current source to a minimum value by setting the
resistance of the resistor to a maximum value among a plurality of
possible values for the resistance and setting the reference
voltage to a minimum value among a plurality of possible values for
the reference voltage.
[0007] In some examples, the apparatus can include a control
circuit to control the variable resistor to adjust the resistance
value of the resistor to control a magnitude of the current flowing
from the second current source to the active loop filter. The
control circuit can be configured to control a magnitude of the
current flowing from the second current source to the active loop
filter by also controlling the adjustable reference voltage source
to adjust the reference voltage. The control circuit can be
configured to set the current flowing from the second current
source to the active loop filter to a minimum value by setting the
resistance of the resistor to a maximum value among a plurality of
possible values for the resistance and setting the reference
voltage to a minimum value among a plurality of possible values for
the reference voltage.
[0008] The first current source can include a transistor that is
configured to operate in an active region and provide an offset
current to the active loop filter. The first current source can be
configured to provide an offset current to the active loop filter
that is not dependent on the signal from the phase detector, and
the second current source can be configured to switch on or off in
response to the signal from the phase detector.
[0009] In one aspect, an apparatus includes a phase-locked loop
circuit having an adjustable voltage reference source to output a
reference voltage that is adjustable, an active loop filter, a
charge pump circuit, and a control circuit. The active loop filter
has a first node, a second node, and third node, in which the first
node is configured to receive the reference voltage from the
adjustable voltage reference source, the second node has a voltage
that is configured to track the reference voltage, and the third
node provides a signal to an oscillator. The charge pump circuit is
electrically coupled to the second node of the active loop filter
to pump current to or draw current from the active loop filter, in
which the current drawn from the active loop filter is configured
to be dependent on the reference voltage, and an operation of the
charge pump circuit is dependent on a signal received from a phase
detector. The control circuit controls the reference voltage to
control a magnitude of the current drawn from the active loop
filter by the charge pump circuit.
[0010] Implementations of the apparatus can include one or more of
the following features. The charge pump circuit can include a
variable resistor, and the control circuit may also control a
resistance value of the variable resistor to control the magnitude
of the current drawn from the active loop filter by the charge pump
circuit. The control circuit can be configured to set the current
flowing from the active loop filter to the second current source to
a minimum value by setting the resistance of the resistor to a
maximum value among a plurality of possible values for the
resistance and setting the reference voltage to a minimum value
among a plurality of possible values for the reference voltage.
[0011] In one aspect, an apparatus includes a phase-locked loop
circuit having an active loop filter to provide a control signal to
an oscillator, and a charge pump circuit electrically coupled to a
node of the active loop filter to pump current to or draw current
from the active loop filter. The charge pump circuit has a P-type
MOSFET operating in an active region to provide an offset current
to the active loop filter, and a current source to draw current
from the active loop filter in response to a signal from a phase
detector. The current source includes a variable resistor and an
N-type MOSFET that is turned on or off by the signal from the phase
detector, in which a resistance value of the variable resistor
affects an amplitude of the current drawn from the active loop
filter to the current source.
[0012] In one aspect, an apparatus includes a phase-locked loop
circuit having an active loop filter to provide a control signal to
an oscillator, and a charge pump circuit electrically coupled to a
node of the active loop filter to pump current to or draw current
from the active loop filter. The charge pump circuit has an N-type
MOSFET operating in an active region to provide an offset current
to the active loop filter, and a current source to pump current to
the active loop filter in response to a signal from a phase
detector. The current source includes a variable resistor and a
P-type MOSFET that is turned on or off by the signal from the phase
detector, in which a resistance value of the variable resistor
affects an amplitude of the current pumped to the active loop
filter.
[0013] In one aspect, a method of operating a charge pump
phase-locked loop circuit is provided. The method includes
providing an adjustable reference voltage to a first node of an
active loop filter; pumping current to or drawing current from a
second node of the active loop filter in response to a signal from
a phase detector; providing a signal from the active loop filter to
an oscillator; and modifying a level of the reference voltage to
adjust an amplitude of the current drawn from or pumped to the
active loop filter.
[0014] Implementations of the method may include one or more of the
following features. Drawing current from the active loop filter can
include passing at least a portion of the current through a
variable resistor, and the method can include modifying a
resistance value of the variable resistor to adjust the amplitude
of the current drawn from the active loop filter. The method can
include setting the current drawn from the active loop filter to a
minimum value by setting the resistance of the variable resistor to
a maximum value among a plurality of possible values for the
resistance and setting the reference voltage to a minimum value
among a plurality of possible values for the reference voltage. The
method can include generating the reference voltage using a
digital-to-analog converter, and controlling a digital signal
provided to the digital-to-analog converter to modify the reference
voltage. Pumping current to the active loop filter can include
providing an offset current from a transistor operating in an
active region. Pumping current to or drawing current from the
active loop filter can include operating a P-type transistor in an
active region to provide an offset current to the active loop
filter, and operating an N-type transistor as a switch to turn on
or off the current drawn from the active loop filter in response to
the signal from the phase detector. The method can include
modifying a level of the reference voltage to adjust an amplitude
of the current drawn from the active loop filter.
BRIEF DESCRIPTION OF DRAWINGS
[0015] FIG. 1 is a block diagram of a fractional-N phase-locked
loop circuit.
[0016] FIG. 2 is a block diagram of a charge pump and an active
loop filter.
[0017] FIG. 3 is a block diagram of another charge pump and an
active loop filter.
[0018] FIG. 4 is a flow diagram of a process for operating a charge
pump phase-locked loop circuit.
DETAILED DESCRIPTION
[0019] Referring to FIG. 1, in some examples, a fractional-N
phase-locked loop circuit 100 includes a reference source that
provides a reference signal 102, a phase frequency detector 104, a
charge pump 106, an active loop filter 108, a voltage controlled
oscillator 110, and an N divider 112. The output of the voltage
controlled oscillator 110 is compared with the reference signal 102
at the phase frequency detector 104, and the phase difference is
used to generate a pump-down signal 116 to control the charge pump
106 to discharge an integrating capacitor in the active loop filter
108. The reference signal 102 can be a clock signal. The output of
the voltage controlled oscillator 110 can also be a clock signal.
The output voltage of the active loop filter 108 is provided to the
voltage controlled oscillator 110 to adjust the frequency and phase
of an output signal 118. The output signal 118 is sent to the N
divider 112 to generate a signal 120 that is compared with the
reference signal 102. The phase-locked loop forms a negative
feedback loop that is configured so that in a locked state, the
frequency of the reference signal 102 is equal to the frequency of
the output signal 118 divided by N, N being an integer at any given
time. In some examples, the reference signal 102 is generated by
dividing a source signal by a factor R, R being an integer at any
given time. The N and R factors are selected so that the
frequencies of the reference signal 102 and the signal 120 are
equal when the output signal 118 is at a desired frequency. The
values for N and R may be adjusted by another circuit, such as a
delta-sigma modulator. The N and R values may change over time such
that the average N value can have an integer and a fractional part,
and the average R value can have an integer and a fractional
part.
[0020] As will be described below, the charge pump 106 and the
active loop filter 108 are designed and configured to have a low
flicker noise and a small area size when the phase-locked loop
circuit 100 is implemented in an integrated circuit. In addition,
the active loop filter 108 has a reference voltage that can be
controlled in order to control the magnitude of the pump-down
current from the charge pump 106. The modification of the charge
pump current can be performed as part of an overall phase-locked
loop calibration that attempts to make the PLL loop gain constant.
In some examples, the charge pump current is modified to counteract
variations in the VCO gain.
[0021] Referring to FIG. 2, in some implementations, the charge
pump 106 includes a pump-up section 130 and a pump-down section
132. The pump-up section 130 functions as a current source that is
connected between a first voltage Vdd (e.g., provided by a positive
power supply) and a node 134 that is coupled to the active loop
filter 108. The pump-down section 132 functions as a current source
that is connected between the node 134 and a second voltage, such
as an electric ground (or a negative voltage provided by a negative
power supply). The pump-up section 130 provides a pump-up current
(e.g., I.sub.offset) to the active loop filter 108, whereas the
pump-down section 132 draws a pump-down current (e.g., I.sub.down)
from the active loop filter 108.
[0022] In this example, the pump-up section 130 includes a P-type
metal oxide semiconductor field effect transistor (MOSFET) 134 that
is biased to operate in the active region. The PMOS transistor 134
has a drain 136 that is connected to the positive power supply Vdd,
a source 138 that is connected to the node 134, and a gate 140 that
is connected to a bias voltage V.sub.pbias. The bias voltage
V.sub.pbias is selected to cause the PMOS transistor 134 to operate
in the active region to provide an offset current I.sub.offset.
[0023] The charge pump 106 may have several advantages. For
example, the charge pump 106 may have a lower noise. PMOS
transistors have lower intrinsic flicker noise (compared to NMOS
transistors). Because the offset current I.sub.offset is low, the
PMOS transistor 134 does not contribute much noise. The NMOS
transistor 142 also does not generate much noise because it is
either off or operates in the triode region. In current cellular
transceivers, a large portion of the in-band PLL phase noise is
contributed by charge pump noise. By lowering the charge pump
noise, the loop filter capacitor size can be reduced, and thus the
cost of a transceiver that includes the phase-locked loop circuit
100 can be reduced. The phase-locked loop circuit 100 can be used
in, e.g., mobile phones, televisions, and many other electronic
devices.
[0024] The phase-locked loop circuit 100 can be implemented as an
integrated circuit. Using an active PMOS transistor to generate the
leakage current I.sub.offset can reduce the area required for the
charge pump 106. Because the desired leakage current I.sub.offset
is small, if the leakage current is produced using a resistor, a
large resistor would be needed, requiring a larger area than the
PMOS transistor. Also, a PMOS transistor operating in the active
region may have a higher power supply rejection ratio (PSRR) to the
power supply than if a resistor were used. Using a resistor in the
pump-down section 132 allows a pump-down switch (e.g., 142) to be
placed on the ground side of the resistor, which minimizes charge
injection and is beneficial for charge pump linearity.
[0025] By operating the PMOS transistor 134 in the active region to
provide a constant offset current, it prevents the PLL circuit 100
from entering a so-called "dead zone" of the phase detector, which
refers to a narrow frequency band such that within this zone, the
feedback clock signal and the external clock signal are so close in
phase that there are no correction pulses out of the phase-detector
circuit. If the PLL circuit 100 enters the dead zone, the offset
current causes the PLL circuit 100 to move away from the dead zone
and the phase detector starts correcting phases again.
[0026] The pump-down section 132 includes an N-type MOSFET 142 and
a digitally controlled variable resistor 144. The variable resistor
144 can have, e.g., a bank of series and/or parallel connected
resistors that can be selected through switches. The transistor 142
functions as a switch that is controlled by a phase detection (PD)
signal 146 provided by the phase frequency detector 104. When the
PD signal 146 is high, the transistor 142 is turned on (operating
in the triode region), allowing a pump-down current I.sub.down to
flow through the resistor 144. When the PD signal 146 is low, the
NMOS transistor 142 is turned off, which shuts off the pump-down
current so that I.sub.down=0. In some examples, the leakage current
I.sub.offset is configure to be about 10% of the pump-down current
I.sub.down. The leakage current can also be other values in order
to avoid the dead zone.
[0027] In some examples, when the pump-down current level is
adjusted, the bias voltage V.sub.pbias is also adjusted so that the
leakage current I.sub.offset is maintained at about 10% of the
pump-down current I.sub.down. In some examples, an array of PMOS
transistors that can be individually selected are used in the
pump-up section 130, and one or more of the PMOS transistors are
selected to generate a desired leakage current.
[0028] The current flowing into the active loop filter is denoted
as I.sub.in. When the NMOS transistor 132 is turned off, the
leakage current I.sub.offset flows to the active loop filter 108,
so I.sub.in=I.sub.offset. When the NMOS transistor 142 is turned
on, the pump-down section 132 draws a pump-down current I.sub.down
so that the current flowing into the active loop filter is
I.sub.in=I.sub.offset-I.sub.down. The pump-down current I.sub.down
is equal to the voltage across the variable resistor 144 divided by
the resistance R.sub.CP of the variable resistor 144. The voltage
across the variable resistor 144 is equal to the voltage at node
134 minus the drain-source voltage V.sub.DS1 of the NMOS transistor
132. When the NMOS transistor is switched on, the drain-source
voltage V.sub.DS1 is typically small, so the pump-down current
I.sub.down is mostly determined by the voltage at the node 134 and
the resistance R.sub.CP of the variable resistor 144.
[0029] The active loop filter 108 includes an operational amplifier
150 that has a positive input node 160 and a negative input node
162. The negative input node 162 is connected to the node 134. A
digital-to-analog converter 158 receives a digital signal 164 and
outputs an analog signal 166 to the positive input node 160. A
feedback network is provided between an output 168 of the
operational amplifier 150 and the negative input 162. The feedback
network includes a capacitor C.sub.1 152 connected in series with a
resistor R.sub.1 154, and a capacitor C.sub.2 156 connected in
parallel with the capacitor C.sub.1 152. For example, the capacitor
C.sub.1 152 can be much larger than the capacitor C.sub.2 156.
[0030] The feedback network and the operational amplifier 150 form
a negative feedback loop. The gain of the amplifier and the
negative feedback cause the voltage at the negative input node 162
to be substantially equal to the voltage at the positive input node
160, which is equal to the output of the digital-to-analog
converter 158. By controlling the reference voltage Vref using the
digital-to-analog converter 158, the voltage at the negative input
node 162 can be controlled, which controls the pump-down current
I.sub.down and in turn controls the current I.sub.in flowing into
the active loop filter 108. The current I.sub.in affects the loop
gain of the phase-locked loop circuit 100. By using the reference
voltage V.sub.ref that is adjustable, the pump-down current
I.sub.down can be varied over a greater range than if a fixed
reference voltage V.sub.ref is used.
[0031] For example, if the reference voltage V.sub.ref is fixed at
1V, and we desire the pump-down current I.sub.down to vary from 1
.mu.A to 1 mA, the variable resistor 144 would need to vary from 1
M.OMEGA. to 1 k.OMEGA., which would require a resistor of a large
size. By using a digital-to-analog converter 158 that adjusts the
reference voltage V.sub.ref to be as low as 100 mV, the variable
resistor 144 only needs to vary from 1 k.OMEGA. to 100 k.OMEGA.,
which requires a much smaller size.
[0032] The pump-down current I.sub.down is affected by both the
resistance value R.sub.CP of the variable resistor, and the digital
input 164 to the digital-to-analog converter. In some examples, the
resistor value R.sub.CP is digitally controlled. In some examples,
both the resistor value R.sub.CP and the digital input 164 to the
digital-to-analog converter 158 are controlled by a control circuit
to maintain a constant loop gain for the phase-locked loop circuit
100.
[0033] For example, the loop gain G can be expressed as:
G=(I.sub.CP*K.sub.v)/(N*C.sub.t),
in which I.sub.CP represents the charge pump current (unit: A),
K.sub.v represents the VCO tuning gain (unit: Hz/V), N represents a
programmed value of the feedback divider 112 (unitless), and
C.sub.t=C1+C2 represents the loop filter capacitor value (unit:
F).
[0034] The charge pump current I.sub.CP affects the loop gain. In
general, it is preferable to have a constant loop gain across all
process/voltage/temperature (PVT) conditions. During operation,
sometimes the VCO may have a large gain variation. The VCO gain is
expressed as change in frequency per change in voltage or units of
Hz/V. A calibration state machine measures the gain of the VCO, and
based on the measured gain it will adjust the charge pump current
to compensate for variations in the VCO gain, thereby maintaining a
constant PLL loop gain.
[0035] Because the pump-down current I.sub.down is controlled by
controlling the reference voltage V.sub.ref, it is preferable that
the pump-up leakage current be unaffected by the changes in the
reference voltage V.sub.ref. Using a PMOS transistor operating in
the active region instead of using a resistor achieves this
goal.
[0036] During operation of the phase-locked loop circuit 100, the
bias voltage V.sub.bias causes the PMOS transistor 134 to operate
in the active region to maintain a constant leakage current
I.sub.offset. The phase/frequency detector 104 controls the PD
signal 146 based on the results of the comparison between the
feedback signal 120 and the reference signal 102. When the PD
signal 146 is high, the NMOS transistor 132 is turned on, and a
pump-down current approximately equal to
I.sub.down=V.sub.ref/R.sub.CP flows through the resistor 144, and a
discharge current -I.sub.in=-(I.sub.offset-I.sub.down) discharges
the capacitors C1 and C2 in the active loop filter 108. When the PD
signal 146 is low, the NMOS transistor 142 is turned off, and a
pump-up current equal to the leakage current I.sub.offset charges
the capacitors C.sub.1 and C.sub.2 in the active loop filter 108.
The magnitude of the pump-down current I.sub.down can be adjusted
by changing the resistance R.sub.CP of the variable resistor 144,
changing the reference voltage V.sub.ref, or both. The pump-down
current I.sub.down (as well as the current drawn from the active
loop filter 108) can be set to a minimum value by setting the
resistance of the variable resistor 144 to a maximum value among a
plurality of possible values for the resistance, and setting the
reference voltage V.sub.ref to a minimum value among a plurality of
possible values for the output of the digital-to-analog converter
158.
[0037] Referring to FIG. 3, in some examples, a charge pump 170 can
be implemented by using a pump-down section 172 that generates a
constant leakage current, and a pump-up section 174 that is
controlled by an inverted pump-up signal 176 from the
phase/frequency detector 104. Each of the pump-down section 172 and
the pump-up section 174 functions as a current source. In this
example, the pump-down section 172 includes an NMOS transistor 178
that is biased by a bias voltage V.sub.nbias to operate in an
active region to provide a pump-down leakage current. The pump-up
section 174 includes a PMOS transistor 180 that functions as a
switch to turn on or off a pump-up current that flows through a
digitally controlled variable resistor 182.
[0038] When the reference voltage V.sub.ref is adjusted by using
the digital-to-analog converter 158, the voltage at the negative
input node 162 follows the reference voltage V.sub.ref at the
positive input node 160. When V.sub.ref varies, the pump-down
current flowing through the NMOS transistor 178 remains
substantially the same, while the pump-up current I.sub.up flowing
through the variable resistor 182 depends on the reference voltage
V.sub.ref according to the relationship:
I.sub.up=(Vdd-V.sub.DS2-V.sub.ref)/R.sub.CP,
where V.sub.DS2 is the drain-source voltage for the PMOS transistor
180.
[0039] The charge pump 170 has several advantages, similar to those
of the charge pump 106 (FIG. 2). For example, using an active NMOS
transistor to generate the leakage current can reduce the area
required for the charge pump 170. Because the desired leakage
current is small, if the leakage current is produced using a
resistor, a large resistor would be needed, requiring a larger area
than the NMOS transistor. By using a reference voltage V.sub.ref
that is adjustable, the pump-up current can be varied over a
greater range than if a fixed reference voltage V.sub.ref is
used.
[0040] FIG. 4 is a flow diagram of an example process 200 for
operating a charge pump phase-locked loop circuit. For example, the
process 200 can be implemented using the phase-locked loop circuit
100. In the process 200, an adjustable reference voltage is
provided to a first node of an active loop filter (202). For
example, the first node can be the positive input node 160 of the
operational amplifier 150. Current is pumped to or drawn from a
second node of the active loop filter in response to a signal from
a phase detector (204). For example, the second node can be the
negative input node 162 of the operational amplifier 150. A signal
from the active loop filter is provided to an oscillator (206). For
example, the oscillator can be the voltage controlled oscillator
110. A level of the reference voltage is modified and/or a
resistance value of a variable resistor to adjust an amplitude of
the current drawn from or pumped to the active loop filter (208).
For example, the reference voltage can be the reference voltage
V.sub.ref generated by the digital-to-analog converter 158.
[0041] For example, in the process 200, drawing current from the
active loop filter can include passing at least a portion of the
current through the variable resistor. A resistance value of the
variable resistor can be modified to adjust the amplitude of the
current drawn from the active loop filter. The current drawn from
the active loop filter can be set to a minimum value by setting the
resistance of the variable resistor to a maximum value among a
plurality of possible values for the resistance and setting the
reference voltage to a minimum value among a plurality of possible
values for the reference voltage. The reference voltage can be
generated using a digital-to-analog converter, and a digital signal
provided to the digital-to-analog converter can be controlled to
modify the reference voltage. Pumping current to the active loop
filter can include providing an offset current from a transistor
operating in an active region. Pumping current to or drawing
current from the active loop filter can include operating a P-type
transistor in an active region to provide an offset current to the
active loop filter, and operating an N-type transistor as a switch
to turn on or off the current drawn from the active loop filter in
response to the signal from the phase detector. A level of the
reference voltage can be modified to adjust an amplitude of the
current drawn from the active loop filter.
[0042] A number of implementations have been described.
Nevertheless, it will be understood that various modifications may
be made. For example, elements of one or more implementations may
be combined, deleted, modified, or supplemented to form further
implementations. As yet another example, the logic flows depicted
in the figures do not require the particular order shown, or
sequential order, to achieve desirable results. In addition, other
steps may be provided, or steps may be eliminated, from the
described flows, and other components may be added to, or removed
from, the described systems. Accordingly, other implementations are
within the scope of the following claims.
* * * * *