U.S. patent application number 14/315922 was filed with the patent office on 2014-10-16 for semiconductor device and method of manufacturing semiconductor device.
The applicant listed for this patent is FUJITSU SEMICONDUCTOR LIMITED. Invention is credited to Taiji Ema, Kazushi Fujita.
Application Number | 20140308783 14/315922 |
Document ID | / |
Family ID | 45889073 |
Filed Date | 2014-10-16 |
United States Patent
Application |
20140308783 |
Kind Code |
A1 |
Ema; Taiji ; et al. |
October 16, 2014 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR
DEVICE
Abstract
A first transistor includes a first impurity layer of a first
conduction type formed in a first region of a semiconductor
substrate, a first epitaxial semiconductor layer formed above the
first impurity layer, a first gate insulating film formed above the
first epitaxial semiconductor layer, a first gate electrode formed
above the first gate insulating film, and first source/drain
regions of a second conduction type formed in the first epitaxial
semiconductor layer and in the semiconductor substrate in the first
region. A second transistor includes a second impurity layer of the
first conduction type formed in a second region of the
semiconductor substrate, a second epitaxial semiconductor layer
formed above the second impurity layer and being thinner than the
first epitaxial semiconductor layer, a second gate insulating film
formed above the second epitaxial semiconductor layer, a second
gate electrode formed above the second gate insulating film, and
second source/drain regions of the second conduction type formed in
the second epitaxial semiconductor layer and in the semiconductor
substrate in the second region.
Inventors: |
Ema; Taiji; (Inabe, JP)
; Fujita; Kazushi; (Kuwana, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
FUJITSU SEMICONDUCTOR LIMITED |
Yokohama-shi |
|
JP |
|
|
Family ID: |
45889073 |
Appl. No.: |
14/315922 |
Filed: |
June 26, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13170762 |
Jun 28, 2011 |
8822280 |
|
|
14315922 |
|
|
|
|
Current U.S.
Class: |
438/232 |
Current CPC
Class: |
H01L 21/823807 20130101;
H01L 29/7833 20130101; H01L 29/1045 20130101; H01L 27/088 20130101;
H01L 21/823828 20130101; H01L 21/82385 20130101; H01L 21/823857
20130101; H01L 21/823814 20130101; H01L 29/105 20130101 |
Class at
Publication: |
438/232 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 30, 2010 |
JP |
2010-220777 |
Claims
1. A method of manufacturing a semiconductor device comprising:
forming a first impurity layer of a first conduction type in a
first region of a substrate and a second impurity layer of the
first conduction type in a second region of the substrate;
epitaxially growing a semiconductor layer above the semiconductor
substrate after forming the first impurity layer and the second
impurity layer; removing a part of the semiconductor layer in the
first region to make the semiconductor layer in the first region
thinner than the semiconductor layer in the second region; forming
a first gate insulating film on the semiconductor layer after
removing the part of the semiconductor layer; forming a first gate
electrode above the first gate insulating film in the first region
and a second gate electrode above the first gate insulating film in
the second region; forming a first source region and a first drain
region in the semiconductor layer in the first region; and forming
a second source region and a second drain region in the
semiconductor layer in the second region.
2. The method of manufacturing a semiconductor device according to
claim 1, further comprising: before growing the semiconductor
layer, forming a third impurity region of a second conduction type
in a third region of the semiconductor substrate and a fourth
impurity region of the second conduction type in a fourth region of
the semiconductor substrate; a forming the first gate electrode and
the second gate electrode, forming a third source region and a
third drain region in the semiconductor layer in the third region;
and after a forming the first gate electrode and the second gate
electrode, forming a fourth source region and a fourth drain region
in the semiconductor layer in the fourth region, wherein in
removing the part of the semiconductor layer in the first region, a
part of the semiconductor layer in the third region is removed to
make the semiconductor layer in the third region thinner than the
semiconductor layer in the fourth region, and in forming the first
gate electrode and the second gate electrode, a third gate
electrode is formed above the first gate insulating film in the
third region and a fourth gate electrode is formed above the first
gate insulating film in the fourth region.
3. The method of manufacturing a semiconductor device according to
claim 1, further comprising: before growing the semiconductor
layer, forming a fifth impurity layer of the first conduction type
in a fifth region of the semiconductor substrate; forming a second
gate insulating film, that has a thickness different from a
thickness of the first gate insulating film, above the
semiconductor layer in the fifth region, and after a forming the
first gate electrode and the second gate electrode, forming a fifth
source region and a fifth drain region in the semiconductor layer
in the fifth region, wherein in removing the part of the
semiconductor layer, a part of the semiconductor layer in the fifth
region is removed to make the semiconductor layer in the fifth
region thinner than the semiconductor layer in the first region,
and in forming the first gate electrode and the second gate
electrode, a fifth gate electrode is formed above the second gate
insulating film.
4. The method of manufacturing a semiconductor device according to
claim 2, further comprising: before growing the semiconductor
layer, forming a fifth impurity layer of the first conduction type
in a fifth region of the semiconductor substrate; forming a second
gate insulating film, that has a thickness different from a
thickness of the first gate insulating film, above the
semiconductor layer in the fifth region, and after a forming the
first gate electrode and the second gate electrode, forming a fifth
source region and a fifth drain region in the semiconductor layer
in the fifth region, wherein in removing the part of the
semiconductor layer, a part of the semiconductor layer in the fifth
region is removed to make the semiconductor layer in the fifth
region thinner than the semiconductor layer in the second region,
and in forming the first gate electrode and the second gate
electrode, a fifth gate electrode is formed above the second gate
insulating film.
5. The method of manufacturing a semiconductor device according to
claim 4, further comprising: before growing the semiconductor
layer, forming a sixth impurity layer of the second conduction type
in a sixth region of the semiconductor substrate; after a forming
the first gate electrode and the second gate electrode, forming a
sixth source region and a sixth drain region in the semiconductor
layer in the sixth region, wherein in removing the part of the
semiconductor layer, a part of the semiconductor layer in the sixth
region is removed to make the semiconductor layer in the sixth
region thinner than the semiconductor layer in the second region,
the second gate insulating layer is formed on the semiconductor
layer in the sixth region, and in forming the first gate electrode
and the second gate electrode, a sixth gate electrode is formed
above the second gate insulating film.
6. The method of manufacturing a semiconductor device according to
claim 3, wherein: forming the first gate insulating film and the
second gate insulating film includes: thermally oxidizing the
semiconductor layer to form an oxide film on a surface of the
semiconductor layer; removing the oxide film in a region the first
gate insulating film is formed; and thermally oxidizing the surface
of the semiconductor layer to form the first gate insulating film
and to form the second gate insulating film of the oxide film
further oxidized.
7. The method of manufacturing a semiconductor device according to
claim 1, further comprising: after removing the part of the
semiconductor layer in the first region and before forming the
first gate insulating film, forming a device isolation film in the
semiconductor substrate.
8. The method of manufacturing a semiconductor device according to
claim 1, wherein the semiconductor layer is a non-doped
semiconductor layer.
9. The method of manufacturing a semiconductor device according to
claim 1, wherein the semiconductor layer is an epitaxial silicon
layer.
10. The method of manufacturing a semiconductor device according to
claim 1, wherein the first source region and the first drain region
are formed in the semiconductor layer and the first impurity layer,
and the second source region and the second drain region are formed
in the semiconductor layer and the second impurity layer.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 13/170,762, filed Jun. 28, 2011, which is based upon and claims
the benefit of priority of the prior Japanese Patent Application
No. 2010-220777, filed on Sep. 30, 2010, the entire contents of
which are incorporated herein by reference.
FIELD
[0002] The embodiments discussed herein are related to a
semiconductor device and a method of manufacturing a semiconductor
device.
BACKGROUND
[0003] As semiconductor devices are downsized and highly
integrated, the fluctuations of the threshold voltages of the
transistors due to statistical fluctuations of the channel impurity
becomes conspicuous. The threshold voltage is one of important
parameters for deciding the performance of the transistors, and to
manufacture semiconductor device of high performance and high
reliability, it is important to decrease the fluctuations of the
threshold voltage due to the statistical fluctuations of the
impurity.
[0004] As one technique of decreasing the fluctuations of the
threshold voltage due to the statistical fluctuations is proposed
the technique that a non-doped epitaxial silicon layer is formed on
a highly doped channel impurity layer having a steep impurity
concentration distribution.
[0005] The following are examples of related: U.S. Pat. No.
6,482,714; U.S. Patent Publication No. 2009/0108350; A. Asenov,
"Suppression of Random Dopant-Induced Threshold Voltage
Fluctuations in Sub-0.1-.mu.m MOSFET's with Epitaxial and
.delta.-doped Channels", IEEE Transactions on Electron Devices,
vol. 46, No. 8. p. 1718, 1999; Woo-Hyeong Lee, "MOS Device
Structure Development for ULSI: Low Power/High Speed Operation",
Microelectron. Reliab., Vol. 37, No. 9, pp. 1309-1314, 1997; and A.
Hokazono et al., "Steep Channel Profiles in n/pMOS Controlled by
Boron-Doped Si:C Layers for Continual Bulk-CMOS Scaling",
IEDM09-673.
[0006] No method for incorporating the proposed techniques
described above in the semiconductor device manufacturing processes
have been specifically proposed. Especially, new problems which
will take place by adopting the above-described techniques in
manufacturing processes, and their solving means have not been
specifically studied.
SUMMARY
[0007] According to one aspect of an embodiment, there is provided
a method of manufacturing a semiconductor device including ion
implanting a first impurity of a first conduction type in a first
region and a second region of a semiconductor substrate, activating
the first impurity to form a first impurity layer in the first
region and the second region, epitaxially growing a semiconductor
layer above the semiconductor substrate with the first impurity
layer formed in, forming above the semiconductor layer a mask
exposing the first region and covering the second region, removing
partially the semiconductor layer in the first region by using the
mask, forming a first gate insulating film above the semiconductor
layer after the mask is removed, and forming a first gate electrode
above the first gate insulating film in the first region and a
second gate electrode above the first gate insulating film in the
second region.
[0008] According to another aspect of an embodiment, there is
provided a semiconductor device including a first transistor
including a first impurity layer of a first conduction type formed
in a first region of a semiconductor substrate, a first epitaxial
semiconductor layer formed above the first impurity layer, a first
gate insulating film formed above the first epitaxial semiconductor
layer, a first gate electrode formed above the first gate
insulating film, and first source/drain regions of a second
conduction type formed in the first epitaxial semiconductor layer
and in the semiconductor substrate in the first region, and a
second transistor including a second impurity layer of the first
conduction type formed in a second region of the semiconductor
substrate, a second epitaxial semiconductor layer formed above the
second impurity layer and being thinner than the first epitaxial
semiconductor layer, a second gate insulating film formed above the
second epitaxial semiconductor layer, a second gate electrode
formed above the second gate insulating film, and second
source/drain regions of the second conduction type formed in the
second epitaxial semiconductor layer and in the semiconductor
substrate in the second region.
[0009] The object and advantages of the embodiment will be realized
and attained by means of the elements and combinations particularly
pointed out in the claims.
[0010] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are not restrictive of the embodiments, as
claimed.
BRIEF DESCRIPTION OF DRAWINGS
[0011] FIGS. 1 and 2 are diagrammatic sectional views illustrating
a structure of a semiconductor device according to an
embodiment;
[0012] FIGS. 3-20 are sectional views illustrating a method of
manufacturing the semiconductor device according to the
embodiment;
[0013] FIGS. 21A-21D are sectional views illustrating a method of
manufacturing a semiconductor device according to a first reference
example;
[0014] FIGS. 22A-22B, 23A-23B and 24A-24B are sectional views
illustrating a method of manufacturing a semiconductor device
according to a second reference example; and
[0015] FIGS. 25A-25B, 26A-26B, 27A-27B, 28A-28B, 29A-29B and 30 are
sectional views illustrating a method of manufacturing a
semiconductor device according to a third reference example.
DESCRIPTION OF EMBODIMENTS
An Embodiment
[0016] A semiconductor device and a method of manufacturing a
semiconductor device according to an embodiment will be described
with reference to FIGS. 1 to 20.
[0017] FIGS. 1 and 2 are diagrammatic sectional views illustrating
a structure of the semiconductor device according to the present
embodiment. FIGS. 3-20 are sectional views illustrating a method of
manufacturing the semiconductor device according to the present
embodiment.
[0018] First, the structure of the semiconductor device according
to the present embodiment will be described with reference to FIGS.
1 and 2.
[0019] Above a silicon substrate 10, a low-threshold
voltage/low-voltage NMOS transistor (LVt LV NMOS) and a
low-threshold voltage/low-voltage PMOS transistor (LVt LV PMOS) are
formed. These low-threshold voltage/low-voltage transistors are
transistors having a low threshold voltage which operate at low
voltage and are used in a circuit unit which requires high speed
operation.
[0020] Above the silicon substrate 10, a high-threshold
voltage/low-voltage NMOS transistor (HVt LV NMOS) and a
high-threshold voltage/low-voltage PMOS transistor (HVt LV PMOS)
are formed. These high-threshold voltage/low-voltage transistors
are transistors having a high threshold voltage which operate at
low voltage and are used in a circuit unit which requires low
leakage current.
[0021] Above the silicon substrate 10, a high voltage NMOS
transistor (HV NMOS) and a high voltage PMOS transistor (HV PMOS)
are formed. These high voltage transistors are used in a circuit
unit, e.g., 3.3V I/O, which high voltage is applied to.
[0022] The high-threshold voltage/low-voltage NMOS (HVt LV NMOS) is
formed in a high-threshold voltage/low-voltage NMOS transistor
forming region 16H of the silicon substrate 10.
[0023] In the silicon substrate 10 in the high-threshold
voltage/low-voltage NMOS transistor forming region 16H, a p-well 20
and a p-type highly doped impurity layer 22 are formed. Above the
p-type highly doped impurity layer 22, a silicon layer 48
epitaxially grown on the silicon substrate 10 is formed. Above the
silicon layer 48, a gate insulating film 64a is formed. Above the
gate insulating film 64a, a gate electrode 66 is formed. In the
silicon layer 48 and the silicon substrate 10 on both sides of the
gate electrode 66, source/drain regions 78 are formed. Thus, the
high-threshold voltage/low-voltage NMOS transistor (HVt LV NMOS) is
formed.
[0024] The low-threshold voltage/low-voltage NMOS transistor (LVt
LV NMOS) is formed in a low-threshold voltage/low-voltage NMOS
transistor forming region 16L of the silicon substrate 10.
[0025] In the silicon substrate 10 in the low-threshold
voltage/low-voltage NMOS transistor forming region 16L, a p-well 20
and a p-type highly doped impurity layer 22 are formed. Above the
p-type highly doped impurity layer 22, a silicon layer 48
epitaxially grown on the silicon substrate 10 is formed. Above the
silicon layer 48, a gate insulating film 64a is formed. Above the
gate insulating film 64a, a gate electrode 66 is formed. In the
silicon layer 48 and the silicon substrate 10 on both sides of a
gate electrode 66, source/drain regions 78 are formed. Thus, the
low-threshold voltage/low-voltage NMOS transistor (LVt LV NMOS) is
formed.
[0026] The p-well 20 and the p-type highly doped impurity layer 22
in the high-threshold voltage/low-voltage NMOS transistor forming
region 16H and the low-threshold voltage/low-voltage NMOS
transistor forming region 16L are simultaneously formed and have
the same impurity concentration distribution.
[0027] The threshold voltage of the high-threshold
voltage/low-voltage NMOS transistor (HVt LV NMOS) and the
low-threshold voltage/low-voltage NMOS transistor (LVt LV NMOS) are
adjusted by the film thickness difference of the silicon layer 48.
That is, the film thickness of the silicon layer 48 formed in the
high-threshold voltage/low-voltage NMOS transistor forming region
16H is thinner than the film thickness of the silicon layer 48
formed in the low-threshold voltage/low-voltage NMOS transistor
forming region 16L. Thus, the threshold voltage of the
high-threshold voltage/low-voltage NMOS transistor (HVt LV NMOS) is
higher than the threshold voltage of the low-threshold
voltage/low-voltage NMOS transistor (LVt LV NMOS).
[0028] The low-threshold voltage/low-voltage PMOS (LVt LV PMOS) is
formed in the low-threshold voltage/low-voltage PMOS transistor
forming region 24L of the silicon substrate 10.
[0029] In the silicon substrate 10 in the low-threshold
voltage/low-voltage PMOS transistor forming region 24L, an n-well
28 and an n-type highly doped impurity layer 30 are formed. Above
the n-type highly doped impurity layer 30, a silicon layer 48
epitaxially grown on the silicon substrate 10 is formed. Above the
silicon layer 48, a gate insulating film 64a is formed. Above the
gate insulating film 64a, a gate electrode 66 is formed. In the
silicon layer 48 and the silicon substrate 10 on both sides of the
gate electrode 66, source/drain regions 80 are formed. Thus, the
low-threshold voltage/low-voltage PMOS transistor (LVt LV PMOS) is
formed.
[0030] In the high-threshold voltage/low-voltage PMOS (HVt LV PMOS)
is formed in a high-threshold voltage/low-voltage PMOS transistor
forming region 24H of the silicon substrate 10.
[0031] In the silicon substrate 10 of the high-threshold
voltage/low-voltage PMOS transistor (HVt LV PMOS) forming region
24H, an n-well 28 and an n-type highly doped impurity layer 30 are
formed. Above the n-type highly doped impurity layer 30, a silicon
layer 48 epitaxially grown on the silicon substrate 10 is formed.
Above the silicon layer 48, a gate insulating film 64a is formed.
Above the gate insulating film 64a, a gate electrode 66 is formed.
In the silicon layer 48 and the silicon substrate 10 on both sides
of the gate electrode 66, source/drain regions 80 are formed. Thus,
the high-threshold voltage/low-voltage PMOS transistor (HVt LV
PMOS) is formed.
[0032] Here, the n-well 28 and the n-type highly doped impurity
layers 30 formed in the high-threshold voltage/low-voltage PMOS
transistor forming region 24H and the low-threshold
voltage/low-voltage PMOS transistor forming region 24L are
simultaneously formed and have the same impurity concentration
distribution.
[0033] The threshold voltages of the high-threshold
voltage/low-voltage PMOS transistor (HVt LV PMOST) and the
low-threshold voltage/low-voltage PMOS transistor (LVt LV PMOS) are
adjusted by the film thickness difference between the silicon
layers 48. That is, the thickness of the silicon layer 38 formed in
the high-threshold voltage/low-voltage PMOS transistor (HVt LV
PMOS) formed region 24H is smaller than the thickness of the
silicon layer 48 formed in low-threshold voltage/low-voltage PMOS
transistor (LVT Lv) PMOS. Thus, the threshold voltage of the
high-threshold voltage/low-voltage PMOS transistor (Hvt LV PMOS) is
higher than the threshold voltage of the low-threshold
voltage/low-voltage PMOS transistor (LVt LV PMOS).
[0034] The high voltage NMOS transistor (HV NMOS) is formed in a
high voltage NMOS transistor forming region 32 of the silicon
substrate 10.
[0035] In the silicon substrate 10 in the high voltage NMOS
transistor forming region 32, a p-well 36 and a p-type impurity
layer 38 are formed. To improve the junction breakdown voltage, the
p-type impurity layer 38 has a lower concentration and a gradual
impurity distribution than the p-type highly doped impurity layers
22 of the low voltage NMOS transistors. Above the p-type impurity
layer 38, a silicon layer 48 epitaxially grown on the silicon
substrate 10 is formed. Above the silicon layer 48, a gate
insulating film 60a thicker than the gate insulating films 64a of
the low voltage transistors is formed. Above the gate insulating
film 60a, a gate electrode 66 is formed. In the silicon layer 48
and the silicon substrate 10 on both sides of the gate electrode
66, source/drain regions 78 are formed. Thus, the high voltage NMOS
transistor (HV NMOS) is formed.
[0036] A high voltage PMOS transistor (HV PMOS) is formed in a high
voltage PMOS transistor forming region 40 of the silicon substrate
10.
[0037] In the silicon substrate 10 in the high voltage PMOS
transistor forming region 40, an n-well 44 and an n-type impurity
layer 46 are formed. To improve the junction breakdown voltage, the
n-type impurity layer 46 has a lower concentration and a gradual
impurity distribution than the n-type highly doped impurity layers
30 of the low voltage PMOS transistors. Above the n-type impurity
layer 46, a silicon layer 48 epitaxially grown on the silicon
substrate 10 is formed. Above the silicon layer 48, a gate
insulating film 60a thicker than the gate insulating films 64a of
the low voltage transistors is formed. Above the gate insulating
film 60a, a gate electrode 66 is formed. In the silicon layer 48
and the silicon substrate 10 on both sides of the gate electrode
66, source/drain regions 80 are formed. Thus, the high voltage PMOS
transistor (HV PMOS) is formed.
[0038] Above the gate electrodes 66 and the source/drain regions
78, 80 of the respective transistors, a metal silicide film 84 is
formed.
[0039] Above the silicon substrate 10 with the transistors of the
six kinds formed on, an inter-layer insulating film 86 is formed.
In the inter-layer insulating film 86, contact plugs 88 connected
to the transistors are buried. To the contact plugs 88,
interconnections 90 are connected.
[0040] As described above, the semiconductor device according to
the present embodiment includes four kinds of low voltage
transistors and two kinds of high voltage transistors.
[0041] As exemplified in FIG. 2, the low voltage transistors of the
four kinds each include in the channel region 106, a highly-doped
impurity layer 108 having a steep impurity concentration
distribution, and a non-doped silicon layer 110 epitaxially grown
on the highly-doped impurity layer 108. Such transistor structure
is effective to suppress the threshold voltage fluctuations of the
transistors due to the statistical fluctuations of the
impurity.
[0042] As described above, the threshold voltages of the
high-threshold voltage/low-voltage NMOS transistor (HVt LV NMOS)
and the low-threshold voltage/low-voltage NMOS transistor (LVt LV
NMOS) are adjusted by the thickness difference of the silicon
layers 48. Accordingly, it is not necessary to differ the impurity
profiles of the channel regions between the high-threshold
voltage/low-voltage NMOS transistor (HVt LV NMOS) and the
low-threshold voltage/low-voltage NMOS transistor (LVt LV NMOS),
which can simplify the manufacturing process.
[0043] Similarly, the threshold voltages of the high-threshold
voltage/low-voltage PMOS transistor (HVt LV PMOS) and the
low-threshold voltage/low-voltage PMOS transistor (LVt LV PMOS) are
also adjusted by the thickness difference of the silicon layers 48.
Accordingly, it is not necessary to differ the impurity profiles of
the channel regions between the high-threshold voltage/low-voltage
PMOS transistor (HVt LV PMOS) and the low-threshold
voltage/low-voltage PMOS transistor (LVt LV PMOS), which can
simplify the manufacturing process.
[0044] Making the respective thicknesses of the silicon layer 48 of
the high threshold voltage transistors and the silicon layer 48 of
the low threshold voltage transistors equal to each other between
the NMOS transistors and the PMOS transistors can further simplify
the manufacturing process. Thus, the manufacturing cost can be
decreased.
[0045] Next, the method of manufacturing the semiconductor device
according to the present embodiment will be described with
reference to FIGS. 3 to 20.
[0046] First, by photolithography and etching, a trench to be used
as the mark for the mask alignment is formed in a region other than
the product to be formed region of the silicon substrate 10 (e.g.,
a scribe region).
[0047] In the method of manufacturing the semiconductor device
according to the present embodiment, before device isolation
insulating film 58 is formed, the wells and the channel impurity
layers are formed. The trench 12 is used as the mark for the mask
alignment in the lithography process made before the device
isolation insulating film 58 is formed (e.g., the lithography
process for forming the wells and the channel impurity layers).
[0048] The wells and the channel impurity layers are formed before
the device isolation insulating films 58 are formed so as to
suppress the film thickness decrease of the device isolation
insulating film 58 in removing the silicon oxide films 14, 52, 60
(refer to a first reference example and a second reference example
described later).
[0049] Next, above the entire surface of the silicon substrate 10,
a silicon oxide film 14 as the protection film of the surface of
the silicon substrate 10 is formed by, e.g., thermal oxidation
method (FIG. 3).
[0050] Next, by photolithography, a photoresist film 18 exposing
the low voltage NMOS transistor forming regions and covering the
rest region is formed. For the alignment for the photolithography,
the trench 12 is used as the alignment mark.
[0051] Next, ion implantation is made with the photoresist film 18
as the mask to form a p-well 20 and p-type highly doped impurity
layers 22 in the low voltage NMOS transistor forming regions 16
(FIG. 4).
[0052] The p-well 20 is formed, e.g., by implanting boron ions
(B.sup.30) respectively in 4 directions tilted to the normal
direction of the substrate under the conditions of 150 keV
acceleration energy and 7.5.times.10.sup.12 cm.sup.-2 dose. The
p-type highly doped impurity layers 22 are formed, e.g., by
respectively implanting germanium ions (Ge.sup.+) under the
conditions of 50 keV acceleration energy and 5.times.10.sup.14
cm.sup.-2, carbon ions (C.sup.+) under the conditions of 3 keV
acceleration energy and 3.times.10.sup.14 cm.sup.-2 and boron ions
(B.sup.+) under the conditions of 2 keV acceleration energy and
3.times.10.sup.13 cm.sup.-2. Germanium acts to amorphize the
silicon substrate 10 to thereby prevent the channeling of the boron
ions and amorphize the silicon substrate 10 to increase the
probability of positioning the carbon at the lattice points. The
carbon positioned at the lattice points acts to suppress the
diffusion of boron. In view of this, it is preferable to ion
implant germanium before carbon and boron, and the p-well 20 is
formed before the p-type highly doped impurity layers 22.
[0053] Next, by, e.g., ashing method, the photoresist film 18 is
removed.
[0054] Then, by photolithography, a photoresist film 26 exposing
the low voltage PMOS transistor forming regions and covering the
rest region is formed. For the alignment for the photolithography,
the trench 12 is used as the alignment mark.
[0055] Next, with the photoresist film 26 as the mask, ion
implantation is made to form an n-well 28 and n-type highly doped
impurity layers 30 are formed in the low voltage PMOS transistor
forming regions 24 of the silicon substrate 10 (FIG. 5).
[0056] The n-well 28 is formed, e.g., by implanting respectively in
4 directions tilted to the normal direction of the substrate
phosphorus ions (P.sup.+) under the conditions of 360 keV
acceleration energy and 7.5.times.10.sup.12 cm.sup.-2 dose and
arsenic ions (As.sup.+) under the conditions of 80 keV acceleration
energy and 6.times.10.sup.12 cm.sup.-2 dose. The n-type highly
doped impurity layers 30 are formed, e.g., by implanting arsenic
ions under the conditions of 6 keV acceleration energy and
2.times.10.sup.13 cm.sup.-2 dose, or antimony ions (Sb.sup.+) under
the conditions of 20 keV-50 keV acceleration energy (e.g., 20 keV)
and 0.5.times.10.sup.13 cm.sup.-2-2.0.times.10.sup.13 cm.sup.-2
dose (e.g., 1.5.times.10.sup.13 cm.sup.-2).
[0057] Next, by, e.g., ashing method, the photoresist film 26 is
removed.
[0058] In the method of manufacturing the semiconductor device
according to the present embodiment, the p-well 20 and the p-type
highly doped impurity layers 22 of the high-threshold
voltage/low-voltage NMOS transistor (HVt LV NMOS) and the
low-threshold voltage/low-voltage NMOS transistor (LVt LV NMOS) are
simultaneously formed. The n-well 28 and the n-type highly doped
impurity layer 30 of the high-threshold voltage/low-voltage PMOS
transistor (HVt LV PMOS) and the low-threshold voltage/low-voltage
PMOS transistor (LVt LV PMOS) are simultaneously formed. Thus, the
lithography step for implanting ions into the channel regions of
the 4 low voltage transistors is 2 steps.
[0059] On the other hand, when the high-threshold
voltage/low-voltage NMOS transistor (Hvt LV NMOS) and the
low-threshold voltage/low-voltage NMOS transistor (LVt LV NMOS) are
separately formed by changing concentrations or distributions of
the p-well 20 and the p-type highly doped impurity layers 22, the
required lithography step is at least 2 steps. Similarly, when the
high-threshold voltage/low-voltage PMOS transistor (HVt LV PMOS)
and the low-threshold voltage/low-voltage PMOS (LVt LV PMOS) are
formed separately by changing concentrations and distributions of
the n-well 28 and the n-type highly doped impurity layers 30, the
required lithography step is at least 2 steps. The lithography step
required for the ion implantation into the channel regions of the 4
low voltage transistors is at least 4 steps.
[0060] Thus, according to the method of manufacturing the
semiconductor device according to the present embodiment, in the
process of the channel ion implantation for the 4 low voltage
transistors, the lithography steps can be decreased by at least 2
steps (refer to a third reference example described later).
[0061] Then, by photolithography, a photoresist film 34 exposing
the high voltage NMOS transistor forming region and covering the
rest region is formed. For the alignment for the photolithography,
the trench 12 is used as the alignment mark.
[0062] Next, with the photoresist film 34 as the mask, ion
implantation is made to form a p-well 36 and a p-type impurity
layer 38 in the high voltage NMOS transistor forming region 32 of
the silicon substrate 10 (FIG. 6).
[0063] The p-well 36 is formed, e.g., by implanting respectively in
4 directions tilted to the normal direction of the substrate boron
ions under the conditions of 150 keV acceleration energy and
7.5.times.10.sup.12 cm.sup.-2 dose. The p-type impurity layer 38 is
formed, e.g., by implanting boron ions under the conditions of 2
keV acceleration energy and 5.times.10.sup.12 cm.sup.-2 dose. In
the high voltage operative NMOS transistor, in view of making the
impurity concentration distribution of the channel region gradual
to thereby improve the junction breakdown voltage and the hot
carrier immunity, neither carbon nor germanium is ion
implanted.
[0064] Next, by, e.g., ashing method, the photoresist film 34 is
removed.
[0065] Next, by photolithography, a photoresist film 42 exposing
the high voltage PMOS transistor forming region and covering the
reset region is formed. For the alignment for the photolithography,
the trench 12 is used as the alignment mark.
[0066] Next, with the photoresist film 42 as the mask, ion
implantation is made to form an n-well 44 and an n-type impurity
layer 46 in the high voltage PMOS transistor forming region 40 of
the silicon substrate 10 (FIG. 7).
[0067] The n-well 44 is formed, e.g., by implanting respectively in
4 directions tilted to the normal direction of the substrate
phosphorus ions at 360 keV acceleration energy and
7.5.times.10.sup.12 cm.sup.-2 dose. The n-type impurity layer 46 is
formed, e.g., by implanting phosphorus ions at 2 keV acceleration
energy and 5.times.10.sup.12 cm.sup.-2 dose. In the high voltage
operative PMOS transistor, in view of making the impurity
concentration distribution of the channel region gradual to thereby
improve the junction breakdown voltage and hot carrier immunity,
phosphorus in place of arsenic or antimony is ion implanted.
[0068] Next, by, e.g., ashing method, the photoresist film 42 is
removed.
[0069] Next, thermal processing is made in an inert ambient
atmosphere to recover ion implantation damages introduced in the
silicon substrate 10 while activating the implanted impurities. For
example, the thermal processing is made in nitrogen ambient
atmosphere on two stages of 600.degree. C. and 150 seconds and
1000.degree. C. and 0 second.
[0070] At this time, the p-type highly doped impurity layers 22, in
which germanium and carbon are implanted together with boron, can
suppress the diffusion of boron in comparison with the p-type
impurity layer 38, in which boron alone is implanted. Thus, with
the steep distribution of the p-type highly doped impurity layer 22
retained, the impurity of the p-type impurity layer 38 can be
distributed broad.
[0071] The n-type highly doped impurity layer 30 is formed of
arsenic or antimony, whose diffusion constant is smaller than
phosphorus implanted in the n-type impurity layer 46, whereby with
the steep distribution of the n-type highly doped impurity layer 30
retained, the impurity of the n-type impurity layer 46 can be
distributed broad.
[0072] Then, by wet etching with, e.g., hydrofluoric acid aqueous
solution, the silicon oxide film 14 is removed. At this time the
device isolation insulating film 58 has not been formed on the
silicon substrate, and the film thickness decrease of the device
isolation insulating film 58 due to the etching of the silicon
oxide film 14 does not take place.
[0073] Then, by wet etching with, e.g., TMAH (Tetra-Methyl Ammonium
Hydroxide), the surface of the silicon substrate 10 is etched by
about 3 nm.
[0074] Next, by, e.g., CVD method, a non-doped silicon layer 48 of,
e.g., a 40 nm-thickness is grown on the surface of the silicon
substrate 10 (FIG. 8).
[0075] Next, by photolithography, a photoresist film 50 covering
the low-threshold voltage/low-voltage NMOS transistor forming
region 16L and the low-threshold voltage/low-voltage PMOS
transistor forming region 24L and exposing the rest region is
formed. For the alignment for the photolithography, the trench 12
is used as the alignment mark.
[0076] Then, by wet etching with, e.g., TMAH or hydrofluoric
acid-nitric acid solution (HF/HNO.sub.3/H.sub.2O) and with the
photoresist film 50 as the mask, the silicon layer 48 in the region
not covered by the photoresist film 50 is etched by about 10 nm
(FIG. 9).
[0077] Thus, the film thickness of the silicon layer 48 in the
high-threshold voltage/low-voltage NMOS transistor forming region
16H, the high-threshold voltage/low-voltage PMOS transistor forming
region 24H, the high voltage NMOS transistor forming region 32 and
the high voltage PMOS transistor forming region 40 becomes 30 nm.
The film thickness of the silicon layer 48 in the low-threshold
voltage/low-voltage NMOS transistor forming region 16L and the
low-threshold voltage/low-voltage PMOS transistor forming region
24L, which has not been etched remains 40 nm.
[0078] To form the silicon layer 48 of 2 kinds of the film
thickness, 1 step of lithography is added. However, as described
above, the lithography step in the channel ion implantation step
can be decreases by 2 steps, and resultantly, the lithography steps
are decreased by 1 step.
[0079] The silicon layer 48 is etched to differ the threshold
voltage between the high threshold voltage transistors and the low
threshold voltage transistors. It is preferable that the film
thickness of the silicon layer 48 in the respective regions is
suitably set corresponding to values of the threshold voltages the
respective transistors require.
[0080] In the present embodiment, the silicon layer 48 of the
high-threshold voltage/low-voltage NMOS transistor forming region
16H, the high-threshold voltage/low-voltage PMOS transistor forming
region 24H, the high voltage NMOS transistor forming region 32 and
the high voltage PMOS transistor forming region 40 are the same but
may not be essentially the same. It is preferable that the silicon
layer 48 of the respective regions have film thicknesses selected
suitably corresponding to threshold voltage, characteristics, etc.
the respective transistors required or required simplification of
the steps.
[0081] Then, by, e.g., ashing method, the photoresist film 50 is
removed.
[0082] Next, by, e.g., ISSG (In-Situ Steam Generation) method, the
surface of the silicon layer 48 is wet oxidized under a reduced
pressure to form a silicon oxide film 52 of, e.g., a 3
nm-thickness. As the processing conditions, for example, the
temperature is set at 810.degree. C., and the processing period of
time is set at 20 seconds.
[0083] Then, above the silicon oxide film 52, a silicon nitride
film 54 of, e.g., a 90 nm-thickness is deposited by, e.g., LPCVD
method. As the processing conditions, for example, the temperature
is set at 700.degree. C., and the processing period of time is set
at 150 minutes.
[0084] Next, by photolithography and dry etching, the silicon
nitride film 54, the silicon oxide film 52, the silicon layer 48
and the silicon substrate 10 are anisotropically etched to form a
device isolation trench 56 in the device isolation region
containing the regions between the respective transistor forming
regions (FIG. 10). For the alignment for the photolithography, the
trench 12 is used as the alignment mark.
[0085] Next, by, e.g., ISSG method, the surface of the silicon
layer 48 and the silicon substrate 10 are wet oxidized under a
decreased pressure to form a silicon oxide film of, e.g., a 2
nm-thickness as the liner film on the inside walls of the device
isolation trench 56. As the processing conditions, for example, the
temperature is set at 810.degree. C., and the processing period of
time is set at 12 seconds.
[0086] Next, by, e.g., high density plasma CVD method, a silicon
oxide film of, e.g., a 500 nm-thickness is deposited to fill the
device isolation trench 56 by the silicon oxide film.
[0087] Then, by, e.g., CMP method, the silicon oxide film above the
silicon nitride film 54 is removed. Thus, by the so-called STI
(Shallow Trench Isolation) method, the device isolation insulating
film 58 of the silicon oxide film buried in the device isolation
trench 56 is formed (FIG. 11).
[0088] Next, by, e.g., wet etching with hydrofluoric acid aqueous
solution and with the silicon nitride film 54 as the mask, the
device isolation insulating film 58 is etched by, e.g., about 30
nm. This etching is for adjusting the surface of the silicon layer
48 of the completed transistors and the surface of the device
isolation insulating film 58 to be on the substantially the same
height.
[0089] Next, by, e.g., wet etching with hot phosphoric acid, the
silicon nitride film 54 is removed (FIG. 12).
[0090] Next, by, e.g., wet etching with hydrofluoric acid aqueous
solution, the silicon oxide film 52 is removed. At this time, the
device isolation insulating film 58 is never excessively etched
because the impurities for the channel ion implantation are not
implanted in the device isolation insulating film 58.
[0091] Next, by thermal oxidation method, a silicon oxide film 60
of, e.g., a 7 nm-thickness is formed. As the processing conditions,
for example, the temperature is set at 750.degree. C., and the
processing period of time is set at 52 minutes.
[0092] Next, by photolithography, a photoresist film 62 covering
the high voltage NMOS transistor forming region 32 and the high
voltage PMOS transistor forming region 40 and exposing the reset
region is formed.
[0093] Then, by, e.g., wet etching with hydrofluoric acid aqueous
solution and with the photoresist film 62 as the mask, the silicon
oxide film 60 is etched. Thus, the silicon oxide film 60 in the low
voltage NMOS transistor forming region 16 and the low voltage PMOS
transistor forming region 24 is removed (FIG. 13). At this time,
the device isolation insulating film 58 is never excessively etched
because the impurities for the channel ion implantation have not
been implanted in the device isolation insulating film 58.
[0094] Then, by, e.g., ashing method, the photoresist film 62 is
removed.
[0095] Next, by thermal oxidation method, a silicon oxide film 64
of, e.g., a 2 nm-thickness is formed. As the processing conditions,
for example, the temperature is set at 810.degree. C., and the
processing period of time is set at 8 seconds.
[0096] Next, thermal processing of, e.g., 870.degree. C. and 13
seconds is made in NO atmosphere to introduce nitrogen into the
silicon oxide films 60, 64.
[0097] Thus, the gate insulating films 60a of the silicon oxide
film 60 are formed in the high voltage NMOS transistor forming
region 32 and the high voltage PMOS transistor forming region 40.
In the low voltage NMOS transistors forming region 16 and the low
voltage PMOS transistors forming region 24, the gate insulating
films 64a of the silicon oxide film 64 thinner than the silicon
oxide film 60 are formed (FIG. 14).
[0098] Then, above the entire surface, a non-doped polycrystalline
silicon film of, e.g., a 100 nm-thickness is deposited by, e.g.,
LPCVD method. As the processing conditions, for example, the
temperature is set at 605.degree. C.
[0099] Next, by photolithography and dry etching, the
polycrystalline silicon film is patterned to form the gate
electrodes 66 in the respective transistor forming regions (FIG.
15).
[0100] Next, by photolithography and ion implantation, n-type
impurity ions are implanted selectively in the high voltage NMOS
transistor forming region 32 with the gate electrode 66 as the mask
to form n-type impurity layers 68 to be the LDD regions. The n-type
impurity layers 68 are formed by implanting, e.g., phosphorus ions
under the conditions of 35 keV acceleration energy and
2.times.10.sup.13 cm.sup.-2 dose.
[0101] Next, by photolithography and ion implantation, p-type
impurity ions are implanted selectively in the high voltage PMOS
transistor forming region 40 with the gate electrode 66 as the mask
to form p-type impurity layers 70 to be the LDD regions (FIG. 16).
The p-type impurity layers 70 are formed by implanting, e.g., boron
ions under the conditions of 10 keV acceleration energy and
2.times.10.sup.13 cm.sup.-2 dose.
[0102] Next, by photolithography and ion implantation, n-type
impurity ions are implanted selectively in the low voltage NMOS
transistor forming regions 16 with the gate electrodes 66 as the
mask to form n-type impurity layers to be the extension regions.
The n-type impurity layers 72 are formed by implanting, e.g.,
arsenic ions at 6 keV acceleration energy and 2.times.10.sup.14
cm.sup.-2 dose.
[0103] Then, by photolithography and ion implantation, p-type
impurity ions are implanted selectively in the low voltage PMOS
transistor forming regions 24 with the gate electrodes 66 as the
mask to form p-type impurity layers to be the extension regions
(FIG. 17). The p-type impurity layers 74 are formed by implanting,
e.g., boron ions at 0.6 keV acceleration energy and
7.times.10.sup.14 cm.sup.-2 dose.
[0104] Then, above the entire surface, a silicon oxide film of,
e.g., an 80 nm-thickness is deposited by, e.g., CVD method. As the
processing condition, for example, the temperature is set at
520.degree. C.
[0105] Next, the silicon oxide film deposited above the entire
surface is anisotropically etched to be left selectively on the
side walls of the gate electrodes 66. Thus, the sidewall spacers 76
of the silicon oxide film are formed (FIG. 18).
[0106] Next, by photolithography and ion implantation, ion
implantation is made selectively in the low voltage NMOS transistor
forming regions 16 and the high voltage NMOS transistor forming
region 32 with the gate electrodes 66 and the sidewall spacers 76
as the mask. Thus, the n-type impurity layers 78 to be the
source/drain regions are formed, and n-type impurities are doped to
the gate electrodes 66 of the NMOS transistors. As the conditions
for the ion implantation, for example, phosphorus ions are ion
implanted at 8 keV acceleration energy and at 1.2.times.10.sup.16
cm.sup.-2 dose.
[0107] Next, by photolithography and ion implantation, ion
implantation is made selectively in the low voltage PMOS transistor
forming regions 24 and the high voltage PMOS transistor forming
region 40 with the gate electrodes 66 and the sidewall spacers 76
as the mask. Thus, the p-type impurity layers 80 to be the
source/drain regions are formed, and p-type impurities are doped to
the gate electrodes 66 of the PMOS transistors. As the conditions
for the ion implantation, for example, boron ions are ion implanted
at 4 keV acceleration energy and 6.times.10.sup.15 cm.sup.-2
dose.
[0108] Then, rapid thermal processing of, e.g., 1025.degree. C. and
0 second is made in an inert gas ambient atmosphere to activate the
implanted impurities and diffuse the impurities in the gate
electrodes 66. The thermal processing of 1025.degree. C. and 0
second is sufficient to diffuse the impurities to the interfaces
between the gate electrodes 66 and the gate insulating films.
[0109] The channel portions of the low voltage NMOS transistors can
retain steep impurity distributions by carbon suppressing the
diffusion of boron, and the channel portions of the low voltage
PMOS transistors can retain steep impurity distributions by the
slow diffusion of arsenic or antimony. On the other hand, the
channel portion of the high voltage NMOS transistor, in which no
carbon is implanted, the diffusion is not suppressed, and the
channel portion of the high voltage PMOS transistor, in which
phosphorus, whose diffusion constant is larger than arsenic and
antimony, can have gradual impurity distribution.
[0110] Thus, the 6 kinds of the transistors are completed on the
silicon substrate 10. That is, in the high-threshold
voltage/low-voltage NMOS transistor forming region 16H, the
high-threshold voltage/low-voltage NMOS transistor (HVt LV NMOS) is
formed. In the low-threshold voltage/low-voltage NMOS transistor
forming region 16L, the low-threshold voltage/low-voltage NMOS
transistor (LVt LV NMOS) is formed. In the low-threshold
voltage/low-voltage PMOS transistor forming region 24L, the
low-threshold voltage/low-voltage PMOS transistor (LVt LV PMOS) is
formed. In the high-threshold voltage/low-voltage POMOS transistor
forming region 24H, the high-threshold voltage/low-voltage PMOS
transistor (HVt LV PMOS) is formed. In the high voltage NMOS
transistor forming region, the high voltage NMOS transistor (HV
NMOS) is formed. In the high voltage PMOS transistor forming
region, the high voltage PMOS transistor (HV PMOS) is formed (FIG.
19).
[0111] Then, by salicide (self-aligned silicide) process, a metal
silicide film 84 of, e.g., a cobalt silicide film is formed on the
gate electrodes 66, the n-type impurity layers 78 and the p-type
impurity layers 80.
[0112] Next, above the entire surface, a silicon nitride film of,
e.g., a 50 nm-thickness is deposited by, e.g., CVD method to form
the silicon nitride film as the etching stopper film.
[0113] Next, above the silicon nitride film, a silicon oxide film
of, e.g., a 500 nm-thickness is deposited by, e.g., high density
plasma CVD method.
[0114] Thus, the inter-layer insulating film 86 of the layer film
of the silicon nitride film and the silicon oxide film is
formed.
[0115] Next, the surface of the inter-layer insulating film 86 is
polished by, e.g., CMP method to planarize.
[0116] Then, the contact plugs 88 buried in the inter-layer
insulating film 86, interconnections 90 connected to the contact
plugs 88, and others are formed, and the semiconductor device is
completed (FIG. 20).
[0117] As described above, according to the present embodiment, the
threshold voltage of the transistor including the epitaxial
semiconductor layer in the channel region are controlled by the
film thickness of the epitaxial semiconductor layer, whereby
without varying the profile of the channel impurity layer, the
transistors of different threshold voltages can be formed. Thus,
the step number of the photolithography for forming different
channel impurity layers can be reduced, and the manufacturing cost
can be suppressed.
[0118] The device isolation insulating film is formed after the
wells and the channel impurity layers have been formed, whereby the
introduction of high concentrations of the channel impurities in
the device isolation insulating film is decreased, and the film
thickness decrease of the device isolation insulating film in the
etching step can be drastically suppressed. Thus, the planarity of
the substrate surface is improved, and the generation of parasitic
transistor channel can be prevented. The semiconductor device of
high reliability and high performance can be realized.
A First Reference Example
[0119] A method of manufacturing a semiconductor device according
to a first reference example will be described with reference to
FIG. 21. The same members of the present reference example as those
of the semiconductor device and the method of manufacturing the
same according to the embodiment illustrated in FIGS. 1 to 20 are
represented by the same reference numbers not to repeat or to
simplify the description.
[0120] FIGS. 21A-21D are sectional views illustrating the method of
manufacturing the semiconductor device according to the present
reference example.
[0121] In the present reference example, the process of making the
channel ion implantation in the p-type highly doped impurity layers
22, the n-type highly doped impurity layers 30, etc. after the
device isolation insulating film 58 have been formed will be
described.
[0122] First, in the silicon substrate 10, the device isolation
insulating film 58 is formed by STI method.
[0123] Next, above the active regions defined by the device
isolation insulating film 58, the silicon oxide film 14 as the
protection oxide film is formed (FIG. 21A).
[0124] Next, by photolithography and ion implantation, the p-type
highly doped impurity layer 22 is formed in the low voltage NMOS
transistor forming region 16.
[0125] Next, by photolithography and ion implantation, the n-type
highly doped impurity layer 30 is formed in the low voltage PMOS
transistor forming region 24.
[0126] Next, thermal processing is made to recover the ion
implantation damage and activate the implanted impurities.
[0127] Next, by wet etching with hydrofluoric acid aqueous
solution, the silicon oxide film 14 is removed to expose the
silicon substrate 10 in the active regions (FIG. 21C).
[0128] At this time, in the device isolation insulating film 58,
high concentrations of the impurities are introduced by the ion
implantation for forming the p-type highly doped impurity layer 22
and the n-type highly doped impurity layer 30, whereby the etching
of the device isolation insulating film 58 is accelerated.
Especially, when arsenic is implanted to form the n-type impurity
layer 30 for the purpose of obtaining steep impurity profiles or
others, the etching rate increase in the low voltage PMOS
transistor forming region 24 is conspicuous.
[0129] Accordingly, in etching the silicon oxide film 14, the
device isolation insulating film 58 is excessively etched, and the
side surfaces of the active regions are exposed.
[0130] Next, above the silicon substrate 10, the non-doped silicon
layer 48 is epitaxially grown (FIG. 21D). At this time, the growth
of the silicon layer 48 starts from the surface and the side
surface of the active region, and crystalline defects are
introduced in the parts where the silicon layers grown along
different plane orientations are met, i.e., in the edges of the
device isolation insulating film 58.
[0131] The crystalline defects introduced in the silicon layer 48
much influence the characteristics, such as leakage current
increases, etc., and are unpreferable.
[0132] The film thickness decrease of the device isolation
insulating film 58 also takes place in the following etching
processes, and the film decrease of the device isolation insulating
film 58 lowers the planarity of the substrate surface, which often
causes inconveniences in the processes in later steps.
A Second Reference Example
[0133] A method of manufacturing a semiconductor device according
to a second reference example will be described with reference to
FIGS. 22A to 24B. The same members of the present reference example
as those of the semiconductor device and the method of
manufacturing the same according to the embodiment illustrated in
FIGS. 1 to 20 are represented by the same reference numbers not to
repeat or to simplify the description.
[0134] FIGS. 22A to 24B are sectional views illustrating the method
of manufacturing the semiconductor device according to the present
reference example.
[0135] In the present reference example, the method of
manufacturing the semiconductor device including low voltage
transistors and high voltage transistors is manufactured by the
same process as in the first reference example.
[0136] First, in the silicon substrate 10, the device isolation
insulating film 58 is formed by STI method.
[0137] Next, above the active regions defined by the device
isolation insulating film 58, the silicon oxide film 14 as the
protection oxide film is formed (FIG. 22A).
[0138] Next, by photolithography and ion implantation, the p-type
highly doped impurity layer 22 is formed in the low voltage NMOS
transistor forming region 16.
[0139] Next, by photolithography and ion implantation, the n-type
highly doped impurity layer 30 is formed in the low voltage PMOS
transistor forming region 24.
[0140] Next, by photolithography and ion implantation, the p-type
impurity layer 38 is formed in the high voltage NMOS transistor
forming region 32.
[0141] Next, by photolithography and ion implantation, the n-type
impurity layer 46 is formed in the high voltage PMOS transistor
forming region 40 (FIG. 22B).
[0142] Next, thermal processing is made to recover the ion
implantation damages and activate the implanted impurities.
[0143] Next, by wet etching with hydrofluoric acid aqueous
solution, the silicon oxide film 14 is removed to expose the
silicon substrate 10 in the active regions.
[0144] At this time, as described in the first reference example,
the device isolation insulating film is excessively etched in the
low voltage NMOS transistor forming region 16 and the low voltage
PMOS transistor forming region 24, and the side surfaces of the
active regions are exposed.
[0145] The impurity concentrations of the p-type impurity layer 38
and the n-type impurity layer 46 are lower by about 1 place in
comparison with the impurity concentrations of the p-type highly
doped impurity layer and the n-type highly doped impurity layer 30.
Accordingly, the etched amounts of the device isolation insulating
film 58 in the high voltage NMOS transistor forming region 32 and
the high voltage PMOS transistor forming region 40 are relatively
small.
[0146] Next, above the silicon substrate 10, the non-doped silicon
layer 48 is epitaxially grown (FIG. 23A). At this time, the growth
of the silicon layer 48 starts from the surface and the side
surface of the active region, and crystalline defects are
introduced in the parts where the silicon layers grown along
different plane orientations are met, i.e., in the edges of the
device isolation insulating film 58.
[0147] The crystalline defects introduced in the silicon layer 48
much influence the characteristics of the transistors, such as
leakage current increases, etc., and are unpreferable.
[0148] Then, above the active regions, the silicon oxide film 60 to
be the gate insulating films 60a for the high voltage NMOS
transistor and the high voltage PMOS transistor is formed (FIG.
23B).
[0149] Next, by photolithography and wet etching, the silicon oxide
film 60 in the low voltage NMOS transistor forming region 16 and
the low voltage PMOS transistor forming region 24 is selectively
removed (FIG. 24A).
[0150] At this time, the device isolation insulating film 58 is
etched together with the silicon oxide film 60, and in the low
voltage NMOS transistor forming region 16 and the low voltage PMOS
transistor forming region 24, the lower surface of the silicon
layer 48 is exposed at the ends of the device isolation insulating
film 58.
[0151] Next, above the active regions of the low voltage NMOS
transistor forming region 16 and the low voltage PMOS transistor
forming region 24, the silicon oxide film 64 to be the gate
insulating films 64a is formed (FIG. 24B).
[0152] Then, when the gate electrodes 66 are formed above the gate
insulating films 64a, below the silicon layer 48 at the edges of
the device isolation insulating film 58, parasitic transistor
channels opposed to the gate electrodes without the silicon layer
48 therebetween are formed. Such parasitic channels are unavoidable
when the silicon layer 48 is epitaxially grown and then 2 or more
kinds of the gate insulating films of different film thicknesses
are formed.
A Third Reference Example
[0153] A method of manufacturing a semiconductor device according
to a third reference example will be described with reference to
FIGS. 25A to 30. The same members of the present reference example
as those of the semiconductor device and the method of
manufacturing the same according to the embodiment illustrated in
FIGS. 1 to 20 are represented by the same reference numbers not to
repeat or to simplify the description.
[0154] FIGS. 25A to 30 are sectional views illustrating the method
of manufacturing the semiconductor device according to the present
reference example.
[0155] In the present reference example, the process of forming the
device isolation insulating film 58 after the p-type highly doped
impurity layers 22 and the n-type highly doped impurity layers 30
have been formed will be described.
[0156] First, photolithography and etching, the trench to be used
as the mark for the mask alignment is formed in a region other than
the product to be formed region of the silicon substrate 10.
[0157] Next, above the entire surface of the silicon substrate 10,
the silicon oxide film 14 as the protection film for the surface of
the silicon substrate 10 is formed (FIG. 25A).
[0158] Next, by photolithography and ion implantation, the p-wells
20 and the p-type highly doped impurity layers 22 are formed in the
low voltage NMOS transistor forming region 16 and the high voltage
NMOS transistor forming region 32.
[0159] Next, by photolithography and ion implantation, the n-wells
28 and the n-type highly doped impurity layers 30 are formed in the
low voltage PMOS transistor forming region 24 and the high voltage
PMOS transistor forming region 40 (FIG. 25B).
[0160] In the present reference example, the p-wells 20 and the
p-type highly doped impurity layers 22 are simultaneously formed in
the low voltage NMOS transistor forming region 16 and the high
voltage NMOS transistor forming region 32. In the low voltage PMOS
transistor forming region 24 and the high voltage PMOS transistor
forming region 40, the n-wells 28 and the p-type highly doped
impurity layers 30 are formed.
[0161] When different channel impurity profiles are necessary for
the low voltage transistor and the high voltage transistor, one
more photolithography step is added for the respective
transistors.
[0162] Next, thermal processing is made to recover the ion
implantation damage and activate the implanted impurities.
[0163] Next, by wet etching with hydrofluoric acid aqueous
solution, the silicon oxide film 14 is removed.
[0164] Then, above the silicon substrate, the non-doped silicon
layer 48 is epitaxially grown (FIG. 26A).
[0165] Next, by STI method, the device isolation insulating film 58
is formed in the silicon substrate 10 and the silicon layer 48
(FIG. 26B).
[0166] Next, above the active regions, the silicon oxide film 60 to
be the gate insulating films 60a of the high voltage NMOS
transistor and the high voltage PMOS transistors is formed (FIG.
27A).
[0167] Then, by photolithography and wet etching, the silicon oxide
film 60 in the low voltage NMOS transistor forming region 16 and
the low voltage PMOS transistor forming region 24 is selectively
removed (FIG. 27B).
[0168] Next, above the active regions of the low voltage NMOS
transistor forming region 16 and the low voltage PMOS transistor
forming region 24, the silicon oxide film 64 to be the gate
insulating films 64a is formed (FIG. 28A).
[0169] Then, above the entire surface, a polycrystalline silicon
film 66a is formed.
[0170] Next, by photolithography and ion implantation, an n-type
impurity ions are implanted into the polycrystalline silicon film
66a in the low voltage NMOS transistor forming region 16 and the
high voltage NMOS transistor forming region 32. Into the
polycrystalline silicon film 66a in the low voltage PMOS transistor
forming region 24 and the high voltage PMOS transistor forming 40,
a p-type impurity ions are implanted (FIG. 28B).
[0171] Next, the polycrystalline silicon film 66a is patterned to
form the gate electrodes 66 in the respective transistor forming
regions.
[0172] Next, by photolithography and ion implantation, n-type
impurity layers 72 to be the extension regions are formed in the
low voltage NMOS transistor forming region 16. In the low voltage
PMOS transistor forming region 24, p-type impurity layers 74 to be
the extension regions are formed. In the high voltage NMOS
transistor forming region 32, n-type impurity layers 68 to be the
LDD regions are formed. In the high voltage PMOS transistor forming
region 40, p-type impurity layer 70 to be the LDD regions are
formed (FIG. 29A).
[0173] Next, a silicon oxide film is deposited and anisotropically
etched to form the sidewall spacers 68 on the side walls of the
gate electrodes 66 (FIG. 29B).
[0174] Next, by photolithography and ion implantation, n-type
impurity layers 78 to be the source/drain regions are formed in the
low voltage NMOS transistor forming region 16 and the high voltage
NMOS transistor forming region 32. In the low voltage PMOS
transistor forming region 24 and the high voltage PMOS transistor
forming region 40, p-type impurity layers 80 to be the source/drain
regions are formed (FIG. 30).
[0175] Next, thermal processing is made to activate the implanted
impurities.
[0176] Thus, above the silicon substrate 10, the low voltage NMOS
transistor, the low voltage PMOS transistor, the high voltage NMOS
transistor and the high voltage PMOS transistor are formed.
[0177] In the present reference example, as the low voltage
transistors, 1 kind of NMOS transistor and 1 kind of PMOS
transistor are formed.
[0178] However, in many actual products, as both NMOS transistors
and PMOS transistors, a low voltage transistor of a low threshold
voltage is used in circuit units requiring high operation, and a
low voltage transistor of a high threshold voltage is used in
circuit units requiring low leakage current.
[0179] In the process of the present reference example, the
photolithography step is required 4 times when channel ion
implantation is made to form the low-threshold voltage/low-voltage
NMOS transistor, the high-threshold voltage/low-voltage NMOS
transistor, the low-threshold voltage/low-voltage PMOS transistor
and the high-threshold voltage/low-voltage PMOS transistor. For
simplify the manufacturing process and the resultant manufacturing
cost reduction, it is desirable to form transistors of different
threshold voltages by as a small number of steps as possible.
Modified Embodiments
[0180] The above-described embodiment can cover other various
modifications.
[0181] For example, in the above-described embodiment, as the base
semiconductor substrate, a silicon substrate is used, but the base
semiconductor substrate may not be essentially a bulk silicon
substrate. Other semiconductor substrates, such as SOI substrate,
etc., may be used.
[0182] In the above-described embodiment, as the epitaxially
semiconductor layer, a silicon layer is used, but the silicon layer
is not essential. In place of the silicon layer, other
semiconductor layers, such as SiGe layer, SiC layer, etc., may be
used.
[0183] In the above-described embodiment, as the high voltage
transistors, the high voltage NMOS transistor and the high voltage
PMOS transistor are used, but plural kinds of high voltage
transistors of different threshold voltages may be provided, as are
the low voltage transistors. For this, the high-threshold
voltage/high-voltage transistor is formed in a region where the
thickness of the epitaxial semiconductor layer is small, and the
low-threshold voltage/high-voltage transistor is formed in the
region where the thickness of the epitaxial semiconductor layer is
large, whereby, as can be the low voltage transistors, the high
voltage transistors of plural different threshold voltages can be
formed by setting the same the channel impurity implantation for
them. However, the difference of the threshold voltage between the
high-threshold voltage and the low-threshold voltage is smaller
than that of the low voltage transistors.
[0184] In the above-described embodiment, the wells of the low
voltage NMOS transistors and the high voltage NMOS transistor and
the wells of the low voltage PMOS transistors and the high voltage
PMOS transistor are formed separately, but, as in the third
reference example, the wells of the low voltage transistors and the
well of the high voltage transistor may be formed
simultaneously.
[0185] The structure, the constituent material, the manufacturing
conditions, etc. of the semiconductor device described in the
embodiment described above are one example and can be changed or
modified suitably in accordance with the technical common sense,
etc. of those skilled in the art.
[0186] All examples and conditional language recited herein are
intended for pedagogical purposes to aid the reader in
understanding the invention and the concepts contributed by the
inventor to furthering the art, and are to be construed as being
without limitation to such specifically recited examples and
conditions, nor does the organization of such examples in the
specification relate to a showing of the superiority and
inferiority of the invention. Although the embodiments of the
present inventions have been described in detail, it should be
understood that the various changes, substitutions, and alterations
could be made hereto without departing from the spirit and scope of
the invention.
* * * * *