U.S. patent application number 14/068628 was filed with the patent office on 2014-10-09 for printed circuit board and manufacturing method thereof, and semiconductor package including the printed circuit board.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. The applicant listed for this patent is SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Seong Ryul Choi, Suk Chang HONG, Sang Kab PARK, Kwang Seop YOUM.
Application Number | 20140300001 14/068628 |
Document ID | / |
Family ID | 51653880 |
Filed Date | 2014-10-09 |
United States Patent
Application |
20140300001 |
Kind Code |
A1 |
Choi; Seong Ryul ; et
al. |
October 9, 2014 |
PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF, AND
SEMICONDUCTOR PACKAGE INCLUDING THE PRINTED CIRCUIT BOARD
Abstract
A printed circuit board, a manufacturing method thereof, and a
semiconductor package including the printed circuit board. The
printed circuit board includes a base substrate including a
plurality of circuit patterns, a cavity formed above the base
substrate, a pad embedded in the base substrate and being exposed
through the substrate bottom surface of the cavity, and an
electronic component mounted in the cavity and electrically
connected to the pad. A cavity having a predetermined depth is
formed in a base substrate of a printed circuit board so as to
mount an electronic component therein, such that a gap between an
upper semiconductor package and a lower semiconductor package may
be obtained even if pitches between the balls are decreased for
high density and high performance of the upper semiconductor
package in the manufacturing of a semiconductor package having a
PoP structure.
Inventors: |
Choi; Seong Ryul; (Seoul,
KR) ; HONG; Suk Chang; (Yeongi-gun, KR) ;
PARK; Sang Kab; (Cheongju, KR) ; YOUM; Kwang
Seop; (Yeongi-gun, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
Suwon |
|
KR |
|
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Suwon
KR
|
Family ID: |
51653880 |
Appl. No.: |
14/068628 |
Filed: |
October 31, 2013 |
Current U.S.
Class: |
257/774 ; 29/852;
361/761 |
Current CPC
Class: |
H01L 23/5389 20130101;
H05K 1/183 20130101; Y10T 29/49165 20150115; H01L 2924/181
20130101; H01L 2224/32145 20130101; H01L 23/49827 20130101; H05K
1/112 20130101; H01L 2224/73265 20130101; H05K 2201/10515 20130101;
H01L 2224/48091 20130101; H05K 2201/10492 20130101; H05K 3/4697
20130101; H01L 21/486 20130101; H01L 2224/73204 20130101; H01L
2924/15311 20130101; H01L 2224/32225 20130101; H01L 2924/15153
20130101; H01L 23/49811 20130101; H01L 2224/16225 20130101; H05K
2201/10734 20130101; H01L 2224/48227 20130101; H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2224/73265 20130101; H01L
2224/32225 20130101; H01L 2224/48227 20130101; H01L 2924/00
20130101; H01L 2924/15311 20130101; H01L 2224/73265 20130101; H01L
2224/32225 20130101; H01L 2224/48227 20130101; H01L 2924/00
20130101; H01L 2224/73265 20130101; H01L 2224/32145 20130101; H01L
2224/48227 20130101; H01L 2924/00 20130101; H01L 2924/181 20130101;
H01L 2924/00012 20130101; H01L 2224/73204 20130101; H01L 2224/16225
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101; H01L
2924/15311 20130101; H01L 2224/73204 20130101; H01L 2224/16225
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/774 ; 29/852;
361/761 |
International
Class: |
H05K 1/18 20060101
H05K001/18; H01L 23/498 20060101 H01L023/498; H05K 3/00 20060101
H05K003/00; H05K 3/10 20060101 H05K003/10 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 9, 2013 |
KR |
10-2013-0038654 |
Claims
1. A printed circuit board, comprising: a base substrate including
a plurality of circuit patterns; a cavity formed above the base
substrate; pads embedded in the base substrate and being exposed
through the substrate bottom surface of the cavity; and an
electronic component mounted in the cavity and electrically
connected to the pads.
2. The printed circuit board according to claim 1, wherein the top
surface of the pads and the bottom surface of the cavity are in the
same plane.
3. The printed circuit board according to claim 1, wherein an
alignment pattern for forming the cavity is formed at a lower
portion of a sidewall of the cavity
4. The printed circuit board according to claim 1, wherein the
electronic component includes external terminals and is mounted in
a face-down position in which the external terminals face the
pads.
5. The printed circuit board according to claim 1, further
comprising a via formed in the base substrate and electrically
connecting the circuit patterns to each other and the circuit
patterns to the pads.
6. A manufacturing method of a printed circuit board, the method
comprising: forming a first protective layer for protecting
circuits on a predetermined region of an upper surface of a base
substrate; forming insulating layers on the upper surface of the
base substrate on which the first protective layer is formed, and
on a lower surface of the base substrate; forming vias in the upper
insulating layer and in the lower insulating layer and then forming
circuits on an upper surface of the upper insulating layer and a
lower surface of the lower insulating layer; forming second
protective layers for protecting circuits gaps between the circuit
patterns formed on the surfaces of the upper and lower insulating
layers; and forming a cavity for mounting the electronic component
in the upper insulating layer at a position corresponding to the
first protective layer.
7. The method according to claim 6, wherein the base substrate has
circuits formed on the upper surface, the lower surface and an
inside thereof, and has a via connecting the circuits on the upper
surface and on the lower surface to each other.
8. The method according to claim 6, wherein, in the forming of the
cavity, the first protective layer embedded in the upper insulating
layer is removed so that the top surfaces of the circuit patterns
exposed through the bottom surface of the cavity and the bottom
surface are in the same plane with no difference in level.
9. The method according to claim 6, wherein, in the forming of the
cavity, a part of the first protective layer remains at a lower
portion of a sidewall of the cavity.
10. A semiconductor package having a PoP structure of which an
upper semiconductor package is stacked on an lower semiconductor
package, the lower semiconductor package comprising: a printed
circuit board having a cavity of a predetermined size formed at a
predetermined region of its upper surface; and an electronic
component mounted in the cavity, wherein the printed circuit board
includes: a base substrate including a plurality of circuit
patterns; a cavity formed above the base substrate; and pads
embedded in the base substrate and being exposed through the
substrate bottom surface of the cavity.
11. The semiconductor package according to claim 10, wherein the
top surface of the pads and the bottom surface of the cavity are in
the same plane.
12. The semiconductor package according to claim 10, wherein an
alignment pattern for forming the cavity is formed at a lower
portion of a sidewall of the cavity.
13. The semiconductor package according to claim 10, wherein the
electronic component includes external terminals and is mounted in
a face-down position in which the external terminals face the
pads.
14. The semiconductor package according to claim 10, further
comprising a via formed in the base substrate and electrically
connecting the circuit patterns to each other and the circuit
patterns to the pads.
Description
CROSS REFERENCE(S) TO RELATED APPLICATIONS
[0001] This application claims the benefit under 35 U.S.C. Section
119 of Korean Patent Application Serial No. 10-2013-0038654,
entitled "Printed Circuit Board and Manufacturing Method thereof,
and Semiconductor Package including the Printed Circuit Board"
filed on Apr. 9, 2013, which is hereby incorporated by reference in
its entirety into this application.
BACKGROUND OF THE INVENTION
[0002] 1. Technical Field
[0003] The present invention relates to a printed circuit board
(PCB), a manufacturing method thereof, and a semiconductor package
including the printed circuit board. More specifically, the present
invention relates to a printed circuit board in which a cavity for
mounting an electronic component is formed on its upper surface so
that a gap between upper and lower packages is obtained at the time
of manufacturing a semiconductor package having a package on
package (PoP) structure.
[0004] 2. Description of the Related Art
[0005] Recently, as mobile products become thinned and highly
functional, the number of inputs/outputs (I/O) of flip chips
employed in the mobile products has been increased accordingly.
Further, as the number of the I/Os increases, it is required to
provide fine pitch solder bumps on a PCB.
[0006] As shown in FIG. 1, in a typical semiconductor package
having a PoP structure, a electronic component 122 (e.g., AP chip)
is mounted on the upper surface of the PCB 121 of the lower
semiconductor package. In this structure, if the ball pitch is
reduced in order to increase the number of I/Os of the upper
semiconductor package 110, it is difficult to have a sufficient gap
between the upper semiconductor package and the lower semiconductor
package.
[0007] To cope with this, a structure has been proposed in which an
electronic component 222 (e.g., a IC chip) is embedded in a PCB 221
as shown in FIG. 2. However, in this structure, costly IC chips in
PCBs failed during the manufacturing process are discarded together
with the boards, thereby causing the manufacturing cost to be
increased. In FIG. 2, reference numerals 210 and 220 denote the
upper semiconductor and the lower semiconductor, respectively.
RELATED ART DOCUMENTS
Patent Documents
[0008] (Patent Document 1) Korean Patent Laid-Open Publication No.
10-1997-7007576
[0009] (Patent Document 2) Japanese Patent Laid-Open Publication
No. 2005-512335
SUMMARY OF THE INVENTION
[0010] An object of the present invention is to provide a printed
circuit board in which a cavity having a predetermined depth is
formed in a base substrate of the printed circuit board so as to
mount an electronic component therein, such that a gap between an
upper semiconductor package and a lower semiconductor package may
be obtained even if pitches between the balls are decreased for
high density and high performance of the upper semiconductor
package in the manufacturing of a semiconductor package having a
PoP structure, a manufacturing method thereof, and a semiconductor
package including the printed circuit board.
[0011] According to an exemplary embodiment of the present
invention, there is provided a printed circuit board, including: a
base substrate including a plurality of circuit patterns; a cavity
formed above the base substrate; a pad embedded in the base
substrate and being exposed through the substrate bottom surface of
the cavity; and an electronic component mounted in the cavity and
electrically connected to the pad.
[0012] The top surfaces of the pads and the bottom surface of the
cavity may be in the same plane.
[0013] An alignment pattern for forming the cavity may be formed at
a lower portion of a sidewall of the cavity
[0014] The electronic component may include external terminals and
may be mounted in a face-down position in which the external
terminals face the pads.
[0015] The printed circuit board may further include a via formed
in the base substrate and electrically connecting the circuit
patterns to each other and the circuit patterns to the pad.
[0016] According to another exemplary embodiment of the present
invention, there is provided a manufacturing method of a printed
circuit board, the method including: forming a first protective
layer for protecting circuits on a predetermined region of an upper
surface of a base substrate; forming insulating layers on the upper
surface of the base substrate on which the first protective layer
is formed, and on a lower surface of the base substrate; forming
vias in the upper insulating layer and in the lower insulating
layer and then forming circuits on an upper surface of the upper
insulating layer and a lower surface of the lower insulating layer;
forming second protective layers for protecting circuits gaps
between the circuit patterns formed on the surfaces of the upper
and lower insulating layers; and forming a cavity for mounting the
electronic component in the upper insulating layer at a position
corresponding to the first protective layer 601.
[0017] The base substrate may have circuits formed on the upper
surface, the lower surface and an inside thereof, and may have a
via connecting the circuits on the upper surface and on the lower
surface to each other.
[0018] In the forming of the cavity, the first protective layer
embedded in the upper insulating layer may be removed so that the
top surfaces of the circuit patterns exposed through the bottom
surface of the cavity and the bottom surface are in the same plane
with no difference in level.
[0019] Preferably, in the forming of the cavity, a part of the
first protective layer may remain at a lower portion of a sidewall
of the cavity.
[0020] According to yet another exemplary embodiment of the present
invention, there is provided a semiconductor package having a PoP
structure of which an upper semiconductor package is stacked on an
lower semiconductor package, the lower semiconductor package
comprising: a printed circuit board having a cavity of a
predetermined size formed at a predetermined region of its upper
surface; and an electronic component mounted in the cavity, wherein
the printed circuit board includes a base substrate including a
plurality of circuit patterns; a cavity formed above the base
substrate; a pad embedded in the base substrate and being exposed
through the substrate bottom surface of the cavity.
[0021] Preferably, the top surfaces of the pads and the bottom
surface of the cavity may be in the same plane.
[0022] An alignment pattern for forming the cavity may be formed at
a lower portion of a sidewall of the cavity
[0023] The electronic component may include external terminals and
may be mounted in a face-down position in which the external
terminals face the pads.
[0024] The printed circuit board may further include a via formed
in the base substrate and electrically connecting the circuit
patterns to each other and the circuit patterns to the pad.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a view illustrating an example of a typical
semiconductor package having a PoP structure;
[0026] FIG. 2 is a view illustrating another example of a typical
semiconductor package having a PoP structure;
[0027] FIG. 3 is a cross-sectional view showing a structure of a
printed circuit board according to an exemplary embodiment of the
present invention;
[0028] FIG. 4 is a view of a semiconductor package including the
printed circuit board according to the exemplary embodiment shown
in FIG. 3;
[0029] FIG. 5 is a flowchart illustrating a manufacturing method of
the printed circuit board according to the exemplary embodiment of
the present invention;
[0030] FIGS. 6A to 6E are views sequentially illustrating the
manufacturing processes according to the manufacturing method of
the printed circuit board according to the exemplary embodiment of
the present invention; and
[0031] FIGS. 7A and 7B are partially enlarged views of portion A of
FIG. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0032] Terms and words used in the present specification and claims
are not to be construed as a general or dictionary meaning, but are
to be construed as meaning and concepts meeting the technical ideas
of the present invention based on a principle that the inventors
can appropriately define the concepts of terms in order to describe
their own inventions in the best mode.
[0033] Throughout the present specification, unless explicitly
described to the contrary, "comprising" any components will be
understood to imply the inclusion of other elements rather than the
exclusion of any other elements. A term "part," "module," "device,"
or the like, described in the specification means a unit of
processing at least one function or operation and may be
implemented by hardware or software or a combination of hardware
and software.
[0034] Hereinafter, exemplary embodiments of the present invention
will be described in detail with reference to the accompanying
drawings.
[0035] FIG. 3 is a view showing a structure of a printed circuit
board according to an exemplary embodiment of the present
invention.
[0036] Referring to FIG. 3, the printed circuit board 320'
according to the exemplary embodiment of the present invention is
configured to include a base substrate 321, a cavity 321c, pads
322p and an electronic component 330. Here, the printed circuit
board 320' including the electronic component 330 is substantially
identical to a lower semiconductor package 320 of a semiconductor
package to be described below.
[0037] The base substrate 321 includes a plurality of circuit
patterns 322, 606 and 607. The base substrate 321 may have a single
layer or multi layer structure. In the exemplary embodiment, the
base substrate 321 of a multi layer structure will be described.
Further, the circuit patterns 322, 606 and 607 are formed on at
least one of the upper surface and the lower surface, or the inside
of the base substrate 321. As shown in the drawing, in the base
substrate 321 employed in the present invention, the circuit
patterns 322, 606 and 607 are formed on all of the upper and lower
surfaces and the inside of the base substrate 321.
[0038] The cavity 321c is formed above the base substrate 321. The
cavity 321c serves to mount an electronic component 330 (e.g., a
semiconductor chip) therein. Further, an alignment pattern 601 may
be formed on the lower portion of the sidewall of the cavity 321c
for forming the cavity (see FIG. 7A). The alignment pattern 601 is
the remaining part of the protective layer 601 during the
manufacturing process of the printed circuit board to be described
below. The detailed description of which will be given below. The
dimensions of the cavity 321c, that is, the width and depth are
variable depending on the width and depth of an electronic
component 330 mounted therein and on the manufacturing
specifications of a semiconductor package to be described
below.
[0039] The pads 322p are exposed through the substrate bottom
surface of the cavity 321c and are embedded in the base substrate
321. The pads 322p exposed through the bottom surface of the
substrate are the top surfaces of the respective circuit patterns
322. The upper surfaces of the pads 322p and the bottom surface of
the cavity 321c are in the same plane. The detailed description of
which will be given below.
[0040] The electronic component 330 is mounted in the cavity 321c
and is electrically connected to the pads 322p. Here, the
electronic component 330 includes external terminals and is mounted
in a face-down position in which the external terminals face the
pads 322p.
[0041] The printed circuit board according to the exemplary
embodiment the present invention is preferably formed in the inside
of the base substrate 321, and may further include vias 323, 604
and 605 electrically connecting the circuit patterns 322, 606 and
607 to each other and the pads 322p to the circuit patterns 322,
606 and 607.
[0042] Now, a manufacturing method of the printed circuit board
according to the exemplary embodiment will be described.
[0043] For the sake of easy understating, FIG. 4 which illustrates
a semiconductor package will be described after FIG. 5 and FIGS. 6A
to 6E are described, which relate to a manufacturing method of the
printed circuit board.
[0044] FIG. 5 is a flowchart illustrating a manufacturing method of
the printed circuit board according to the exemplary embodiment,
and FIGS. 6A to 6E are views sequentially illustrating the
manufacturing processes of the manufacturing method of the printed
circuit board according to the present invention.
[0045] Referring to FIG. 5 and FIGS. 6A to 6E, in a manufacturing
method of a printed circuit board according to the present
invention, firstly, a first protective layer 601 for protecting
circuits is formed on a predetermined region of an upper surface of
a base substrate 321 (S501, FIG. 6A). The base substrate 321 may
have circuit patterns 322 formed on its upper and lower surfaces
and its inside, and vias 323 connecting the upper and lower circuit
patterns 322 formed therein.
[0046] The first protective layer 601 may be formed by removing the
protective layer formed on both surfaces of a detach core used in
the early process, leaving only a predetermined region for forming
the cavity 321c to be described. Alternatively, the first
protective layer 601 may be formed only on a predetermined region
where the cavity 321c is to be formed, including the circuit
patterns on the upper surface of the base substrate 321 and
adjacent insulating portion. As the material for the protective
layer, a single metal or an alloy may be used. In some cases,
non-metal material may also be used.
[0047] After the first protective layer 601 is formed, insulating
layers 602 and 603 are formed on the upper surface where the first
protective layer 601 is formed and on the lower surface,
respectively (S502, FIG. 6B). As the material for the insulating
layers 602 and 603, synthetic resins (epoxy resins, polyester
resins, urea resins, phenolic resins) may be used.
[0048] After the insulating layers 602 and 603 are formed, vias 604
and 605 are formed through the upper and lower insulators 602 and
603, and then circuits 606 and 607 are formed on the upper surface
of the upper insulator 602 and on the lower surface of the lower
insulator 603, respectively (S503, FIG. 6C). The vias 604 and 605
may be formed by forming holes in the upper and lower insulating
layers 602 and 603 using a laser drill and then filling the holes
with metal material (e.g., copper) by electrical plating. The
circuits 606 and 607 formed on the upper and lower surfaces of the
insulating layers 602 and 603 may be formed by performing
photolithography using a mask.
[0049] After the circuits 606 and 607 are formed on the upper and
lower surfaces of the insulators 602 and 603, second protective
layers 608 and 609 for protecting circuits may be formed, at the
gaps between the circuits 606 and 607, respectively (S504, FIG.
6D). As the material for the second protective layers 608 and 609,
solder resist may be used. Again, photolithography using a mask may
be used for forming the second protective layers 608 and 609.
[0050] After the second protective layers 608 and 609 are formed, a
cavity 321c for mounting an electronic component 330 (shown in FIG.
3) is formed at a position in the upper insulating layer 602 where
the first protective layer 601 has been formed (S505, FIG. 6E). Any
one of wet etching and dry etching, preferably dry etching may be
used for forming the cavity 321c.
[0051] In forming of the cavity 321c, the first protective layer
601 embedded in the upper insulating layer 602 is also removed,
such that the top surfaces of the circuit patterns 322 exposed
through the bottom of the cavity 321c are in the same plane with
the bottom surface of the cavity 321c with no difference in
level.
[0052] Since the plane of the circuits 322 exposed through the
bottom of the cavity 321c where the electronic component 330 is
mounted is flat with the plane of the bottom of the cavity 321c, an
insulation distance may be formed high so that the electronic
component 330 may be inserted into the cavity 321c. Accordingly, it
is easy to obtain the depth of the cavity 321c with relatively wide
ranges (e.g., 40 to 150 .mu.m) in the upper insulating layer
602.
[0053] Further, in forming the cavity 321c, as shown in FIG. 7A, a
part of the first protective layer 601 may remain at the lower
portion of the sidewall of the cavity 321c. The remaining part of
the first protective layer 601 may be used as an alignment mark to
allow the electronic component 330 to be accurately mounted when
the electronic component 330 is mounted in the cavity 321c in the
process of manufacturing a semiconductor package. As appreciated,
the first protective layer 601 may be completely removed when the
cavity 321c is formed as shown in FIG. 7B.
[0054] Now, a description will be made referring back to FIG.
4.
[0055] FIG. 4 is a view of a semiconductor package including the
printed circuit board according to the exemplary embodiment shown
in FIG. 3.
[0056] Referring to FIG. 4, the semiconductor package including the
printed circuit board according to the exemplary embodiment of the
present invention has a PoP structure that an upper semiconductor
package 310 is stacked on an lower semiconductor package 320.
[0057] The lower semiconductor package 320 includes a printed
circuit board 320' having a cavity 321c of a predetermined size
formed on a part of the upper surface, and an electronic component
330 mounted in the cavity 321c.
[0058] Further, the printed circuit board 320' is the one described
above with reference to FIG. 3.
[0059] That is, the printed circuit board 320' includes the base
substrate 321, the cavity 321c and the pads 322p.
[0060] The base substrate 321 includes a plurality of circuit
patterns 322, 606 and 607. The base substrate 321 may have a single
layer or multi layer structure. Further, the circuit patterns 322,
606 and 607 are formed on at least one of the upper surface and the
lower surface, or the inside of the base substrate 321. As shown in
the drawing, in the base substrate 321 employed in the present
invention, the circuit patterns 322, 606 and 607 are formed on all
of the upper and lower surfaces and the inside of the base
substrate 321.
[0061] The cavity 321c is formed above the base substrate 321. The
cavity 321c is formed to mount an electronic component 330 (e.g., a
semiconductor chip) therein. Further, an alignment pattern 601 may
be formed on the lower portion of the sidewall of the cavity 321c
for forming the cavity. The alignment pattern 601 is the remaining
part of the protective layer 601 during the manufacturing process
of the printed circuit board. The dimensions of the cavity 321c,
that is, the width and depth are variable depending on the width
and depth of an electronic component 330 mounted therein and on the
manufacturing specifications of a semiconductor package to be
described below.
[0062] The pads 322p are exposed through the substrate bottom
surface of the cavity 321c and embedded in the base substrate 321.
The pads 322p exposed through the bottom surface of the substrate
are the top surfaces of the respective circuit patterns 322. The
upper surfaces of the pads 322p and the bottom surface of the
cavity 321c are in the same plane.
[0063] The electronic component 330 is mounted in the cavity 321c
and electrically connected to the pads 322p. Here, the electronic
component 330 includes external terminals and is mounted in a
face-down position in which the external terminals face the pads
322p.
[0064] The printed circuit board 320' according to the exemplary
embodiment the present invention is preferably formed in the inside
of the base substrate 321, and may further include vias 323, 604
and 605 electrically connecting the circuit patterns 322, 606 and
607 to each other and the pads 322p to the circuit patterns 322,
606 and 607.
[0065] As described above, according to the present invention, a
cavity having a predetermined depth is formed in a base substrate
of a printed circuit board so as to mount an electronic component
therein, such that a gap between an upper semiconductor package and
a lower semiconductor package may be obtained even if pitches
between the balls are decreased for high density and high
performance of the upper semiconductor package in the manufacturing
of a semiconductor package having a PoP structure.
[0066] Further, since the plane of circuits exposed through the
bottom surface of the cavity in which an electronic component is
mounted is flat with the bottom surface of the cavity, an
insulation distance may be formed high so that the electronic
component may be inserted into the cavity. Accordingly, it is easy
to obtain the depth of the cavity with relatively wide ranges in
the upper insulating layer.
[0067] As stated above, according to the present invention, a
cavity having a predetermined depth is formed in a base substrate
of a printed circuit board so as to mount an electronic component
therein, such that a gap between an upper semiconductor package and
a lower semiconductor package may be obtained even if pitches
between the balls are decreased for high density and high
performance of the upper semiconductor package in the manufacturing
of a semiconductor package having a PoP structure.
[0068] Although the exemplary embodiments of the present invention
have been disclosed for illustrative purposes, the present
invention is not limited thereto, but those skilled in the art will
appreciate that various modifications, additions and substitutions
are possible, without departing from the scope and spirit of the
invention as disclosed in the accompanying claims. Therefore, the
true scope of the present invention to be protected should be
defined only by the appended claims and it is apparent to those
skilled in the art that technical ideas equivalent thereto are
within the scope of the present invention.
* * * * *