U.S. patent application number 14/178747 was filed with the patent office on 2014-10-02 for semiconductor packages having package-on-package structures.
The applicant listed for this patent is TAEJOO HWANG. Invention is credited to TAEJOO HWANG.
Application Number | 20140291830 14/178747 |
Document ID | / |
Family ID | 51620000 |
Filed Date | 2014-10-02 |
United States Patent
Application |
20140291830 |
Kind Code |
A1 |
HWANG; TAEJOO |
October 2, 2014 |
SEMICONDUCTOR PACKAGES HAVING PACKAGE-ON-PACKAGE STRUCTURES
Abstract
A semiconductor package includes a lower package with a lower
semiconductor chip on a lower package substrate, and an upper
package with an upper semiconductor chip on an upper package
substrate. The upper semiconductor chip has a plurality of chip
pads and the upper package substrate has a plurality of substrate
pads. The upper package is stacked on the lower package. The chip
pads have a first pitch and the substrate pads have a second pitch
greater than the first pitch. The upper package substrate has a
plurality of connection lines that electrically connect the
substrate pads to the chip pads.
Inventors: |
HWANG; TAEJOO; (Yongin-si,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
HWANG; TAEJOO |
Yongin-si |
|
KR |
|
|
Family ID: |
51620000 |
Appl. No.: |
14/178747 |
Filed: |
February 12, 2014 |
Current U.S.
Class: |
257/686 |
Current CPC
Class: |
H01L 25/07 20130101;
H01L 25/50 20130101; H01L 2224/73253 20130101; H01L 2224/12105
20130101; H01L 2224/16225 20130101; H01L 25/18 20130101; H01L
2924/15311 20130101; H01L 2225/1035 20130101; H01L 2924/1815
20130101; H01L 2225/1041 20130101; H01L 2924/181 20130101; H01L
25/105 20130101; H01L 2225/1023 20130101; H01L 24/19 20130101; H01L
2225/1058 20130101 |
Class at
Publication: |
257/686 |
International
Class: |
H01L 25/07 20060101
H01L025/07 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 1, 2013 |
KR |
10-2013-0035310 |
Claims
1. A semiconductor package, comprising: a lower package including a
lower semiconductor chip on a lower package substrate; and an upper
package, stacked on the lower package, including an upper
semiconductor chip on an upper package substrate, the upper
semiconductor chip having a plurality of chip pads and the upper
package substrate having a plurality of substrate pads, wherein the
chip pads have a first pitch and the substrate pads have a second
pitch greater than the first pitch, and wherein the upper package
substrate comprises a plurality of connection lines that
electrically connect the substrate pads to the chip pads.
2. The semiconductor package of claim 1, further comprising a
plurality of connection terminals that electrically connect the
upper package to the lower package, wherein the connection
terminals are provided between the upper package and the lower
package.
3. The semiconductor package of claim 2, wherein the lower package
further comprises: a lower mold layer; and a plurality of
connection patterns on the lower mold layer, wherein the connection
patterns are electrically connected to the connection lines.
4. The semiconductor package of claim 3, wherein the lower mold
layer comprises an opening exposing a portion of the lower package
substrate, and wherein the connection patterns extend toward inside
the opening to be electrically connected to the lower package
substrate.
5. The semiconductor package of claim 4, wherein the opening
comprises at least one of a line-type trench and a plurality of
holes arranged along lateral sides of the lower semiconductor
chip.
6. A semiconductor package, comprising: a lower package including a
lower package substrate, a lower semiconductor chip mounted on the
lower package substrate, a lower mold layer encapsulating the lower
semiconductor chip, and connection patterns on the lower mold layer
that penetrate the lower mold layer to be electrically connected to
the lower package substrate; an upper package including an upper
package substrate having substrate pads, and an upper semiconductor
chip mounted on the upper package substrate, the upper package
being stacked on the lower package; and connection terminals
interposed between the lower and upper packages, the connection
terminals electrically connecting the lower and upper packages,
wherein the upper semiconductor chip includes chip pads having a
pitch narrower than a pitch of the substrate pads, wherein the
upper package substrate includes connection lines that provide
electrical paths between the substrate pads and the chip pads, and
wherein the connection lines allow the chip pads to access a wider
pitch of the substrate pads to electrically connect the upper
semiconductor chip to the lower package substrate.
7. The semiconductor package of claim 6, wherein the lower package
substrate comprises circuit patterns electrically connected to the
connection patterns, wherein the lower mold layer comprises an
opening that is spaced apart from a lateral side of the lower
semiconductor chip and vertically penetrates the lower mold layer
to expose the circuit patterns, and wherein the connection patterns
extend toward the lower package substrate to pass through the
opening to be electrically connected to the circuit patterns.
8. The semiconductor package of claim 6, wherein the upper
semiconductor chip is disposed on the upper package substrate while
a surface of the upper semiconductor chip faces the upper package
substrate, and wherein the surface of the upper semiconductor chip
contacts the upper package substrate.
9. The semiconductor package of claim 6, wherein the lower package
further includes internal terminals provided between the lower
semiconductor chip and the lower package substrate, wherein the
lower semiconductor chip is disposed on the lower package substrate
to be electrically connected thereto through the internal terminals
while a surface of the lower semiconductor chip faces the lower
package substrate.
10. The semiconductor package of claim 6, wherein the lower
semiconductor chip comprises a logic chip and the upper
semiconductor chip comprises a memory chip.
11. A semiconductor package comprising: a package-on-package type
package including lower and upper packages vertically stacked and
electrically connected, wherein the lower package comprises a lower
semiconductor chip mounted on a lower package substrate and
encapsulated by a lower mold layer, wherein the upper package
comprises an upper semiconductor chip having chip pads mounted on
an upper package substrate without a gap between the upper
semiconductor chip and the upper package substrate, and wherein the
upper package substrate includes connection lines electrically
connected to the upper semiconductor chip, the connection lines
configured to provide the chip pads with access to a wider pitch to
electrically connect the upper semiconductor chip to the lower
package substrate.
12. The semiconductor package of claim 11, wherein the upper
package substrate comprises substrate pads having a pitch greater
than a pitch of the chip pads.
13. The semiconductor package of claim 11, wherein the
package-on-package type package further comprises connection
terminals provided between the lower and upper packages, wherein
the lower package further comprises connection patterns disposed on
the lower mold layer to be electrically connected to the connection
terminals.
14. The semiconductor package of claim 13, wherein the connection
patterns penetrate through the lower mold layer to be electrically
connected to the lower package substrate.
15. The semiconductor package of claim 14, wherein the lower
package further comprises an opening that penetrates through the
lower mold layer and provides the connection patterns with paths
toward the lower package substrate, wherein the opening comprises
at least one of a line-type trench extending along lateral sides of
the lower semiconductor chip and a plurality of holes arranged
along the lateral sides of the lower semiconductor chip.
16. The semiconductor package of claim 11, wherein the upper
package excludes micro-bumps between the upper semiconductor chip
and the upper package substrate.
17. The semiconductor package of claim 11, wherein the lower
semiconductor chip is embedded in the lower package substrate.
18. The semiconductor package of claim 12, wherein the substrate
pads are located at one of a center of, an edge of, a specific
region of, and uniformly across a lower surface of the upper
package substrate, and the chip pads are located at one of a center
of, an edge of, and uniformly across an active surface of the upper
semiconductor chip.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of priority under 35
U.S.C. .sctn.119 to Korean Patent Application 10-2013-0035310,
filed on Apr. 1, 2013, the content of which is incorporated herein
in its entirety by reference.
BACKGROUND
[0002] 1. Field
[0003] An embodiment of the present inventive concept relates to
semiconductors and, more particularly, to semiconductor packages
having package-on-package structures.
[0004] 2. Description of the Related Art
[0005] In the semiconductor industry, various package technologies
have been developed to meet demands for large storage, thin
thickness, and small size of semiconductor devices and/or
electronic appliances. One approach is a package technology through
which semiconductor chips are vertically stacked to realize a high
density chip stacking. This package technology can integrate many
kinds of semiconductor chips in smaller areas compared to a general
package with a single semiconductor chip.
[0006] However, a problem with using a multi-chip stack package is
that there is a strong possibility of a reduction in yield compared
to using a single chip package. A package-on-package (POP)
technology was developed to solve the problem with the reduction in
yield and to still realize a high density chip stack. Inusing POP
technology, known good packages are stacked to reduce the
inferiority of the final product. This POP type package can be used
to meet the trend toward both compact size of electronic portable
appliances and multiple functions of mobile products.
[0007] System-in-Package (SiP) is another packing technology. The
SiP structure also presents a possibility of a reduction in yield
but, unlike the POP structure, does not restrict the selection of
chips. Thus, there may be a need to improve the POP type
semiconductor package to include the merits described above.
SUMMARY
[0008] The present inventive concept provides semiconductor
packages having through electrodes and methods of fabricating the
same in which a narrower pitch may expand to a wider pitch without
interposers.
[0009] Additional features and utilities of the present general
inventive concept will be set forth in part in the description
which follows and, in part, will be obvious from the description,
or may be learned by practice of the general inventive concept.
[0010] The foregoing and/or other features and utilities of the
present general inventive may be achieved by providing
semiconductor packages having through electrodes and methods of
fabricating the same in which a package substrate and a
semiconductor chip are electrically directly connected to each
other without micro-bumps and/or through electrodes.
[0011] The foregoing and/or other features and utilities of the
present general inventive may be achieved by providing
semiconductor packages having through electrodes and methods of
fabricating the same in which there is no gap between the package
substrate and the semiconductor chip.
[0012] The foregoing and/or other features and utilities of the
present general inventive may be achieved by providing a
semiconductor package that has a lower package including a lower
semiconductor chip on a lower package substrate, and an upper
package including an upper semiconductor chip on an upper package
substrate. The upper semiconductor chip may have a plurality of
chip pads and the upper package substrate may have a plurality of
substrate pads. The upper package may be stacked on the lower
package. The chip pads may have a first pitch and the substrate
pads may have a second pitch greater than the first pitch. The
upper package substrate may comprise a plurality of connection
lines that electrically connect the substrate pads to the chip
pads.
[0013] In an embodiment, the semiconductor package may further
comprise a plurality of connection terminals that electrically
connect the upper package to the lower package. The connection
terminals may be provided between the upper package and the lower
package.
[0014] In an embodiment, the lower package may further comprise a
lower mold layer and a plurality of connection patterns on the
lower mold layer. The connection patterns may be electrically
connected to the connection lines.
[0015] In an embodiment, the lower mold layer may comprise an
opening exposing a portion of the lower package substrate. The
connection patterns may extend toward inside the opening to be
electrically connected to the lower package substrate.
[0016] In an embodiment, the opening may comprise at least one of a
line-type trench and a plurality of holes arranged along lateral
sides of the lower semiconductor chip.
[0017] The foregoing and/or other features and utilities of the
present general inventive concept may be achieved by providing a
semiconductor package that has a lower package including a lower
package substrate, a lower semiconductor chip mounted on the lower
package substrate, a lower mold layer encapsulating the lower
semiconductor chip, and connection patterns on the lower mold layer
that penetrate the lower mold layer to be electrically connected to
the lower package substrate, an upper package including an upper
package substrate having substrate pads, and an upper semiconductor
chip mounted on the upper package substrate, the upper package
being stacked on the lower package, and connection terminals
interposed between the lower and upper packages, the connection
terminals electrically connecting the lower and upper packages. The
upper semiconductor chip may include chip pads having a pitch
narrower than a pitch of the substrate pads. The upper package
substrate may include connection lines that provide electrical
paths between the substrate pads and the chip pads. The connection
lines may allow the chip pads to access a wider pitch of the
substrate pads to electrically connect the upper semiconductor chip
to the lower package substrate.
[0018] In an embodiment, the lower package substrate may comprise
circuit patterns electrically connected to the connection patterns.
The lower mold layer may comprise an opening that is spaced apart
from a lateral side of the lower semiconductor chip and vertically
penetrates the lower mold layer to expose the circuit patterns. The
connection patterns may extend toward the lower package substrate
to pass through the opening to be electrically connected to the
circuit patterns.
[0019] In an embodiment, the upper semiconductor chip may be
disposed on the upper package substrate while a surface of the
upper semiconductor chip faces the upper package substrate. The
surface of the upper semiconductor chip may contact the upper
package substrate.
[0020] In an embodiment, the lower package further may include
internal terminals provided between the lower semiconductor chip
and the lower package substrate. The lower semiconductor chip may
be disposed on the lower package substrate to be electrically
connected thereto through the internal terminals while a surface of
the lower semiconductor chip faces the lower package substrate.
[0021] In an embodiment, the lower semiconductor chip may comprise
a logic chip and the upper semiconductor chip may comprise a memory
chip.
[0022] The foregoing and/or other features of the present general
inventive concept may be achieved by providing a semiconductor
package that has a package-on-package type package including lower
and upper packages vertically stacked and electrically connected.
The lower package may comprise a lower semiconductor chip mounted
on a lower package substrate and encapsulated by a lower mold
layer. The upper package may comprise an upper semiconductor chip
having chip pads mounted on an upper package substrate without a
gap between the upper semiconductor chip and the upper package
substrate. The upper package substrate may include connection lines
electrically connected to the upper semiconductor chip. The
connection lines may be configured to provide the chip pads with
access to a wider pitch to electrically connect the upper
semiconductor chip to the lower package substrate.
[0023] In an embodiment, the upper package substrate may comprise
substrate pads having a pitch greater than a pitch of the chip
pads.
[0024] In an embodiment, the package-on-package type package may
further comprise connection terminals provided between the lower
and upper packages. The lower package may further comprise
connection patterns disposed on the lower mold layer to be
electrically connected to the connection terminals.
[0025] In an embodiment, the connection patterns may penetrate
through the lower mold layer to be electrically connected to the
lower package substrate.
[0026] In an embodiment, the lower package may further comprise an
opening that penetrates through the lower mold layer and provides
the connection patterns with paths toward the lower package
substrate. The opening may comprise at least one of a line-type
trench extending along lateral sides of the lower semiconductor
chip and a plurality of holes arranged along the lateral sides of
the lower semiconductor chip.
[0027] The foregoing and/or other features of the present general
inventive concept may be achieved by providing as electronic system
including a semiconductor memory having a first package including a
first semiconductor chip on a first substrate, and a second package
electrically connected to the first package and including a second
semiconductor chip, with chip pads having a first pitch, on a
second substrate with substrate pads having a second pitch greater
than the first pitch, the chip pads electrically connected to the
substrate pads by connection lines, and a memory controller
electrically connected to the semiconductor memory and configured
to write in data to and to read the data from at least one of the
first semiconductor chip and the second semiconductor chip.
[0028] In an embodiment, the second package may exclude micro-bumps
between the second semiconductor chip and the second substrate.
[0029] In an embodiment, the first semiconductor chip may be
embedded in the first substrate.
[0030] In an embodiment, the substrate pads may be located at one
of a center of, an edge of, a specific region of, and uniformly
across a lower surface of the second substrate, and the chip pads
are located at one of a center of, an edge of, and uniformly across
an active surface of the second semiconductor chip.
[0031] In an embodiment, the electronic system may further include
a system bus, a central processing unit electrically connected to
the system bus, a random-access memory electrically connected to
the system bus, a user interface electrically connected to the
system bus, and a modem electrically connected to the system bus,
and the memory controller may be electrically connected to the
system bus.
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] These and/or other features and utilities of the present
general inventive concept will become apparent and more readily
appreciated from the following description of the embodiments,
taken in conjunction with the accompanying drawings of which:
[0033] FIGS. 1A is a cross sectional view illustrating a
semiconductor package according to an embodiment of the present
inventive concept;
[0034] FIGS. 1B to 1E are plan views illustrating various examples
of an opening of the semiconductor package according to an
embodiment of the present inventive concept;
[0035] FIG. 1F is a schematic diagram illustrating an electrical
connection in an upper package of the semiconductor package
according to an embodiment of the present inventive concept;
[0036] FIG. 1G is a cross sectional view illustrating a portion of
the upper package included in the semiconductor package according
to an embodiment of the present inventive concept;
[0037] FIGS. 2A to 2F are cross sectional views illustrating
semiconductor packages according to embodiments of the present
inventive concept;
[0038] FIG. 3A is a schematic block diagram illustrating an example
of a memory card that includes a semiconductor package according to
embodiments of the present inventive concept; and
[0039] FIG. 3B is a schematic block diagram illustrating an example
of an information process system that includes a semiconductor
package according to embodiments of the present inventive
concept.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0040] Reference will now be made in detail to the embodiments of
the present general inventive concept, examples of which are
illustrated in the accompanying drawings, wherein like reference
numerals refer to the like elements throughout. The embodiments are
described below in order to explain the present general inventive
concept while referring to the figures. Example embodiments, may,
however, be embodied in many different forms and should not be
construed as being limited to the embodiments set forth herein;
rather, these example embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope of example embodiments of the present inventive concept to
those of ordinary skill in the art. In the drawings, the
thicknesses of layers and regions are exaggerated for clarity.
[0041] FIGS. 1A is a cross sectional view illustrating a
semiconductor package 1 according to an embodiment of the present
inventive concept. FIGS. 1B to 1E are plan views illustrating
various examples of an opening 137 of the semiconductor package 1
according to an embodiment of the present inventive concept. FIG.
1F is a schematic diagram illustrating an electrical connection in
an upper package 20 of the semiconductor package 1 according to an
embodiment of the present inventive concept. FIG. 1G is a cross
sectional view illustrating a portion of the upper package 20
included in the semiconductor package 1 according to exemplary
embodiments of the present inventive concepts.
[0042] Referring to FIG. 1A, the semiconductor package 1 may be a
package-on-package type package that includes the upper package 20
stacked on a lower package 10. For example, the lower package 10
may comprise a lower package substrate 110, a lower semiconductor
chip 120 disposed on the lower package substrate 110, and a lower
mold layer 130 that encapsulates the lower semiconductor chip 120.
The upper package 20 may comprise an upper package substrate 210,
an upper semiconductor chip 220 disposed on the upper package
substrate 210, and an upper mold layer 230 that encapsulates the
upper semiconductor chip 220. The upper semiconductor chip 220 and
the lower semiconductor chip 120 may be a same or a different kind
of chip. For example, the upper semiconductor chip 220 may be a
memory chip and the lower semiconductor chip 120 may be a logic
chip.
[0043] The lower semiconductor chip 120 may be bonded onto the
lower package substrate 110, which has circuit patterns 112, in a
flip-chip manner in which an active surface 120f faces the lower
package substrate 110, and may be electrically connected to the
lower package substrate 110 through one or more internal terminals
124. The circuit patterns 112 may provide electrical paths that
vertically penetrate the lower package substrate 110. The lower
mold layer 130 may comprise the at least one vertical opening 137
that exposes the circuit patterns 112.
[0044] The opening 137 may have, for example, a trench shape or a
hole shape. For example, the opening 137 may have a ring-type
trench shape that continuously extends along lateral sides of the
lower semiconductor chip 120 as illustrated in FIG. 1B, or a
line-type trench shape that extends along opposing lateral sides of
the lower semiconductor chip 120 as illustrated in FIG. 10.
Alternatively, the opening 137 may have, for example, a hole shape
that includes a plurality of holes arranged continuously along
lateral sides of the lower semiconductor chip 120 as illustrated in
FIG. 1D, or arranged along opposing lateral sides of the lower
semiconductor chip 120 as illustrated in FIG. 1E.
[0045] A plurality of connection patterns 135 may be disposed on
the lower mold layer 130 to be electrically connected to the
circuit patterns 112. The connection patterns 135 may extend toward
inside the opening 137 to be directly coupled to the circuit
patterns 112 such that the connection patterns 135 may be
electrically connected to the lower package substrate 110.
[0046] An insulation layer 132 may be further provided between the
lower mold layer 130 and the connection patterns 135. For example,
when the lower mold layer 130 is formed to expose the lower
semiconductor chip 120, the insulation layer 132 may prevent an
electrical interconnection between the connection patterns 135 and
the lower semiconductor chip 120. A sidewall of the opening 137 may
be covered by the insulation layer 132. However, a bottom floor of
the opening 137 may not be covered by the insulation layer 132 such
that the circuit patterns 112 may be exposed through the opening
137. The lower package substrate 110 may further comprise one or
more external terminals 114 coupled to the circuit patterns
112.
[0047] The lower semiconductor chip 120 may be mounted in a
flip-chip manner on the lower package substrate 110, the lower mold
layer 130 may be formed and patterned to form the opening 137, and
the connection patterns 135 may be formed on the lower mold layer
130, which may fabricate the lower package 10. Before the
connection patterns 135 are formed, the lower mold layer 130 may be
grinded to expose the lower semiconductor chip 120 and thereafter
the insulation layer 132 may be further formed.
[0048] The upper semiconductor chip 220 may be formed and then the
upper package substrate 210 may be formed on an active surface 220f
of the upper semiconductor chip 220, and the upper mold layer 230
may be formed to encapsulate the upper semiconductor chip 220,
which may fabricate the upper package 20. In other words, the upper
package 20 may be fabricated by forming the upper semiconductor
chip 220, depositing an insulating material to form the upper
package substrate 210 on the upper semiconductor chip 220, and
depositing and patterning a metal layer to form connection lines
215 embedded in the upper package substrate 210, rather than by
mounting the upper semiconductor chip 220 on the upper package
substrate 210.
[0049] The upper semiconductor chip 220 may further comprise chip
pads 222 electrically connected to the connection lines 215, and
the upper package substrate 210 may further comprise substrate pads
212 coupled to the connection lines 215. In an embodiment, the
upper semiconductor chip 220 may be a wide input/output (I/O)
memory chip that includes about 128 or more chip pads 222. The
substrate pads 212 may be arranged, for example, uniformly and
entirely on a lower surface of the upper package substrate 210.
Alternatively, the substrate pads 212 may be arranged, for example,
locally on a center, an edge, or a specific region of the lower
surface of the upper package substrate 210. The connection lines
215 may provide vertical electrical paths between the chip pads 222
and the substrate pads 212, as illustrated in FIG. 1F. Connection
terminals 214 may be further provided to be coupled to the
substrate pads 212. The connection terminals 214 may be attached to
the upper package substrate 210.
[0050] Because the upper package substrate 210 and the upper
semiconductor chip 220 may be directly or indirectly contacted to
each other, there may no gap between the upper package substrate
210 and the upper semiconductor chip 220. Because the connection
lines 212 and the chip pads 222 may be directly connected to each
other, the upper package substrate 210 and the upper semiconductor
chip 220 may be electrically connected to each other without an
electrical medium such as, for example, micro-bumps. The connection
lines 215 may be electrically connected to the connection patterns
135 via the connection terminals 214. Consequently, the connection
terminals 214 may electrically connect the upper package 20 to the
lower package 10.
[0051] Referring to FIG. 1G, the connection lines 215 may expand a
pitch of the chips pad 222. For example, the connection lines 215
may electrically connect the chip pads 222 that has a first pitch
P1 to the substrate pads 212 that has a second pitch P2. The second
pitch P2 may be greater than the first pitch P1, as illustrated in
FIG. 1G. In an embodiment, the first pitch P1 of the chip pad 222
may be 60 .mu.m or less, the second pitch P2 of the substrate pad
212 may be 120 .mu.m or more. The connection terminals 214 may be
arranged to have a pitch that may be identical to or similar to the
second pitch P2. According to an embodiment, the upper
semiconductor chip 220 may be electrically connected to the upper
package substrate 210 without an electrical medium such as, for
example, micro-bumps or through electrodes. The connection lines
215 may expand the narrower pitch P1 of the chip pad 222 to the
wider pitch P2 of the connection terminal 214 without the help of
an interposer, and the connection terminals 214 may electrically
connect the upper package 20 to the lower package 10.
[0052] As described above, because there may no gap between the
upper semiconductor chip 220 and the upper package substrate 210, a
total height of the semiconductor package 1 may be reduced. Because
there may be no need to form micro-bumps between the upper
semiconductor chip 220 and the upper package substrate 210, there
may be no electrical and/or mechanical problems due to, for
example, electromigration and/or an intermetallic compound of
micro-bumps. In addition, because there may be no interposer,
processes to form the interposer and through electrodes
therethrough may be skipped.
[0053] FIGS. 2A to 2F are cross sectional views illustrating
semiconductor packages according to embodiments of the present
inventive concept. In order to keep the description concise,
previously described elements may be identified by similar or
identical reference numbers without repeating overlapping
descriptions thereof.
[0054] Referring to FIG. 2A, a semiconductor package 2 may further
comprise a filling-up insulation layer 134 that fills the opening
137 and covers the connection patterns 135 in the opening 137. The
filling-up insulation layer 134 may further extend from the opening
137 toward a center of the lower semiconductor chip 120 to cover
the insulation layer 132.
[0055] Referring to FIG. 2B, a semiconductor package 3 may comprise
a lower mold layer 131 that covers lateral sides and top surfaces
of the lower semiconductor chip 120. Therefore, there may be no
need to form the insulation layer 132 of the embodiment illustrated
in FIG. 1A on the lower mold layer 131.
[0056] Referring to FIG. 2C, a semiconductor package 4 may comprise
the upper semiconductor chip 220 that has an edge pad structure.
For example, the semiconductor chip 220 may include the chip pads
222 arranged locally on an edge of the active surface 220f of the
upper semiconductor chip 220.
[0057] Referring of FIG. 2D, a semiconductor package 5 may comprise
the upper semiconductor chip 220 that has a full matrix structure.
For example, the upper semiconductor chip 220 may include the chip
pads 222 arranged uniformly on the entire active surface 220f of
the upper semiconductor chip 220.
[0058] Referring of FIG. 2E, a semiconductor package 6 may comprise
the lower semiconductor chip 120 embedded in the lower package
substrate 110 that has vias 115. The lower semiconductor chip 120
may be electrically connected to the circuit patterns 112 through
the internal terminals 124, the circuit patterns 112 may be
electrically connected to the connection patterns 135 through the
vias 115. Consequently, the lower package 10 may be electrically
connected to the upper package 20 through the connection patterns
135.
[0059] Referring to FIG. 2F, a semiconductor package 7 may comprise
the lower semiconductor chip 120 embedded in the lower package
substrate 110 that has the connection patterns 135 formed therein.
For example, the connection patterns 135 may be provided on the
lower package substrate 110, and the opening 137 that exposes the
circuit patterns 112 may be arranged along an edge of the lower
package substrate 110. The lower semiconductor chip 120 may be
exposed through a top surface of the lower package substrate 110,
and the insulation layer 132 may be further provided between the
lower semiconductor chip 120 and the connection patterns 135 to
electrically insulate the connection patterns 135 from the lower
semiconductor chip 120. In an embodiment, the semiconductor package
7 may exclude the lower mold layer 130 of the embodiment
illustrated in FIG. 1A. Therefore, the semiconductor package 7 may
have a reduced total height with respect to the case in which the
lower mold layer 130 is included.
[0060] FIG. 3A is a schematic block diagram illustrating an example
of a memory card 1200 that includes a semiconductor package
according to embodiments of the present inventive concept. FIG. 3B
is a schematic block diagram illustrating an example of an
information process system 1300 that includes a semiconductor
package according to embodiments of the present inventive
concept.
[0061] Referring to FIG. 3A, a semiconductor memory 1210 that
includes at least one of the semiconductor packages 1 to 7
according to embodiments of the present inventive concept may be
applicable to the memory card 1200. For example, the memory card
1200 may include a memory controller 1220 that may generally
control data exchange between a host 1230 and the semiconductor
memory 1210. A Static Random-Access Memory (SRAM) 1221 may be used
as a work memory of a central processing unit (CPU) 1222. A host
interface (Host I/F) 1223 may have a data exchange protocol of the
host 1230 connected to the memory card 1200. An error correction
coding (ECC) block 1224 may detect and/or may correct errors of
data that are read from the semiconductor memory 1210. A memory
interface (Memory I/F) 1225 may interface with the semiconductor
memory 1210 according to an embodiment. The CPU 1222 may generally
control data exchange of the memory controller 1220.
[0062] Referring to FIG. 3B, the information processing system 1300
may include a memory system 1310 that has at least one of the
semiconductor packages 1 to 7 according to embodiments of the
present inventive concept. The information processing system 1300
may include, for example, a mobile device or a computer. For
example, the information processing system 1300 may include a modem
1320, a central processing unit (CPU) 1330, a Random-Access Memory
(RAM) 1340, and a user interface (User I/F) 1350 electrically
connected to the memory system 1310 via a system bus 1360. The
memory system 1310 may include a memory 1311 and a memory
controller 1312 and may have substantially the same configuration
as that of the memory card 1200 in the embodiment illustrated in
FIG. 3A. The memory system 1310 may store data processed by the CPU
1330 or data input from outside. The information process system
1300 may be provided, for example, as a memory card, a solid state
disk, a semiconductor device disk, a camera image sensor, and/or
other application chipsets. In an embodiment, the memory system
1310 may be used as a portion of a solid state drive (SSD), and in
this case, the information processing system 1300 may stably and
reliably store a large amount of data in the memory system
1310.
[0063] According to an embodiment of the present inventive concept,
the upper semiconductor chip 220 may be electrically connected to
the upper package substrate 210 without the help of, for example,
micro-bumps such that the semiconductor package 1, 2, 3, 4, 5, 6,
or 7 may be shrunk and the reliability of the semiconductor package
1, 2, 3, 4, 5, 6, or 7 may be improved. Moreover, there may be no
need to form an interposer so that processes to form the interposer
and through electrodes therethrough may be skipped, which may
reduce fabrication cost. According to an embodiment, known good
semiconductor packages may be stacked to fabricate a
package-on-package type semiconductor package 1, 2, 3, 4, 5, 6, or
7 that has a good yield as compared with a different type
semiconductor packaging technology such as, for example,
system-in-package technology. Additionally, according to an
embodiment of the present inventive concept, a designer may be free
to select or choose the kinds of upper and lower semiconductor
chips 220 and 120 that may be included in the semiconductor package
1, 2, 3, 4, 5, 6, or 7. Moreover, although seven specific
embodiments of the present general inventive concept have been
described herein, those skilled in the art will understand and
appreciate additional embodiments that may be realized from the
disclosures, teachings, and suggestions of the seven specific
embodiments of the present general inventive concept have been
described herein.
[0064] Although a few embodiments of the present general inventive
concept have been shown and described, it will be appreciated by
those skilled in the art that changes may be made in these
embodiments without departing from the principles and spirit of the
general inventive concept, the scope of which is defined in the
appended claims and their equivalents.
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