U.S. patent application number 14/066324 was filed with the patent office on 2014-09-18 for automatic clock tree synthesis exceptions generation.
This patent application is currently assigned to Synopsys, Inc.. The applicant listed for this patent is Synopsys, Inc.. Invention is credited to Aiqun Cao, Ssu-Min Chang, Cheng-Liang Ding.
Application Number | 20140282350 14/066324 |
Document ID | / |
Family ID | 51534613 |
Filed Date | 2014-09-18 |
United States Patent
Application |
20140282350 |
Kind Code |
A1 |
Chang; Ssu-Min ; et
al. |
September 18, 2014 |
AUTOMATIC CLOCK TREE SYNTHESIS EXCEPTIONS GENERATION
Abstract
Systems and techniques are described for automatically
generating clock tree synthesis (CTS) exceptions. The process can
use on one or more criteria to identify sequential circuit elements
that can be ignored during clock skew minimization. For example,
the process can identify sequential circuit elements whose clock
skew cannot be balanced with other sequential circuit elements due
to structural reasons, identify sequential timing elements that do
not have a timing relationship with other sequential timing
elements in the clock tree, and/or identify sequential circuit
elements whose data pins have a sufficiently large slack so that
clock skew is not expected to cause timing violations at any of the
data pins. Next, the process can generate clock tree exceptions
based on the identified sequential circuit elements.
Inventors: |
Chang; Ssu-Min; (Cupertino,
CA) ; Cao; Aiqun; (Sunnyvale, CA) ; Ding;
Cheng-Liang; (Cupertino, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Synopsys, Inc. |
Mountain View |
CA |
US |
|
|
Assignee: |
Synopsys, Inc.
Mountain View
CA
|
Family ID: |
51534613 |
Appl. No.: |
14/066324 |
Filed: |
October 29, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61792688 |
Mar 15, 2013 |
|
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|
Current U.S.
Class: |
716/136 |
Current CPC
Class: |
G06F 2119/12 20200101;
G06F 30/327 20200101; G06F 30/396 20200101 |
Class at
Publication: |
716/136 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Claims
1. A method for generating clock tree synthesis (CTS) exceptions
for a circuit design, the method comprising: a computer identifying
a set of sequential circuit elements in the circuit design that can
be ignored during clock skew minimization; and the computer
generating CTS exceptions based on the identified set of sequential
circuit elements.
2. The method of claim 1, further comprising performing CTS on the
circuit design by using the CTS exceptions.
3. The method of claim 1, wherein said identifying includes
identifying sequential circuit elements in the circuit design whose
clock skew cannot be balanced with other sequential circuit
elements due to structural reasons.
4. The method of claim 1, wherein said identifying includes
identifying sequential timing elements in the circuit design that
do not have a timing relationship with other sequential timing
elements in the clock tree.
5. The method of claim 1, wherein said identifying includes
identifying sequential circuit elements in the circuit design whose
data pins have a sufficiently large slack so that clock skew is not
expected to cause timing violations at any of the data pins.
6. A non-transitory computer-readable storage medium storing
instructions that, when executed by a computer, cause the computer
to execute a method for generating clock tree synthesis (CTS)
exceptions for a circuit design, the method comprising: identifying
a set of sequential circuit elements in the circuit design that can
be ignored during clock skew minimization; and generating CTS
exceptions based on the identified set of sequential circuit
elements.
7. The non-transitory computer-readable storage medium of claim 6,
wherein the method further comprises performing CTS on the circuit
design using the CTS exceptions.
8. The non-transitory computer-readable storage medium of claim 6,
wherein said identifying includes identifying sequential circuit
elements in the circuit design whose clock skew cannot be balanced
with other sequential circuit elements due to structural
reasons.
9. The non-transitory computer-readable storage medium of claim 6,
wherein said identifying includes identifying sequential timing
elements in the circuit design that do not have a timing
relationship with other sequential timing elements in the clock
tree.
10. The non-transitory computer-readable storage medium of claim 6,
wherein said identifying includes identifying sequential circuit
elements in the circuit design whose data pins have a sufficiently
large slack so that clock skew is not expected to cause timing
violations at any of the data pins.
11. An apparatus, comprising: a processor; and non-transitory
computer-readable storage medium storing instructions that, when
executed by the processor, cause the apparatus to execute a method
for generating clock tree synthesis (CTS) exceptions for a circuit
design, the method comprising: identifying a set of sequential
circuit elements in the circuit design that can be ignored during
clock skew minimization; and generating CTS exceptions based on the
identified set of sequential circuit elements.
12. The apparatus of claim 11, wherein the method further comprises
performing CTS on the circuit design using the CTS exceptions.
13. The apparatus of claim 11, wherein said identifying includes
identifying sequential circuit elements in the circuit design whose
clock skew cannot be balanced with other sequential circuit
elements due to structural reasons.
14. The apparatus of claim 11, wherein said identifying includes
identifying sequential timing elements in the circuit design that
do not have a timing relationship with other sequential timing
elements in the clock tree.
15. The apparatus of claim 11, wherein said identifying includes
identifying sequential circuit elements in the circuit design whose
data pins have a sufficiently large slack so that clock skew is not
expected to cause timing violations at any of the data pins.
Description
RELATED APPLICATION
[0001] This application claims priority to U.S. Provisional Patent
Application No. 61/792,688, entitled "Automatic CTS exceptions," by
the same inventors, having Attorney Docket No. SNPS-2173US01P,
filed on 15 Mar. 2013, the contents of which are herein
incorporated by reference in their entirety for all purposes.
BACKGROUND
[0002] 1. Technical Field
[0003] This disclosure relates to clock tree synthesis during
electronic circuit design. More specifically, this disclosure
relates to automatic clock tree synthesis exceptions
generation.
[0004] 2. Related Art
[0005] Advances in semiconductor technology presently make it
possible to integrate hundreds of millions of transistors onto a
single semiconductor chip. This dramatic increase in semiconductor
integration densities has made it considerably more challenging to
design circuits.
[0006] Clock tree synthesis (CTS) is an important step in
electronic design automation (EDA) that refers to the process of
creating a clock distribution network for distributing a clock
signal to a set of sequential circuit elements in a circuit design.
The quality of the clock trees that is generated by CTS can have a
significant impact on downstream steps in the EDA design flow.
SUMMARY
[0007] Some embodiments described herein automatically generate CTS
exceptions. A CTS exception instructs the CTS engine to ignore one
or more sequential circuit elements during clock skew minimization.
Once the CTS exceptions for a circuit design have been generated,
CTS can be performed on the circuit design by using the CTS
exceptions.
[0008] Some embodiments described herein use on one or more
criteria to identify sequential circuit elements that can be
ignored during clock skew minimization. Specifically, some
embodiments can identify sequential circuit elements whose clock
skew cannot be balanced with other sequential circuit elements due
to structural reasons, identify sequential timing elements that do
not have a timing relationship with other sequential timing
elements in the clock tree, and/or identify sequential circuit
elements whose data pins have a sufficiently large slack so that
clock skew is not expected to cause timing violations at any of the
data pins. Next, the embodiments can generate clock tree exceptions
based on the identified sequential circuit elements.
BRIEF DESCRIPTION OF THE FIGURES
[0009] FIG. 1 illustrates synchronous circuitry in accordance with
some embodiments described herein.
[0010] FIG. 2 illustrates a situation where it is structurally
impossible to balance the clock tree in accordance with some
embodiments described herein.
[0011] FIG. 3 illustrates a process for generating CTS exceptions
in accordance with some embodiments described herein.
[0012] FIG. 4 illustrates a computer system in accordance with some
embodiments described herein.
DETAILED DESCRIPTION
[0013] The following description is presented to enable any person
skilled in the art to make and use the invention, and is provided
in the context of a particular application and its requirements.
Various modifications to the disclosed embodiments will be readily
apparent to those skilled in the art, and the general principles
defined herein may be applied to other embodiments and applications
without departing from the spirit and scope of the present
invention. Thus, the present invention is not limited to the
embodiments shown, but is to be accorded the widest scope
consistent with the principles and features disclosed herein. In
this disclosure, when the term "and/or" is used with a list of
entities, it refers to all possible combinations of the list of
entities. For example, the phrase "X, Y, and/or Z" covers the
following cases: (1) only X; (2) only Y; (3) only Z; (4) X and Y;
(5) X and Z; (6) Y and Z; and (7) X, Y, and Z. Additionally, in
this disclosure, the term "based on" means "based solely or
partially on."
Overview of an Electronic Design Automation (EDA) Flow
[0014] An EDA flow can be used to create a circuit design. Once the
circuit design is finalized, it can undergo fabrication, packaging,
and assembly to produce integrated circuit chips. An EDA flow can
include multiple steps, and each step can involve using one or more
EDA software tools. Some EDA steps and software tools are described
below. These examples of EDA steps and software tools are
illustrative purposes only and are not intended to limit the
embodiments to the forms disclosed.
[0015] Some EDA software tools enable circuit designers to describe
the functionality that they want to implement. These tools also
enable circuit designers to perform what-if planning to refine
functionality, check costs, etc. During logic design and functional
verification, the HDL (hardware description language), e.g.,
SystemVerilog, code for modules in the system can be written and
the design can be checked for functional accuracy, e.g., the design
can be checked to ensure that it produces the correct outputs.
[0016] During synthesis and design for test, the HDL code can be
translated to a netlist using one or more EDA software tools.
Further, the netlist can be optimized for the target technology,
and tests can be designed and implemented to check the finished
chips. During netlist verification, the netlist can be checked for
compliance with timing constraints and for correspondence with the
HDL code.
[0017] During design planning, an overall floorplan for the chip
can be constructed and analyzed for timing and top-level routing.
During physical implementation, circuit elements can be positioned
in the layout (placement) and can be electrically coupled
(routing).
[0018] During analysis and extraction, the circuit's functionality
can be verified at a transistor level and parasitics can be
extracted. During physical verification, the design can be checked
to ensure correctness for manufacturing, electrical issues,
lithographic issues, and circuitry.
[0019] During resolution enhancement, geometric manipulations can
be performed on the layout to improve manufacturability of the
design. During mask data preparation, the design can be "taped-out"
to produce masks which are used during fabrication.
Clock Trees
[0020] Synchronous circuit designs can be viewed as a collection of
sequential circuit elements that are electrically connected via
combinational logic clouds. For example, FIG. 1 illustrates
synchronous circuitry in accordance with some embodiments described
herein. Circuitry 100 includes buffers 104, 106, 107, and 108,
sequential circuit elements 110, 112, 114, 116, and 118, and
combinational logic clouds 120, 122, and 124. A clock signal is
distributed from clock pin 102 to sequential circuit elements 110,
112, 114, 116, and 118 via a clock tree that includes buffers 104,
106, 107, and 108. A sequential circuit element is generally any
element that performs an operation based on a clock signal. For
example, a flip-flop is a sequential circuit element. A
combinational logic cloud includes one or more combinational logic
gates (e.g., AND gates, OR gates, NOT gates, XOR gates,
multiplexers, demultiplexers, buffers, repeaters, etc.), but does
not include any sequential circuit elements.
[0021] Data transfer between sequential circuit elements is
synchronized using one or more clock signals. For example,
sequential circuit element 110 can launch a signal that passes
through combinational logic cloud 120 (which may logically combine
the signal with other signals), and which can then be captured by
sequential circuit element 118. The launch and capture are
synchronized based on the clock signal that is provided to
sequential circuit elements 110 and 118.
[0022] A clock tree comprises circuitry that distributes a clock
signal to one or more sequential circuit elements in the circuit
design. For example, the clock tree shown in FIG. 1 includes
buffers 104, 106, 107, and 108, and electrically connects clock pin
102 to the clock input pins of sequential circuit elements 110,
112, 114, 116, and 118. A clock domain can refer to a portion of a
circuit design that is clocked using a given clock signal. For
example, circuitry 100 shown in FIG. 1 is part of the clock domain
that corresponds to the clock signal that is distributed from clock
pin 102. A circuit design may include multiple clock domains, and
each clock domain can include multiple clock trees.
Process for Automatically Generating CTS Exceptions
[0023] The goal of CTS is to create an optimal clock tree.
According to one definition, an optimal clock tree is a clock tree
that minimizes clock skew while satisfying timing, area, and
leakage power constraints. In general, a clock tree optimization
problem becomes harder as the size of the clock tree increases.
Furthermore, if CTS generates a clock tree that includes clock pins
for which balancing clock skew was not necessary, then the
generated clock tree is unlikely to be as optimal as a clock tree
that would have been generated by the CTS engine if the CTS engine
had ignored clock pins for which balancing clock skew was not
necessary. Therefore, it is beneficial to identify pins that can be
ignored for clock skew minimization during CTS. Each pin that can
be ignored for clock skew minimization during CTS is called a "CTS
exception." Some embodiments described in this disclosure
automatically generate CTS exceptions. A few situations in which a
pin can be ignored for clock skew minimization are now
described.
[0024] In some situations it is structurally impossible to balance
the clock tree (i.e., structurally impossible to minimize the skew
across the clock tree). This situation can occur when a sequential
circuit element is being used to generate a clock (e.g., when the
sequential circuit element is being used as a clock divider). FIG.
2 illustrates a situation where it is structurally impossible to
balance the clock tree in accordance with some embodiments
described herein. Circuitry 200 includes two groups of sequential
circuit elements: groups 202 and 204. Multiplexer 208 receives two
clock signals: FCLK (this clock is used during normal functioning
of circuitry 200) and SCANCLK (this clock is used for testing
circuitry 200). Select input "MODE" determines which clock signal
is outputted by multiplexer 208. Specifically, depending on the
mode of operation of circuitry 200 (e.g., "normal" or "test"),
multiplexer 208 outputs the appropriate clock on its output
pin.
[0025] Group 202 is clocked using the output of multiplexer 208.
Group 204 is clocked using clock signal GenFCLK that is generated
by sequential circuit element 206 based on clock signal FCLK. In
the example shown in FIG. 2, the frequency of clock signal GenFCLK
is half of the frequency of clock signal FCLK.
[0026] Note that the functional clock signal FCLK and the scan
clock signal SCANCLK have conflicting clock skew balancing
requirements. Specifically, for SCANCLK, the clock skew needs to be
balanced between sequential circuit elements in group 202 and
sequential circuit element 206. In other words, for SCANCLK, it is
desirable to minimize the clock skew between any two of the
following set of sequential circuit elements: sequential circuit
element 206 and the sequential circuit elements in group 202. On
the other hand, for clock signal FCLK, the clock skew needs to be
balanced between sequential circuit elements in groups 202 and 204.
In other words, for FCLK, it is desirable to minimize the clock
skew between any two of the following set of sequential circuit
elements: sequential circuit elements in groups 202 and 204. Note
that, these two clock skew balancing requirements imply minimizing
the clock skew between any two of the following set of sequential
circuit elements: sequential circuit element 206 and the sequential
circuit elements in group 204. However, that is structurally
impossible because the sequential circuit elements in group 204 are
clocked using the output from sequential circuit element 206.
[0027] Therefore, in such situations, some embodiments described
herein create a CTS exception for sequential circuit element 206
when the clock tree is being balanced for clock signal SCANCLK. The
CTS exception instructs the CTS engine to ignore the clock input of
sequential circuit element 206 when clock skew is being minimized
for SCANCLK.
[0028] Another situation in which a pin can be ignored during clock
skew minimization is when no timing relationship exists between a
sequential circuit element and other sequential circuit elements. A
direct timing relationship exists between two sequential circuit
elements if one sequential circuit element launches a signal and
the other captures the signal (the signal may optionally pass
through a combinational logic cloud before being captured). For
example, in FIG. 1, sequential circuit element 112 launches a
signal that passes through combinational logic cloud 122 (which may
logically combine the signal with other signals) and is captured by
sequential circuit element 114. Therefore, sequential circuit
elements 112 and 114 have a direct timing relationship.
[0029] A transitive timing relationship exists between sequential
circuit elements F.sub.1 and F.sub.N if and only if a series of
sequential circuit elements F.sub.1, F.sub.2, . . . , F.sub.N-1,
F.sub.N exists such that a direct timing relationship exists
between every pair of neighboring sequential circuit elements in
the series (i.e., a direct timing relationship exists between
sequential circuit elements F.sub.i and F.sub.i+1, where
1.ltoreq.i.ltoreq.N-1). For example, a direct timing relationship
exists between sequential circuit elements 114 and 112 (because
sequential circuit element 114 launches a signal that passes
through combination logic block 124 and is captured by sequential
circuit element 112), and a direct timing relationship exists
between sequential circuit elements 112 and 116 (because sequential
circuit element 112 launches a signal that passes through
combination logic block 122 and is captured by sequential circuit
element 116). Therefore, a transitive timing relationship exists
between sequential circuit elements 114 and 116. Note that both a
direct and a transitive timing relationship may exist between two
sequential circuit elements.
[0030] However, there are situations where no timing relationship
(i.e., neither a direct nor a transitive timing relationship)
exists between a sequential circuit element and other sequential
circuit elements. For example, no timing relationship exists
between sequential circuit element 110 and the other sequential
circuit elements. Likewise, no timing relationship exists between
sequential circuit element 118 and the other sequential circuit
elements. Therefore, some embodiments described herein can generate
CTS exceptions for sequential circuit elements 110 and 118 so that
these sequential circuit elements can be ignored as far as clock
skew minimization is concerned.
[0031] In some embodiments, the system can identify sequential
circuit elements that do not have any timing relationship with
other sequential circuit elements as follows. Each sequential
circuit element in the circuit design can be represented by a
vertex in a graph, and an edge can be created between two vertices
if the corresponding sequential circuit elements have a direct or a
transitive timing relationship. Note that a connected component in
the graph corresponds to a group of sequential circuit elements
that have timing relationship among themselves. Therefore, if a
connected component in the graph has only one sequential circuit
element, then some embodiments can generate a CTS exception for
this sequential circuit element (so that the sequential circuit
element is ignored during clock skew minimization).
[0032] Yet another situation in which a pin can be ignored during
CTS is when the slacks on the data pins of a sequential circuit
element are sufficiently large. Specifically, if the slack on the
data pins of a sequential circuit element is so large that the
clock skew is never expected to cause a timing violation, then the
clock pin on the sequential circuit element can be ignored during
CTS. During static timing analysis, the arrival times are
propagated forward from the timing start-points to the timing
end-points, and the required times are propagated backward from the
timing end-points to the timing start-points. The slack at a given
pin in the circuit design is the difference between the propagated
arrival time at the pin and the propagated required time at the
pin.
[0033] To illustrate arrival times and required times, consider
circuitry 100 shown in FIG. 1. Sequential circuit element 112
launches a data signal at a given clock edge. This data signal then
passes through logic cloud 122 and arrives at the data input pin of
sequential circuit element 114 (this is the arrival time). For
correct circuit operation, the data signal must arrive at the data
input pin of sequential circuit element 114 at a certain time (this
is the required time) before the next clock edge arrives at the
clock input of sequential circuit element 114. The setup time of
the sequential circuit element dictates the time difference between
when the data signal arrives at the data pin and the next clock
edge arrives at the clock input pin. A similar timing constraint
can be derived based on the hold time for a sequential circuit
element.
[0034] The difference between the arrival time and the required
time at a pin is called the slack at the pin. A negative slack
corresponds to a timing violation and needs to be fixed to ensure
correct operation of the circuit. A positive slack corresponds to
the amount of time by which the arrival time or the required time
can worsen (i.e., the arrival time can be delayed or the required
time can be moved earlier) without causing a timing violation. Note
that both the delay through logic cloud 122 and the clock skew
between sequential circuit elements 112 and 114 affect the slack at
the data input pin of sequential circuit element 114. If the slack
at the data input pin of sequential circuit element 114 is
sufficiently large, then it is very unlikely that the clock skew
between sequential circuit elements 112 and 114 would cause a
timing violation. In such situations, sequential circuit element
114 can be ignored as far as clock skew minimization is
concerned.
[0035] Some embodiments described herein can determine the minimum
slack over all of the data input pins of a sequential circuit
element. Next, the embodiments can compare the minimum slack with
the maximum clock skew that is expected to exist in the clock tree.
If the minimum slack is greater than the maximum clock skew by a
threshold amount (the threshold can be zero or can be a positive
value), then some embodiments can generate a CTS exception for the
sequential circuit element.
[0036] FIG. 3 illustrates a process for generating CTS exceptions
in accordance with some embodiments described herein. The process
can use on one or more criteria to identify sequential circuit
elements that can be ignored during clock skew minimization. For
example, the process can identify sequential circuit elements whose
clock skew cannot be balanced with other sequential circuit
elements due to structural reasons (operation 302), identify
sequential timing elements that do not have a timing relationship
with other sequential timing elements in the clock tree (operation
304), and/or identify sequential circuit elements whose data pins
have a sufficiently large slack so that clock skew is not expected
to cause timing violations at any of the data pins (operation 306).
Next, the process can generate clock tree exceptions based on the
identified sequential circuit elements (operation 308).
Computer System
[0037] FIG. 4 illustrates a computer system in accordance with an
embodiment of the present invention. A computer or a computer
system can generally be any system that can perform computations.
Specifically, a computer system can be a microprocessor, an
application specific integrated circuit, a distributed computing
system, a cloud computing system, or any other computing system now
known or later developed. Computer system 402 comprises processor
404, memory 406, and storage 408. Computer system 402 can be
coupled with display 414, keyboard 410, and pointing device 412.
Storage 408 can generally be any device that can store data.
Specifically, a storage device can be a magnetic, an optical, or a
magneto-optical storage device, or it can be based on flash memory
and/or battery-backed up memory. Storage 408 can store application
416, operating system 418, and data 420.
[0038] Application 416 can include instructions that when executed
by computer 402 cause computer 402 to perform one or more processes
that are implicitly or explicitly described in this disclosure.
Data 420 can include any data that is inputted into or outputted by
application 416.
[0039] The above description is presented to enable any person
skilled in the art to make and use the embodiments. Various
modifications to the disclosed embodiments will be readily apparent
to those skilled in the art, and the general principles defined
herein are applicable to other embodiments and applications without
departing from the spirit and scope of the present disclosure.
Thus, the present invention is not limited to the embodiments
shown, but is to be accorded the widest scope consistent with the
principles and features disclosed herein.
[0040] The data structures and code described in this disclosure
can be partially or fully stored on a non-transitory
computer-readable storage medium and/or a hardware module and/or
hardware apparatus. A non-transitory computer-readable storage
medium includes all computer-readable storage mediums with the sole
exception of a propagating electromagnetic wave or signal.
Specifically, a non-transitory computer-readable storage medium
includes, but is not limited to, volatile memory, non-volatile
memory, magnetic and optical storage devices such as disk drives,
magnetic tape, CDs (compact discs), DVDs (digital versatile discs
or digital video discs), or other media, now known or later
developed, that are capable of storing code and/or data. Hardware
modules or apparatuses described in this disclosure include, but
are not limited to, application-specific integrated circuits
(ASICs), field-programmable gate arrays (FPGAs), dedicated or
shared processors, and/or other hardware modules or apparatuses now
known or later developed.
[0041] The methods and processes described in this disclosure can
be partially or fully embodied as code and/or data stored in a
non-transitory computer-readable storage medium or device, so that
when a computer system reads and executes the code and/or data, the
computer system performs the associated methods and processes. The
methods and processes can also be partially or fully embodied in
hardware modules or apparatuses. Note that the methods and
processes can be embodied using a combination of code, data, and
hardware modules or apparatuses.
[0042] The foregoing descriptions of embodiments of the present
invention have been presented only for purposes of illustration and
description. They are not intended to be exhaustive or to limit the
present invention to the forms disclosed. Accordingly, many
modifications and variations will be apparent to practitioners
skilled in the art. Additionally, the above disclosure is not
intended to limit the present invention. The scope of the present
invention is defined by the appended claims.
* * * * *