U.S. patent application number 13/831473 was filed with the patent office on 2014-09-18 for method for producing photovoltaic device isolated by porous silicon.
This patent application is currently assigned to Yissum Research Development Company of the Hebrew University of Jerusalem Ltd.. The applicant listed for this patent is TOWER SEMICONDUCTOR LTD., Yissum Research Development Company of The Hebrew Univsersity of Jerusalem Ltd.. Invention is credited to Micha Asscher, Irit Chen-Zamero, Ora Eli, Evgeny Pikhay, Yakov Roizin, Amir Saar.
Application Number | 20140273332 13/831473 |
Document ID | / |
Family ID | 51455134 |
Filed Date | 2014-09-18 |
United States Patent
Application |
20140273332 |
Kind Code |
A1 |
Roizin; Yakov ; et
al. |
September 18, 2014 |
METHOD FOR PRODUCING PHOTOVOLTAIC DEVICE ISOLATED BY POROUS
SILICON
Abstract
Photovoltaic devices are produced using a minimally modified
standard process flow by forming lateral P-I-N light-sensitive
diodes on silicon islands that are isolated laterally by trenches
performed by RIE, and from an underlying support substrate by
porous silicon regions. P+ and N+ doped regions are formed in a P-
epitaxial layer, trenches are etched through the epitaxial layer
into a P+ substrate, a protective layer (e.g., SiN) is formed on
the trench walls, and then porous silicon is formed (e.g., using HF
solution) in the trenches that grows laterally through the P+
substrate and merges under the island. The method is either
utilized to form low-cost embedded photovoltaic arrays on CMOS IC
devices, or the devices are separated from the P+ substrate by
etching through the porous silicon to produce low-cost, high
voltage solar arrays for solar energy sources, e.g., solar
concentrators.
Inventors: |
Roizin; Yakov; (Afula,
IL) ; Pikhay; Evgeny; (Haifa, IL) ;
Chen-Zamero; Irit; (Haifa, IL) ; Eli; Ora;
(Afula, IL) ; Asscher; Micha; (Jerusalem, IL)
; Saar; Amir; (Jerusalem, IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Univsersity of Jerusalem Ltd.; Yissum Research Development Company
of The Hebrew
TOWER SEMICONDUCTOR LTD. |
Migdal Haemek |
|
US
IL |
|
|
Assignee: |
Yissum Research Development Company
of the Hebrew University of Jerusalem Ltd.
Jerusalem
IL
Tower Semiconductor Ltd.
Migdal Haemek
IL
|
Family ID: |
51455134 |
Appl. No.: |
13/831473 |
Filed: |
March 14, 2013 |
Current U.S.
Class: |
438/80 |
Current CPC
Class: |
H01L 31/1804 20130101;
H01L 31/047 20141201; Y02P 70/521 20151101; H01L 31/075 20130101;
Y02E 10/548 20130101; Y02E 10/547 20130101; H01L 27/142 20130101;
Y02P 70/50 20151101 |
Class at
Publication: |
438/80 |
International
Class: |
H01L 31/042 20060101
H01L031/042 |
Claims
1. A method for fabricating a photovoltaic device on an epitaxial
layer disposed on a silicon substrate, wherein a base epitaxial
portion of the epitaxial layer adjacent to the silicon substrate
has a first doping level that is greater than a second doping level
of an upper epitaxial portion of the epitaxial layer, and is lower
than a third doping level of the silicon substrate, the method
comprising: forming a plurality of doped regions in the epitaxial
layer including at least one P+ doped region and at least one N+
doped region; forming first and second elongated trenches extending
through the epitaxial layer into the silicon substrate such that an
elongated island is formed by a portion of said epitaxial layer
that is disposed between first and side walls defined by said first
and second elongated trenches, wherein at least one P+ doped region
and the at least one N+ doped region are disposed on said elongated
island; and forming a porous silicon region under said elongated
island such that said porous silicon region electrically isolates
said elongated island from said silicon substrate.
2. The method of claim 1, wherein forming said elongated trenches
comprises reactive ion etching through said epitaxial layer into
said silicon substrate.
3. The method of claim 2, further comprising forming black silicon
on side walls of the island.
4. The method of claim 1, wherein forming said porous silicon
region comprises performing an electochemical etch through bottom
surfaces of the first and second trenches such that the
electochemical etch generates porous silicon portions that merge
under the elongated island.
5. The method of claim 1 where the drive in of N+ and P+ implant is
performed after the trench etch with a target to reach the surface
of the formed porous silicon.
6. The method of claim 4, wherein performing said electochemical
etch comprises placing said substrate in a hydro-fluoric (HF)
solution.
7. The method of claim 6, wherein performing said electochemical
etch further comprises generating a current between an electrode
disposed on a lower surface of the substrate and the hydrofluoric
(HF) solution.
8. The method of claim 5, further comprising forming a protective
layer on said first and second side walls of the island after
performing said electochemical etch.
9. The method of claim 8, wherein forming the protective layer
comprises depositing Silicon Nitride on the first and second side
walls and on said bottom surfaces of the first and second
trenches.
10. The method of claim 9, wherein disposing Silicon Nitride on the
first and second side walls and on said bottom surfaces comprises
performing chemical vapor deposition (CVD).
11. The method of claim 8, further comprising removing a portion of
said protective layer disposed on said bottom surfaces of said
trench before performing said electochemical etch.
12. The method of claim 11, wherein removing said portion of said
protective layer comprises removing said portion by reactive ion
etching.
13. The method of claim 12, wherein performing said electochemical
etch further comprises generating a current between an electrode
disposed on a lower surface of the substrate and the hydro-fluoric
(HF) solution.
14. The method of claim 1, further comprising forming electrical
contacts on the epitaxial portion such that each electrical contact
forms an electrical connection between a first N+ doped region
associated with a first diode and a P+ doped region of an adjacent
second diode.
15. The method of claim 1, wherein forming said porous silicon
region comprises performing a galvanic etch through bottom surfaces
of the first and second trenches such that the galvanic etch
generates porous silicon regions that merge under the elongated
island.
16. The method of claim 1, further comprising etching said porous
silicon layer such that said island becomes detached from said
silicon substrate.
17. The method of claim 16, further comprising: forming a second
epitaxial layer on said substrate; forming a second plurality of
doped regions in the second epitaxial layer; forming third and
fourth elongated trenches extending through the second epitaxial
layer into the silicon substrate; and forming a second porous
silicon region in said silicon substrate.
18. A method for fabricating an embedded high voltage (HV)
photovoltaic device on an epitaxial layer disposed on a silicon
substrate, wherein a doping level of the epitaxial layer is lower
than a doping level of the silicon substrate, the method
comprising: forming a plurality of spaced apart doped regions on
the epitaxial layer; forming a plurality of trenches extending
through the epitaxial layer into the silicon substrate such that a
plurality of islands are formed by portions of said epitaxial layer
disposed between each adjacent pair of said plurality of trenches,
wherein at least one pair of said doped regions is disposed on each
of the plurality of islands; forming a porous silicon region under
each of said plurality of said islands by exposing silicon inside
the trenches to an etchant such that said porous silicon region
electrically isolates all of said islands from said silicon
substrate; and forming electrical conductors on the top of
epitaxial layer portions that operably connect said plurality of
doped regions to form a plurality of series-connected photo
sensitive diodes.
19. A method for isolating an embedded photovoltaic device formed
on a silicon substrate having a high doping level and including an
epitaxial layer having a low doping level, the method comprising:
forming first and second trenches extending through the epitaxial
layer into the silicon substrate such that an island is formed by a
portion of the epitaxial layer portion that is disposed between the
first and second trenches; and forming a porous silicon region
under said island by applying an etchant to bottom surfaces of said
first and second trenches such that said porous silicon region
extends entirely under and electrically isolates said island from
said silicon substrate, wherein said embedded photovoltaic device
is at least partially disposed on said epitaxial layer portion
forming said island.
Description
FIELD OF THE INVENTION
[0001] This invention relates to photovoltaic devices, and
particularly to photovoltaic devices including P-I-N light
sensitive diodes.
BACKGROUND OF THE INVENTION
[0002] High voltage low-power photovoltaic sources have a variety
of applications including solar chargers, wireless sensors and
detectors, different portable consumer products, self-powered light
detectors, energy sources for driving MEMS engines, etc. Many of
the state of the art integrated circuits (ICs) are capable of
operating at milliwatt-microwatt power consumption levels that can
be obtained from photovoltaic cells fabricated on the same silicon
chip as the IC. Such photovoltaic HV sources can also be used for
continuous charging of batteries in power management systems to
prevent total discharge and enabling energy savings. If the output
of the photoelectric source is high enough, it can be connected to
a battery or energy storage capacitor (supercapacitor) to allow
higher current peak values. The resulting energy harvesting system
strongly increases the application field covering long-range RFID
systems, smart dust products, etc.
[0003] There are two conventional approaches in integrating
photovoltaic sources into the silicon IC.
[0004] The first conventional approach is to use conventional
low-voltage (single p-n junction) photovoltaic elements and dc-dc
boost converters capable of increasing the low-level input voltages
to the levels of the IC system voltage (Vdd). This approach is
utilized, for example, in products such as LTC 3108 produced by
Linear Technology Corporation of Milpitas, Calif., USA. This
approach requires a complicated analog circuit, and faces many
challenges related to the need to process very low signals and
distinguish them from stray voltages.
[0005] The second conventional approach is to connect the
individual solar cells (p-n junction) in series on silicon (not the
external connection of silicon dice). Some companies (e.g., Clare,
an IXYS Company, of Beverly, Mass., USA) fabricate specialized
chips that generate voltages up to several volts by connecting
individual solar cells on the chip (e.g., Clare's CPC1822-CPC1832
products).
[0006] In most cases, in order to obtain high voltages, solar cells
are fabricated at the isolated areas of silicon and then connected
in series or series-and-parallel combinations.
[0007] A standard photovoltaic p-n diode cell typically generates
from 0.4 to 0.7 V under illumination by the sunlight. The
connection of photovoltaic elements can be, of course, external, if
the solar cells are on separate silicon substrates (separate
wafers). This is what can be found in most commercial solar
energetics (photovoltaic) systems. It is clear that external
connections strongly increase the system cost and decrease
reliability. In case of working with light concentrators, the
problem of connections becomes a bottleneck since the currents from
individual solar wafers reach tens and hundreds of Amperes. HV
cells solve the problem by decreasing the current for the same
light power per unit square of the solar array surface.
[0008] Several solutions have been proposed to make HV solar cells
on one silicon substrate.
[0009] A high voltage multi-junction solar cell is disclosed in
U.S. Pat. No. 4,341,918 (Evans, et. al), where a plurality of
discrete voltage generating regions or unit cells are formed in a
single generally planar semiconductor body. The unit cells comprise
doped regions of opposite conductivity type separated by a gap or
undiffused region. Metal contacts connect adjacent cells together
in series so that the output voltages of the individual cells are
additive. A problem with this approach is that special
metallization is needed by forming a pattern of parallel bars of
aluminum paste that is screen-printed on the surface and fired to
assure penetration of the aluminum through the diffused N+ region
on this face and to make connection to P+ regions. Another problem
is that the output voltage is limited since the common P-type base
shunts the serially connected individual N+P (base) junctions.
[0010] Attempts to isolate the elements comprising the high-voltage
where SOI isolation was employed are disclosed, for example, in
U.S. Pat. No. 6,281,428 (Chiu et al). Chiu has demonstrated how to
use the oxide layer of the SOI wafer as the isolating layer. The
approach makes use of serially connected transverse photovoltaic
cells formed by diffusions using special masks (six masks together
with a special mask forming a mesa structure on the peripheral
region to isolate the light-sensitive array). The photosensitive
diodes are connected in series by metal plugs. Light enters the
photosensitive array through dielectric layers.
[0011] The limitation of the approach taught by Chiu is the large
number of additional masks specially added to the SOI core process
in case of thin silicon on insulator layers. Also, for the
mentioned thick Si substrates it is difficult to reach the bottom
oxide-BOX (32) interface with the P+ diffusion, making the proposed
P+-p device structure problematic.
[0012] What is needed is a photovoltaic device that addresses the
problems listed above and can be produced using a standard process
flow with minimal additional masks.
SUMMARY OF THE INVENTION
[0013] The present invention is directed to a method for
fabricating a photovoltaic device on an "island" portion of a
silicon epitaxial layer that is disposed on a monocrystalline
silicon substrate that involves forming porous silicon between the
"island" and the underlying silicon substrate, whereby the porous
silicon isolates the photovoltaic device from the underlying
substrate. The epitaxial layer includes a base (lower) epitaxial
portion (i.e., a portion disposed adjacent to epi/substrate silicon
substrate, and which due to intentional tuning the epi process or
up-diffusion of dopant from the substrate, has an intermediate
(first) doping level that is greater than the relatively low
(second) doping level of an upper portion of the epitaxial layer,
and is lower than a relatively high (third) doping level of the
silicon substrate. The method includes forming P+ and N+ doped
regions in the upper epitaxial layer (which later serve to form
lateral P-I-N light-sensitive diodes), then forming trenches
extending through the epitaxial layer into the silicon substrate
that form side edges of the island, and then utilizing an etchant
entered into the trench to form a porous silicon region that
extends under the island and electrically isolates the island from
the silicon substrate. A benefit of the disclosed production method
is that, by initiating the porous silicon formation at the bottom
of the trench, the porous silicon grows in the silicon substrate
and extends under the island. Further, the change from high doping
level to low doping level in the base epitaxial portion serves both
as an enabler of a self-limiting mechanism that stops the upward
growth of porous silicon in the island, and also serves to suppress
electron-hole recombination. Moreover, the production method is
easily integrated into standard process flows (e.g., established
CMOS, PM CMOS, or MEMS process flows) with only the addition of one
mask used to form the trenches, whereby the photovoltaic device can
be embedded into (i.e., formed on the same base substrate as) an
integrated circuit device, wherein the photovoltaic device is
electrically isolated from the base substrate by the trenches and
porous silicon. By forming the light-sensitive diodes using
existing (or only slightly modified) process flows, the present
invention enables low-cost embedded photovoltaic arrays that can be
integrally formed as part of a CMOS IC (electronic) device (e.g.,
PM, MEMS, RFID and other mixed signal/RFCMOS devices).
Alternatively, the disclosed photovoltaic device can be separated
by etching through the porous silicon to provide, for example,
low-cost, high voltage solar arrays for solar energy
concentrators.
[0014] According to an aspect of the present invention, various
existing processes are beneficially utilized to produce isolated
photovoltaic devices in a highly efficient and cost effective
manner. For example, the trenches are formed by reactive ion
etching through said epitaxial layer into said silicon substrate,
which produces side walls that efficiently capture and retain
light. Optional black silicon is formed on the trench walls to
further enhance light capture. The porous silicon is efficiently
generated using various established methods, such as an
electochemical etch (e.g., using an HF solution and applied
current) or galvanic etching, and passivation is then performed
(e.g., by oxidation or deposition of ALD alumina) to decrease
surface recombination. A protective layer (e.g., SiN formed by CVD)
is selectively formed on the trench walls and over the island to
prevent damage during processing, and a portion of the protective
layer is removed (e.g., by REI) from the bottom of the trenches to
facilitate porous silicon formation in substrate regions under the
island. After porous silicon formation is completed, and optional
porous silicon oxidation performed, the trench is filled with a
dielectric and the protective layer is removed from the upper
surface of the island, thereby exposing the P+ and N+ doped regions
during subsequent contact formation using existing electrical
conductor formation processes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] These and other features, aspects and advantages of the
present invention will become better understood with regard to the
following description, appended claims, and accompanying drawings,
where:
[0016] FIG. 1 is a top front perspective view showing a simplified
photovoltaic device according to a generalized embodiment of the
present invention;
[0017] FIG. 2 is a flow diagram showing a generalized process flow
associated with the photovoltaic device of FIG. 1 according to
another embodiment of the present invention;
[0018] FIGS. 3(A), 3(B), 3(C), 3(D), 3(E), 3(F), 3(G), 3(H) and
3(I) are top front perspective views showing a simplified
photovoltaic device during various stages of fabrication according
to the process flow of FIG. 2;
[0019] FIGS. 4(A), 4(B), 4(C), 4(D), 4(E) and 4(F) are SEM
cross-section images showing buried porous silicon regions
generated in accordance with the process flow according to
exemplary embodiments of the present invention;
[0020] FIG. 5 is a top front perspective view showing a
photovoltaic device according to another embodiment of the present
invention;
[0021] FIG. 6 is a top side perspective view showing a simplified
CMOS IC device including the photovoltaic device as an embedded
power source according to another specific embodiment of the
present invention;
[0022] FIGS. 7(A), 7(B), 7(C) and 7(D) are top front perspective
views showing a method for producing a detached a photovoltaic
device according to another specific embodiment of the present
invention;
[0023] FIG. 8 is a top front perspective view showing a simplified
solar panel formed by detached photovoltaic devices produced in
accordance with the method of FIGS. 6(A) to 6(D) according to
another specific embodiment of the present invention; and
[0024] FIG. 9 is cross-sectional side view showing a photovoltaic
devices produced in accordance with another specific embodiment of
the present invention.
DETAILED DESCRIPTION OF THE DRAWINGS
[0025] The present invention relates to an improvement in
photovoltaic devices produced substantially entirely using existing
process flows. The following description is presented to enable one
of ordinary skill in the art to make and use the invention as
provided in the context of a particular application and its
requirements. As used herein, directional terms such as "upper",
"lower", "above", "below", "vertical" and "horizontal" are intended
to provide relative positions for purposes of description, and are
not intended to designate an absolute frame of reference. The terms
"coupled" and "connected", which are utilized herein, are defined
as follows. The term "connected" is used to describe a direct
connection between two circuit elements, for example, by way of a
metal line formed in accordance with normal integrated circuit
fabrication techniques. In contrast, the term "coupled" is used to
describe either a direct connection or an indirect connection
between two circuit elements. For example, two coupled elements may
be directly connected by way of a metal line, or indirectly
connected by way of an intervening circuit element (e.g., a
capacitor, resistor, inductor, or by way of the source/drain
terminals of a transistor). Various modifications to the preferred
embodiment will be apparent to those with skill in the art, and the
general principles defined herein may be applied to other
embodiments. Therefore, the present invention is not intended to be
limited to the particular embodiments shown and described, but is
to be accorded the widest scope consistent with the principles and
novel features herein disclosed.
[0026] FIG. 1 is perspective view showing a simplified photovoltaic
device 100 according to a generalized embodiment of the present
invention. Photo-voltaic device 100 is at least partially disposed
on one or more silicon "islands" 110 that comprise portions of a P-
epitaxial silicon layer 103, which is formed on a P+
mono-crystalline Si, or germanium, or silicon germanium, or other
semiconductor material, e.g. epitaxial gallium nitride silicon
substrate 101 using known techniques. In particular, the epitaxial
silicon material forming each island 110 includes a base epitaxial
portion 111, which is disposed immediately above an interface
(boundary) 102 between substrate 101 and epitaxial layer 103, and
an upper epitaxial portion 113 disposed over base epitaxial portion
111. Base epitaxial portion 111 is characterized by having an
intermediate "P+/-" (first) doping level that is higher than the
lightly doped P- (second) doping level of upper epitaxial portion
113, and lower than the heavily doped P+ doping level of substrate
101. The intermediate P+/- doping level of base epitaxial portion
111 is generated by the up-diffusion of P-type dopant (e.g., Boron)
from P+ substrate 101 (i.e., through the interface 102 between P+
substrate 101 and epitaxial layer 103). It can be also formed
during the epi growth of the initial P+-epi layer 103 stack (to
control the self limiting process of PS formation). Thus, P+/- base
epitaxial portion 111 is a portion of epitaxial layer 103 when P-
epitaxial silicon is formed on a heavily doped P+ substrate. As
used herein "P+/-" denotes an intermediate doping level (dopant
concentration) that is between the lightly doped "P-" level of
upper epitaxial portion 113 and the highly doped "P+" level of
substrate 101.
[0027] The periphery of island 110 is defined by trench regions
(trenches) T1 and T2, whereby island 110 is electrically isolated
in a lateral direction from a remainder of substrate 101 by
trenches T1 and T2, which are typically filled with a passivation
material (not shown). As such, island 110 is defined by a width
I.sub.W measured between a first vertical side wall 114-1 and a
second vertical side wall 114-2, and an orthogonally oriented
length I.sub.L. Trenches T1 and T2, which are formed in the manner
described below, respectively have widths T.sub.W extending between
side walls 114-1 and 114-2 of island 110 and facing side walls
104-1 and 104-2 of adjacent portions of epitaxial layer 103, and
have depths T.sub.D extending from upper surface 116 of upper
epitaxial portion 113 to bottom surfaces 104-31 and 104-32. Note
that the features depicted in FIG. 1 and the remaining drawings are
not to scale in order to better illustrate the various device
structures.
[0028] Referring to the top of island 110, photo-voltaic device 100
includes at least one lateral P-I-N photo-sensitive diode 120
formed by spaced-apart P+ and N+ doped regions 124 and 125.
Although photo-voltaic device 100 typically includes multiple
lateral light-sensitive P-I-N diodes, only one such diode 120 is
shown in FIG. 1 for purposes of simplifying the following
description. P+ doped region 124 is formed according to well
established methods by a P+ dopant diffused into an associated
portion of upper epitaxial portion 113, and N+ doped region 126 is
formed by an N+ dopant diffused into another portion of upper
epitaxial portion 113, with an intrinsic (undoped) region 125 of
upper epitaxial portion 113 being disposed between P+ region 124
and N+ region 125. Lateral P-I-N photo-sensitive diode structures
are known in the art, so a detailed explanation is omitted here.
The important aspect of showing diode 120 in FIG. 1 is to indicate
that it is substantially formed by doped regions 124 and 126 formed
in P- upper epitaxial portion 113 on island 110.
[0029] According to an aspect of the present invention, base
epitaxial portion 111 of island 110 is entirely disposed on a
porous silicon region 115 that serves, for example, to electrically
isolate island 110 from underlying structures (i.e., in the
vertical direction), such as substrate 101. As indicated by the
shaded region below island 110, porous silicon region 115 extends
under the entire width I.sub.W and the entire length I.sub.L of
island 110, and also extends into portions of substrate 101
disposed adjacent to trenches T1 and T2. As understood in the art,
the phrase "porous silicon" refers to a form of silicon including
nanopores and mesopores (voids) having a width in the range of 2 to
10 nm and 10 to 100 nm respectively (typically, the size of the
pores is in the range of 20-50 nm). The term "porosity" is
generally used to define the amount of space occupied by pores
(voids) in a porous silicon structure, which can range from 4% to
95%. As used herein, the phrases "porous silicon" (PS) and
"oxidized porous silicon" (OPS) refer to regions of silicon
material (i.e., monocrystalline silicon, polycrystalline silicon or
silicon germanium) that are processed to include dispersed
nanopores such that the silicon material exhibits an electrical
resistance greater than 10.sup.7 Ohm. Note that OPS is formed by
oxidizing PS (either chemically or electro-chemically or thermally
or by any other means) to increase its electrical resistance. For
brevity, the phrase "porous silicon" is used herein to refer to
both PS and OPS.
[0030] According to an embodiment of the present invention, base
epitaxial portion 111 has an intermediate (first) P-type doping
concentration forming P+/- (first) doping level (e.g., producing
conductivity in the range of 0.1-0.2 ohm-cm), upper epitaxial
portion 113 and has a relatively low (second) P-type doping
concentration forming a P- (second) doping level (e.g., producing
conductivity in the range of 1-10 ohm-cm), and P+ substrate 101 has
a relatively high (third) P-type doping concentration forming a P+
(third) doping level (e.g., producing conductivity in the range of
0.01-0.02 ohm-cm). The significance of the difference between these
doping levels is that, as described in additional detail below,
this difference causes the etching process used to form porous
silicon region 115 to be self-limiting (i.e., stop) in the
direction of P- epitaxial portion 113 when the etch front
approaches the P-/P+ interface 112 between P+/- base epitaxial
portion 111 and P- upper epitaxial portion 113, resulting in a high
level of control over the thickness of porous silicon region 115
and good lateral uniformity. That is, porous silicon region 115
typically extends into portions of base epitaxial portion 111, but
stops before it reaches lightly doped P- upper epitaxial region
113.
[0031] According to the embodiment depicted in FIG. 1, island 110
is formed by epitaxial material integrally disposed on a silicon
substrate 101, and photo-voltaic device 100 comprises an "embedded"
power source for an associated integrated circuit (IC, not shown)
that is formed in other regions of silicon substrate 101. As used
herein, the phrase "integrally disposed" and "embedded" are
intended to mean that photo-voltaic device 100 and the associated
IC are formed on a single continuous semiconductor substrate (e.g.,
a single "chip" or "die" cut from a monocrystalline wafer). As
such, island 110 is formed by epitaxial material disposed on a
portion of silicon substrate 101 that is isolated laterally from
the IC by trenches T1 and T2, and is isolated vertically from the
IC by porous silicon region 115. An exemplary process for
generating this characteristic structure is described below with
reference to FIGS. 2 and 3(A) to 3(I). According to an aspect of
such "embedded" embodiments, base epitaxial portion 111 has the
same intermediate (first) P+/- doping level as that of all lower
regions of epitaxial layer 103 disposed adjacent to interface 102
with silicon substrate 101, and upper epitaxial portion 113 has the
same (second) P- doping level as that of the remaining upper
regions of epitaxial layer 103. That is, by utilizing a fabrication
process such as that described below, island 110 comprises a
section of epitaxial layer 103 that is electrically isolated from
the remainder of epitaxial layer 103 and substrate 101 by the
formation of trenches T1 and T2 and porous silicon region 115, but
is otherwise electrically identical to the remainder of epitaxial
layer 103.
[0032] FIG. 2 is a flow diagram depicting a generalized method for
producing photovoltaic devices on a silicon substrate (such as
silicon substrate 101, described above) according to another
embodiment of the present invention. Referring to the upper portion
of FIG. 2, the generalized method begins by (block 210) forming P+
and N+ doped regions in the P- epitaxial layer, e.g., utilizing the
standard P+ and N+ implants associated with a standard CMOS process
flow. Next, (block 220) one or more islands are formed by etching
elongated trenches through the epitaxial layer and into the
underlying P+ silicon substrate. As described above, the resulting
island includes the P+ and N+ doped regions disposed in a portion
of the P- epitaxial layer, which in turn is disposed over a portion
of the P+ silicon substrate. The generalized method then involves
(block 230) forming a porous silicon region in the portion of P+
silicon substrate disposed under the elongated island such that the
porous silicon region electrically isolates the elongated island
from the underlying P+ silicon substrate. As described in detail
below, the formation of porous silicon involves etching a region of
the P+ substrate accessed through bottom surfaces of the trenches
such that porous silicon grows and spreads laterally until adjacent
porous silicon (PS) growths merge under the islands. A significant
benefit of the generalized production method is that the associated
fabrication processes needed to produce the various structures of
photovoltaic device 100 can be easily integrated into standard
process flows (e.g., established CMOS process flows, power
management (PV) CMOS process flows, and microelectromechanical
system (MEMS) process flows) with minimal modifications (i.e., the
addition of a single "trench" mask, described below). That is,
other than the formation of the "trench" mask, all of the
associated fabrication processes described below are either
implemented during or easily added to a conventional process flow.
Other features and advantages of the generalized production method
are described below with reference to FIGS. 3(A) to 3(I).
[0033] FIGS. 3(A) to 3(I) are perspective drawings illustrating the
generalized production method of FIG. 2 in additional detail, and
the related description provides further information regarding
practical embodiments performed in accordance with specific
embodiments of the present invention.
[0034] Referring to FIG. 3(A), the production method begins with a
P+ silicon substrate 101 having a silicon epitaxial layer 103 that
is produced using known techniques. As described above, epitaxial
layer 103 includes a P+/- base epitaxial portion 111 disposed
immediately above an interface 102 with P+ substrate 101, and a P-
upper epitaxial portion 113 disposed over base epitaxial portion
111. Note that in embedded applications, epitaxial layer 103 is
utilized both for the formation of photovoltaic devices and the
formation of other CMOS IC structures that are simultaneously
fabricated on another portion of epitaxial layer 103. That is,
patterned P+ doped regions 124-1, 124-2 and 124-3 and patterned N+
doped regions 126-1, 126-2 and 126-3, which are associated with
three photo-sensitive diodes 120-1, 120-2 and 120-3, respectively,
where each associated N+ and P+ doped region is separated by an
associated intrinsic region 125-1, 125-2 and 125-3 formed by the P-
material of epitaxial layer 103. For example, diode 120-1 includes
P+ doped region 124-1, N+ doped region 126-1, and intrinsic region
125-1 that is disposed between P+ doped region 124-1 and N+ doped
region 126-1. Similarly, diode 120-2 includes P+ doped region
124-2, N+ doped region 126-2, and intrinsic region 125-2, and diode
120-3 includes P+ doped region 124-3, N+ doped region 126-3, and
intrinsic region 125-3. With this arrangement, the P+ and N+ doped
regions are entirely separated (e.g., P+ doped region 124-1 is
entirely separated from the N+ doped region 126-1 by intrinsic
region 125-1), thereby forming the desired lateral P-I-N diode
structure. Note that N+ doped region 126-1 of diode 120-1 and P+
doped region 124-2 of diode 120-2 are disposed in corresponding
adjacent regions of epitaxial layer 103, and that N+ doped region
126-2 of diode 120-2 and P+ doped region 124-3 of diode 120-3 are
disposed in corresponding adjacent regions of epitaxial layer 103.
In a practical example, the geometry defined by the associated P+
and N+ implantation masks includes: N+ implant (5 .mu.m), space (5
.mu.m), P+ implant (5 .mu.m), intrinsic (100.mu.). As set forth
below, the adjacent doped regions are connected in a later part of
the fabrication process utilized to complete the formation of
diodes 120-1, 120-2 and 120-3. Note also that each doped region
(e.g., P+ doped region 124-1 and N+ doped region 126-1 of diode
120-1) is elongated in the lateral (width) direction of the
yet-to-be-formed island, and that each doped region is implanted to
a depth (e.g., less than 100 nm) from upper surface 106 of
epitaxial layer 103 so that they do not influence subsequent trench
etch and PS formation procedures, described below). The drive of N+
and P+ is performed after the trench etch and porous silicon
formation. FIG. 3(C) shows N+ and P+ regions before the
drive-in.
[0035] FIG. 3(B) shows a "trench" mask 212, which represents the
single additional mask required to be added to a standard process
flow (e.g., an established CMOS, PM CMOS, or MEMS process flow).
Mask 212, which is formed using conventional methods and materials,
is disposed on upper surface 106 covered with thermal SiO.sub.2/SiN
layers (to decrease recombination for SiO.sub.2 and protect the
surface during etch back when cleaning the bottom of trenches after
SiN deposition; the top protective layer of SiN is 0.1-0.3 .mu.m;
SiO.sub.2 liner under is .about.100-200 A). Mask 212 is patterned
to include an elongated mask portion 214 disposed between parallel
openings 216, where mask portion 214 extends over (masks) all of
the previously formed P+ and N+ doped regions (i.e., extends in the
length direction of the yet-to-be-formed island).
[0036] FIG. 3(C) depicts the formation of trenches T1 and T2
through openings 216 of mask 212 (i.e., over regions of substrate
101 where local isolation will be formed). In one embodiment,
trenches T1 and T2 are etched using well known reactive ion etching
techniques such that substantially vertical side walls 104-1,
104-2, 114-1 and 114-2 are formed on opposite sides of each trench,
and extend through epitaxial layer 103 and into said silicon
substrate 101, whereby upper epitaxial portion 113 is separated
from epitaxial layer 103 and base epitaxial portion 111 is disposed
above and between the lower ends of trenches T1 and T2. In a
practical embodiment, a pattern of 4-40 .mu.m deep and 2 .mu.m wide
trenches was fabricated using a standard deep dry etching process
(Bosch process) on wafers of heavily doped P+Si (0.01-0.02 ohm-cm)
having a 4 .mu.m thick epi-layer of lightly doped Si (1-10 ohm-cm),
with base epitaxial portion 111 having a nominal conductivity of
0.1-0.2 ohm-cm. According to an aspect of the present invention,
the pattern of trenches acts as a light trap. The light entering
the deep trench has small chances to be reflected by the HV solar
array. In another embodiment, black silicon is formed on the walls
of the trenches to further enhance light capture. Mask 212 is
removed after the trenches are formed.
[0037] FIGS. 3(D) and 3(E) depict the subsequent formation of a
protective layer 228 over island 110 and on the vertical side walls
and bottom surfaces defined by trenches T1 and T2, and then the
subsequent removal of protective material from the bottom surfaces.
Referring to FIG. 3(D), protective layer 128 is formed, for
example, by chemical vapor deposition such that portions of the
protective material layer are disposed on side walls 114-1 and
114-2 of island 110, on side walls 104-1 and 104-2 of substrate
101, and on bottom surfaces 104-31 and 104-32 that extends between
the facing vertical side walls in trenches T1 and T2. A portion
128A of protective layer 128 is also formed on upper surface 116 of
island 110. The function of protective layer 128 is to isolate
contact of the subsequent etch used to form porous silicon to P+
substrate region 101 (i.e., to prevent the PS etchant from
contacting upper epitaxial portion 113 through side walls 114-1 and
114-2), and also to protect the P+ and N+ doped regions formed on
island 110. The presence of protective layer 128 in trenches T1 and
T2 is thus critical to the formation of the PS layer under island
110. In a presently preferred embodiment, protective layer 228
comprises a layer of silicon nitride (e.g., 5 nm-50 nm SiO.sub.2
liner and then SiN; the SiO.sub.2 liner allows passivating the
vertical walls of the solar cell and decreases recombination)
formed by chemical vapor deposition and having a thickness in the
range of 100 to 300 nm, although other protective layers formed by
other deposition methods may also be utilized. To further
facilitate the formation of PS in substrate 101 below island 110,
as indicated in FIG. 3(E), a portion of protective layer 128
disposed on bottom surfaces 104-31 and 104-32 of trenches T1 and T2
is removed by a suitable method (e.g., reactive ion etch in the
case of SiN), whereby bottom surfaces 104-31 and 104-32 are exposed
through protective layer 128. That is, protective material is
etched off of bottom surfaces 104-31 and 104-32 to enable
electrical contact between the electrochemical solution
subsequently used to form porous silicon and heavily doped P+
substrate 101 through the trenches T1 and T2.
[0038] FIGS. 3(F) and 3(G) depict the subsequent formation of
porous silicon (PS) under island 110 according to an exemplary
embodiment of the present invention such that P+/- base epitaxial
portion 111 is retained between upper epitaxial portion 113 and the
porous silicon. As indicated in FIG. 3(F), porous silicon formation
is initiated by introducing a suitable etchant 232 into trenches T1
and T2 such that etchant 232 acts on exposed bottom surfaces 104-31
and 104-32 (i.e., remaining protective layer 128 prevents etchant
128 from acting on side walls 114-1 and 114-2 of island 110) to
initiate the growth of porous silicon regions 115-1 and 115-2 at
the bottom of trenches T1 and T2, respectively. In one embodiment
this process is performed using electrochemical (EC) etching by
placing substrate 101 into the hydro-fluoric (HF) solution, and the
process is activated by an external current source connected
between a top electrode 234 (inside the HF solution) and a bottom
metal electrode 235 at the backside surface 101L of Si substrate
101. The main advantage of using this EC etching process is it is
relative high speed (from few nm/min up to few .mu.m/min) and is
self-limiting (meaning that the etch in the direction of P-
epitaxial portion 113 stops when the etch front approaches the P-
P+ interface 102, resulting in a high level of PS thickness control
and good lateral uniformity. In addition, by controlling the
current, one can vary the porosity and size of the pores of PS
regions 115-1 and 115-2 quite easily. As indicated in FIG. 3(G),
the EC etching process is continued until the two PS regions merge
under island 110, thereby forming continuous PS region 115 that
entirely isolates island 110 from P+ substrate 101. Further,
because of the self-limiting characteristics of the EC etching
process, island 110 is characterized by having P+/- base epi
portion 111 disposed between P- upper epitaxial portion 113 and PS
region 115, which serves to suppress electron-hole recombination at
porous silicon-silicon interface.
[0039] The EC process etch rate (PS formation) strongly depends on
the doping of the P+ substrate. During experiments conducted by the
inventors, samples were placed into a standard electrochemical cell
that operated in the "galvanostatic" mode (i.e., under a constant
current). The process lasted for typical times of about 50-100
seconds. The results of these experiments showed PS having been
selectively created at the bottom of the trenches where the EC
solution is in contact with the heavily doped Si substrate. FIGS.
4(A) to 4(D) show a few SEM cross-section images showing the
resulting porous silicon structures formed at the bottoms of
trenches. The thickness of the epitaxial P- layer in the structures
of these figures is 4 .mu.m. FIGS. 4(A) and 4(B) show the results
of EC etching at a current density of 50 mA/cm.sup.2 after a 30
second etch, and FIGS. 4(C) and 4(D) shows similar structures using
a EC current density of 2 mA/cm.sup.2 and etching time of 150 s. As
can clearly be seen in FIGS. 4(A) and 4(B), a `mushroom-like` PS
film is created at the bottom of the trenches indicating that most
of the EC current flows towards the heavily doped (and
low-resistivity) substrate rather than towards the upper lightly
doped epi-layer. The smaller the EC current density, the less
etching of the epi-layer and less damage to the sidewalls and the
top Si surfaces occurs. In FIGS. 4(A) and 4(C), the distance
between the trenches is 12 .mu.m so that the etching time is not
long enough to generate a connected network of mushroom, while in
FIGS. 4(B) and 4(D) the distance between the trenches is 5 .mu.m
and the mushrooms merge, creating a complete isolation between the
top epi-layers and the substrate.
[0040] In another embodiment the surface of trenches was converted
into PS by a special etch before SiN deposition and passivated by
oxidation or deposition of ALD (atomic layer deposited) alumina
(see, e.g., Extremely low surface recombination velocities in black
silicon passivated by atomic layer deposition, Martin Otto,
Matthias Kroll, Thomas Kasebier, Roland Salzer, Andreas Tunnermann
et al., Applied Physics Letters, 100, 191603 (2012)). The formation
of black silicon is believed to enhance light absorption inside the
islands, providing a further advantage to photovoltaic devices
formed in accordance with the present invention. In addition, as
indicated in FIGS. 3 (H-I) and 4 (A-D) the mushroom-like, buried
layer of PS acts as random scatterers also to create a "black
silicon" effect, i.e., increase the light absorption in the films,
mainly due to the large refractive index difference between the PS
films and the epi-silicon above.
[0041] According to an alternative embodiment, the EC etching
process is modified to generate electrochemical oxidation in order
to increase the resistivity of the PS region. Forming porous
silicon without special further oxidation facilitates effective
electrical isolation that is sufficient for operating solar cell
arrays (i.e., 10.sup.7-10.sup.8 Ohm for an isolated 100 .mu.m long
and 12 .mu.m wide silicon island with respect to the P+ substrate).
During practical testing, subsequent mild electrochemical oxidation
increased the resistance of the PS to 10.sup.10-10.sup.11 Ohm.
[0042] According to another alternative embodiment, in addition to
the EC process described above, similar PS formation is achieved
with Galvanic Etching, where electrochemical closed circuit is also
formed but no external bias applied. The galvanic etching (GE) to
produce PS layers is based on the chemical oxidation-reduction
reaction at the interface of the metallic back contact and using of
the HF-oxidant (H.sub.2O.sub.2) solution. The reaction proceeds via
generation of a hole at the metal-covered (Au or silver alloy) side
after oxidation of the metal while the just generated hole diffuses
to the other side of the silicon wafer to react with HF and start
the silicon etching process. An advantage of the GE method is its
parallel processing nature, enabling the production of many samples
simultaneously. A demonstration of the GE process is shown in FIGS.
4(E) and 4(F).
[0043] FIG. 3(H) shows island 110 after filling of the trenches
with a dielectric 140 (HD plasma CVD), followed by a chemical
mechanical polishing (CMP) step to expose SiN over P+ doped regions
124-1 to 124-3 and N+ doped regions 126-1 to 126-3 on upper surface
116 of epitaxial portion 113, followed by removal of the protective
layer over island 110. In one embodiment, the CMP process stops at
the nitride layer disposed on surface 116, and when processing
continues with the formation of interconnects, the remaining SiN
layer over island 110 is removed by wet or dry etch locally through
a mask. Annealing is then performed (e.g., 6-10 hours at
1000-1100.degree. C. for trenches having a depth of 4 .mu.m) to
cause the N+ and P+ doped regions to diffuse to the surface of the
PS layer.
[0044] FIG. 3(I) shows a substantially completed photovoltaic
device 100B in accordance with an embodiment of the present
invention. Photovoltaic device 100B differs from device 100 (FIG.
1) in that device 100B includes retained portions of protective
layer 128 (e.g., silicon nitride) disposed on side walls 114-1 and
114-2 of island 110. Such protective layer portions are a byproduct
of the process described above and improve the performance of
photovoltaic device 100B by passivating the walls thus
substantially decreasing surface recombination. As mentioned above,
the retained protective layers may include a portion of passivated
black silicon to further improve light absorption in the
trenches.
[0045] Photovoltaic device 100B also differs from device 100 (FIG.
1) in that device 100B includes a series of photo-sensitive diodes
120-1 to 120-3 that are connected in series along island 110 by
electrically conductive structures 130-1 to 130-4. Specifically,
structures 130-1 and 130-4 are disposed on P+ doped region 124-1
and 126-3, respectively to provide terminals of the device formed
by diodes 120-1 to 120-3. To decrease series resistance, structures
130-2 and 130-3 are respectively connected across a (first) P/N
junction formed by N+ region 126-1 and P+ region 124-2 (i.e.,
between diodes 120-1 and 120-2), and a (second) P/N junction formed
by N+ region 126-2 and P+ region 124-3 (i.e., between diodes 120-2
and 120-3). Electrically conductive structures 130-2 and 130-3 are
preferably metal film structures that are elongated in the lateral
direction and have just enough length in the longitudinal direction
to operably contact a portion of each associated doped region such
that electrically conductive structure 130-2 forms a low resistance
electrically conductive path between lateral light-sensitive diodes
120-1 and 120-2, and electrically conductive structure 130-3 forms
a low resistance electrically conductive path between lateral
light-sensitive diodes 120-2 and 120-3. In one embodiment,
structures 130-1 and 130-4 are formed by salicide-butted contact
structures or a conductive paste. In other embodiments, an aluminum
film, a titanium film, a titanium-nitride stack, gold, and tungsten
are used.
[0046] FIG. 5 shows a simplified high voltage (HV) solar array
(photovoltaic device) 100C formed on a host substrate 101C
according to another embodiment of the present invention. Array
100C includes twelve photo-sensitive diodes 120 disposed on four
parallel elongated islands 110-1 to 110-4 that are separated by
intervening elongated trenches T.sub.1. Each island 110-1 to 110-4
includes three photodiodes 120 formed in the manner described above
with reference to FIG. 3(I), and conductive structures 130 are
disposed on the islands and connect diodes 120 in series (along
each island) with the four island connected in parallel in the
manner described above with reference to FIG. 3(I). The drive-in of
the P+ and N+ implant is performed after the trench etch, so that
N+ and P+ regions reach the porous silicon layer. According to an
aspect of the invention, silicon islands 110-1 to 110-4 are
integrally connected by silicon end island portions 110-5 and 110-6
(having N+ and P+ doping levels, respectively), and a peripheral
trench T.sub.p surrounds all of islands 110-1 to 110-4 and end
island portions 110-5 and 110-6, thus isolating array 100C
laterally from a remainder of host substrate 101C. End island
portions 110-5 and 110-6 are formed during the same process as that
described above, and therefore all of islands 110-1 to 110-4 and
end island portions 110-5 and 110-6 comprise a P+/- base epi
portion 111 disposed between a porous silicon layer 115 and a P-
upper epitaxial portion 113 in the manner described above.
[0047] Array 100C provides an advantage over conventional
photovoltaic devices in that the associated fabrication processes
needed to produce the various photovoltaic device structures of
array 100C can be easily integrated into standard process flows
(e.g., established CMOS process flows, power management (PV) CMOS
process flows, and microelectromechanical system (MEMS) process
flows) without requiring any (or requiring very few) additional
masks. Thus, the novel structural arrangement of array 100C is
easily integrated into standard process flows using only slightly
modified) process steps. By forming photovoltaic devices using
existing (or only slightly modified) process flows, the present
invention facilitates the use of photovoltaic device 100C to form
low-cost embedded photoelectric arrays on IC devices formed by
these standard process technologies. For example, referring briefly
to FIG. 6, a simplified CMOS IC 300 is shown that includes both
photovoltaic device 100C (described above) and a generic CMOS
circuit 310 (e.g., a PM, MEMS, RFID or other mixed signal/RFCMOS
device) that are entirely formed on a monocrystalline silicon
substrate 301 using a standard CMOS process flow that is modified
as described above to facilitate trench and PS formation. In this
example, photovoltaic device 100C is connected as a supply power to
CMOS circuit 310 by way of metal lines formed in accordance with
the techniques described herein.
[0048] According to another alternative embodiment of the present
invention described with reference to FIGS. 7(A) to 7(D), the
photovoltaic devices of the present invention are separated from
their base substrate and mounted onto low-cost substrates (e.g.,
glass or other types of isolators) to produce, for example,
low-cost, high voltage solar arrays for medium-level (i.e., from
several to tens of suns) solar energy concentrators. As indicated
in FIGS. 7(A) and 7(B), the presence of porous silicon layer 115
facilitates separating ("lifting") array 100C from substrate 101C
after it is completed by etching through porous silicon layer 115
such that array 100C becomes separated from substrate 101C. As
indicated in the lower portion of FIG. 7(B), by starting with a
relatively thick layer of substrate material, a significant portion
of substrate 101C remains after array 100C is removed, with the
newly-exposed "upper" surface comprising porous silicon 115.
Referring to FIGS. 7(C) and 7(D), substrate 101C is prepared for
further processing by performing a surface polishing process (e.g.,
CMP) to generate a planar surface 102C, and then a new P- epitaxial
layer 103C is formed on surface 102C, thereby preparing substrate
101C for processing in the manner described above to generate a new
array 100C. Only a thickness of approximately 10 .mu.m to 20 .mu.m
is removed from P+ substrate 101C during the CMP procedure
preceding P- layer growth, thereby facilitating the use of a single
substrate 1010 to make multiple HV solar cell arrays 100C. Further,
as indicated in FIG. 8, a low cost HV solar array 500 is fabricated
by mounting multiple separated arrays 100C on a low cost (e.g.,
glass) substrate 501.
[0049] FIG. 9 is cross-sectional side view showing a photovoltaic
device 100D produced in accordance with yet another specific
embodiment of the present invention. Like previous embodiments,
device 100D includes multiple silicon islands separated by
intervening trenches (e.g., islands 110-21 and 110-22 are separated
by trench T21), and each island includes both a P- upper epitaxial
portion 113C and a P+/- base epi portion 111C formed on a porous
silicon layer 115C. In addition, each island 110-21 and 110-22
includes P+ and N+ regions separated by intrinsic P- material
(e.g., island 110-21 includes P+ region 124-21 and N+ region
126-21, and island 110-22 includes P+ region 124-22 and N+ region
126-22). However, device 100D differs from previous embodiments in
that one photo-sensitive diode is formed on each island, and the
diodes are connected in series by conductive structures extending
over the intervening trench (e.g., P+ region 124-21 is connected to
N region 126-22 by intervening structure 130-21). The benefit of
separating the series-connected diodes on separate islands is that
P+ and N+ regions can be more shallow than in previous embodiments
thus not needing high thermal budgets to drive-in the N+ and P+
implants through the whole thickness of the epitaxial layer. Light
conversion efficiency can be increased by way of the "black
silicon" produced on the side walls of the trenches (forming black
silicon before SIN and passivating the surfaces). Note that device
110D also depicts the use of standardized metallization to provide
conductive structure 130-21 (i.e., using vias and metal lines
formed in M1 metallization), which can be used to further reduce
manufacturing costs.
[0050] Although the present invention has been described with
respect to certain specific embodiments, it will be clear to those
skilled in the art that the inventive features of the present
invention are applicable to other embodiments as well, all of which
are intended to fall within the scope of the present invention. For
example, although the process is described above with reference to
the formation of photovoltaic devices on a P-type substrate, the
methods descried above may be modified using techniques known in
the art to produce similar devices on N-type substrates. Further,
the Si epitaxial layer described above may be implemented using
another semiconductor such as Ge, SiGe and GaN.
* * * * *