U.S. patent application number 14/216858 was filed with the patent office on 2014-09-18 for methods for reducing charge effects and separation forces in nanoimprint.
The applicant listed for this patent is The Trustees of Princeton University. Invention is credited to Stephen Y. Chou, Yixing Liang.
Application Number | 20140264989 14/216858 |
Document ID | / |
Family ID | 51523990 |
Filed Date | 2014-09-18 |
United States Patent
Application |
20140264989 |
Kind Code |
A1 |
Chou; Stephen Y. ; et
al. |
September 18, 2014 |
METHODS FOR REDUCING CHARGE EFFECTS AND SEPARATION FORCES IN
NANOIMPRINT
Abstract
The present invention relates to methods to reduce release force
caused by tribo-charge. The invented mold is termed as MicroE mold
and substrate is termed as MicroE substrate. The addition of
conductive thin coatings (less than 10 nm and approaching monolayer
coating) onto surface of insulating mold or substrate provides a
reduction of the separation force caused by tribo-electric charge.
The MicroE mold and MicroE substrate are specifically good for a
lithographic method that involves contact between mold and
substrate, or between mold and thin film carried on substrate, and
used for creation and replication of ultra-fine structures (sub-25
nm) as well as millimeter scale. The present invention is
particularly but not exclusively applied to any contact
lithographic method.
Inventors: |
Chou; Stephen Y.;
(Princeton, NJ) ; Liang; Yixing; (Princeton,
NJ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
The Trustees of Princeton University |
Princeton |
NJ |
US |
|
|
Family ID: |
51523990 |
Appl. No.: |
14/216858 |
Filed: |
March 17, 2014 |
Related U.S. Patent Documents
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Application
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Patent Number |
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61802223 |
Mar 15, 2013 |
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61802020 |
Mar 15, 2013 |
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61794317 |
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61801933 |
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61793092 |
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61800915 |
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61801096 |
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61801424 |
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Current U.S.
Class: |
264/39 |
Current CPC
Class: |
B29C 33/424 20130101;
G01N 21/6486 20130101; G01N 21/658 20130101; B29C 37/0003 20130101;
B29C 2059/023 20130101; B29C 59/026 20130101; G01N 21/648 20130101;
B29C 33/56 20130101; B29K 2995/0005 20130101; G03F 7/0002 20130101;
B29C 59/02 20130101 |
Class at
Publication: |
264/39 |
International
Class: |
B29C 33/00 20060101
B29C033/00 |
Claims
1. A method to reduce tribo-electricity effect between a mold and a
resist on a substrate and improve mold separation and/or
nanoimprint quality, comprising: (a) adding a conducting layer on
the mold; (b) adding a conducing layer on the substrate; and (c)
grounding the conducting layer on the mold and the conducting layer
on the substrate, thereby reducing the tribo-electricity effect
between a mold and a resist on a substrate, and/or improving the
mold separation and/or nanoimprint quality.
Description
CROSS-REFERENCING
[0001] This application is also claims the benefit of: provisional
application Ser. No. 61/801,424, filed Mar. 15, 2013 (NSNR-004PRV),
provisional application Ser. No. 61/801,096, filed Mar. 15, 2013
(NSNR-005PRV), provisional application Ser. No. 61/800,915, filed
Mar. 15, 2013 (NSNR-006PRV), provisional application Ser. No.
61/793,092, filed Mar. 15, 2013 (NSNR-008PRV), provisional
Application Ser. No. 61/801,933, filed Mar. 15, 2013 (NSNR-009PRV),
provisional Application Ser. No.61/794,317, filed Mar. 15, 2013
(NSNR-010PRV), provisional application Ser. No. 61/802,020, filed
Mar. 15, 2013 (NSNR-011PRV) and provisional application Ser. No.
61/802,223, filed Mar. 15, 2013 (NSNR-012PRV), all of which
applications are incorporated by reference herein for all
purposes.
BACKGROUND
[0002] Nanoimprint needs reduction charge effects and separation
forces.
SUMMARY
[0003] The following brief summary is not intended to include all
features and aspects of the present invention, nor does it imply
that the invention must include all features and aspects discussed
in this summary.
[0004] The invention is related to the methods and apparatus to
reduce charge effects and separation forces in nanoimprint, hence
improve nanoimprint quality.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The skilled artisan will understand that the drawings,
described below, are for illustration purposes only. The drawings
are not intended to limit the scope of the present teachings in any
way. Some of the drawings are not in scale.
[0006] FIG. 1 Schematics of a nanoimprint mold and a substrate,
each has three layers. The table shows which layer should be
grounded. The best approach is the ground layer as close to the
contact surface as possible.
[0007] FIG. 2 Schematics of the possibility of grounding.
[0008] FIG. 3 (A) the cross section view of one type of MicroE mold
that has an insulating body. (B) the cross section view of one type
of MicroE mold that has a conductive body. And (C) the cross
section view of MicroE substrate that carries a thin film as
resist.
[0009] FIG. 4 is the experimental results comparing the effect in
reducing the separation force between planar MicroE mold and
conventional mold.
[0010] FIG. 5 The experimental results comparing the effect in
reducing the separation force between the nanostructured MicroE
mold and conventional mold, showing the advantage of the MicroE
mold.
[0011] Corresponding reference numerals indicate corresponding
parts throughout the several figures of the drawings. It is to be
understood that the drawings are for illustrating the concepts set
forth in the present disclosure and are not to scale.
[0012] Before any embodiments of the invention are explained in
detail, it is to be understood that the invention is not limited in
its application to the details of construction and the arrangement
of components set forth in the following description or illustrated
in the drawings.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
[0013] The following detailed description illustrates some
embodiments of the invention by way of example and not by way of
limitation.
[0014] This disclosure incorporates by reference the following
disclosures: U.S. application Ser. No.13/838,600, filed Mar. 15,
2013 (NSNR-003), and U.S. application Ser. No. 13/699,270, filed
Jun. 13, 2013 (NSNR-001).
[0015] The invention is related to nanoparticle structures,
[0016] The methods invented, that can reduce the charge effects in
nanoimprint, comprising [0017] 1. Having a substrate with a thin
conducting layer up close to the surface; [0018] 2. Having a mold
with conducting layer close to surface, therefore the contact
charge between the mold and the substrate will be reduced.
[0019] In another approach, when separating the mold and substrate,
an ion beam discharge will be used to discharge the charge between
the mold and substrate. The separation will start from edge and
gradually open up.
[0020] the deposit metal film on the surface of the mold, in thin
resist with good conductivity using light after imprint to increase
conductivity of the resist, if resist is photoconductive.
[0021] The present invention relates to the strength of electric
field between mold and substrate in their separation. For any
lithography that involves contact, tribo-electricity is generated
after lithography mask separates from substrate. The tribo-charge
on the surface of mold and thin film on substrate give rise to
electric field between them. The electric field caused attraction
between mold and substrate and enlarges the mold-substrate
separation force.
[0022] The present invention relates to the method to reduce the
strength of electric field between mold and substrate in their
separation. The method is to coat a thin conductive layer (thinner
than 10 nm and approaching monolayer) onto insulating mold surface
and onto surface of substrate carrying on insulating thin film. The
image charge induced in the process of mold-substrate separation
reduces the strength of electric field in the gap between them. The
description of conductive and insulating material may be described
as follows. A conductive coating or material is one whose
relaxation time is shorter than the time taken to separate mold
from substrate. The relaxation time of material is the product of R
and C, where R is the material resistance and C is the material
capacitance. In addition, the relaxation time equals to
.epsilon..sub.0/.sigma. a for metallic materials and
.epsilon..sub.r.epsilon..sub.0/.sigma. for semiconducting or
dielectric materials, where .epsilon..sub.0 and .epsilon..sub.r are
vacuum permittivity and relative dielectric constant respectively,
and .sigma. is conductivity of material. Setting t as the process
time to release mold from substrate, by conductive materials, it
meant that conductivity of materials is larger than .epsilon./t,
while insulating materials means materials whose conductivity
smaller than .epsilon./t. For example, if it takes 1 ms to separate
mold from substrate, then materials and coating film having a
conductivity larger than 10.sup.-6 S/m are conductive materials. By
the same principle, conductivity of insulating materials is smaller
than 10.sup.-6 S/m.
[0023] FIG. 3A shows MicroE mold 1 that has insulating body 2 as
defined above. Surface of MicroE mold is coated by a thin
conductive layer 3. On top of 3 deposited a layer of release layer
that has non-stick functionality as US 2001/6309580 (Stephen Chou).
The conductive coating material can be, but not limited to,
metallic, semi-metallic, metallic and semi-metallic oxides,
carbides and nitrides, polymeric, semiconductors, glass, ceramic,
dielectrics and composites, as long as the charge relaxation time
of materials (RC time) is shorter than time t used in separation.
The thickness of the coating is thinner than 10 nm and approaches
monolayer thickness until the conductivity of thin film
significantly drop and the film transforms to insulator. The
insulating body 2 in FIG. 1A has a relaxation time longer than
separation time t, particularly but not exclusively includes glass,
ceramic, polymeric materials, oxides, carbides and nitrides
dielectrics and composites.
[0024] FIG. 3B shows another type of MicroE mold 5. It has a
conductive body 6, on top of which coated by anti-sticky layer 8 as
disclosed in US 2005/0146079 (Stephen Chou). The conductive thin
layer 7 between 6 and 8 is coated only when the surface of MicroE
mold body 6 does not provide sufficient bonds to anti-sticky layer
8 and performs to assist molecular bonding. The materials of
conductive layer coating includes but not limited to metallic,
semi-metallic, metallic and semi-metallic oxides, carbides and
nitrides, polymeric, semiconductors, glass, ceramic, dielectrics
and composites.
[0025] FIG. 3C shows the MicroE substrate 9. It consists of a
substrate body 10. A thin conductive layer 11 is coated on the
surface of substrate body 10 and carries the thin film 12 known as
resist in lithography methods. Examples of thin layer 11 are but
not limited to metallic, semi-metallic, metallic and semi-metallic
oxides, carbides and nitrides, polymeric, semiconductors, glass,
ceramic, dielectrics and composites. Thin film 12 may comprise
thermally or optically curable polymer material or any other
materials that may change materials property following the change
of environment (e.g. heating, mechanically re-shaping, optically
shinning, electron beam treating).
[0026] Furthermore, light can be used to reduce the tribo-electric
charge.
[0027] Although the foregoing invention has been described in some
detail by way of illustration and example for purposes of clarity
of understanding, it is readily apparent to those of ordinary skill
in the art in light of the teachings of this invention that certain
changes and modifications may be made thereto without departing
from the spirit or scope of the appended claims.
[0028] Accordingly, the preceding merely illustrates the principles
of the invention. It will be appreciated that those skilled in the
art will be able to devise various arrangements which, although not
explicitly described or shown herein, embody the principles of the
invention and are included within its spirit and scope.
Furthermore, all examples and conditional language recited herein
are principally intended to aid the reader in understanding the
principles of the invention and the concepts contributed by the
inventors to furthering the art, and are to be construed as being
without limitation to such specifically recited examples and
conditions. Moreover, all statements herein reciting principles,
aspects, and embodiments of the invention as well as specific
examples thereof, are intended to encompass both structural and
functional equivalents thereof. Additionally, it is intended that
such equivalents include both currently known equivalents and
equivalents developed in the future, i.e., any elements developed
that perform the same function, regardless of structure. The scope
of the present invention, therefore, is not intended to be limited
to the exemplary embodiments shown and described herein. Rather,
the scope and spirit of present invention is embodied by the
appended claims.
EXAMPLES
[0029] An example of MircroE mold body consists of silicon dioxide
backed by silicon bulk. The conductive layer used in one experiment
is Ti. A 5 nm Ti coating layer was coated onto the surface of
MicroE mold body using electron beam sputtering machine. A mold
release layer of 1H, 1H, 2H, 2H-perfluorodocecyltrichlorosilane
(commercially available as a 97% solids solution) is bonded to the
surface of Ti and used as an anti-release layer.
[0030] The MicroE mold was then applied in nanoimprint lithography
US 1998/5772905 (Stephen Y Chou). In nanoimprint lithography, the
silicon substrate carries a commercially thermal-plastic resist
(NX-1025) that would get intimate get with the MicroE mold and get
separated afterwards.
[0031] FIG. 4 shows experimental results on peak separation force
comparing MicroE mold with conventional mold without 5 nm
conductive coating. In the experiment, MicroE mold is planar. A
8.times. reduction in separation force is obtained by using MicroE
mold with a bulky silicon dioxide body and nanomprinted onto
thermal-plastic resist on silicon substrate.
[0032] FIG. 5. shows experimental results on peak separation force
comparing MicroE mold with conventional mold without 5 nm
conductive coating. In the experiment, MicroE mold has 200 nm pitch
160 nm deep grating and 1 micro-meter pitch, 160 nm deep grating
feature size. The substrate used is silicon substrate that carries
NX-1025 thermal-plastic resist. A 3.times. reduction in separation
force is obtained for MicroE mold with 1 micron-meter pitch grating
and 2.times. reduction for the one with 200 nm pitch grating
features.
[0033] Table 1 shows results on measured charge density on
as-imprinted thin film on substrate as a function of thickness of
SiO2 middle layer.
TABLE-US-00001 TABLE 1 Imprint Charge Substrate Type Surface
Potential (V) density (C/m.sup.2) Si* T-NIL 19 2.5 .times.
10.sup.-3 1 .mu.m SiO.sub.2/Si* T-NIL 80 2.2 .times. 10.sup.-3 2.5
.mu.m SiO.sub.2/Si* T-NIL 179 2.3 .times. 10.sup.-3 5 .mu.m
SiO.sub.2/Si* T-NIL 347 2.2 .times. 10.sup.-3 10 .mu.m
SiO.sub.2/Si* T-NIL 388 1.3 .times. 10.sup.-3 500 .mu.m
SiO.sub.2/Cr** T-NIL 1600 1.1 .times. 10.sup.-4 Fused Silica T-NIL
27,000 1.0 .times. 10.sup.-5 UV-NIL 20,000 7.5 .times. 10.sup.-6
*Si was grounded during separation and surface potential
measurement **Cr was grounded during separation and surface
potential measurement
* * * * *