U.S. patent application number 14/136000 was filed with the patent office on 2014-09-18 for method of fabricating igzo by sputtering in oxidizing gas.
This patent application is currently assigned to Intermolecular, Inc.. The applicant listed for this patent is Intermolecular, Inc.. Invention is credited to Charlene Chen, Minh Huu Le, Sang Lee, Haifan Liang, Jeroen Van Duren.
Application Number | 20140264321 14/136000 |
Document ID | / |
Family ID | 51523482 |
Filed Date | 2014-09-18 |
United States Patent
Application |
20140264321 |
Kind Code |
A1 |
Liang; Haifan ; et
al. |
September 18, 2014 |
Method of Fabricating IGZO by Sputtering in Oxidizing Gas
Abstract
In some embodiments, oxidants such as ozone (O.sub.3) and/or
nitrous oxide (N.sub.2O) are used during the reactive sputtering of
metal-based semiconductor layers used in TFT devices. The O.sub.3
and N.sub.2O gases are stronger oxidants and result in a decrease
in the concentration of oxygen vacancies within the metal-based
semiconductor layer. The decrease in the concentration of oxygen
vacancies may result in improved stability under conditions of
negative bias illumination stress (NBIS).
Inventors: |
Liang; Haifan; (Fremont,
CA) ; Chen; Charlene; (San Jose, CA) ; Lee;
Sang; (San Jose, CA) ; Le; Minh Huu; (San
Jose, CA) ; Van Duren; Jeroen; (Palo Alto,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intermolecular, Inc. |
San Jose |
CA |
US |
|
|
Assignee: |
Intermolecular, Inc.
San Jose
CA
|
Family ID: |
51523482 |
Appl. No.: |
14/136000 |
Filed: |
December 20, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61778986 |
Mar 13, 2013 |
|
|
|
Current U.S.
Class: |
257/43 ;
204/192.1 |
Current CPC
Class: |
H01L 21/32134 20130101;
H01L 29/66969 20130101; H01L 27/1262 20130101; H01L 29/45 20130101;
H01L 21/465 20130101; H01L 21/02565 20130101; H01L 21/707 20130101;
H01L 21/02631 20130101; H01L 29/7869 20130101; H01L 21/30604
20130101; H01L 27/1225 20130101 |
Class at
Publication: |
257/43 ;
204/192.1 |
International
Class: |
H01L 27/12 20060101
H01L027/12; H01L 21/02 20060101 H01L021/02 |
Claims
1. A method comprising: providing a substrate; forming a
metal-based semiconductor layer above a surface of the substrate,
wherein the metal-based semiconductor layer is formed using a
physical vapor deposition (sputtering) process, and wherein a
sputtering atmosphere during the forming comprises at least one of
ozone or nitrous oxide.
2. The method of claim 1, wherein the metal-based semiconductor
layer comprises indium, gallium, zinc, and oxygen.
3. The method of claim 1, wherein the metal-based semiconductor
layer is operable as a semiconductor layer in a thin film
transistor device.
4. The method of claim 3, wherein the thin film transistor device
is operable as a transistor in a display device.
5. The method of claim 1, wherein a temperature setpoint of a
substrate holder during the forming is between room temperature and
500 C.
6. The method of claim 1, wherein a concentration of the at least
one of ozone or nitrous oxide is between 1 to 100 volume % of the
sputtering atmosphere.
7. The method of claim 1, wherein a pressure of the sputtering
atmosphere is between 1 and 20 millitorr.
8. The method of claim 1, wherein a sputtering target with a
composition of In.sub.xGa.sub.yZn.sub.zO.sub.4 is used for forming
the metal-based semiconductor layer, wherein x:y:z is about
1:1:1.
9. The method of claim 1, wherein a plurality of sputtering targets
with compositions of In.sub.aO.sub.b, Ga.sub.cO.sub.d, and
Zn.sub.eO.sub.f are used to co-sputter the IGZO layer during the
forming of the metal-based semiconductor layer.
10. The method of claim 1, wherein the sputtering atmosphere
further comprises one or more of argon, oxygen, or nitrogen.
11. A thin film transistor device comprising: a metal-based
semiconductor layer, wherein the metal-based semiconductor layer is
formed using a physical vapor deposition (sputtering) process, and
wherein a sputtering atmosphere during the forming comprises at
least one of ozone or nitrous oxide.
12. The thin film transistor device of claim 11, wherein the
metal-based semiconductor layer comprises indium, gallium, zinc,
and oxygen.
13. The thin film transistor device of claim 11, wherein the
metal-based semiconductor layer is operable as a semiconductor
layer in a thin film transistor device.
14. The thin film transistor device of claim 13, wherein the thin
film transistor device is operable as a transistor in a display
device.
15. The thin film transistor device of claim 11, wherein a
temperature setpoint of a substrate holder during the forming is
between room temperature and 500 C.
16. The thin film transistor device of claim 11, wherein a
concentration of the at least one of ozone or nitrous oxide is
between 1 to 100 volume % of the sputtering atmosphere during the
physical vapor deposition (sputtering) process.
17. The thin film transistor device of claim 11, wherein a pressure
of the sputtering atmosphere is between 1 and 20 millitorr during
the physical vapor deposition (sputtering) process.
18. The thin film transistor device of claim 11, wherein a
sputtering target with a composition of
In.sub.xGa.sub.yZn.sub.zO.sub.4 is used for the forming of the
metal-based semiconductor layer during the physical vapor
deposition (sputtering) process, wherein x:y:z is about 1:1:1.
19. The thin film transistor device of claim 11, wherein a
plurality of sputtering targets with compositions of
In.sub.aO.sub.b, Ga.sub.cO.sub.d, and Zn.sub.eO.sub.f are used to
co-sputter the IGZO layer during the forming of the metal-based
semiconductor layer during the physical vapor deposition
(sputtering) process.
20. The thin film transistor device of claim 11, wherein the
sputtering atmosphere further comprises one or more of argon,
oxygen, or nitrogen during the physical vapor deposition
(sputtering) process.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional
Application Ser. No. 61/778,986 filed on Mar. 13, 2013, which is
herein incorporated by reference for all purposes.
TECHNICAL FIELD
[0002] The present disclosure relates generally to methods of
employing deposition processes to the formation of metal based
semiconductor materials for use in thin film transistors (TFTs)
used in display applications.
BACKGROUND
[0003] TFTs are employed as switching and/or driving devices in
many electronic circuits. As an example, TFTs are used as control
devices for pixels in display applications such as flat panel
displays (FPD), whether based on active-matrix-liquid-crystal
displays (AMLCD), or active-matrix-organic-light-emitting-displays
(AMOLED). These FPD are used in televisions, computer monitors,
smart phones, tablets, etc. Traditionally, TFTs based on amorphous
silicon technology (a-Si) have been used due to the low cost and
ease of manufacture. However, a-Si-based TFTs have a number of
issues such as low mobility, low ON/OFF current ratios (e.g. higher
power), and limited durability. Additionally, TFTs based on a-Si
are not transparent, thereby limiting the size of the TFT within
the pixel so that the display characteristics are not compromised.
With the market moving to higher resolution, higher refresh rate,
lower power consumption, lower cost, and larger displays, there is
a need to replace a-Si.
[0004] Metal-based semiconductor materials (e.g. metal oxides,
metal oxy-nitrides, metal oxy-chalcogenides, metal chalcogenides)
are candidates for replacing a-Si in display applications. The
metal-based semiconductor materials may be amorphous, crystalline,
or polycrystalline. Some examples of metal-based semiconductor
materials include those based on In--Ga--Zn--O (IGZO) and related
materials, like In--Zn--O (IZO), Zn--Sn--O (ZTO), Hf--In--Zn--O
(HIZO), and Al--Zn--Sn--O (AZTO). Some examples of metal
oxy-nitrides include Zn--O--N (ZnON), In--O--N (InON), Sn--O--N
(SnON). Examples of crystalline metal-based semiconductor materials
include c-axis aligned crystalline (CAAC) materials like CAAC-IGZO,
or polycrystalline materials like ZnO and In--Ga--O (IGO). In
addition to the application of these materials into TFTs, these
materials are also being considered for memory (e.g. non-volatile
random access memory (RAM)), sensor applications (e.g. image
sensors), and central processing units (CPU). Some of these
materials exhibit stable amorphous phases, high mobility (e.g.
>5 cm.sup.2/Vs), low threshold voltage (close to zero, e.g. in a
range of -1.0V to -F2.0V), low carrier concentrations (e.g.
10.sup.16-10.sup.17 cm.sup.-3), high ON/OFF current ratios (e.g.
>10.sup.6), and high durability (e.g. negative bias temperature
illumination stress NBTIS with threshold voltage shift in a range
of -1.5V to -F0.5V). However, since these materials are multinary
compounds (e.g. three or more elements), their performance and
properties are sensitive to factors such as composition,
concentration gradients, deposition parameters, post-deposition
treatments, interactions with adjacent materials, and the like.
Further, since the electrical, physical, and chemical behavior of
these materials is difficult or impossible to model, much of the
development and optimization must be accomplished empirically.
Comprehensive evaluation of the entire composition range and
deposition parameter space for the formation of a TFT device
utilizing these materials requires thousands or millions of
experiments.
SUMMARY
[0005] The following summary of the disclosure is included in order
to provide a basic understanding of some aspects and features of
the invention. This summary is not an extensive overview of the
invention and as such it is not intended to particularly identify
key or critical elements of the invention or to delineate the scope
of the invention. Its sole purpose is to present some concepts of
the invention in a simplified form as a prelude to the more
detailed description that is presented below.
[0006] In some embodiments, oxidants such as ozone (O.sub.3) and/or
nitrous oxide (N.sub.2O) are used during the reactive sputtering of
metal oxide semiconductor layers used in TFT devices. The O.sub.3
and N.sub.2O gases are stronger oxidants and result in a decrease
in the concentration of oxygen vacancies within the metal oxide
semiconductor layer. The decrease in the concentration of oxygen
vacancies may result in improved stability under conditions of
negative bias illumination stress (NBIS) and improved manufacturing
yield due improved process control.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] To facilitate understanding, identical reference numerals
have been used, where possible, to designate identical elements
that are common to the figures. The drawings are not to scale and
the relative dimensions of various elements in the drawings are
depicted schematically and not necessarily to scale.
[0008] The techniques of the present invention can readily be
understood by considering the following detailed description in
conjunction with the accompanying drawings, in which:
[0009] FIG. 1 is a simplified cross-sectional view of a TFT
according to some embodiments.
[0010] FIG. 2 is a flow chart illustrating the steps of a method
according to some embodiments.
[0011] FIG. 3 is a simplified cross-sectional view of a TFT
according to some embodiments.
[0012] FIG. 4 is a flow chart illustrating the steps of a method
according to some embodiments.
[0013] FIG. 5 is a schematic of a system used to deposit layers in
accordance with some embodiments.
DETAILED DESCRIPTION
[0014] A detailed description of one or more embodiments is
provided below along with accompanying figures. The detailed
description is provided in connection with such embodiments, but is
not limited to any particular example. The scope is limited only by
the claims and numerous alternatives, modifications, and
equivalents are encompassed. Numerous specific details are set
forth in the following description in order to provide a thorough
understanding. These details are provided for the purpose of
example and the described techniques may be practiced according to
the claims without some or all of these specific details. For the
purpose of clarity, technical material that is known in the
technical fields related to the embodiments has not been described
in detail to avoid unnecessarily obscuring the description.
[0015] It must be noted that as used herein and in the claims, the
singular forms "a," "an" and "the" include plural referents unless
the context clearly dictates otherwise. Thus, for example,
reference to "a layer" includes two or more layers, and so
forth.
[0016] Where a range of values is provided, it is understood that
each intervening value, to the tenth of the unit of the lower limit
unless the context clearly dictates otherwise, between the upper
and lower limit of that range, and any other stated or intervening
value in that stated range, is encompassed within the invention.
The upper and lower limits of these smaller ranges may
independently be included in the smaller ranges, and are also
encompassed within the invention, subject to any specifically
excluded limit in the stated range. Where the stated range includes
one or both of the limits, ranges excluding either or both of those
included limits are also included in the invention. Where the
modifier "about" or "approximately" is used, the stated quantity
can vary by up to 10%. Where the modifier "substantially equal to"
or "substantially the same" is used, the two quantities may vary
from each other by no more than 5%.
[0017] The term "horizontal" as used herein will be understood to
be defined as a plane parallel to the plane or surface of the
substrate, regardless of the orientation of the substrate. The term
"vertical" will refer to a direction perpendicular to the
horizontal as previously defined. Terms such as "above", "below",
"bottom", "top", "side" (e.g. sidewall), "higher", "lower",
"upper", "over", and "under", are defined with respect to the
horizontal plane. The term "on" means there is direct contact
between the elements. The term "above" will allow for intervening
elements.
[0018] As used herein, a material (e.g. a dielectric material or an
electrode material) will be considered to be "crystalline" if it
exhibits greater than or equal to 30% crystallinity as measured by
a technique such as x-ray diffraction (XRD).
[0019] Those skilled in the art will appreciate that each of the
layers discussed herein and used in the TFT may be formed using any
common formation technique such as physical vapor deposition (PVD),
atomic layer deposition (ALD), plasma enhanced atomic layer
deposition (PE-ALD), atomic vapor deposition (AVD), ultraviolet
assisted atomic layer deposition (UV-ALD), chemical vapor
deposition (CVD), plasma enhanced chemical vapor deposition (PECVD)
or evaporation. Generally, because of the morphology and size of
the display devices, PVD or PECVD are preferred methods of
formation. However, any of these techniques are suitable for
forming each of the various layers discussed herein. Those skilled
in the art will appreciate that the teachings described herein are
not limited by the technology used for the deposition process.
[0020] In FIGS. 1, and 3, a TFT stack is illustrated using a simple
inverted-staggered, bottom-gate, with etch-stopper island, device
structure. Those skilled in the art will appreciate that the
description and teachings herein can be readily applied to any
simple or complex TFT structure, including inverted-staggered,
bottom-gate, back-channel-etch device structures, co-planar device
structures, inverted-staggered, bottom-gate, etch-stopper contact
(via) hole device structures, self-aligned, inverted-staggered,
bottom-gate, etch-stopper island device structures, and various
device structures based on top-gate, bottom-gate, staggered,
inverted-staggered, co-planar, back-channel-etch, single-gate, or
double-gate features. The drawings are for illustrative purposes
only and do not limit the application of the present
disclosure.
[0021] As used herein, the notation "(IIIA)" will be understood to
represent the sum of the concentrations of all Group-IIIA elements.
This notation will be used herein in calculations of the
composition ratios of various elements. This notation will be
understood to extend to each of the other Groups of the periodic
table respectively (e.g. "(IA)", "(IIA)", "(IVA)", "(VIA)", "(IB)",
"(IIB)", etc.).
[0022] As used herein, the notation "In--Ga--Zn--O" will be
understood to include a material containing these elements in any
ratio. This notation will be shortened to "IGZO" for brevity. Where
a specific composition is discussed, the atomic concentrations (or
ranges) will be provided. The notation is extendable to other
materials and other elemental combinations.
[0023] As used herein, the notation
"In.sub.xGa.sub.yZn.sub.zO.sub.w" will be understood to include a
material containing these elements in a specific ratio given by x,
y, z, and w (e.g. In.sub.33Ga.sub.33Zn.sub.33 contains 33 atomic %
In, 33 atomic % Ga, and 33 atomic % Zn). The notation is extendable
to other materials and other elemental combinations.
[0024] As used herein, the notation
"(In,Ga).sub.x(Zn,Cd).sub.y(O,Se,S,Te).sub.z" will be understood to
include a material containing a total amount of Group-IIA elements
(i.e. In plus Ga, etc.) in a ratio given by "x", a total amount of
Group-IIB elements (i.e. Zn plus Cd, etc.), etc. in a ratio given
by "y", and a total amount of Group-VIA elements (i.e. O plus Se
plus S plus Te, etc.) in a ratio given by "z". The notation is
extendable to other materials and other elemental combinations.
[0025] As used herein, the terms "film" and "layer" will be
understood to represent a portion of a stack. They will be
understood to cover both a single layer as well as a multilayered
structure (i.e. a nanolaminate). As used herein, these terms will
be used synonymously and will be considered equivalent.
[0026] As used herein, "substrate" will be understood to generally
be one of float glass, low-iron glass, borosilicate glass, display
glass, alkaline earth boro-aluminosilicate glass, fusion drawn
glass, flexible glass, specialty glass for high temperature
processing, polyimide, plastics, polyethylene terephthalate (PET),
etc. for either applications requiring transparent or
non-transparent substrate functionality. For substrates with no
need for transparency, substrates like aluminum foil, stainless
steel, carbon steel, paper, cladded foils, etc. can be
utilized.
[0027] The typical materials in a TFT stack consist of a substrate,
a diffusion barrier layer, a gate electrode, source electrode,
drain electrode, gate insulator, and a semiconducting channel
layer, in addition to an optional etch stopper and/or passivation
layer. As used herein, "metal-based semiconductor layer", and
"metal-based semiconductor material", etc. will be understood to be
equivalent and be understood to refer to a layer and/or material
related to the channel layer. This disclosure will describe methods
and apparatus for forming and evaluating at least portions of TFT
devices based on metal-based semiconductor materials. The
metal-based semiconductor materials may include at least one of
metal oxides, metal oxy-nitrides, metal oxy-chalcogenides, or metal
chalcogenides. In--Ga--Zn--O (IGZO), will be used as an example of
a metal-based semiconductor material for purposes of illustration,
but this is not intended to be limiting. Those skilled in the art
will understand that the present disclosure can be applied to any
suitable metal-based semiconductor material applicable to TFT
devices.
[0028] FIG. 1 is a simplified cross-sectional view of a TFT
according to some embodiments. Bottom gate electrode, 104, is
formed above substrate, 102. As discussed previously, the substrate
may be any commonly used substrate for display devices such as one
of float glass, low-iron glass, borosilicate glass, display glass,
alkaline earth boro-aluminosilicate glass, fusion drawn glass,
flexible glass, specialty glass for high temperature processing,
polyimide, plastics, PET, etc. for either applications requiring
transparent or non-transparent substrate functionality. For
substrates with no need for transparency, substrates like aluminum
foil, stainless steel, carbon steel, paper, cladded foils, etc. can
be utilized. The substrate optionally is covered by a diffusion
barrier, (e.g. silicon oxide, silicon nitride, or silicon
oxy-nitride). The bottom gate electrode, 104, is typically formed
by a deposition process followed by a patterning process.
Optionally, an anneal step is implemented prior to patterning, post
patterning, or both. A typical deposition method involves sputter
deposition. Patterning is typically performed by photolithography.
The photolithography most commonly relies on wet etching, yet dry
etching (e.g. reactive ion etching) can be used as well. Wet etch
chemistries are most commonly aqueous, and include a mixture of
inorganic acids, optionally organic acids, and optionally an
oxidizer like hydrogen peroxide, or nitric acid, and optionally
other chemicals, either as stabilizers, to control critical
dimension loss, taper angle, or etch selectivity. The gate
electrode is most commonly a stack of two or more layers. Examples
of suitable materials for the bottom gate electrode include a stack
of Cu and a Cu-alloy, a stack of Cu and Mo, a stack of Cu and Ti, a
stack of Cu and Mo--Ti alloy, a stack of Cu and Mo--Ta alloy, Cu,
Mo, Al, a stack of Al and Mo, a stack of Al and Ti, or a stack of
Al and Mo--Ti alloy. It should be noted that Al can contain a small
concentration of Neodymium (Nd). It should be understood that the
Cu in the Cu stacks, and Al in the Al stacks are thicker than the
adjacent layers (e.g. Cu-alloy, or Mo--Ti alloy). Furthermore, the
stacks can be a bi-layer of Cu and Cu-alloy, or a tri-layer of
Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo. Typical Cu-alloys include
Cu--Mg--Al, and Cu--Mn, wherein the Cu-alloys can also contain
small concentrations of phosphides, Mg, or Ca. For some transparent
TFTs, the gate electrode consists of a transparent conductive
oxide, (e.g. In--Sn--O (ITO), In--Zn--O (IZO)), and related
materials. The performance of the gate electrode can be sensitive
to composition and process parameters. The same holds for the
diffusion barrier layer underneath the gate electrode.
[0029] Gate dielectric, 106, is formed above bottom gate electrode,
104. Examples of suitable materials for the gate dielectric include
silicon oxide and silicon nitride, a stack of silicon nitride and
silicon oxide, a mixture, multi-layer, or combination thereof of a
high bandgap (e.g. silicon oxide, or aluminum oxide) and high-k
dielectric material (e.g. hafnium oxide, zirconium oxide, titanium
oxide), a high bandgap material (e.g. silicon oxide, or aluminum
oxide) or high-k dielectric material (e.g. hafnium oxide, zirconium
oxide, titanium oxide). The gate dielectric, 106, is typically
formed by a deposition process followed by a patterning process.
Optionally, an anneal step is implemented prior to patterning, post
patterning, or both. The gate dielectric, 106, may be formed using
deposition techniques such as PVD, ALD, or PECVD, or a combination
thereof. The performance of the gate dielectric can be sensitive to
composition and process parameters. The gate dielectric, 106, may
be patterned using either wet techniques such as chemical etching,
or dry techniques such as reactive ion etching (RIE). In both of
these techniques, parameters such as the uniformity, etch rate,
selectivity, critical dimension loss, taper angle, cost,
throughput, etc. are sensitive to the process parameters of the
etch process.
[0030] Metal-based semiconductor layer, 108, is formed above gate
dielectric, 106. The metal-based semiconductor layer, 108, is
typically formed by a deposition process followed by a patterning
process. Optionally, an anneal step is implemented prior to
patterning, post patterning, or both. The anneal step may occur
just below atmospheric pressure, at atmospheric pressure, or
slightly above atmospheric pressure. Typical anneal ambient
atmospheres contain at least one of oxygen, ozone, water, hydrogen,
nitrogen, argon, or a combination thereof. In addition, the
metal-based semiconductor layer may be treated prior to etch
stopper or source/drain deposition with a plasma containing O.sub.2
or N.sub.2O. The metal-based semiconductor layer, 108, may be
formed using deposition techniques such as PVD, MOCVD, or wet
depositions, (e.g. based on sol-gels). The performance of the
metal-based semiconductor layer can be sensitive to composition and
process parameters. Examples of suitable materials for the
metal-based semiconductor layer include indium gallium zinc oxide
(In--Ga--Zn--O or IGZO), amorphous silicon, low-temperature
polysilicon, In--Zn--O (IZO), Zn--Sn--O (ZTO), Hf--In--Zn--O
(HIZO), and Al--Zn--Sn--O (AZTO), oxy-nitrides such as Zn--O--N
(ZnON), In--O--N (InON), Sn--O--N (SnON), c-axis aligned
crystalline (CAAC) materials such as CAAC-IGZO, or polycrystalline
materials such as ZnO or In--Ga--O (IGO). Indium in these materials
might be partially or completely replaced by Sn, or Sb. Gallium in
these materials might be partially or completely replaced by one or
more of Al, Hf, In, Nb, Si, Sn, Ta, Ti, Zn, or Zr. Oxygen in these
materials might be partially or completely replaced by one or more
of C, N, P, S, Se, Si, or Te. Other potential candidates as active
channel (semiconductor) materials are refractory metal
chalcogenides, (e.g. molybdenum sulfides). It should be noted that
it is possible to deposit a bi-, or tri-layer, where each layer has
a composition optimized for its functionality, the latter being
contact layer with the gate insulator, bulk active channel layer,
and contact layer with the source and drain electrodes and etch
stopper or passivation layers. Furthermore, the active
(semiconducting) channel layer might have a continuous change in
composition (e.g. a gradient) through the thickness of the film.
Common extrinsic (n-type) dopants for ZnO-based semiconductors are
Al, B, Cr, Ga, H, In and Li. Furthermore, the metal cations in the
metal-based semiconductor material (e.g. IGZO) may be partially or
completely replaced by Ag, As, Au, Bi, Cd, Cu, Zn, Ga, Ge, Hg, In,
Pb, Sb, Sn, and Tl. Other dopants of interest include halogens like
CI and F. The metal-based semiconductor layer, 108, may be
patterned using either wet techniques such as chemical etching, or
dry techniques such as RIE. In both of these techniques, parameters
such as the uniformity, etch rate, selectivity, critical dimension
loss, taper angle, cost, throughput, etc. are sensitive to the
process parameters of the etch process. This disclosure will use
IGZO as an example, but this is not meant to be limiting. The
techniques described herein can be applied to any material suitable
for display applications.
[0031] Etch stopper, 110, is formed above metal-based semiconductor
layer, 108. The etch stopper, 110, is typically formed by a
deposition process followed by a patterning process. Optionally, an
anneal step is implemented prior to patterning, post patterning, or
both. The etch stopper, 110, may be formed using deposition
techniques such as PVD, ALD, PECVD, or by wet coating techniques.
The performance of the etch stopper can be sensitive to composition
and process parameters. Examples of suitable materials for the etch
stopper include silicon oxide, silicon nitride, a stack of silicon
nitride and silicon oxide, a mixture, multi-layer, or combination
thereof of a high bandgap material (e.g. silicon oxide, or aluminum
oxide) and high-k dielectric material (e.g. hafnium oxide,
zirconium oxide, titanium oxide), a high bandgap (e.g. silicon
oxide, or aluminum oxide) or high-k dielectric material (e.g.
hafnium oxide, zirconium oxide, titanium oxide). In addition to
these inorganic materials, various organic materials may be used as
etch stopper materials as well. Examples of organic etch stopper
materials include photoresist, organic polymers, UV-curable
polymers, and heat-curable polymers. The etch stopper, 110, may be
patterned using either wet techniques such as chemical etching, or
dry techniques such as RIE. In both of these techniques, parameters
such as the uniformity, etch rate, selectivity, critical dimension
loss, taper angle, cost, throughput, etc. are sensitive to the
process parameters of the etch process.
[0032] Source and drain electrodes, 112 and 114, are formed above
etch stopper, 110 and exposed regions of the metal-based
semiconductor layer, 108. The source and drain electrodes, 112 and
114, are typically formed by a deposition process followed by a
patterning process. Optionally, an anneal step is implemented prior
to patterning, post patterning, or both. The source and drain
electrodes, 112 and 114, may be formed using deposition techniques
such as PVD, wet deposition (e.g. plating), or MOCVD (for TCOs).
Typically, the deposition steps involve sputter deposition.
Patterning is commonly performed by photolithography. The
photolithography most commonly relies on wet etching, yet dry
etching (e.g. reactive ion etching) can be used as well. Wet etch
chemistries are most commonly aqueous, and include a mixture of
inorganic acids, optionally organic acids, and optionally an
oxidizer like hydrogen peroxide, or nitric acid, and optionally
other chemicals, either as stabilizers, to control critical
dimension loss, taper angle, or etch selectivity. The performance
of the source and drain electrodes can be sensitive to composition
and process parameters. The source/drain electrode is most commonly
a stack of two or more layers. Examples of suitable materials for
the bottom source/drain electrode include a stack of Cu and a
Cu-alloy, a stack of Cu and Mo, a stack of Cu and Ti, a stack of Cu
and Mo--Ti alloy, a stack of Cu and Mo--Ta alloy, Cu, Mo, Al, a
stack of Al and Mo, a stack of Al and Ti, or a stack of Al and
Mo--Ti alloy. It should be noted that Al can contain a small
concentration of Neodymium (Nd). It should be understood that the
Cu in the Cu stacks, and Al in the Al stacks are thicker than the
adjacent layers (e.g. Cu-alloy, or Mo--Ti alloy). Furthermore, the
stacks can be a bi-layer of Cu and Cu-alloy, or a tri-layer of
Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo. Typical Cu-alloys include
Cu--Mg--Al, and Cu--Mn, wherein the Cu-alloys can also contain
small concentrations of phosphides, Mg, or Ca. For some transparent
TFTs, the gate electrode consists of a transparent conductive
oxide, (e.g. In--Sn--O (ITO), In--Zn--O (IZO)), and related
materials. The source and drain electrodes, 112 and 114, may be
patterned using either wet techniques such as chemical etching, or
dry techniques such as RIE. In both of these techniques, parameters
such as the uniformity, etch rate, selectivity, critical dimension
loss, taper angle, cost, throughput, etc. are sensitive to the
process parameters of the etch process.
[0033] Passivation layer, 116, is formed above source and drain
electrodes, 112 and 114. The passivation layer, 116, is typically
formed by a deposition process followed by a patterning process.
Optionally, an anneal step is implemented prior to patterning, post
patterning, or both. The passivation layer, 116, may be formed
using deposition techniques such as PVD, ALD, or PECVD, or by wet
coating techniques. The performance of the passivation layer can be
sensitive to composition and process parameters. Examples of
suitable materials for the passivation layer include silicon oxide
and silicon nitride, a stack of silicon nitride and silicon oxide,
a mixture, multi-layer, or combination thereof of a high bandgap
(e.g. silicon oxide, or aluminum oxide) and high-k dielectric
material (e.g. hafnium oxide, zirconium oxide, titanium oxide), a
high bandgap material (e.g. silicon oxide, or aluminum oxide) or
high-k dielectric material (e.g. hafnium oxide, zirconium oxide,
titanium oxide). The passivation layer, 116, may be patterned using
either wet techniques such as chemical etching, or dry techniques
such as RIE. In both of these techniques, parameters such as the
uniformity, etch rate, selectivity, critical dimension loss, taper
angle, cost, throughput, etc. are sensitive to the process
parameters of the etch process.
[0034] In some embodiments, between one or more of the deposition
and patterning steps discussed previously (e.g. the formation of
the gate electrode layer, the gate dielectric layer, the
metal-based semiconductor layer, the etch stopper layer, the
source/drain electrode layers, or the passivation layer), the
surface of the deposited film may be subjected to a treatment
process before the patterning step. Examples of treatment processes
include degas steps to remove adsorbed moisture due to exposure to
ambient, anneal treatments, surface cleaning treatments (either wet
or dry), and plasma treatments (e.g. exposure to plasma generated
species of Ar, H.sub.2, N.sub.2, N.sub.2O, O.sub.2, O.sub.3,
etc.).
[0035] FIG. 2 is a flow chart illustrating the steps of a method
according to some embodiments. In step 202, a gate electrode layer
is deposited above the substrate. Typically, the gate electrode is
a material with high conductivity such as a metal, metal alloy, or
conductive metal compound (e.g. titanium nitride, tantalum nitride,
and the like). Examples of suitable materials for the gate
electrode include a stack of Cu and a Cu-alloy, a stack of Cu and
Mo, a stack of Cu and Ti, a stack of Cu and Mo--Ti alloy, a stack
of Cu and Mo--Ta alloy, Cu, Mo, Al, a stack of Al and Mo, a stack
of Al and Ti, or a stack of Al and Mo--Ti alloy. It should be noted
that Al can contain a small concentration of Neodymium (Nd). It
should be understood that the Cu in the Cu stacks, and Al in the Al
stacks are thicker than the adjacent layers (e.g. Cu-alloy, or
Mo--Ti alloy). Furthermore, the stacks can be a bi-layer of Cu and
Cu-alloy, or a tri-layer of Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo.
Typical Cu-alloys include Cu--Mg--Al, and Cu--Mn, wherein the
Cu-alloys can also contain small concentrations of phosphides, Mg,
or Ca. For some transparent TFTs, the gate electrode consists of a
transparent conductive oxide, (e.g. In--Sn--O (ITO), In--Zn--O
(IZO)), and related materials. The performance of the gate
electrode can be sensitive to composition and process parameters.
The same holds for the diffusion barrier layer underneath the gate
electrode. The gate electrode layer can be deposited using well
known deposition techniques such as PVD, CVD, PECVD, PLD,
evaporation, etc.
[0036] In step 204, the gate electrode layer is patterned. The gate
electrode layer is patterned using known photolithography
techniques followed by etching the gate electrode layer using wet
and/or dry etching processes. In some embodiments, the gate
electrode layer is etched using a combination of wet and dry
etching processes. Examples of wet etching processes include the
application of acidic, basic, or organic-solvent based solutions
(depending on the material to be etched) to the gate electrode
layer. Examples of dry etching processes include reactive ion
etching (RIE), plasma etching, ion milling, and the like.
[0037] In step 206, a gate dielectric layer is deposited above the
gate electrode layer. Typically, the gate dielectric is an
insulating material such as a silicon oxide, silicon nitride, or a
metal oxide such as aluminum oxide, and the like. Examples of
suitable materials for the gate dielectric include silicon oxide
and silicon nitride, a stack of silicon nitride and silicon oxide,
a mixture, multi-layer, or combination thereof of a high bandgap
(e.g. silicon oxide, or aluminum oxide) and high-k dielectric
material (e.g. hafnium oxide, zirconium oxide, titanium oxide), a
high bandgap material (e.g. silicon oxide, or aluminum oxide) or
high-k dielectric material (e.g. hafnium oxide, zirconium oxide,
titanium oxide). In some embodiments, the deposition process is a
vacuum-based process such as PVD, ALD, PE-ALD, AVD, UV-ALD, CVD,
PECVD, PLD, or evaporation. In some embodiments, the deposition
process is a solution-based process such as printing or spraying of
inks, screen printing, inkjet printing, slot die coating, gravure
printing, wet chemical depositions, or from sol-gel methods, such
as the coating, drying, and firing of polysilazanes. Furthermore,
the substrates may be processed in many configurations such as
single substrate processing, multiple substrate batch processing,
in-line continuous processing, in-line "stop and soak" processing,
or roll-to-roll processing.
[0038] In step 208, the gate dielectric layer is patterned.
Optionally, an anneal step is implemented prior to patterning, post
patterning, or both. The gate dielectric layer is patterned using
known photolithography techniques followed by etching the gate
dielectric layer using wet and/or dry etching processes. In some
embodiments, the gate dielectric layer is etched using a
combination of wet and dry etching processes. Examples of wet
etching processes include the application of acidic, basic, or
organic-solvent based solutions (depending on the material to be
etched) to the gate dielectric layer. Examples of dry etching
processes include reactive ion etching (RIE), plasma etching, ion
milling, and the like.
[0039] In step 210, a metal-based semiconductor layer is deposited
above the gate dielectric layer. Examples of suitable materials for
the semiconductor layer include indium gallium zinc oxide
(In--Ga--Zn--O or IGZO), amorphous silicon, low-temperature
polysilicon, In--Zn--O (IZO), Zn--Sn--O (ZTO), Hf--In--Zn--O
(HIZO), and Al--Zn--Sn--O (AZTO), oxy-nitrides such as Zn--O--N
(ZnON), In--O--N (InON), Sn--O--N (SnON), c-axis aligned
crystalline (CAAC) materials such as CAAC-IGZO, or polycrystalline
materials such as ZnO or In--Ga--O (IGO). Indium in these materials
might be partially or completely replaced by Sn, or Sb. Gallium in
these materials might be partially or completely replaced by one or
more of Al, Hf, In, Nb, Si, Sn, Ta, Ti, Zn, or Zr. Oxygen in these
materials might be partially or completely replaced by one or more
of C, N, P, S, Se, Si, or Te. Other potential candidates as active
channel (semiconductor) materials are refractory metal
chalcogenides, (e.g. molybdenum sulfides). It should be noted that
it is possible to deposit a bi-, or tri-layer, where each layer has
a composition optimized for its functionality, the latter being
contact layer with the gate insulator, bulk active channel layer,
and contact layer with the source and drain electrodes and etch
stopper or passivation layers. Furthermore, the active
(semiconducting) channel layer might have a continuous change in
composition (e.g. a gradient) through the thickness of the film.
Common extrinsic (n-type) dopants for ZnO-based semiconductors are
Al, B, Cr, Ga, H, In and Li. Furthermore, the metal cations in IGZO
may be partially or completely replaced by Ag, As, Au, Bi, Cd, Cu,
Zn, Ga, Ge, Hg, In, Pb, Sb, Sn, and Tl. Other dopants of interest
include halogens like CI and F. In some embodiments, the deposition
process is a vacuum-based process such as PVD, ALD, PE-ALD, AVD,
UV-ALD, CVD, PECVD, or evaporation. In some embodiments, the
deposition process is a solution-based process such as printing or
spraying of inks, screen printing, inkjet printing, slot die
coating, gravure printing, wet chemical depositions, or from
sol-gel methods, such as the coating, drying, and firing of
polysilazanes. Furthermore, the substrates may be processed in many
configurations such as single substrate processing, multiple
substrate batch processing, in-line continuous processing, in-line
"stop and soak" processing, or roll-to-roll processing.
[0040] In step 212, the metal-based semiconductor layer is
patterned. Optionally, an anneal step is implemented prior to
patterning, post patterning, or both. The anneal step may occur
just below atmospheric pressure, at atmospheric pressure, or
slightly above atmospheric pressure. Typical anneal ambient
atmospheres contain at least one of oxygen, ozone, water, hydrogen,
nitrogen, argon, or a combination thereof. In addition, the
semiconductor layer may be treated prior to etch stopper or
source/drain deposition with a plasma containing O.sub.2 or
N.sub.2O. The metal-based semiconductor layer is patterned using
known photolithography techniques followed by etching the
metal-based semiconductor layer using wet and/or dry etching
processes. In some embodiments, the metal-based semiconductor layer
is etched using a combination of wet and dry etching processes.
Examples of wet etching processes include the application of
acidic, basic, or organic-solvent based solutions (depending on the
material to be etched) to the metal-based semiconductor layer.
Examples of dry etching processes include reactive ion etching
(RIE), plasma etching, ion milling, and the like.
[0041] In step 214, an etch stop layer is deposited above the
metal-based semiconductor layer. Examples of suitable materials for
the etch stopper include silicon oxide, silicon nitride, a stack of
silicon nitride and silicon oxide, a mixture, multi-layer, or
combination thereof of a high bandgap material (e.g. silicon oxide,
or aluminum oxide) and high-k dielectric material (e.g. hafnium
oxide, zirconium oxide, titanium oxide), a high bandgap (e.g.
silicon oxide, or aluminum oxide) or high-k dielectric material
(e.g. hafnium oxide, zirconium oxide, titanium oxide). In addition
to these inorganic materials, various organic materials may be used
as etch stopper materials as well. Examples of organic etch stopper
materials include photoresist, organic polymers, UV-curable
polymers, and heat-curable polymers. In some embodiments, the
deposition process is a vacuum-based process such as PVD, ALD,
PE-ALD, AVD, UV-ALD, CVD, PECVD, PLD, or evaporation. In some
embodiments, the deposition process is a solution-based process
such as printing or spraying of inks, screen printing, inkjet
printing, slot die coating, gravure printing, wet chemical
depositions, or from sol-gel methods, such as the coating, drying,
and firing of polysilazanes. Furthermore, the substrates may be
processed in many configurations such as single substrate
processing, multiple substrate batch processing, in-line continuous
processing, in-line "stop and soak" processing, or roll-to-roll
processing.
[0042] In step 216, the etch stop layer is patterned. Optionally,
an anneal step is implemented prior to patterning, post patterning,
or both. The etch stop layer is patterned using known
photolithography techniques followed by etching the etch stop layer
using wet and/or dry etching processes. In some embodiments, the
etch stop layer is etched using a combination of wet and dry
etching processes. Examples of wet etching processes include the
application of acidic, basic, or organic-solvent based solutions
(depending on the material to be etched) to the etch stop layer.
Examples of dry etching processes include reactive ion etching
(RIE), plasma etching, ion milling, and the like. When dry
processes are used, the upper surface of the underlying metal-based
semiconductor layer may become damaged, negatively affecting the
transport properties. This may require an additional step to remove
a portion of the upper surface of the underlying metal-based
semiconductor layer to recover the required transport
properties.
[0043] In step 218, a source/drain electrode layer is deposited
above the etch stop layer. The source and drain electrodes are
typically deposited as a single layer and then defined during the
patterning step. Typically, the source/drain electrode is a
material with high conductivity such as a metal, metal alloy, or
conductive metal compound (e.g. titanium nitride, tantalum nitride,
and the like). Examples of suitable materials for the bottom gate
electrode include a stack of Cu and a Cu-alloy, a stack of Cu and
Mo, a stack of Cu and Ti, a stack of Cu and Mo--Ti alloy, a stack
of Cu and Mo--Ta alloy, Cu, Mo, Al, a stack of Al and Mo, a stack
of Al and Ti, or a stack of Al and Mo--Ti alloy. It should be noted
that Al can contain a small concentration of Neodymium (Nd). It
should be understood that the Cu in the Cu stacks, and Al in the Al
stacks are thicker than the adjacent layers (e.g. Cu-alloy, or
Mo--Ti alloy). Furthermore, the stacks can be a bi-layer of Cu and
Cu-alloy, or a tri-layer of Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo.
Typical Cu-alloys include Cu--Mg--Al, and Cu--Mn, wherein the
Cu-alloys can also contain small concentrations of phosphides, Mg,
or Ca. For some transparent TFTs, the gate electrode consists of a
transparent conductive oxide, (e.g. In--Sn--O (ITO), In--Zn--O
(IZO)), and related materials. The source/drain electrode layer can
be deposited using well known deposition techniques such as PVD,
CVD, PECVD, PLD, evaporation, etc.
[0044] In step 220, the source/drain electrode layer is patterned
into individual source and drain electrodes. Optionally, an anneal
step is implemented prior to patterning, post patterning, or both.
The source/drain electrode layer is patterned using known
photolithography techniques followed by etching the source/drain
electrode layer using wet and/or dry etching processes. In some
embodiments, the source/drain electrode layer is etched using a
combination of wet and dry etching processes. Examples of wet
etching processes include the application of acidic, basic, or
organic-solvent based solutions (depending on the material to be
etched) to the source/drain electrode layer. Wet etch chemistries
are most commonly aqueous, and include a mixture of inorganic
acids, optionally organic acids, and optionally an oxidizer like
hydrogen peroxide, or nitric acid, and optionally other chemicals,
either as stabilizers, to control critical dimension loss, taper
angle, or etch selectivity. Examples of dry etching processes
include reactive ion etching (RIE), plasma etching, ion milling,
and the like. The performance of the source and drain electrodes
can be sensitive to composition and process parameters.
[0045] In step 222, a passivation layer is deposited above the
source/drain layer to form a TFT stack. Typically, the passivation
layer is an insulating material such as a silicon oxide, silicon
nitride, or a metal oxide such as aluminum oxide, and the like.
Examples of suitable materials for the passivation layer include
silicon oxide and silicon nitride, a stack of silicon nitride and
silicon oxide, a mixture, multi-layer, or combination thereof of a
high bandgap (e.g. silicon oxide, or aluminum oxide) and high-k
dielectric material (e.g. hafnium oxide, zirconium oxide, titanium
oxide), a high bandgap material (e.g. silicon oxide, or aluminum
oxide) or high-k dielectric material (e.g. hafnium oxide, zirconium
oxide, titanium oxide). The passivation layer can be deposited
using well known deposition techniques such as PVD, CVD, PECVD,
PLD, evaporation, etc.
[0046] In step 224, the TFT stack is annealed. The annealing serves
to passivate defects that may have been formed during any of the
deposition and/or etching steps and also serves to reduce the
number of oxygen vacancies that may have been formed in the
metal-based semiconductor material. The anneal step may occur just
below atmospheric pressure, at atmospheric pressure, or slightly
above atmospheric pressure. Typical anneal ambient atmospheres
contain at least one of oxygen, ozone, water, hydrogen, nitrogen,
argon, or a combination thereof. The annealing is typically
performed in a temperature range between 150 C. and 400 C. for
times between 10 minutes and 60 minutes.
[0047] In some embodiments, between one or more of the deposition
and patterning steps discussed previously (e.g. the formation of
the gate electrode layer, the gate dielectric layer, the
metal-based semiconductor layer, the etch stopper layer, the
source/drain electrode layers, or the passivation layer), the
surface of the deposited film may be subjected to a treatment
process before the patterning step. Examples of treatment processes
include degas steps to remove adsorbed moisture due to exposure to
ambient, anneal treatments, surface cleaning treatments (either wet
or dry), and plasma treatments (e.g. exposure to plasma generated
species of Ar, H.sub.2, N.sub.2, N.sub.2O, O.sub.2, O.sub.3,
etc.).
[0048] The performance of the metal-based semiconductor layer will
be sensitive to parameters such as composition, crystal structure,
oxygen vacancies, surface defects, interface state density, and the
like. Many of these parameters will be influenced by the processing
of the material and the process conditions to which the material is
exposed. As an example, in the method as outlined in FIG. 2, the
metal-based semiconductor material is exposed to air (after
deposition), photoresist and photoresist developer (during
patterning), etch chemistries (either wet, dry, or both),
processing conditions related to the deposition of the etch stop
layer (e.g. elevated temperatures, plasma bombardment, etc.),
processing conditions related to the patterning of the etch stop
layer (either wet, dry, or both), and processing conditions related
to the deposition of the source/drain layer (e.g. elevated
temperatures, plasma bombardment, etc.). Those skilled in the art
will understand that the active channel of the metal-based
semiconductor layer is protected by the etch stop layer, but that
regions of the metal-based semiconductor layer outside the active
channel will be exposed to the processing conditions related to the
deposition of the source/drain layer.
[0049] FIG. 3 is a simplified cross-sectional view of a TFT
according to some embodiments. Gate electrode, 304, is formed above
substrate, 302. As discussed previously, the substrate may be any
commonly used substrate for display devices such as one of float
glass, low-iron glass, borosilicate glass, display glass, alkaline
earth boro-aluminosilicate glass, fusion drawn glass, flexible
glass, specialty glass for high temperature processing, polyimide,
plastics, PET, etc. for either applications requiring transparent
or non-transparent substrate functionality. For substrates with no
need for transparency, substrates like aluminum foil, stainless
steel, carbon steel, paper, cladded foils, etc. can be utilized.
The substrate optionally is covered by a diffusion barrier, (e.g.
silicon oxide, silicon nitride, or silicon oxy-nitride). The bottom
gate electrode, 304, is typically formed by a deposition process
followed by a patterning process. Optionally, an anneal step is
implemented prior to patterning, post patterning, or both. A
typical deposition method involves sputter deposition. Patterning
is typically performed by photolithography. The photolithography
most commonly relies on wet etching, yet dry etching (e.g. reactive
ion etching) can be used as well. Wet etch chemistries are most
commonly aqueous, and include a mixture of inorganic acids,
optionally organic acids, and optionally an oxidizer like hydrogen
peroxide, or nitric acid, and optionally other chemicals, either as
stabilizers, to control critical dimension loss, taper angle, or
etch selectivity. The gate electrode is most commonly a stack of
two or more layers. Examples of suitable materials for the bottom
gate electrode include a stack of Cu and a Cu-alloy, a stack of Cu
and Mo, a stack of Cu and Ti, a stack of Cu and Mo--Ti alloy, a
stack of Cu and Mo--Ta alloy, Cu, Mo, Al, a stack of Al and Mo, a
stack of Al and Ti, or a stack of Al and Mo--Ti alloy. It should be
noted that Al can contain a small concentration of Neodymium (Nd).
It should be understood that the Cu in the Cu stacks, and Al in the
Al stacks are thicker than the adjacent layers (e.g. Cu-alloy, or
Mo--Ti alloy). Furthermore, the stacks can be a bi-layer of Cu and
Cu-alloy, or a tri-layer of Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo.
Typical Cu-alloys include Cu--Mg--Al, and Cu--Mn, wherein the
Cu-alloys can also contain small concentrations of phosphides, Mg,
or Ca. For some transparent TFTs, the gate electrode consists of a
transparent conductive oxide, (e.g. In--Sn--O (ITO), In--Zn--O
(IZO)), and related materials. The performance of the gate
electrode can be sensitive to composition and process parameters.
The same holds for the diffusion barrier layer underneath the gate
electrode.
[0050] Gate dielectric, 306, is formed above bottom gate electrode,
304. Examples of suitable materials for the gate dielectric include
silicon oxide and silicon nitride, a stack of silicon nitride and
silicon oxide, a mixture, multi-layer, or combination thereof of a
high bandgap (e.g. silicon oxide, or aluminum oxide) and high-k
dielectric material (e.g. hafnium oxide, zirconium oxide, titanium
oxide), a high bandgap material (e.g. silicon oxide, or aluminum
oxide) or high-k dielectric material (e.g. hafnium oxide, zirconium
oxide, titanium oxide). The gate dielectric, 306, is typically
formed by a deposition process followed by a patterning process.
Optionally, an anneal step is implemented prior to patterning, post
patterning, or both. The gate dielectric, 306, may be formed using
deposition techniques such as PVD, ALD, or PECVD, or a combination
thereof. The performance of the gate dielectric can be sensitive to
composition and process parameters. The gate dielectric, 306, may
be patterned using either wet techniques such as chemical etching,
or dry techniques such as reactive ion etching (RIE). In both of
these techniques, parameters such as the uniformity, etch rate,
selectivity, critical dimension loss, taper angle, cost,
throughput, etc. are sensitive to the process parameters of the
etch process.
[0051] Metal-based semiconductor layer, 308, is formed above gate
dielectric, 306. The metal-based semiconductor layer, 308, is
typically formed by a deposition process followed by a patterning
process. Optionally, an anneal step is implemented prior to
patterning, post patterning, or both. The anneal step may occur
just below atmospheric pressure, at atmospheric pressure, or
slightly above atmospheric pressure. Typical anneal ambient
atmospheres contain at least one of oxygen, ozone, water, hydrogen,
nitrogen, argon, or a combination thereof. In addition, the
metal-based semiconductor layer may be treated prior to etch
stopper or source/drain deposition with a plasma containing O.sub.2
or N.sub.2O. The metal-based semiconductor layer, 308, may be
formed using deposition techniques such as PVD, MOCVD, or wet
depositions, (e.g. based on sol-gels). The performance of the
metal-based semiconductor layer can be sensitive to composition and
process parameters. Examples of suitable materials for the
metal-based semiconductor layer include indium gallium zinc oxide
(In--Ga--Zn--O or IGZO), amorphous silicon, low-temperature
polysilicon, In--Zn--O (IZO), Zn--Sn--O (ZTO), Hf--In--Zn--O
(HIZO), and Al--Zn--Sn--O (AZTO), oxy-nitrides such as Zn--O--N
(ZnON), In--O--N (InON), Sn--O--N (SnON), c-axis aligned
crystalline (CAAC) materials such as CAAC-IGZO, or polycrystalline
materials such as ZnO or In--Ga--O (IGO). Indium in these materials
might be partially or completely replaced by Sn, or Sb. Gallium in
these materials might be partially or completely replaced by one or
more of Al, Hf, In, Nb, Si, Sn, Ta, Ti, Zn, or Zr. Oxygen in these
materials might be partially or completely replaced by one or more
of C, N, P, S, Se, Si, or Te. Other potential candidates as active
channel (semiconductor) materials are refractory metal
chalcogenides, (e.g. molybdenum sulfides). It should be noted that
it is possible to deposit a bi-, or tri-layer, where each layer has
a composition optimized for its functionality, the latter being
contact layer with the gate insulator, bulk active channel layer,
and contact layer with the source and drain electrodes and etch
stopper or passivation layers. Furthermore, the active
(semiconducting) channel layer might have a continuous change in
composition (e.g. a gradient) through the thickness of the film.
Common extrinsic (n-type) dopants for ZnO-based semiconductors are
Al, B, Cr, Ga, H, In and Li. Furthermore, the metal cations in the
metal-based semiconductor material (e.g. IGZO) may be partially or
completely replaced by Ag, As, Au, Bi, Cd, Cu, Zn, Ga, Ge, Hg, In,
Pb, Sb, Sn, and Tl. Other dopants of interest include halogens like
CI and F. The metal-based semiconductor layer, 108, may be
patterned using either wet techniques such as chemical etching, or
dry techniques such as RIE. In both of these techniques, parameters
such as the uniformity, etch rate, selectivity, critical dimension
loss, taper angle, cost, throughput, etc. are sensitive to the
process parameters of the etch process. This disclosure will use
IGZO as an example, but this is not meant to be limiting. The
techniques described herein can be applied to any material suitable
for display applications.
[0052] Source and drain electrodes, 312 and 314, are formed above
the metal-based semiconductor layer, 308. The source and drain
electrodes, 312 and 314, are typically formed by a deposition
process followed by a patterning process. Optionally, an anneal
step is implemented prior to patterning, post patterning, or both.
The source and drain electrodes, 312 and 314, may be formed using
deposition techniques such as PVD, wet deposition (e.g. plating),
or MOCVD (for TCOs). Typically, the deposition steps involve
sputter deposition. Patterning is commonly performed by
photolithography. The photolithography most commonly relies on wet
etching, yet dry etching (e.g. reactive ion etching) can be used as
well. Wet etch chemistries are most commonly aqueous, and include a
mixture of inorganic acids, optionally organic acids, and
optionally an oxidizer like hydrogen peroxide, or nitric acid, and
optionally other chemicals, either as stabilizers, to control
critical dimension loss, taper angle, or etch selectivity. The
performance of the source and drain electrodes can be sensitive to
composition and process parameters. The gate electrode is most
commonly a stack of two or more layers. Examples of suitable
materials for the bottom gate electrode include a stack of Cu and a
Cu-alloy, a stack of Cu and Mo, a stack of Cu and Ti, a stack of Cu
and Mo--Ti alloy, a stack of Cu and Mo--Ta alloy, Cu, Mo, Al, a
stack of Al and Mo, a stack of Al and Ti, or a stack of Al and
Mo--Ti alloy. It should be noted that Al can contain a small
concentration of Neodymium (Nd). It should be understood that the
Cu in the Cu stacks, and Al in the Al stacks are thicker than the
adjacent layers (e.g. Cu-alloy, or Mo--Ti alloy). Furthermore, the
stacks can be a bi-layer of Cu and Cu-alloy, or a tri-layer of
Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo. Typical Cu-alloys include
Cu--Mg--Al, and Cu--Mn, wherein the Cu-alloys can also contain
small concentrations of phosphides, Mg, or Ca. For some transparent
TFTs, the gate electrode consists of a transparent conductive
oxide, (e.g. In--Sn--O (ITO), In--Zn--O (IZO)), and related
materials. The source and drain electrodes, 312 and 314, may be
patterned using either wet techniques such as chemical etching, or
dry techniques such as RIE. In both of these techniques, parameters
such as the uniformity, etch rate, selectivity, critical dimension
loss, taper angle, cost, throughput, etc. are sensitive to the
process parameters of the etch process.
[0053] Passivation layer, 316, is formed above source and drain
electrodes, 312 and 314. The passivation layer, 316, is typically
formed by a deposition process followed by a patterning process.
Optionally, an anneal step is implemented prior to patterning, post
patterning, or both. The passivation layer, 316, may be formed
using deposition techniques such as PVD, ALD, or PECVD, or by wet
coating techniques. The performance of the passivation layer can be
sensitive to composition and process parameters. Examples of
suitable materials for the passivation layer include silicon oxide
and silicon nitride, a stack of silicon nitride and silicon oxide,
a mixture, multi-layer, or combination thereof of a high bandgap
(e.g. silicon oxide, or aluminum oxide) and high-k dielectric
material (e.g. hafnium oxide, zirconium oxide, titanium oxide), a
high bandgap material (e.g. silicon oxide, or aluminum oxide) or
high-k dielectric material (e.g. hafnium oxide, zirconium oxide,
titanium oxide). The passivation layer, 316, may be patterned using
either wet techniques such as chemical etching, or dry techniques
such as RIE. In both of these techniques, parameters such as the
uniformity, etch rate, selectivity, critical dimension loss, taper
angle, cost, throughput, etc. are sensitive to the process
parameters of the etch process.
[0054] In some embodiments, between one or more of the deposition
and patterning steps discussed previously (e.g. the formation of
the gate electrode layer, the gate dielectric layer, the
metal-based semiconductor layer, the etch stopper layer, the
source/drain electrode layers, or the passivation layer), the
surface of the deposited film may be subjected to a treatment
process before the patterning step. Examples of treatment processes
include degas steps to remove adsorbed moisture due to exposure to
ambient, anneal treatments, surface cleaning treatments (either wet
or dry), and plasma treatments (e.g. exposure to plasma generated
species of Ar, H.sub.2, N.sub.2, N.sub.2O, O.sub.2, O.sub.3,
etc.).
[0055] FIG. 4 is a flow chart illustrating the steps of a method
according to some embodiments. In step 402, a gate electrode layer
is deposited above the substrate. Typically, the gate electrode is
a material with high conductivity such as a metal, metal alloy, or
conductive metal compound (e.g. titanium nitride, tantalum nitride,
and the like). Examples of suitable materials for the gate
electrode include a stack of Cu and a Cu-alloy, a stack of Cu and
Mo, a stack of Cu and Ti, a stack of Cu and Mo--Ti alloy, a stack
of Cu and Mo--Ta alloy, Cu, Mo, Al, a stack of Al and Mo, a stack
of Al and Ti, or a stack of Al and Mo--Ti alloy. It should be noted
that Al can contain a small concentration of Neodymium (Nd). It
should be understood that the Cu in the Cu stacks, and Al in the Al
stacks are thicker than the adjacent layers (e.g. Cu-alloy, or
Mo--Ti alloy). Furthermore, the stacks can be a bi-layer of Cu and
Cu-alloy, or a tri-layer of Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo.
Typical Cu-alloys include Cu--Mg--Al, and Cu--Mn, wherein the
Cu-alloys can also contain small concentrations of phosphides, Mg,
or Ca. For some transparent TFTs, the gate electrode consists of a
transparent conductive oxide, (e.g. In--Sn--O (ITO), In--Zn--O
(IZO)), and related materials. The performance of the gate
electrode can be sensitive to composition and process parameters.
The same holds for the diffusion barrier layer underneath the gate
electrode. The gate electrode layer can be deposited using well
known deposition techniques such as PVD, CVD, PECVD, PLD,
evaporation, etc.
[0056] In step 404, the gate electrode layer is patterned. The gate
electrode layer is patterned using known photolithography
techniques followed by etching the gate electrode layer using wet
and/or dry etching processes. In some embodiments, the gate
electrode layer is etched using a combination of wet and dry
etching processes. Examples of wet etching processes include the
application of acidic, basic, or organic-solvent based solutions
(depending on the material to be etched) to the gate electrode
layer. Examples of dry etching processes include reactive ion
etching (RIE), plasma etching, ion milling, and the like.
[0057] In step 406, a gate dielectric layer is deposited above the
gate electrode layer. Typically, the gate dielectric is an
insulating material such as a silicon oxide, silicon nitride, or a
metal oxide such as aluminum oxide, and the like. Examples of
suitable materials for the gate dielectric include silicon oxide
and silicon nitride, a stack of silicon nitride and silicon oxide,
a mixture, multi-layer, or combination thereof of a high bandgap
(e.g. silicon oxide, or aluminum oxide) and high-k dielectric
material (e.g. hafnium oxide, zirconium oxide, titanium oxide), a
high bandgap material (e.g. silicon oxide, or aluminum oxide) or
high-k dielectric material (e.g. hafnium oxide, zirconium oxide,
titanium oxide). In some embodiments, the deposition process is a
vacuum-based process such as PVD, ALD, PE-ALD, AVD, UV-ALD, CVD,
PECVD, PLD, or evaporation. In some embodiments, the deposition
process is a solution-based process such as printing or spraying of
inks, screen printing, inkjet printing, slot die coating, gravure
printing, wet chemical depositions, or from sol-gel methods, such
as the coating, drying, and firing of polysilazanes. Furthermore,
the substrates may be processed in many configurations such as
single substrate processing, multiple substrate batch processing,
in-line continuous processing, in-line "stop and soak" processing,
or roll-to-roll processing.
[0058] In step 408, the gate dielectric layer is patterned.
Optionally, an anneal step is implemented prior to patterning, post
patterning, or both. The gate dielectric layer is patterned using
known photolithography techniques followed by etching the gate
dielectric layer using wet and/or dry etching processes. In some
embodiments, the gate dielectric layer is etched using a
combination of wet and dry etching processes. Examples of wet
etching processes include the application of acidic, basic, or
organic-solvent based solutions (depending on the material to be
etched) to the gate dielectric layer. Examples of dry etching
processes include reactive ion etching (RIE), plasma etching, ion
milling, and the like.
[0059] In step 410, a metal-based semiconductor layer is deposited
above the gate dielectric layer. Examples of suitable materials for
the semiconductor layer include indium gallium zinc oxide
(In--Ga--Zn--O or IGZO), amorphous silicon, low-temperature
polysilicon, In--Zn--O (IZO), Zn--Sn--O (ZTO), Hf--In--Zn--O
(HIZO), and Al--Zn--Sn--O (AZTO), oxy-nitrides such as Zn--O--N
(ZnON), In--O--N (InON), Sn--O--N (SnON), c-axis aligned
crystalline (CAAC) materials such as CAAC-IGZO, or polycrystalline
materials such as ZnO or In--Ga--O (IGO). Indium in these materials
might be partially or completely replaced by Sn, or Sb. Gallium in
these materials might be partially or completely replaced by one or
more of Al, Hf, In, Nb, Si, Sn, Ta, Ti, Zn, or Zr. Oxygen in these
materials might be partially or completely replaced by one or more
of C, N, P, S, Se, Si, or Te. Other potential candidates as active
channel (semiconductor) materials are refractory metal
chalcogenides, (e.g. molybdenum sulfides). It should be noted that
it is possible to deposit a bi-, or tri-layer, where each layer has
a composition optimized for its functionality, the latter being
contact layer with the gate insulator, bulk active channel layer,
and contact layer with the source and drain electrodes and etch
stopper or passivation layers. Furthermore, the active
(semiconducting) channel layer might have a continuous change in
composition (e.g. a gradient) through the thickness of the film.
Common extrinsic (n-type) dopants for ZnO-based semiconductors are
Al, B, Cr, Ga, H, In and Li. Furthermore, the metal cations in IGZO
may be partially or completely replaced by Ag, As, Au, Bi, Cd, Cu,
Zn, Ga, Ge, Hg, In, Pb, Sb, Sn, and Tl. Other dopants of interest
include halogens like CI and F. In some embodiments, the deposition
process is a vacuum-based process such as PVD, ALD, PE-ALD, AVD,
UV-ALD, CVD, PECVD, or evaporation. In some embodiments, the
deposition process is a solution-based process such as printing or
spraying of inks, screen printing, inkjet printing, slot die
coating, gravure printing, wet chemical depositions, or from
sol-gel methods, such as the coating, drying, and firing of
polysilazanes. Furthermore, the substrates may be processed in many
configurations such as single substrate processing, multiple
substrate batch processing, in-line continuous processing, in-line
"stop and soak" processing, or roll-to-roll processing.
[0060] In step 412, the metal-based semiconductor layer is
patterned. Optionally, an anneal step is implemented prior to
patterning, post patterning, or both. The anneal step may occur
just below atmospheric pressure, at atmospheric pressure, or
slightly above atmospheric pressure. Typical anneal ambient
atmospheres contain at least one of oxygen, ozone, water, hydrogen,
nitrogen, argon, or a combination thereof. In addition, the
semiconductor layer may be treated prior to etch stopper or
source/drain deposition with a plasma containing O.sub.2 or
N.sub.2O. The metal-based semiconductor layer is patterned using
known photolithography techniques followed by etching the
metal-based semiconductor layer using wet and/or dry etching
processes. In some embodiments, the metal-based semiconductor layer
is etched using a combination of wet and dry etching processes.
Examples of wet etching processes include the application of
acidic, basic, or organic-solvent based solutions (depending on the
material to be etched) to the metal-based semiconductor layer.
Examples of dry etching processes include reactive ion etching
(RIE), plasma etching, ion milling, and the like.
[0061] In step 414, a source/drain electrode layer is deposited
above the etch stop layer. The source and drain electrodes are
typically deposited as a single layer and then defined during the
patterning step. Typically, the source/drain electrode is a
material with high conductivity such as a metal, metal alloy, or
conductive metal compound (e.g. titanium nitride, tantalum nitride,
and the like). Examples of suitable materials for the source/drain
electrode include a stack of Cu and a Cu-alloy, a stack of Cu and
Mo, a stack of Cu and Ti, a stack of Cu and Mo--Ti alloy, a stack
of Cu and Mo--Ta alloy, Cu, Mo, Al, a stack of Al and Mo, a stack
of Al and Ti, or a stack of Al and Mo--Ti alloy. It should be noted
that Al can contain a small concentration of Neodymium (Nd). It
should be understood that the Cu in the Cu stacks, and Al in the Al
stacks are thicker than the adjacent layers (e.g. Cu-alloy, or
Mo--Ti alloy). Furthermore, the stacks can be a bi-layer of Cu and
Cu-alloy, or a tri-layer of Cu-alloy/Cu/Cu-alloy, or Mo/Al/Mo.
Typical Cu-alloys include Cu--Mg--Al, and Cu--Mn, wherein the
Cu-alloys can also contain small concentrations of phosphides, Mg,
or Ca. For some transparent TFTs, the gate electrode consists of a
transparent conductive oxide, (e.g. In--Sn--O (ITO), In--Zn--O
(IZO)), and related materials. The source/drain electrode layer can
be deposited using well known deposition techniques such as PVD,
CVD, PECVD, PLD, evaporation, etc.
[0062] In step 416, the source/drain electrode layer is patterned
into individual source and drain electrodes. Optionally, an anneal
step is implemented prior to patterning, post patterning, or both.
The source/drain electrode layer is patterned using known
photolithography techniques followed by etching the source/drain
electrode layer using wet and/or dry etching processes. In some
embodiments, the source/drain electrode layer is etched using a
combination of wet and dry etching processes. Examples of wet
etching processes include the application of acidic, basic, or
organic-solvent based solutions (depending on the material to be
etched) to the source/drain electrode layer. Wet etch chemistries
are most commonly aqueous, and include a mixture of inorganic
acids, optionally organic acids, and optionally an oxidizer like
hydrogen peroxide, or nitric acid, and optionally other chemicals,
either as stabilizers, to control critical dimension loss, taper
angle, or etch selectivity. Examples of dry etching processes
include reactive ion etching (RIE), plasma etching, ion milling,
and the like. The performance of the source and drain electrodes
can be sensitive to composition and process parameters.
[0063] Optionally, a thin layer of the active channel of the
metal-based semiconductor layer is removed after the patterning of
the source/drain layer to remove damage introduced during
processing.
[0064] In step 418, a passivation layer is deposited above the
source/drain layer to form a TFT stack. Typically, the passivation
layer is an insulating material such as a silicon oxide, silicon
nitride, or a metal oxide such as aluminum oxide, and the like.
Examples of suitable materials for the passivation layer include
silicon oxide and silicon nitride, a stack of silicon nitride and
silicon oxide, a mixture, multi-layer, or combination thereof of a
high bandgap (e.g. silicon oxide, or aluminum oxide) and high-k
dielectric material (e.g. hafnium oxide, zirconium oxide, titanium
oxide), a high bandgap material (e.g. silicon oxide, or aluminum
oxide) or high-k dielectric material (e.g. hafnium oxide, zirconium
oxide, titanium oxide). The passivation layer can be deposited
using well known deposition techniques such as PVD, CVD, PECVD,
PLD, evaporation, etc.
[0065] In step 420, the TFT stack is annealed. The annealing serves
to passivate defects that may have been formed during any of the
deposition and/or etching steps and also serves to reduce the
number of oxygen vacancies that may have been formed in the
metal-based semiconductor material. The anneal step may occur just
below atmospheric pressure, at atmospheric pressure, or slightly
above atmospheric pressure. Typical anneal ambient atmospheres
contain at least one of oxygen, ozone, water, hydrogen, nitrogen,
argon, or a combination thereof. The annealing is typically
performed in a temperature range between 150 C. and 400 C. for
times between 10 minutes and 60 minutes.
[0066] In some embodiments, between one or more of the deposition
and patterning steps discussed previously (e.g. the formation of
the gate electrode layer, the gate dielectric layer, the
metal-based semiconductor layer, the etch stopper layer, the
source/drain electrode layers, or the passivation layer), the
surface of the deposited film may be subjected to a treatment
process before the patterning step. Examples of treatment processes
include degas steps to remove adsorbed moisture due to exposure to
ambient, anneal treatments, surface cleaning treatments (either wet
or dry), and plasma treatments (e.g. exposure to plasma generated
species of Ar, H.sub.2, N.sub.2, N.sub.2O, O.sub.2, O.sub.3,
etc.).
[0067] The performance of the metal-based semiconductor layer will
be sensitive to parameters such as composition, crystal structure,
oxygen vacancies, surface defects, interface state density, and the
like. Many of these parameters will be influenced by the processing
of the material and the process conditions to which the material is
exposed. As an example, in the method as outlined in FIG. 4, the
metal-based semiconductor material is exposed to air (after
deposition), photoresist and photoresist developer (during
patterning), etch chemistries (either wet, dry, or both),
processing conditions related to the deposition of the source/drain
layer (e.g. elevated temperatures, plasma bombardment, etc.), and
processing conditions related to the patterning of the source/drain
layer (either wet, dry, or both). Those skilled in the art will
understand that the active channel of the metal-based semiconductor
layer is exposed to all of these processing conditions. As
discussed previously, typically, a thin layer of the active channel
of the metal-based semiconductor layer is removed after the
patterning of the source/drain layer to remove damage introduced
during processing.
[0068] In some embodiments, the metal-based semiconductor layer is
based on an IGZO material. Some of these materials exhibit stable
amorphous phases, high mobility (e.g. >5 cm.sup.2/Vs), low
threshold voltage (close to zero, e.g. in a range of -1.0V to
+2.0V), low carrier concentrations (e.g. 10.sup.16-10.sup.17
cm.sup.-3), high ON/OFF current ratios (e.g. >10.sup.6), and
high durability (e.g. negative bias temperature illumination stress
NBTIS with threshold voltage shift in a range of -1.5V to +0.5V).
However, since these materials are multinary compounds (e.g. three
or more elements), their performance and properties are sensitive
to factors such as composition, concentration gradients, deposition
parameters, post-deposition treatments, interactions with adjacent
materials, and the like.
[0069] A common process for the deposition of the metal-based
semiconductor layer (e.g. IGZO) is PVD, as discussed previously.
The performance and properties of the IGZO layer can be sensitive
to parameters such as composition, composition uniformity, degree
of crystallinity, etc. Typically, the IGZO layer is deposited using
a reactive PVD process wherein the sputtering atmosphere includes
Ar, O.sub.2, and sometimes, N.sub.2. The PVD target may include an
In.sub.xGa.sub.yZn.sub.zO.sub.4 target where x:y:z can be at a
ratio of about 1:1:1.
[0070] One of the performance metrics for IGZO layers is the
stability under negative bias illuminated stress (NBIS). As an
example, the threshold voltage often shifts in a negative direction
under negative bias and when illuminated by light with wavelengths
toward the blue end of the visible spectrum. One explanation of the
negative shift in the threshold voltage involves a hole trapping
model. The model and associated mechanism make use of deep donor
states within the band-gap of IGZO materials. The deep donor states
are typically associated with oxygen vacancies within the
material.
[0071] The concentration of oxygen vacancies within the IGZO
material can be influenced by the process parameters employed
during the deposition. As discussed previously, the sputtering
atmosphere typically includes Ar, O.sub.2, and sometimes N.sub.2.
In some embodiments, the sputtering atmosphere includes at least
one of ozone (O.sub.3) or nitrous oxide (N.sub.2O) as the oxidant.
These gases are more reactive than O.sub.2 and will result in a
lower concentration of oxygen vacancies within the IGZO layer.
Furthermore, utmost care needs to be taken t control hydrogen
incorporation during all processing steps, especially, in the
presence of oxygen vacancies.
[0072] In some embodiments, a sputtering target has a composition
of In.sub.xGa.sub.yZn.sub.zO.sub.4 where x:y:z can be a ratio of
about 1:1:1 and the sputtering atmosphere includes at least one of
O.sub.3 or N.sub.2O. Those skilled in the art will understand that
other PVD targets with other compositions can be used. The
concentration of the at least one of O.sub.3 or N.sub.2O can vary
from 1 to 100 volume % of the sputtering atmosphere. In some
embodiments, the concentration is fixed throughout the deposition
process. In some embodiments, the concentration is varied during
the deposition process. The sputtering atmosphere may further
include other gases such as Ar, He, Xe, O.sub.2, N.sub.2, etc. In
some embodiments, the substrate holder setpoint may be between room
temperature and 500 C. In some embodiments, the pressure within the
sputtering chamber may be between 1 and 20 millitorr (mT).
[0073] In some embodiments, a plurality of sputtering targets with
compositions of In.sub.aO.sub.b, Ga.sub.cO.sub.d, and
Zn.sub.eO.sub.f can be used to co-sputter the IGZO layer. The
sputtering atmosphere includes at least one of O.sub.3 or N.sub.2O.
Those skilled in the art will understand that other PVD targets
with other compositions can be used (e.g. one or more of the PVD
targets may contain two or more of the metal elements). The
concentration of the at least one of O.sub.3 or N.sub.2O can vary
from 1 to 100 volume % of the sputtering atmosphere. The sputtering
atmosphere may further include other gases such as Ar, He, Xe,
O.sub.2, N.sub.2, etc. In some embodiments, the substrate holder
setpoint may be between room temperature and 500 C. In some
embodiments, the pressure within the sputtering chamber may be
between 1 and 20 millitorr (mT).
[0074] In high volume manufacturing, the IGZO layer is typically
deposited using a PVD (sputtering) process. The deposition system
may be a batch system or an in-line system, but the in-line system
is preferred due to higher throughput and lower cost of ownership.
The in-line system may be continuous (i.e. the substrates move
continuously through the system) or the in-line system may use a
"stop and soak" process wherein the substrates are transported to a
process station where they stop until the process is completed.
In-line systems typically include a number of process stations to
allow different compositions to be deposited or to break a long
deposition cycle into smaller, balanced, deposition cycles to
increase the overall equipment efficiency of the system. At each
process station, the substrate may be subjected to small
translational oscillations to improve the uniformity of the
deposition. This oscillation is not considered part of the
transport of the substrate.
[0075] FIG. 5 illustrates an exemplary in-line deposition (e.g.
sputtering) system according to some embodiments. FIG. 5
illustrates a system with three deposition stations, but those
skilled in the art will understand that any number of deposition
stations can be supplied in the system. For example, the three
deposition stations illustrated in FIG. 5 can be repeated and
provide systems with 6, 9, 12, etc. targets, limited only by the
desired layer deposition sequence and the throughput of the system.
A transport mechanism 520, such as a conveyor belt or a plurality
of rollers, can transfer substrate 540 between different deposition
stations. For example, the substrate can be positioned at station
#1, comprising a target assembly 560A, then transferred to station
#2, comprising target assembly 560B, and then transferred to
station #3, comprising target assembly 560C. Station #1 can be
configured to deposit an IGZO layer. Station #2 can be configured
to deposit an additional IGZO layer with the same or different
composition. Station #3 can be configured to deposit an additional
IGZO layer with the same or different composition.
[0076] Although only a single target for each deposition station is
illustrated in FIG. 5, in some embodiments, a deposition station
may include more than one target to allow the co-sputtering of more
than one material as discussed previously.
[0077] Although the foregoing examples have been described in some
detail for purposes of clarity of understanding, the invention is
not limited to the details provided. There are many alternative
ways of implementing the invention. The disclosed examples are
illustrative and not restrictive.
* * * * *