U.S. patent application number 13/931589 was filed with the patent office on 2014-09-11 for engineering change order hold time fixing method.
The applicant listed for this patent is National Chiao Tung University. Invention is credited to Sung-Ting HO, Hiu-Ru JIANG, Yu-Ming YANG.
Application Number | 20140258957 13/931589 |
Document ID | / |
Family ID | 51489532 |
Filed Date | 2014-09-11 |
United States Patent
Application |
20140258957 |
Kind Code |
A1 |
JIANG; Hiu-Ru ; et
al. |
September 11, 2014 |
ENGINEERING CHANGE ORDER HOLD TIME FIXING METHOD
Abstract
An ECO hold time fixing method fulfills a short path padding in
a placed and routed design by a minimum capacitance insertion. In
the method, a padding value determination step receives the placed
and routed design and is based on a cell library, timing
constraints, and a timing analysis report to determine padding
values and locations required for each gate of the placed and
routed design to output. A load/buffer allocation step is based on
a spare cell information, a dummy metal information, and the
padding values and locations to achieve the short path padding in
the placed and routed design.
Inventors: |
JIANG; Hiu-Ru; (New Taipei
City, TW) ; YANG; Yu-Ming; (New Taipei City, TW)
; HO; Sung-Ting; (Taoyuan County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
National Chiao Tung University |
Hsinchu City |
|
TW |
|
|
Family ID: |
51489532 |
Appl. No.: |
13/931589 |
Filed: |
June 28, 2013 |
Current U.S.
Class: |
716/114 |
Current CPC
Class: |
G06F 30/327 20200101;
G06F 2119/12 20200101; G06F 30/39 20200101 |
Class at
Publication: |
716/114 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 5, 2013 |
TW |
102107593 |
Claims
1. A computer-based engineering change order hold time fixing
method executed by using a non-transitory computer readable medium
for fulfilling a short path padding in a placed and routed design
by a minimum capacitance insertion, comprising: a padding value
determination step, which receives the placed and routed design and
is based on a cell library, timing constraints, and a timing
analysis report to determine padding values and locations required
for each gate of the placed and routed design to output; and a
load/buffer allocation step, which is based on a spare cell
information, a dummy metal information, and the padding values and
locations to achieve the short path padding in the placed and
routed design; wherein the padding value determination step
comprises: a padding resource collection step, which is based on
the spare cell information, the dummy metal information to collect
available spare cells and available dummy metal information located
within a bounding box of a fanout net of a gate in the placed and
routed design; a fanout padding flexibility calculation/flexibility
checking step, which calculates a fanout padding flexibility
P.sub.F(g.sub.i) of the gate g.sub.i in the placed and routed
design; a padding value decision step, which is based on the fanout
adding flexibility P.sub.F(g.sub.i) of the gate g.sub.i to
calculate a padding value of the gate; an improvement determination
step, which determines whether all hold violations of short paths
of each gate in the placed and routed design are resolved or no
more violation is eliminated, and returns to the fanout padding
flexibility calculation/flexibility checking step when a violation
is not resolved or eliminated; and a padding value refinement step,
which is based on a reverse topological order to calculate a
refined padding value of the gate in the placed and routed design
when all hold violations of short paths of each gate in the placed
and routed design are resolved or no more violation is eliminated,
so as to further reduce the padding value of the gate; and wherein
the load/buffer allocation step comprises: a finding spare cell
candidate step, which generates spare cell candidates for each
padding gate/wire in the placed and routed design, such that for
each padding gate, the available spare cells located within the
bounding box of the fanout net are programmed as an available
resource for a padding gate; a spare cell selection step, which
assigns an optimal subset sum solution to each padding gate/wire to
completely ad the short paths in the placed and routed design; and
a dummy metal allocation step, which use a dummy metal insertion to
completely pad the short paths in the placed and routed design; and
wherein the placed and routed design is represented by a directed
graph K=(G, E), where K is comprised of gates G and edges E, each
node g.sub.i .di-elect cons. G represents a gate associated with a
gate delay D(g.sub.i), and each edge e(g.sub.i, g.sub.j).di-elect
cons. E represents a wire connecting the gates g.sub.i, g.sub.j
.di-elect cons. G, such that a setup arrival time A(g.sub.i) of an
output of the node is expressed as:
A(g.sub.i)=max.sub.j{A(g.sub.i)|e(g.sub.i, g.sub.j).di-elect cons.
E}+D(g.sub.i), a setup required time R(g.sub.i) of the output of
the node g.sub.i is expressed as: R(g.sub.i)=min.sub.k{R(g.sub.i,
g.sub.k)|R(g.sub.i, g.sub.k)=R(g.sub.k)-D(g.sub.k), e(g.sub.i,
g.sub.k).di-elect cons. E}, a hold arrival time a(g.sub.i) of the
output of the node g.sub.i is expressed as:
a(g.sub.i)=min.sub.j{a(g.sub.j)|e(g.sub.j, g.sub.i).di-elect cons.
E}+D(g.sub.i), and a hold required time r(g.sub.i) of the output of
the node g.sub.i is expressed as: r(g.sub.i)=min.sub.k{r(g.sub.i,
g.sub.k)|r(g.sub.i, g.sub.k)=r(g.sub.k)-D(g.sub.k), e(g.sub.i,
g.sub.k).di-elect cons. E}.
2-4. (canceled)
5. The method as claimed in claim 1, wherein a setup edge slack
S(g.sub.i, g.sub.j) of the edge e(g.sub.i, g.sub.j).di-elect cons.
E contributed from the node g.sub.i to the node g.sub.j is
expressed as: S(i, j)=R(i, j)-A(i), S(g.sub.i, g.sub.j)=R(g.sub.i,
g.sub.j)-A(g.sub.i), a setup node slack S(g.sub.i) of the node
g.sub.i .di-elect cons.0 G is expressed as: S(i)=min.sub.j{S(i,
j)|e(i, j).di-elect cons. E}=R(i)-A(i),
S(g.sub.i)=min.sub.j{S(g.sub.i, g.sub.j)|e(g.sub.i,
g.sub.j).di-elect cons. E}=R(g.sub.i)-A(g.sub.i), a hold edge slack
H(g.sub.i, g.sub.j) of the edge e(g.sub.i, g.sub.j).di-elect cons.
E contributed from the node g.sub.i to the node g.sub.j is
expressed as: H(i, j)=a(i)-r(i, j) H(g.sub.i,
g.sub.j)=a(g.sub.i)-r(g.sub.i, g.sub.j), and a hold node slack
H(g.sub.i) of the node g.sub.i .di-elect cons. G is expressed as:
H(i)=min.sub.j{H(i, j)|e(i, j).di-elect cons. E}=a(i)-r(i)
H(g.sub.i)=min.sub.j{H(g.sub.i, g.sub.j)|e(g.sub.i,
g.sub.j).di-elect cons. E}=a(g.sub.i)-r(g.sub.i).
6. The method as claimed in claim 5, wherein a safe padding value
P.sub.saf(g.sub.i) of each node g.sub.i is expressed as:
P.sub.saf(i)=min{S(i), |min{0, H(i)}|, P.sub.max(i)},
P.sub.saf(g.sub.i)=min{S(g.sub.i), |min{0, H(g.sub.i)}|,
P.sub.max(g.sub.i)}.
7. The method as claimed in claim 6, wherein a fanout padding
flexibility P.sub.F(g.sub.i) of the node g.sub.i .di-elect cons. G
is expressed as: P F ( i ) = { 0 , g i .di-elect cons. PO or H ( i
) .gtoreq. 0 ; min { 0 , min e ( i , j ) .di-elect cons. E { H ' (
i , j ) } } - H ( i ) , otherwise . P F ( g i ) = { 0 , g i
.di-elect cons. PO or H ( g i ) .gtoreq. 0 ; min { 0 , min e ( g i
, g j ) .di-elect cons. E { H ' ( g i , g j ) } } - H ( g i ) ,
otherwise ; , ##EQU00004## where H'(i, j)=H(i,
j)+P.sub.F(j)+P.sub.saf(j)H'(g.sub.i, g.sub.j)=H(g.sub.i,
g.sub.j)+P.sub.F(g.sub.j)+P.sub.saf(g.sub.j).
8. The method as claimed in claim 7, wherein the padding value
P(g.sub.i) of the gate is expressed as:
P(i)=max{P.sub.saf(i)-P.sub.F(i), 0}
P(g.sub.i)=max{P.sub.saf(g.sub.i)-P.sub.F(g.sub.i), 0}.
9. The method as claimed in claim 8, wherein a reverse padding
value P.sub.rev(g.sub.i) for the gate g.sub.i is expressed as: P
rev ( i ) = { P ( i ) , if g i has only one hold violating fanin ;
0 , otherwise . P rev ( g i ) = { P ( g i ) , if g i has only one
hold violation fanin ; 0 , otherwise ; , ##EQU00005## an added safe
padding value P.sub.add(g.sub.i) of the gate g.sub.i is defined as:
P.sub.add(i)=min{S(i), P.sub.max(i)-P(i)};
P.sub.add(g.sub.i)=min{S(g.sub.i), P.sub.max(g.sub.i)-P(g.sub.i)};
where P.sub.max(g.sub.i) is maximum padding delay of the gate
g.sub.i, and a refined padding value P.sub.ref(g.sub.i) of the gate
g.sub.i is expressed as: P.sub.ref(i)=P(i)+min{P.sub.add(i),
min.sub.j{P.sub.rev(j)|H(i, j)<P(i)}
P.sub.ref(g.sub.i)=P(g.sub.i)+min{P.sub.add(g.sub.i),
min.sub.jP.sub.rev(g.sub.j)|H(g.sub.i,
g.sub.j)<P(g.sub.i)}}.
10. The method as claimed in claim 9, wherein the padding value
refinement step further comprises a wire padding value step to
calculate a wire padding value for a wire e(g.sub.i, g.sub.j), so
as to further reduce the padding values of each gate/wire in the
placed and routed design, where the wire padding value P(g.sub.i,
g.sub.j) expressed as: P(i, j)=min{S(i, j), |min{0, H(i, j)}|}
P(g.sub.i, g.sub.j)=min{S(g.sub.i, g.sub.j), |min{0, H(g.sub.i,
g.sub.j)}|}.
11. The method as claimed in claim 10, wherein the spare cell
selection step extracts conflicted padding gates/wires and their
multiple subset sum solutions in case of one or more conflicts,
sorts the conflicted padding gates/wires in an ascending order of
the number of their recorded subset sum solutions, and accordingly
assigns each padding gate to a best and available subset sum
solution.
12. The method as claimed in claim 11, wherein the dummy metal
allocation step uses a maximum flow network process to assign a
virtual metal in case of one or more conflicts.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to the technical field of
integrated circuits and, more particularly, to an engineering
change order (ECO) hold time fixing method.
[0003] 2. Description of Related Art
[0004] Due to a wide range of dynamic variations, e.g., supply
voltage droops, process variations, temperature fluctuations, soft
errors, and transistor aging degradation, the timing
characterization is extremely difficult in modern IC designs.
Therefore, in conventional design, designers conservatively reserve
a timing guardband to ensure correct functionality even under the
worst-case circumstance. However, this reserved guardband may
severely degrade circuit performance, i.e., limit the clock
frequency.
[0005] Accordingly, several resilient circuits have been proposed
to eliminate the guardband by error detection and correction. For
example, a Razor flip-flop (FF) is used as an error detection
circuit (See D. Ernst et al., "Razor: a low-power pipeline based on
circuit-level timing speculation" MICRO, pp. 7-18, 2003). FIG. 1
illustrates a conventional Razor FF used as the error detection
circuit. As shown in FIG. 1, the error detection circuit has an
extra storage element, i.e., the shadow latch 110, to sample the
output of a combinational logic 120 by a delayed clock clk_dly. The
output of a main flip-flop 130 is compared with the output of the
shadow latch by a comparator 140, i.e., an XNOR gate. When the
comparison result indicates a detected timing error, a timing error
signal is generated, and the error correction is performed through
an instruction replay.
[0006] However, these resilient circuits require a significant hold
time margin for short paths. Taking the circuit of FIG. 1 as an
example, the resilient circuit may detect a false timing error if
the result of the next computation is propagated through a short
path and sampled by the delayed clock. To avoid such false error
detection, the short paths have to exceed an error detection window
w, i.e., the phase difference between the normal clock clk and the
delayed clock clk_dly. The error detection window w causes an extra
hold time margin requirement. This issue also exists in the
resilient circuits proposed in other articles. Due to the extra
hold time margin requirement, the short path padding or hold timing
fixing in the resilient circuits becomes more challenging.
[0007] To resolve this padding problem, prior works typically
insert buffers to lengthen the short paths.
[0008] Among the prior works, the delay padding is combined with a
clock skew scheduling to minimize the clock period at the logic
re-synthesis stage. The goal is to determine the padding path for
each path rather than to decide where to insert the delay.
[0009] By contrast, another short path padding method determines
the positions to insert the delay. This problem is solved by a
linear programming proposed in N. V. Shenoy et al. "Minimum padding
to satisfy short path constraints." ICCAD, pp. 156-161, 1993.
However, such linear programming is time-consuming and not
applicable to large-scale circuits. Hence, another prior art
provides greedy heuristics. One greedy rule is to pad the gate with
the largest setup slack for trying not to hurt the longest path
delay. The other is to pad at the gate passed by the most hold
violating paths for trying to reduce the total padding delay.
[0010] FIG. 2 shows a flowchart of integrating timing error
resilient circuits into a design. Because of considering the timing
guardband, based on the logic synthesis and timing analysis of
conservative clock period, the target clock period and the error
detection window w are determined. Moreover, the invention proposes
coarse-grained and fine-grained padding allocation methods to
further achieve the derived padding values at physical
implementation. S.sub.th/H.sub.th represents a ratio of the target
clock period over the conservative clock period. The timing
suspicious flip-flops, whose longest path delays exceed the target
clock period, can be replaced by the resilient circuits. Before the
replacement, the design is re-synthesized where the suspicious
flip-flops are assigned with an extra hold time margin to cover the
error detection window w. After the replacement, a placement and
routing is applied. Because of the significant hold time margin,
the hold violations may still exist in a placed and routed design.
Finally, the short path padding is performed.
[0011] In addition, it is found that the cited greedy heuristics
cannot pad the short paths well. FIGS. 3A-3D show typical short
path padding. FIG. 3A gives an input design, where gates g.sub.1,
g.sub.2, g.sub.3 incur hold violations. After iteratively padding
delay on the gate either with the largest setup slack or with the
most hold violating paths, the result is shown in FIG. 3B or 3C.
From FIGS. 3B and 3C, it is found that the unresolved hold
violation at gate g.sub.2 exists. However, all the hold violations
can be cleaned by the padding way shown in FIG. 3D. Accordingly, it
is clear that the padding based only on local views cannot pad all
the short paths. Moreover, even an optimal padding solution is
found, it may still fail at a physical implementation because the
delay offered by buffers is fixed. For example, if one buffer
offers either a 0.15-unit or 0.25-unit delay, the padding task
still fails on gate g.sub.2.
[0012] Therefore, it is desirable to provide an improved hold
timing fixing method to mitigate and/or obviate the aforementioned
problems.
SUMMARY OF THE INVENTION
[0013] The object of the present invention is to provide an
engineering change order (ECO) hold time fixing method, which
determines the padding values and locations with a global view and
uses spare cells in a coarse-grained delay padding and a dummy
metal in a fine-grained delay padding, so as to successfully
achieve the hold time fixing in a placed and routed design.
[0014] To achieve the object, the present invention provides an ECO
hold time fixing method, which fulfills the short path padding in a
placed and routed design by a minimum capacitance insertion. The
method includes a padding value determination step and a
load/buffer allocation step. The padding value determination step
receives the placed and routed design and is based on a cell
library, timing constraints, and a timing analysis report to
determine padding values and locations required for each gate of
the placed and routed design to output. The load/buffer allocation
step is based on a spare cell information, a dummy metal
information, and the padding values and locations to achieve the
short path padding in the placed and routed design.
[0015] Other objects, advantages, and novel features of the
invention will become more apparent from the following detailed
description when taken in conjunction with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a schematic diagram of a conventional Razor
flip-flop;
[0017] FIG. 2 is a flowchart of integrating timing error resilient
circuits into a design;
[0018] FIGS. 3A-3D are schematic charts of typical short path
padding;
[0019] FIG. 4 is a flowchart of an ECO hold time fixing method
according to the invention;
[0020] FIGS. 5A and 5B are schematic diagrams of delay padding of
short paths according to the invention;
[0021] FIGS. 6A and 6B are schematic charts of applying padding
values to a placed and routed design according to the
invention;
[0022] FIG. 7 is a schematic chart of available spare cells within
a bounding box according to the invention;
[0023] FIG. 8 is a table illustrating a relationship between spare
cells and padding values when subset sums are solved by a dynamic
programming according to the invention;
[0024] FIG. 9 is a schematic chart of a spare cell competition
according to the invention;
[0025] FIG. 10 is a schematic chart of optimal selections between
padding gates/wires and spare cells according to the invention;
[0026] FIG. 11 is a schematic diagram of a dummy metal of
conflicted padding gates/wires according to the invention;
[0027] FIG. 12 is a schematic chart of a maximum flow network
process according to the invention;
[0028] FIG. 13 is a table of benchmark statistics according to the
invention;
[0029] FIGS. 14A and 14B are a comparison table of padding values
of the invention and the prior art; and
[0030] FIG. 15 is a comparison table of negative setup
slack/negative hold slack of the invention and the prior art.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0031] FIG. 4 is a flowchart of an engineering change order (ECO)
hold time fixing method according to the invention. The method
inserts the minimum capacitance in a placed and routed design to
thereby fulfill the short path padding in the placed and routed
design.
[0032] The cell timing model used in the invention is based on
Synopsys' Liberty library. The calibrated delay values of each
library cell are stored in lookup tables and indexed by its input
slew and output capacitance. Thus, each gate delay can be obtained.
The wire delay of each net is lumped into the delay of its driving
gate. The output capacitance of a gate includes its wire loading,
the input capacitance of its fanout gates, and its output pin
capacitance. Proposed by Chen et al. "ECO timing optimization using
spare cells", the ICCAD, pp. 530-535, 2007, it teaches a loading
dominance phenomenon, i.e., the change on the gate delay is
dominated by the change on the output loading, as compared with the
change on the input slew. Thus, the invention increases the output
capacitance of the gate to thereby increase the delay. Namely, the
increased delay is converted into the capacitance. In addition, the
output capacitance of the gate is not greater than the maximum load
capacitance defined in the cell library.
[0033] The short path padding is not only important for the
conventional IC designs but also more challenging in the resilient
circuits. In order to validate the error detection and correction
mechanism of the resilient circuits, the invention focuses on the
short path padding problem which is formulated as follows: given a
placed and routed design, the cell library, spare cells, dummy
metal information, timing constraints, and a timing analysis report
for inserting the minimum capacitance to pad all the short paths
under the timing constraints.
[0034] Since the reported timing is somewhat inaccurate and the
available resource for padding is uncertain at early stages, the
invention performs the short path padding at the post-output stage.
FIGS. 5A and 5B are schematic diagrams of delay padding of short
paths according to the invention. As shown in FIG. 5A, a buffer
insertion is performed to increase the short path delay. As shown
in FIG. 5B, an extra load capacitance is introduced to lengthen the
short paths. Therefore, the inserted delay can be provided by cells
and metal wires. A design is usually sprinkled with spare cells
(redundant cells) at the placement stage, as well as with a dummy
metal which offers an abundant resource of capacitance and can be
tuned. Hence, padding at the post-layout stage can then be done by
rewiring the spare cells and dummy metal. Upon Synopsys' Liberty
library standards, the amount of delay increment and the amount of
correspondingly inserted load/buffers can be directly converted to
each other by a table lookup.
[0035] As shown in FIG. 4, the method includes a step of padding
value determination and a step of load/buffer allocation.
[0036] The padding value determination step receives the placed and
routed design and is based on a cell library, timing constraints,
and a timing analysis report to determine padding values and
locations required for each gate of the placed and routed design to
output. The padding value determination step determines or
generates the padding values and locations with a global view.
[0037] The load/buffer allocation step is based on a spare cell
information, a dummy metal information, and the padding values and
locations required for each gate of the placed and routed design to
achieve the short path padding in the placed and routed design. The
load/buffer allocation step is realized by introducing extra load
capacitance and inserting the buffers. To achieve the assigned
padding values generated in the padding value determination step,
the load/buffer allocation step is divided into two stages of
coarse-grained delay padding and fine-grained delay padding. The
coarse-grained delay padding uses the spare cells, and the
fine-grained delay padding uses a dummy metal.
[0038] Generally, the more total padding delay means the more total
padding overhead. Hence, the invention first targets to minimize
the total padding delay and then converts the padding delay of each
gate/wire into padding load/buffers. However, there are two
challenges. One is to find good location to pad the delay, and the
other is not to hurt the setup time of the gate.
[0039] The difficulty of the first challenge is that padding on
gates close to primary inputs can easily satisfy the timing
constraints, but may increase the total padding values. By
contrast, padding on gates shared by many short paths can lower
total padding values, but may violate the timing constraints. As
shown in FIG. 2A, if the gates g.sub.2 and g.sub.3 are padded with
0.3-unit delay individually, the timing constraints are satisfied,
but the total padding value is 0.6, which is somewhat large. If the
gate g.sub.1 is padded with 0.3-unit delay, the short path through
g.sub.2 to the primary output o.sub.1 is unresolved. Thus, to
tackle these challenges, using the global view to determine the
padding values and locations is required.
[0040] The padding value determination step includes a padding
resource collection, a fanout padding flexibility
calculation/flexibility checking, a padding value decision, an
improvement determination, and a padding value refinement.
[0041] Since the ECO hold time fixing method is applied at the
post-layout stage, the available padding resource is collected
firstly. The available resource to pad each gate includes the spare
cell and dummy metal information located within a bounding box of
its fanout net. Thus, the padding resource collection can collect
available spare cells and available dummy metal information located
within a bounding box of the fanout net of a gate in the placed and
routed design.
[0042] The maximum padding capacitance C.sub.max(i) of a gate
g.sub.i is the minimum of the maximum output capacitance defined in
the cell library and its available padding resource, and thus we
have C.sub.max(i)=0 for a primary output or a flip-flop (FF) input.
The maximum padding capacitance C.sub.max(i, j) of a wire between
the gates g.sub.i and g.sub.j is defined similarly. Both of the
maximum padding capacitances C.sub.max(i) and C.sub.max(ii) give
the upper bounds but still preserve flexibilities to set the
padding values. The fanout padding flexibility
calculation/flexibility checking calculates the fanout padding
flexibility P.sub.F(i) of a gate in the placed and routed design.
With a global view to determine the padding values and locations,
the fanout padding flexibility P.sub.F(i) of the whole fanout cone
of each hold violating gate is first calculated.
[0043] A circuit design is represented by a directed graph K=(G,
E), where K is comprised of gates G and edges E, each node g.sub.i
.di-elect cons. G represents a gate associated with a gate delay
D(i), and each edge e(i, j).di-elect cons. E represents a wire
connecting the gates g.sub.i, g.sub.j .di-elect cons. G. The setup
arrival time A(i) of the output of the node g.sub.i is expressed as
follows:
A(i)=max.sub.j{A(j)|e(j, i).di-elect cons. E}+D(i).
The setup required time R(i) of the output of the node g.sub.i is
expressed as follows:
R(i)=min.sub.k{R(i, k)|(R(i, k)=R(k)-D(k), e(i, k).di-elect
cons.E}.
The hold arrival time a(i) of the output of the node g.sub.i is
expressed as follows:
a(i)=min.sub.j{a(j)|e(j, i).di-elect cons. E}+D(i).
The hold required time r(i) of the output of the node g.sub.i is
expressed as follows:
r(i)=max.sub.k{r(i, k)|r(i, k)=r(k)-D(k), e(i, k).di-elect cons.
E}.
[0044] The setup edge slack S(i, j) of the edge e(i, j).di-elect
cons. E contributed from the node g.sub.j back to the node g.sub.i
is expressed as follows:
S(i, j)=R(i, j)-A(i).
The setup node slack S(i) of the node g.sub.i .di-elect cons. G is
expressed as follows:
S(i)=min.sub.j{S(i, j)|e(i, j).di-elect cons. E}=R(i)-A(i).
The hold edge slack H(i, j) of the edge e(i, j).di-elect cons. E
contributed from the node g.sub.j back to the node g.sub.i is
expressed as follows:
H(i, j)=a(i)-r(i, j).
The hold node slack H(i) of the node g.sub.i .di-elect cons. G is
expressed as follows:
H(i)=min.sub.j{H(i, j)|e(i, j).di-elect cons. E}=a(i)-r(i).
For example, as shown in FIG. 3A, H(2, 1)=0.1-0.4=-0.3, H(2,
o.sub.1)=0.1-0.3=-0.2 and H(2)=-0.3 are calculated.
[0045] The safe padding value P.sub.saf(i) of each node or gate
g.sub.i is expressed as follows:
P.sub.saf(i)=min{S(i), min{0, H(i)}|, P.sub.max(i)},
where P.sub.max(i) indicates the maximum padding delay of the node
or gate g.sub.i converted from the maximum padding capacitance
C.sub.max(i), and P.sub.max(i)=0 for a primary output or a
flip-flop input.
[0046] Accordingly, the timing constraints are satisfied when the
delay of a node g.sub.i on a short path is increased by t, for
t.ltoreq.P.sub.saf(i).
[0047] The fanout padding flexibility P.sub.F(i) of the node
g.sub.i .di-elect cons. G is expressed as follows:
P F ( i ) = { 0 , g i .di-elect cons. PO or H ( i ) .gtoreq. 0 ;
min { 0 , min e ( i , j ) .di-elect cons. E { H ' ( i , j ) } } - H
( i ) , otherwise . ##EQU00001##
where H'(i, j)=H(i, j)+P.sub.F(j)+P.sub.saf(j). In addition, we
have:
H ' ( i ) = min j { H ' ( i , j ) , e ( i , j ) .di-elect cons. E }
, S ' ( i ) = min j { ( i , j ) - ( S ' ( j ) - S ( j ) ) - P saf (
j ) e ( i , j ) .di-elect cons. E } . ##EQU00002##
H'(i) and S'(i) represent the updated slacks when the fanout cone
is padded with the maximum allowable delay, and accordingly
P.sub.saf(i) is dynamically updated.
[0048] The invention defines the fanout padding flexibility
P.sub.F(i) for each gate g.sub.i to reflect the maximum padding
value allowed on the whole fanout cone of the gate g.sub.i. For a
hold satisfying gate or a primary output, the fanout padding
flexibility P.sub.F(i) is 0. For a hold violating gate g.sub.i, the
fanout padding flexibility P.sub.F(i) is the difference between its
current hold slack H(i) and the minimum updated hold edge slack
over all fanout edges when each fanout is padded with the maximum
allowable value.
[0049] By the cited equations, the fanout padding flexibility
P.sub.F(i) is thus calculated from primary outputs toward primary
inputs. From the case shown in FIG. 3A and upon the cited
equations, the parameters are obtained as follows:
P.sub.F(o1)=0.0, P.sub.F(FF2)=0.0;
P.sub.F(1)=min{0, (-0.3+0.0+0.0)}-(-0. 3)=0.0;
H'(1)=-0.3, S'(1)=0.4;
P.sub.F(2)=min{0, (-0.2+0.0+0.0), (-0.3+0.0+0.3)}-(-0.3)=0.1;
H'(2)=min{(-0.3+0.0+0.3), (-0.2+0.0+0.0)}=-0.2;
S'(2)=min{(0.4-0.0-0.3), (0.3-0.0-0.0)}=0.1;
P.sub.F(3)=min{(-0.3+0.0+0.3), 0.0}-(-0.3)=0.3;
H'(3)=min{(-0.3+0.0+0.3)}=0.0; and
S'(3)=min{(1.0-0.0-0.3)}=0.7.
[0050] Upon the cited equations, the fanout padding flexibility
P.sub.F(i) can be checked as follows:
[0051] If |min{0, H(i)}|>P.sub.F(i), g.sub.i .di-elect cons.PI,
where PI stands for primary input, the hold violations cannot be
resolved by padding gates; and if S(i, j)<|min{0, H(i, j)}|,
e(i, j).di-elect cons. E, the hold violations cannot be resolved by
padding wires.
[0052] The padding value decision is based on the fanout padding
flexibility P.sub.F(i) of a gate to calculate a padding value P(i)
of the gate. After the fanout padding flexibility P.sub.F(i) is
calculated with a global view, the padding value is decided
accordingly. The padding value of each hold violating gate g.sub.i
is derived in the topological order. For each hold violating gate
g.sub.i, the fanout padding flexibility can be considered as the
maximum allowable delay padded on its fanout cone. Thus, the hold
violating gate g.sub.i only needs to be padded to fix the remaining
negative hold slack, i.e., the difference between the safe padding
value and the fanout padding flexibility P.sub.F(i). Upon the cited
equations, the padding value of the gate g.sub.i is expressed as
follows:
P(i)=max{P.sub.saf(i)-P.sub.F(i), 0}.
[0053] The parameter P.sub.saf(i) represents the safe padding value
after the fanin gates of a gate g.sub.i are padded. When the
padding value of each gate g.sub.i is decided, the increased delay
affects the arrival time of its fanout gates. Therefore, the fanout
edge slack of the padding gate is updated accordingly. The updated
fanout edge slack is expressed as follows:
S(i, j)=R(i, j)-A(i)-P(i),
H(i, j)=P(i)+a(i)-r(i, j).
[0054] After updating the fanout edge slacks of each padding gate
g.sub.i, the setup and hold node slacks of its fanout gates are
also updated.
[0055] FIGS. 6A and 6B are schematic charts of applying padding
values to a placed and routed design according to the invention.
FIG. 6A gives an example of padding value decision, when assuming
P.sub.max(2)=0.5, P.sub.max(3)=0.4, P.sub.max(1)=0.4, respectively.
Based on the fanout padding flexibility P.sub.F(i), the parameters
are obtained as follows:
P.sub.saf(2)=min{0.3, 1-0.31, 0.5}=0.3, P(2)=, 0.3-0.1=0.2;
S(2, 1)=1.1-0.7-0.2=0.2, H(2, 1)=0.2+0.1-0.4=-0.1;
P.sub.saf(3)=min{0.3, 1-0.31, 0.4}=0.3, P(3)=0.3-0.3=0.0;
S(3, 1)=1.1-0.1-0.0=1.0, H(3,1)=0.0+0.1-0.4=-0.3;
S(1)=min{1.0, 0.2}=0.2, H(1)=min{-0.3, -0.1}=-0.3;and
P.sub.saf(1)=min{0.2, 1-0.31, 0.4}=0.2, P(1)=0.2-0.0=0.2.
[0056] After the padding value decision, it is found from FIG. 6A
that the short path from the gate g.sub.3 to the gate g.sub.1 still
has a negative hold slack, -0.1, because of the over-estimated
fanout padding flexibility P.sub.F(i). This short path can be
resolved by applying another iteration of fanout padding value
calculation/flexibility checking plus padding value decision, and
the obtained padding values are accumulated to have the result as
shown in FIG. 6B, where all short paths are resolved. The fanout
padding flexibility calculation/flexibility checking step and the
padding value decision step are repeated until all hold violations
are resolved or further improved. Next, the improvement
determination step determines whether all hold violations of the
short paths of each gate in the placed and routed design are
resolved or no more violation is eliminated. When any violation is
not resolved or eliminated, the procedure returns to the fanout
padding flexibility calculation/flexibility checking step.
[0057] The invention intents to further reduce the total padding
delay on the gates and resolve unfixed hold violations by padding
wires, thereby increasing the delay.
[0058] In the padding value decision step, the padding locations
are selected as close to primary outputs PO as possible. For a
circuit with forked short paths, the total padding value is
increased if the padding location is not determined on the gate
where two or more short paths fork. As shown in FIG. 6A, the total
padding delay is 0.5 according to the cited calculation. However,
while the gate g.sub.4 has forked paths, the total padding delay
can be further reduced to 0.4 by changing the padding values and
locations as shown in FIG. 6B.
[0059] The invention intents to further reduce the padding value by
pushing the padding values toward the gates where more short paths
fork. When the improvement determination step determines that all
hold violations of the short paths of each gate in the placed and
routed design are resolved or no more violation is eliminated, the
padding value refinement step is based on a reverse topological
order to calculate the refined padding value of a gate in the
placed and routed design in order to further reduce the padding
value of the gate.
[0060] To achieve this, a reverse padding value P.sub.rev(i) for
the gate g.sub.i is defined as follows:
P rev ( i ) = { P ( i ) , if g i has only one hold violating fanin
; 0 , otherwise . ##EQU00003##
The reverse padding value P.sub.rev(i) of the gate g.sub.i is to
record how much padding is able to be propagated backward to its
fanin gate. To avoid propagating padding values to jointed paths,
assume that the gate g.sub.i has only one fanin with a hold
violation. When the hold edge slack is smaller than the padding
value of the gate g it indicates that a fanin of the gate g.sub.i
has a hold violation. In this case, the original hold violations
can be shown from the updated result after the padding.
[0061] Further, an added safe padding value P.sub.add(i) of the
gate g.sub.i is defined as follows:
P.sub.add(i)=min{S(i), P.sub.max(i)-P(i)}.
[0062] The added safe padding value P.sub.add(i) of the gate
g.sub.i is to record how much padding is able to be added under the
setup constraints and the maximum padding delay P.sub.max(i). The
refined padding value P.sub.ref(i) of the gate g.sub.i is expressed
as follows:
P.sub.ref(i)=P(i)+min{P.sub.add(i), min.sub.j{P.sub.rev(j)|H(i,
j)<P(i)}.
[0063] Based on the above definitions, the refined padding values
are calculated in the reverse topological order, and thus the total
padding delay can be further reduced.
[0064] In case of insufficient setup slacks or maximum output
capacitance constraints, the hold violations cannot be fully
cleaned by the padding gates. In this case, after the above
refinement, the invention further applies padding wires to thereby
resolve the remaining hold violations. Namely, the padding value
refinement further includes a wire padding value step.
[0065] The wire padding value step calculates a wire padding value
for a wire e(i, j), so as to further reduce the padding values of
each gate/wire in the placed and routed design. The wire padding
value P(i, j) is expressed as follows:
P(i, j)=min{S(i, j), |min{0, H(i, j)}|}.
[0066] The wire padding value P(i, j) is determined in the
topological order. According to the timing library, the final
padding delay of each gate/wire is converted to an amount of
padding load or padding buffers.
[0067] The load/buffer allocation step includes a finding spare
cell candidate step, a spare cell selection step; and a dummy metal
allocation step.
[0068] To achieve the padding values generated in the padding value
decision step, the load/buffer allocation step is divided into two
stages of coarse-grained delay padding and fine-grained delay
padding.
[0069] The delay for each cell can be found by converting the
capacitance of the cell obtained from the cell library. Since the
available cell capacitances/delays are discrete for a given cell
library, spare cells may not match the required padding load/buffer
for a padding gate/wire. Therefore, the coarse-grained padding is
done by spare cells, and the fine-grained delay padding is done by
dummy metal insertion.
[0070] The finding spare cell candidate step generates spare cell
candidates for each padding gate/wire in the placed and routed
design. For each padding gate, the available spare cells located
within the bounding box of its fanout net are programmed as the
available resource for a padding gate. FIG. 7 is a schematic chart
of available spare cells within a bounding box according to the
invention. As shown in FIG. 7, the available spare cells of the
padding gate g.sub.2 are s.sub.1, s.sub.2, and s.sub.3 while that
of the wire between the gates g.sub.2 and g.sub.3 is s.sub.2. Next,
how to pad the gate/wire by the spare cells is decided. The amount
of delay offered by the spare cells and related rewiring needs to
be as close to the determined padding delay for each gate as
possible but does not exceed the determined padding value, so as to
avoid the timing violations.
[0071] The invention reduces the task of finding suitable spare
cell candidates for a single padding gate/wire to the subset sum
problem, which can optimally be solved by dynamic programming. The
step size of the dynamic programming is selected to keep a balance
between the precision and the efficiency. For example, as shown in
FIG. 7, the assigned padding delay of a padding gate g.sub.2 is
0.25, and its available spare cells are s.sub.1, s.sub.2, and
s.sub.3. FIG. 8 lists the dynamic programming table for the subset
sum problem, where the step size used herein is 0.05. It is seen
that the combination of s.sub.2 and s.sub.3 is the optimal at the
padding delay of 0.25. Accordingly, the spare cells s.sub.2 and
s.sub.3 are recorded as the spare cell candidates of g.sub.2.
Similarly, the spare cell candidates for a padding wire can be
extracted.
[0072] However, the subset sum solutions for different padding
gates/wires may compete for the same spare cell. FIG. 9 is a
schematic chart of a spare cell competition according to the
invention. As shown in FIG. 9, both g.sub.1 and g.sub.2 desire to
be padded by s.sub.3. To deal with the resource competition
problem, multiple subset sum solutions within a user-defined
tolerance are recorded as the spare cell candidates. As shown in
FIG. 8, if the padding value is 0.25 and the tolerance is 0.05,
both {s.sub.1} and {s.sub.2, s.sub.3} are recorded as the spare
cell candidates. Next, it is determined to assign which spare cells
for each padding gate/wire.
[0073] The spare cell selection step assigns the best or optimal
subset sum solution to each padding gate/wire to completely pad the
short paths in the placed and routed design.
[0074] Since the subset sum solutions for different padding
gates/wires may compete for the same spare cell, there is a
resource competition problem among the spare cells. Therefore,
several sets of spare cell candidates are recorded for each padding
gate/wire. The spare cell selection step determines the spare cells
for each padding gate/wire. The spare cell selection problem is
NP-hard, which can be reduced from the set packing problem. To do
it efficiently, each padding gate/wire is first assigned to its
best subset sum solution. If there are conflicts, the conflicted
padding gates/wires and their multiple subset sum solutions are
extracted. The conflicted padding gates/wires are sorted in an
ascending order of the number of their recorded subset sum
solutions. Each gate is assigned to their best and available set of
spare cell candidates in the sorted order. FIG. 10 is a schematic
chart of best or optimal selections between padding gates/wires and
spare cells according to the invention. As shown in FIG. 10, the
gate g.sub.1 corresponds to the spare cell {s.sub.4}, the gate
g.sub.2 corresponds to the spare cells {s.sub.2, s.sub.3}, and the
gate g.sub.3 corresponds to the spare cells {s.sub.5, s.sub.6}.
[0075] At the above coarse-grained delay padding step, the spare
cells are selected for each padding gate/wire. If the selected
spare cells cannot match the required padding delay, the remaining
padding is converted into an amount of capacitance, and fixed by
the dummy metal insertion during the fine-grained padding step.
Thus, the dummy metal allocation step can use the dummy metal
insertion to completely pad the short paths in the placed and
routed design.
[0076] The amount of available dummy metal of each padding gate is
decided by the unoccupied routing resource within the bounding box
of its fanout net. As their corresponding bounding boxes overlap,
different padding gates/wires may compete for the same metal
resource. FIG. 11 is a schematic diagram of a dummy metal of
conflicted padding gates/wires according to the invention. The
dummy metal in independent bounding boxes is defined as the
independent virtual metal, and otherwise defined as the dependent
virtual metal. The dummy metal in the independent bounding boxes
are first assigned for the padding gates/wires. If there still are
padding gates/wires with unfixed padding capacitance, a maximum
flow network process is used to assign the dependent virtual
metal.
[0077] FIG. 12 is a schematic chart of a maximum flow network
process according to the invention. The maximum flow network
process includes a source node s and a sink node t. Nodes g.sub.i
and d.sub.i corresponding to each padding gate/wire indicate the
dependent virtual metal. An edge connects the node s to each node
g.sub.i, and its edge capacity is the remaining padding capacitance
of the node g.sub.i. An edge connects each node d.sub.i to the node
t, and its edge capacity is the amount of capacitance of the node
d.sub.i. If the bounding box of the node g.sub.i covers the node
d.sub.i, the edge capacity of an edge connecting between the nodes
g.sub.i and the nodes d.sub.i is infinite. As shown in FIG. 11,
after assigning the independent dummy metal, there are the gates
g.sub.1, g.sub.2, and g.sub.3 with remaining unfixed padding
capacitances 0.15, 0.2, and 0.1 respectively. The dummy metal of
overlapping regions can offer capacitances 0.25 and 0.2. The
corresponding flow network and the maximum flow are shown in FIG.
12. Based on the obtained flow, the dummy metal can be accordingly
assigned to fix the remaining padding capacitance. If there are
still unfixed padding capacitances after the dummy metal insertion,
it means that the resource is limited, and in this case the
procedure returns to the padding value determination step to adjust
the padding values not exceeding the load of a gate with fewer
resources.
[0078] FIG. 13 is a table of benchmark statistics according to the
invention, where "Circuit" indicates the circuit name, "#Gate"
indicates the combinational logic count, "#FF" indicates the number
of flip-flops, "#SFF" indicates the number of timing suspicious
flip-flops, "Conservative clock period (ns)" indicates the clock
period considering a timing guardband, and "THS" indicates the
total negative hold slack contributed from suspicious flip-flops.
Each circuit is synthesized, placed, and routed based on 55-nm
technology using state-of-the-art commercial tools provided by
Synopsys and Cadence. The tools are also used to verify the circuit
timing. The invention assumes that S.sub.th=75% and H.sub.th=25%,
which are typical settings in modern designs.
[0079] FIGS. 14A and 14B are a comparison table of padding values
for the invention and the prior art, where "Padding delay"
indicates the total assigned padding delay including all gates and
wires, "LP" means "Linear Programming" proposed in N. V. Shenoy et
al. "Minimum padding to satisfy short path constraints." the ICCAD,
pp. 156-161, 1993, which is implemented using ILOG CPLEX Optimizer
provided by IBM, "Greedy 1" indicates to greedily pad from the gate
with the largest setup slack proposed by Y. Sun et al. in U.S. Pat.
No. 7,278,126, and "Greedy 2" indicates to greedily pad from the
gate passed by most hold violating paths. As shown in FIGS. 14A and
14B, it is known that, because of the global view, the method can
clean all hold violations of each circuit. The linear programming
(LP) method is time consuming for large-scale circuits. Greedy 1
and Greedy 2 may either fail to clean all hold violations or suffer
from long runtime due to iterative computation.
[0080] FIG. 15 is a comparison table of negative setup
slack/negative hold slack of the invention and the prior art, where
the load/buffer allocation method is compared with the method
proposed by N. V. Shenoy et al. As mentioned above, even the method
proposed by N. V. Shenoy et al. finds the optimal padding, the
directly mapped results may still incur hold violations. In
contrast, based on two stages of the coarse-grained and the
fine-grained load/buffer allocations, the invention can
successfully achieve the padding values assigned by the padding
value determination step for all cases. The combination of the
spare cells and the dummy metal provides the flexibility to the
capacitance allocation, and thus the dummy metal plays an important
role in solving the discrete buffer delay problem.
[0081] In view of the foregoing, it is known that the invention is
provided with the contributions as follows:
[0082] (1) Finding the padding values with a global view: The
greedy heuristics proposed by the prior arts may fail to fix all
hold violations due to the local views. However, the invention
computes the padding flexibility of the fanout cone of each gate
and accordingly determines the padding value for each gate with the
global view.
[0083] (2) Coarse-grained and fine-grained delay padding: Since the
amount of delay offered by a cell library is discrete, the
coarse-grained delay padding is done using the spare cells, and the
fine-grained delay padding is done using the dummy metal insertion
because the dummy metal can be tuned as needs.
[0084] (3) Short path padding at the post-layout stage: Because the
prior art determines the padding values at the logic re-synthesis
stage, its timing report is not somewhat correct. In addition,
because the available resource of padding is uncertain at the early
stages, the invention realizes the delay padding at the post-layer
stage.
[0085] As cited, based on the above observation, the invention
first tries to reduce the padding values and determine the padding
locations in the padding value determination stage, then allocates
the load/buffers in the load/buffer allocation stage in order to
satisfy the padding values determined in the padding value
determination stage. Furthermore, in the padding value
determination stage, the invention computes the padding flexibility
of the fanout cone of each gate and accordingly determines the
padding value for each gate with the global view. In the
load/buffer allocation stage, to achieve the padding value
determined in the padding value determination stage, the invention
proposes the coarse-grained delay padding and the fine-grained
delay padding. Since the delay offered by the cell library is
discrete, the coarse-grained delay padding is done using the spare
cells, and the fine-grained delay padding for the remainders is
done using the dummy metal insertion because the dummy metal offers
an abundant resource of capacitance and can be tuned.
[0086] Although the present invention has been explained in
relation to its preferred embodiment, it is to be understood that
many other possible modifications and variations can be made
without departing from the spirit and scope of the invention as
hereinafter claimed.
* * * * *