U.S. patent application number 14/286581 was filed with the patent office on 2014-09-11 for process for structuring silicon.
This patent application is currently assigned to BANDGAP ENGINEERING, INC.. The applicant listed for this patent is Bandgap Engineering, Inc.. Invention is credited to Marcie R. Black, Brent A. Buchine, Faris Modawar.
Application Number | 20140252564 14/286581 |
Document ID | / |
Family ID | 42099162 |
Filed Date | 2014-09-11 |
United States Patent
Application |
20140252564 |
Kind Code |
A1 |
Buchine; Brent A. ; et
al. |
September 11, 2014 |
Process for Structuring Silicon
Abstract
A process for etching a silicon-containing substrate to form
structures is provided. In the process, a metal is deposited and
patterned onto a silicon-containing substrate (commonly one with a
resistivity above 1-10 ohm-cm) in such a way that the metal is
present and touches silicon where etching is desired and is blocked
from touching silicon or not present elsewhere. The metallized
substrate is submerged into an etchant aqueous solution comprising
about 4 to about 49 weight percent HF and an oxidizing agent such
as about 0.5 to about 30 weight percent H.sub.2O.sub.2, thus
producing a metallized substrate with one or more trenches. A
second silicon etch is optionally employed to remove nanowires
inside the one or more trenches.
Inventors: |
Buchine; Brent A.;
(Watertown, MA) ; Modawar; Faris; (Orem, UT)
; Black; Marcie R.; (Lincoln, MA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Bandgap Engineering, Inc. |
Salem |
NH |
US |
|
|
Assignee: |
BANDGAP ENGINEERING, INC.
Salem
NH
|
Family ID: |
42099162 |
Appl. No.: |
14/286581 |
Filed: |
May 23, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12576490 |
Oct 9, 2009 |
8734659 |
|
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14286581 |
|
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61195872 |
Oct 9, 2008 |
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61142608 |
Jan 5, 2009 |
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Current U.S.
Class: |
257/622 |
Current CPC
Class: |
B81C 1/00619 20130101;
H01L 29/34 20130101; H01L 21/30604 20130101; Y10T 428/24479
20150115; Y10T 428/2462 20150115 |
Class at
Publication: |
257/622 |
International
Class: |
H01L 29/34 20060101
H01L029/34 |
Claims
1. A silicon substrate having an etched pattern which comprises
features that have an aspect ratio larger than about 80:1, smooth
sidewalls without a zigzag pattern, and features arranged along
more than one crystallographic direction.
2. A substrate as described in claim 1, wherein a bottom of the
etched pattern is coated with silver metal.
3. A substrate as described in claim 1, wherein the minimum
dimension of the features in the etched pattern is greater than
about 100 nm.
4. A substrate as described in claim 1, wherein the minimum
dimension of the features in the etched pattern is less than about
100 nm.
5. A substrate as described in claim 4, wherein either a width or a
length of the etched pattern is below the coherence length of
electrons or holes in silicon.
6. A substrate as described in claim 4, wherein either a width or a
length of the etched pattern is below the de Broglie wavelength of
electrons or holes in silicon.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 12/576,490, filed Oct. 9, 2009, issuing as U.S. Pat. No.
8,734,659, and claims priority to U.S. Provisional Patent
Applications Nos. 61/195,872, filed Oct. 9, 2008, and 61/142,608,
filed Jan. 5, 2009. These applications are incorporated by
reference in their entireties.
BACKGROUND OF THE INVENTION
[0002] The ability to structure and pattern silicon is important
for many applications. Many devices require bulk micromachining,
which defines structures by selectively etching deep inside the
substrate. The process is enabled by modern photolithography in
combination with tools and techniques that have been developed
specifically for deep etching into silicon. Relevant information
regarding silicon fabrication processes known to those of skill in
the art can be found, for example, in Sami Franssila, Introduction
to Microfabrication (John Wiley & Sons, 2004), and the
references cited there.
[0003] Some of the bulk micromachining processes known in the art
are dry and some are wet. For example, reactive ion etching (RIE)
and inductively coupled plasma (ICP) are two dry techniques that
utilize a combination of reactive ions and kinetically charged
species to "mill" into a material and define high aspect ratio
features. For all these methods, the depth of the trenches is
limited by the slight taper in the sidewalls after the etch. The
slight taper causes the trench to get narrower as the silicon wafer
is etched deeper. The taper limits the resulting aspect ratio
(which is the ratio of the maximum depth to the trench width), and
effectively either limits the depth of the features or the minimum
feature size. For deep RIE processes, the aspect ratios can be
slightly better than 20:1.
[0004] Much attention has been devoted to optimizing and reducing
the slight taper in RIE processes. Companies have developed methods
for operating these tools in specific ways to decrease the taper,
increase the aspect ratio, and ease the tradeoff between the
maximum obtainable depth and minimum feature size; for example the
Bosch process used by Oxford. These processes do improve the aspect
ratio, however designers are still limited by the aspect ratio. In
addition, most of the processes to improve the aspect ratio also
result in rough sidewalls, which is non-ideal for many
applications. Furthermore, RIE is expensive, low throughput, and
requires a high vacuum to operate.
[0005] Wet processing is also used to etch high aspect ratio
features into silicon. Potassium hydroxide (KOH) and
tetramethylammonium hydroxide (TMAH) are two chemicals typically
utilized in an aqueous environment to etch and structure silicon.
This process takes advantage of the fact that silicon has a
well-defined crystal structure and certain crystal planes are more
susceptible to etching. The etch results in pits that have angled
walls, with the angle being a function of the crystal orientation
of the substrate. This technique does not require high vacuum
systems thus it is less expensive than the dry processing
techniques described above. However, the crystal-dependent nature
of the process requires additional consideration for wafer
orientation and device design making processing less
straightforward. In addition, although these wet etches are highly
anisotropic and have a preferred etch direction, they still do etch
in the non-preferred directions. Thus, although these processes
obtain high aspect ratio features, they are also limited by the
sidewall taper. In general wet techniques have a larger aspect
ratio and smoother sidewalls than dry techniques, but require fine
alignment of the features with the crystallographic orientation of
the wafer. In addition, since these techniques are limited to
specific crystallographic directions, only rectangles and lines
(and not arbitrary shapes in the x-y plane) can be patterned using
this technique.
[0006] There is thus a need for a process which allows etching of
silicon at high aspect ratios but which improves on existing
processes such as reactive ion etching.
SUMMARY OF THE INVENTION
[0007] A process for etching a silicon-containing substrate to form
structures is provided. In the process, a metal is deposited and
patterned onto a silicon-containing substrate (commonly one with a
resistivity above 1-10 ohm-cm) in such a way that the metal is
present and touches silicon where etching is desired and is blocked
from touching silicon or not present elsewhere. The metallized
substrate is submerged into an etchant aqueous solution comprising
about 4 to about 49 weight percent HF and an oxidizing agent such
as about 0.5 to about 30 weight percent H.sub.2O.sub.2, thus
producing a metallized substrate with one or more trenches. A
second silicon etch is optionally employed to remove nanowires
inside the one or more trenches.
BRIEF DESCRIPTION OF THE FIGURES
[0008] FIG. 1 depicts silicon etching carried out by a
silver-enhanced etching in HF in a process of this invention.
[0009] FIG. 2 depicts the sample in FIG. 1 after 3 minutes in 45%
KOH heated to 50.degree. C.
[0010] FIG. 3 depicts an example of patterning micron-sized devices
with the silver-enhanced etching in HF technique.
[0011] FIG. 4 depicts a setup for using bubbling oxygen as an
oxidizing agent.
DETAILED DESCRIPTION OF THE INVENTION
[0012] Before describing the present invention in detail, it is to
be understood that this invention is not limited to specific
solvents, materials, or device structures, as such may vary. It is
also to be understood that the terminology used herein is for the
purpose of describing particular embodiments only, and is not
intended to be limiting.
[0013] Where a range of values is provided, it is intended that
each intervening value between the upper and lower limit of that
range and any other stated or intervening value in that stated
range is encompassed within the disclosure. For example, if a range
of 1 .mu.m to 8 .mu.m is stated, it is intended that 2 .mu.m, 3
.mu.m, 4 .mu.m, 5 .mu.m, 6 .mu.m, and 7 .mu.m are also disclosed,
as well as the range of values greater than or equal to 1 .mu.m and
the range of values less than or equal to 8 .mu.m.
[0014] This patent application describes a method of etching into
silicon and the structures obtained by this etching process. This
method of etching into silicon can provide deep trenches, with
little, if any, sidewall taper and minimal surface roughness. In
addition, the technique, unlike other high aspect ratio silicon
etch technologies, does not require expensive tools, a high vacuum,
or processing conditions that are expensive to obtain.
[0015] This application discloses a new approach of etching deep
features into silicon that incorporates the advantage of patterning
arbitrary shapes in the x-y plane which are uniform in the
z-direction obtained by dry processing such as RIE, as well as the
advantages of the low cost, high throughput, high aspect ratios,
and low surface roughness of solution based/wet etching. This novel
technique utilizes metal (for example silver) for etching silicon
in a bath of hydrofluoric acid and hydrogen peroxide with a range
of concentrations.
[0016] The invention described here builds on recent work
demonstrated for the fabrication of silicon nanowires using a
solution made up of a metal salt and a strong acid (typically
AgNO.sub.3 and HF). (See reference (a) below.) By controlling the
concentrations of each component in solution, silicon can be etched
normal to the plane of the wafer to form silicon nanowires. (See
reference (b) below.) The mechanism by which etching occurs is not
clearly understood. However the technique may be practiced using
H.sub.2O.sub.2 in the chemical bath and utilizing Ag metal on top
of arrays of silicon dioxide or iron oxide nanoparticles or
polystyrene beads (see references (c) and (d) below). Ag initiates
the etching reaction, so wherever a sufficiently thin (for example,
less than about 30 nm or 50 nm) film of Ag is in contact with
silicon, the silicon is etched. The silicon dioxide or iron oxide
nanoparticles act as a barrier between the Ag and Si and thus the
size of the nanoparticles define the nanowire diameter as the
silicon is etched around the nanowire. This specific technique is
limited in that only silicon nanowire arrays were fabricated.
[0017] In an aspect of this invention, techniques related to the
prior art nanowire fabrication techniques are employed to produce
structures other than nanowire arrays. Instead of using
nanoparticles to define the nanowire dimensions, other techniques
of determining where the Ag touches the silicon are employed. By
extending the patterning process, features such as lines, squares,
or any arbitrary 2-D shape can be defined on the silicon surface.
Thus as long as there are regions where the metal and Si are in
contact and regions where they are not in contact, an arbitrary
shape that is uniform in the z-direction into the wafer can be
etched into the silicon sample. Processes of this invention may add
more control over the shape etched into the silicon compared to the
nanowire array work which could only control the density, wire
diameter, and wire length. In both the nanowire array work and this
invention, the depth of the feature may be controlled by the sample
etch time.
[0018] Unlike KOH wet etches, the resulting features are etched
normal to the wafer plane regardless of the orientation and doping
concentration of the silicon substrate. Thus device design does not
need to consider crystallographic orientation. The zigzag pattern
visible in sidewalls as a result of other etching processes is
generally not observed here.
[0019] In an aspect of the invention, one employs as an etchant an
aqueous solution comprising about 4 to about 49 weight percent HF
and about 0.5 to about 30 weight percent H.sub.2O.sub.2. The
concentration of HF can vary from full strength (49 wt %) to very
nominal concentrations. The length of the resulting nanostructure
may increase as HF concentration is reduced. The solution may
comprise, for example, about 2 to about 25 weight percent HF, or
about 4 to about 15 weight percent HF, or about 6 to about 12
weight percent HF. The solution may comprise, for example, about
0.5 to about 15 weight percent H.sub.2O.sub.2, about 1 to about 10
weight percent H.sub.2O.sub.2, or about 1 to about 5 weight percent
H.sub.2O.sub.2, or about 1.25 to about 2 weight percent
H.sub.2O.sub.2. In place of H.sub.2O.sub.2 other oxidizing agents
may be employed, for example mineral acids such as nitric acid. An
oxidizing agent (also called an oxidant or oxidizer) is a substance
that readily transfers oxygen atoms or tends to gain electrons in a
redox chemical reaction. One such oxidizer is pure oxygen, which
may be introduced by bubbling oxygen through the HF. Other
oxidizers include: ozone, chlorine, iodine, ammonium perchlorate,
ammonium permanganate, barium peroxide, bromine, calcium chlorate,
calcium hypochlorite, chlorine trifluoride, chromic acid, chromium
trioxide (chromic anhydride), peroxides such as hydrogen peroxide,
magnesium peroxide, dibenzoyl peroxide and sodium peroxide,
dinitrogen trioxide, fluorine, perchloric acid, potassium bromate,
potassium chlorate, potassium peroxide, propyl nitrate, sodium
chlorate, sodium chlorite, and sodium perchlorate.
[0020] It may be desirable to use a less reactive alternative
oxidizer used in place of H.sub.2O.sub.2. Comparative reactivity
towards the metal deposited (e.g., silver), silicon, or silicon
dioxide may be of interest in the selection of an oxidizer.
Reactivity may be measured, for example, by the extent to which the
reaction goes forward in a particular period of time, or by
determining a reaction rate as discussed in books on physical
chemistry and chemical kinetics. (See, e.g., Peter W. Atkins &
Julio de Paula, Atkins' Physical Chemistry (8th ed. 2006),
especially chapters 22 and 23.) Measurements may be made in
conditions such as temperature and pressure similar to those of the
etching process.
[0021] The minimum dimensions achievable by processes of the
invention may be, for example, about 50 nm, about 100 nm, about 200
nm, or about 500 nm. A more precise patterning process for the
metal and/or barrier may produce smaller minimum dimensions, but as
is known to those of skill in the art, greater patterning precision
often involves more costly processes.
[0022] The largest possible aspect ratio obtained by processes of
the invention is very large. The aspect ratio may be, for example,
at least about 40:1, about 60:1, about 80:1, about 100:1, or about
500:1. Etching of the silicon will normally commence only at the
metal/Si interface resulting in a limited amount of undercut
underneath the mask due to the lack of metal on the sidewalls of
features during the etching process. Since Ag should be in physical
contact with the silicon to effect etching and Ag is a solid, the
size of the trench remains constant regardless of how deep the
trench is etched. The etch rate of silicon wafer without silver in
the HF/H.sub.2O.sub.2 is minimal. This etch rate compared to the
metal enhanced etch rate is what normally determines the minimum
taper, and thus the maximum aspect ratio obtained by this process.
If a slight taper is desired, a higher HF concentration can be
used. In this case as the etch progresses the HF may attack the
metal, causing it to flake off and become smaller thus decreasing
the size of the etched feature.
[0023] A barrier can be used to separate the metal from the silicon
surface in parts of the wafer. The barrier can be defined by
traditional lithographic processing in order to pattern a wide
variety of geometrical shapes. The utilization of any patterning
process (for example, soft-lithography including surface stamping,
screen-printing, dip-pen, SAMs, e-beam, or FIB) is sufficient for
defining the barrier or localizing the metal layer.
[0024] One possible method for practicing this invention involves
the use of photolithography to pattern a surface of a silicon wafer
with negative photosensitive resist.
[0025] A wide variety of barrier layers can be used other than a
simple positive or negative photoresist. It is desirable to pick a
barrier material that is non-reactive in the HF/H.sub.2O.sub.2
etching solution (photoresist, polymer, ceramic, organic,
inorganic, metallic, non-metallic, in a solid, liquid or gas (air)
phase). A bare silicon surface free of material can also be
effective; however, since HF can etch silicon, although at a slow
rate, the best results are commonly obtained when a barrier is used
to isolate the metal from the Si. In addition, metal occasionally
redeposits on free surfaces that can speed up the reaction locally
and result in a non-uniform result or porous silicon. Thus, the
barrier layer not only protects the silicon from the metal enhanced
etching, but can also prevent the metal from dissolving in the
solution and redepositing elsewhere on the wafer.
[0026] Metals other than Ag can also be used to initiate the
reaction. For example, we have found that nickel, like silver,
enhances the etch rate of silicon in the solution.
[0027] The metal layer can be deposited in a variety of ways:
physical vapor deposition via sputtering, e-beam evaporation, or
thermal evaporation; electrochemically in a bath; or a foil can be
simply placed on the surface, much like in damascening. It is also
possible to initiate specific reaction chemistries in order to
create a metal (barrier) silicon interface. For example, FIB can be
used to reduce an organometallic precursor into Ag wherever an ion
beam reacts, or for example, metal-organic block co-polymers can be
spin coated and reduced to metal.
[0028] Examples of the resulting structures are shown in FIGS. 1
and 3 and described in Example 1 below. Smooth sidewalls with large
aspect ratios are observed. In the example shown, the maximum
aspect ratio is around 1:27. Higher aspect ratios may be achieved
by increasing the etch time.
[0029] The method described results in undesired nanowires in
regions where silver is touching the silicon. In some applications
such as stamps, the nanowires are desirable. However, since many
applications cannot tolerate the presence of such nanowires inside
the trenches, an etch in (for example) 45% KOH at 50.degree. C. may
be used to remove the nanowires. The resulting structure is shown
in FIG. 2.
[0030] Applications:
[0031] The ability of processes of the invention to etch deep
features into a silicon wafer with high aspect ratios, smooth
sidewalls, with a high throughput, and at low cost is useful for
many applications including in micro electro mechanical systems
(MEMs), optoelectronic, and electrochemical devices. Although the
largest benefits of this process are for applications that require
a high aspect ratio deep etching in silicon, the low cost and the
smooth sidewalls would also benefit areas which have less stringent
requirements for taper.
[0032] The most apparent application of this technology is MEMs,
where the aspect ratio limits the device design. One type of MEMs
work that requires deep etches and smooth sidewalls is RF MEMs.
Bulk micromachining of capacitively or piezoelectrically actuated
beams, etched and released from either silicon on insulator (SOI)
or bulk silicon wafers preferably employ near ideal geometries with
vertical sidewalls and minimal surface roughness. Some examples of
RF MEMs devices that would benefit from the processes disclosed
here are phase shifters and resonators. The resonant behavior of
these devices depends directly on geometry. Slight inconsistencies
in the result can cause a dramatic shift in performance. Hence,
sidewall roughness is important and has been also attributed to
non-ideal behavior in these devices. Since the etch described in
this application results in smooth sidewalls with deep etches, RF
MEMs made by this process are likely to be more predictable and
have closer to ideal behavior.
[0033] The processes disclosed here can also be used to fabricate
micro-fluidic channels in micro-fluidic devices. The field of micro
fluidics exploits fluid behavior at the microscale that differs
from the macroscale. Turbulent flow begins to display
characteristics more similar to a laminar flow and interesting
properties like energy dissipation, surface tension and fluidic
resistance begin to dominate fluid behavior. Micro-fluidics has
been key in the development of inkjet print heads, lab-on-a-chip
technology, micro-propulsion, and acoustic droplet ejection and has
even shown promise in the development of fuel cells and drug
delivery systems. Sidewall roughness can drastically alter the flow
behavior of micro fluidic channels and thus micro fluidics might
benefit from using the metal enhanced silicon etching described in
this provisional application.
[0034] The field of wave-guides and photonic crystals is another
area where geometry and roughness are a major challenge. Photonic
crystals are made up of periodic materials with varying dielectric
constants in an effort to affect the propagation of electromagnetic
waves much the same way that semiconductors affect the propagation
of electrons. One of the key difficulties is ensuring that the
structure has sufficient precision with regards to geometry and
that the surfaces are atomically smooth. This leads to very sharp
index of refraction contrasts in the material and prevents
scattering losses. Thus photonic bandgap materials require both
good control of processing with smooth interfaces and scalable
techniques that can be mass-produced. Hence, photonic bandgap
devices can benefit from the manufacturing methods described
here.
[0035] This technique can also be used as a process in the
manufacture of accelerometers, gyroscopes, mass-flow sensors,
pressure sensors, optical switches, optical displays, micro relays,
read-write heads, and RF components for cell phones, radar and
satellite communication.
[0036] In addition to the situation where the inventive process can
contribute to better device performance, the low cost nature of the
process would also be beneficial in areas which have less stringent
requirements for side-wall roughness and taper.
[0037] The following references are of interest in relation to this
application: (a) K. Peng, Z. Huang, J. Zhu, Advanced Materials, 16,
73-76, "Fabrication of Large-Area Silicon Nanowire p-n Junction
Diode Arrays." (b) K. Peng, J. Hu, Y. Yan, Y. Wu, H. Fang, Y. Xu,
S. Lee, and J. Zhu, Advanced Functional Materials, 16, 387-394,
"Fabrication of Single-Crystalline Silicon Nanowires by Scratching
a Silicon Surface With Catalytic Metal Particles." (c) U.S.
Provisional Patent Application No. 61/042,124. (d) Z. Huang, H.
Fang, J. Zhu, Advanced Materials, 19, 744-748 (2007), "Fabrication
of Silicon Nanowire Arrays with Controlled Diameter, Length, and
Density". (e) United States Published Patent Application No.
20070278476; (f) U.S. Provisional Patent Application Ser. No.
61/195,872, filed Oct. 9, 2008.
[0038] All patents, patent applications, and publications mentioned
herein are hereby incorporated by reference in their entireties.
However, where a patent, patent application, or publication
containing express definitions is incorporated by reference, those
express definitions should be understood to apply to the
incorporated patent, patent application, or publication in which
they are found, and not to the remainder of the text of this
application, in particular the claims of this application.
[0039] The following examples are put forth so as to provide those
of ordinary skill in the art with a complete disclosure and
description of how to implement the invention, and are not intended
to limit the scope of what the inventors regard as their invention.
Efforts have been made to ensure accuracy with respect to numbers
(e.g., amounts, temperature, etc.) but some errors and deviations
should be accounted for.
EXAMPLE 1
[0040] Positive 1813 Shipley photoresist was spun onto a clean 4''
(100) silicon wafer using a 2-step coating procedure. First, the
wafer was ramped to 500 RPM (100 RPM/sec) and held for 5 seconds in
order to spread the resist evenly across the wafer surface. Next,
the substrate was ramped to 4000 RPM (1000 RPM/sec) and held for 40
seconds in order to achieve a uniform resist thickness. The wafer
was then soft-baked for 2 minutes at 115.degree. C. on a hotplate
and allowed to cool for 5 minutes at room temperature on a metal
surface. Next, the resist was exposed on an MJB4 mask aligner at a
dose of 60 mJ/cm.sup.2 using a positive photomask. The open area in
the mask consisted of lines with 2 micron, 5 micron, 10 micron and
20 micron line widths. After the exposure was complete, the pattern
was developed using CD-30 developer by swirling for 40 sec. The
wafer was subsequently rinsed with deionized water and dried with
flowing N.sub.2.
[0041] After the pattern was inspected for defects on an optical
microscope, it was hard-baked on a hotplate at 150.degree. C. for
10 minutes and subsequently diced into 1 cm.sup.2 chips. A 40 nm
thin film of silver was then deposited onto an individual chip via
thermal evaporation. The chip was submerged into a solution
consisting of 8 wt % HF and 1.5 wt % H.sub.2O.sub.2 solution for
anywhere between 10-90 min. As a result, etching commenced normal
to the surface of the silicon in regions where silver and silicon
formed an interface; the final etch depth directly correlated with
the length of time the chip spent in the bath. Regions protected by
photoresist were thus prevented from being etched resulting in
features seen in FIGS. 1 and 3. The chip was removed from the
etching bath, rinsed with deionized water and blown dry with
N.sub.2. Next, the photoresist and silver was removed by soaking
the chip in acetone for a period of 15 minutes. In some cases
longer times were required due to the excessive hard-baking of the
resist. Any residual Ag that remained inside the trench was removed
using a "silver etchant" supplied by Transene Corporation with an
expected etch rate of 200 A/sec.
[0042] It can be seen from FIGS. 1 and 3 that a great deal of
"grass" formed inside the trench during the etch process. In order
to remove this, the sample was submerged into a bath of 45 wt % KOH
at 50.degree. C. for a period of 3 minutes. The final result can be
seen in FIG. 2.
EXAMPLE 2
[0043] A process similar to that of Example 1 is carried out.
However, the solution into which the chip is submerged is a aqueous
HF solution without H.sub.2O.sub.2. Before the chip is immersed,
O.sub.2 gas is flowed into the bath to create a vigorous bubbling
for a period of 10 minutes. Once the bath is seasoned, the samples
are submerged. At the completion of the etch, the samples are
removed and put into a dump-tank of flowing DI water and blown dry
with N.sub.2. A setup for O.sub.2 gas flow is depicted in FIG. 4.
At this point the remaining Ag on the surface can be removed with a
silver etchant, for example the etchant supplied by Transene
Corporation.
[0044] With the use of O.sub.2 gas rather than H.sub.2O.sub.2, the
formation of grass may be avoided.
[0045] Since the silicon etch rate is suppressed when grass is
inside the trenches, processes such as those using H.sub.2O.sub.2
that result in grass tend to have smoother sidewalls. In addition,
the more aggressive oxidizers in general etch faster than the less
aggressive oxidizers such as O.sub.2. Since the aspect ratios of
the etched features are commonly limited by the ratio of the bare
silicon etch rate to the metal enhanced etch rate, a decrease in
the metal enhanced etch rate would be expected generally to
decrease the maximum obtainable aspect ratio.
* * * * *