U.S. patent application number 14/250620 was filed with the patent office on 2014-08-07 for epitaxial substrate having nano-rugged surface and fabrication thereof.
The applicant listed for this patent is Jiunn-Yih CHYAN, Suz-Hua HO, Wen-Ching HSU, Jer-Liang YEH. Invention is credited to Jiunn-Yih CHYAN, Suz-Hua HO, Wen-Ching HSU, Jer-Liang YEH.
Application Number | 20140220301 14/250620 |
Document ID | / |
Family ID | 45467215 |
Filed Date | 2014-08-07 |
United States Patent
Application |
20140220301 |
Kind Code |
A1 |
CHYAN; Jiunn-Yih ; et
al. |
August 7, 2014 |
EPITAXIAL SUBSTRATE HAVING NANO-RUGGED SURFACE AND FABRICATION
THEREOF
Abstract
The invention provides an epitaxial substrate and fabrication
thereof. The epitaxial substrate according to the invention
includes a crystalline substrate. In particular, the crystalline
substrate has an epitaxial surface which is nano-rugged and
non-patterned. The epitaxial substrate according to the invention
thereon benefits a compound semiconductor material in growth of
epitaxy films with excellent quality. Moreover, the fabrication of
the epitaxial substrate according to the invention has advantages
of low cost and rapid production.
Inventors: |
CHYAN; Jiunn-Yih; (Hsinchu,
TW) ; YEH; Jer-Liang; (Hsinchu, TW) ; HSU;
Wen-Ching; (Hsinchu, TW) ; HO; Suz-Hua;
(Hsinchu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
CHYAN; Jiunn-Yih
YEH; Jer-Liang
HSU; Wen-Ching
HO; Suz-Hua |
Hsinchu
Hsinchu
Hsinchu
Hsinchu |
|
TW
TW
TW
TW |
|
|
Family ID: |
45467215 |
Appl. No.: |
14/250620 |
Filed: |
April 11, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13067710 |
Jun 22, 2011 |
|
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|
14250620 |
|
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Current U.S.
Class: |
428/141 |
Current CPC
Class: |
B82Y 40/00 20130101;
B82Y 30/00 20130101; H01L 21/0243 20130101; H01L 21/02658 20130101;
H01L 21/3065 20130101; C30B 29/60 20130101; H01L 21/30604 20130101;
H01L 21/02521 20130101; Y10T 428/24355 20150115; H01L 21/3086
20130101; H01L 21/0237 20130101 |
Class at
Publication: |
428/141 |
International
Class: |
C30B 29/60 20060101
C30B029/60 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 15, 2010 |
TW |
099123227 |
Claims
1. An epitaxial substrate, comprising: a crystalline substrate
having an epitaxial surface which is nano-rugged and
non-patterned.
2. The epitaxial substrate of claim 1, wherein the crystalline
substrate is formed of one selected from the group consisting of
sapphire, SiC, GaN, GaAs, ZnO, Si, ScAlMgO.sub.4,
SrCu.sub.2O.sub.2, YSZ(Yttria-Stabilized Zirconia), LiAlO.sub.2,
LiGaO.sub.2, Li.sub.2SiO.sub.3, LiGeO.sub.3, NaAlO.sub.2,
NaGaO.sub.2, Na.sub.2GeO.sub.3, Na.sub.2SiO.sub.3,
Li.sub.3PO.sub.4, Li.sub.3AsO.sub.4, Li.sub.3VO.sub.4,
Li.sub.2MgGeO.sub.4, Li.sub.2ZnGeO.sub.4, Li.sub.2CdGeO.sub.4,
Li.sub.2MgSiO.sub.4, Li.sub.2ZnSiO.sub.4, Li.sub.2CdSiO.sub.4,
Na.sub.2MgGeO.sub.4, Na.sub.2ZnGeO.sub.4, and
Na.sub.2ZnSiO.sub.4.
3. The epitaxial substrate of claim 2, wherein the epitaxial
surface of the crystalline substrate has an average surface
roughness (Ra) in a range from 100 nm to 400 nm.
4. The epitaxial substrate of claim 2, wherein the epitaxial
surface of the crystalline substrate has a mean peak-to-valley
height (Rz) in a range from 50 .mu.m to 350 .mu.m.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This utility application is a divisional application of U.S.
Ser. No. 13/067,710 filed on Jun. 22, 2011 which claims priority to
Taiwan Application Serial Number 099123227, filed on Jul. 15,
2010.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to an epitaxial substrate and
fabrication thereof, and more in particular, to an epitaxial
substrate having a nano-rugged and non-patterned epitaxial surface
and fabrication thereof
[0004] 2. Description of the Prior Art
[0005] Compound semiconductor materials, such as GaN, AlGaN,
AlInGaN, and other III-V group compounds, or CdTe, ZnO, ZnS, and
other II-VI group compounds, have been used for a wide variety of
substrates of microelectronic devices including transistors, field
emission devices, and optoelectronic devices, but not limiting the
above described.
[0006] Taking a GaN-based microelectronic device as an example, a
major problem in manufacture is that the GaN semiconductor layer
manufactured must have low defect density to ensure the performance
of the GaN-based microelectronic device. It is understood that one
of these contributors for defects is the lattice mismatch between
the substrate and the GaN layers grown on the substrate. Therefore,
though the GaN layer has been grown on the sapphire substrate, but
it is well known that the GaN layer is preferably grown on the AlN
buffer layer previously formed on the SiC substrate to reduce the
defect density, especially to reduce the density of threading
dislocations. Even though there are these considerable progresses,
it is still the goal desired to reach to reduce the defect density
continuously on the research.
[0007] It is also well-known that the condition of epitaxy is
controlled to achieve the lateral epitaxy by use of the substrate
with patterned surface, which benefits in preferred orientation of
epitaxy, to reduce the defect density or control defects. For
example, a GaN semiconductor layer can be formed on the sapphire
substrate with patterned surface in lateral epitaxial way to
control dislocations in extending laterally to reduce the density
of threading dislocations.
[0008] However, all of the prior arts regarding manufacture of the
epitaxial substrate with patterned surface must utilize a
photolithography process. Obviously, the prior arts regarding
manufacture of the epitaxial substrate with patterned surface have
high manufacture cost and slow production speed.
SUMMARY OF THE INVENTION
[0009] Accordingly, one scope of the invention is to provide an
epitaxial substrate and fabrication thereof. In particular, an
epitaxial surface of the epitaxial substrate according to the
invention is non-patterned, but thereon still benefits a compound
semiconductor material in lateral epitaxy to grow an epitaxial
layer with excellent quality. Moreover, the method of manufacturing
the epitaxial substrate according to the invention has advantages
of low cost and rapid production.
[0010] An epitaxial substrate according to a preferred embodiment
of the invention includes a crystalline substrate. The crystalline
substrate has an epitaxial surface. In particular, the epitaxial
surface of the crystalline substrate is nano-rugged and
non-patterned.
[0011] A method of fabricating an epitaxial substrate, according to
a preferred embodiment of the invention, firstly, is to prepare a
crystalline substrate which has an epitaxial surface. Next, the
method according to the invention is to deposit a poly-crystalline
layer of a material on the epitaxial surface of the crystalline
substrate. Then, the method according to the invention is to etch
the grain boundaries of the poly-crystalline layer by a first wet
etching process. Afterward, the method according to the invention
is to take the etched poly-crystalline layer as a mask, and to etch
the regions within the grain boundaries of the ploy-crystalline
layer by a plasma etching process. Finally, the method according to
the invention is to remove the etched poly-crystalline layer by a
second wet etching process, where the epitaxial surface of the
crystalline substrate is nano-rugged and non-patterned.
[0012] In one embodiment, the epitaxial surface of the crystalline
substrate has an average surface roughness (Ra) in a range from 100
nm to 400 nm.
[0013] In one embodiment, the epitaxial surface of the crystalline
substrate has a mean peak-to-valley height (Rz) in a range from 50
nm to 350 nm.
[0014] In practical application, the crystalline substrate can be
formed of sapphire, SiC, GaN, GaAs, ZnO, Si, ScAlMgO.sub.4,
SrCu.sub.2O.sub.2, YSZ(Yttria-Stabilized Zirconia), LiAlO.sub.2,
LiGaO.sub.2, Li.sub.2SiO.sub.3, LiGeO.sub.3, NaAlO.sub.2,
NaGaO.sub.2, Na.sub.2GeO.sub.3, Na.sub.2SiO.sub.3,
Li.sub.3PO.sub.4, Li.sub.3AsO.sub.4, Li.sub.3VO.sub.4,
Li.sub.2MgGeO.sub.4, Li.sub.2ZnGeO.sub.4, Li.sub.2CdGeO.sub.4,
Li.sub.2MgSiO.sub.4, Li.sub.2ZnSiO.sub.4, Li.sub.2CdSiO.sub.4,
Na.sub.2MgGeO.sub.4, Na.sub.2ZnGeO.sub.4, Na.sub.2ZnSiO.sub.4, or
other commercial materials provided for epitaxy.
[0015] In practical application, the material to form the
poly-crystalline layer can be Ge, ZnO, ZnS, CdSe, CdTe, CdS, ZnSe,
InAs, InP, Si, or metal/silicide where the metal can be Al, Ni, Fe
or other metal, and the silicide can be SiAl, SiZn, SiNi or other
silicide.
[0016] In one embodiment, the poly-crystalline layer can be
deposited on the epitaxial surface of the crystalline substrate by
an LPCVD (low pressure chemical vapor deposition) process, an PECVD
(plasma-enhanced chemical vapor deposition) process, a sputtering
process, or a thermal evaporation process.
[0017] In one embodiment, the poly-crystalline layer has a
thickness in a range from 20 nm to 2000 nm.
[0018] Compared to the prior arts, the epitaxial surface of the
epitaxial substrate according to the invention is nano-rugged and
non-patterned, and still benefits a compound semiconductor material
in growing epitaxial layers with excellent quality. Moreover, the
method of manufacturing the epitaxial substrate according to the
invention has advantages of low cost and rapid production.
[0019] The advantage and spirit of the invention may be understood
by the following recitations together with the appended
drawings.
BRIEF DESCRIPTION OF THE APPENDED DRAWINGS
[0020] FIG. 1 illustratively shows an epitaxial substrate with
nano-rugged and non-patterned surface according to a preferred
embodiment of the invention.
[0021] FIGS. 2A through 2C illustratively show a method according
to a preferred embodiment of the invention to fabricate an
epitaxial substrate, for example, as shown in FIG. 1.
[0022] FIG. 3 is an atomic force microscopy image of morphology of
a sapphire substrate fabricated according to the invention.
[0023] FIG. 4 is a transmission electron microscope image of an
un-doped GaN layer grown on a sapphire substrate fabricated
according to the invention.
[0024] FIG. 5A is an atomic force microscopy image of an un-doped
GaN layer grown on a sapphire substrate fabricated according to the
invention.
[0025] FIG. 5B is an SEM image of an etched un-doped GaN layer
grown on a sapphire substrate fabricated according to the
invention.
[0026] FIG. 5C is an atomic force microscopy image of an un-doped
GaN layer grown on a sapphire substrate with smooth surface.
DETAILED DESCRIPTION OF THE INVENTION
[0027] Referring to FIG. 1, FIG. 1 is a cross-sectional view of an
epitaxial substrate 1 according to a preferred embodiment of the
invention. The epitaxial substrate 1 can be provided for a compound
semiconductor material in epitaxy, such as GaN, AlGaN, AlInGaN, or
other III-V group compounds, or CdTe, ZnO, ZnS, or other II-VI
group compounds.
[0028] As shown in FIG. 1, the epitaxial substrate 1 according to
the invention includes a crystalline substrate 10. The crystalline
substrate 10 has an epitaxial surface 102.
[0029] Different from the prior arts, the epitaxial surface 102 of
the crystalline substrate 10 is nano-rugged and non-patterned. It
is noted that similar to the epitaxial substrates with patterned
surfaces of the prior arts, the epitaxial substrate 1 according to
the invention can also benefit the compound semiconductor material
in lateral epitaxy.
[0030] In one embodiment, the epitaxial surface 102 of the
crystalline substrate 10 has an average surface roughness (Ra) in a
range from 100 nm to 400 nm.
[0031] In one embodiment, the epitaxial surface 102 of the
crystalline substrate 10 has a mean peak-to-valley height (Rz) in a
range from 50 nm to 350 nm.
[0032] In practical application, the crystalline substrate 10 can
be formed of sapphire, SiC, GaN, GaAs, ZnO, Si, ScAlMgO.sub.4,
SrCu.sub.2O.sub.2, YSZ(Yttria-Stabilized Zirconia), LiAlO.sub.2,
LiGaO.sub.2, Li.sub.2SiO.sub.3, LiGeO.sub.3, NaAlO.sub.2,
NaGaO.sub.2, Na.sub.2GeO.sub.3, Na.sub.2SiO.sub.3,
Li.sub.3PO.sub.4, Li.sub.3AsO.sub.4, Li.sub.3VO.sub.4,
Li.sub.2MgGeO.sub.4, Li.sub.2ZnGeO.sub.4, Li.sub.2CdGeO.sub.4,
Li.sub.2MgSiO.sub.4, Li.sub.2ZnSiO.sub.4, Li.sub.2CdSiO.sub.4,
Na.sub.2MgGeO.sub.4, Na.sub.2ZnGeO.sub.4, Na.sub.2ZnSiO.sub.4, or
other commercial materials provided for epitaxy.
[0033] Referring to FIGS. 2A through 2C and FIG. 1, these figures
of sectional views illustratively show a method according to a
preferred embodiment of the invention to fabricate the epitaxial
substrate 1, for example, as shown in FIG. 1.
[0034] As shown in FIG. 2A, the method according to the invention,
firstly, is to prepare a crystalline substrate 10. The crystalline
substrate 10 has an epitaxial surface 102.
[0035] In practical application, the crystalline substrate 10 can
be formed of sapphire, SiC, GaN, GaAs, ZnO, Si, ScAlMgO.sub.4,
SrCu.sub.2O.sub.2, YSZ(Yttria-Stabilized Zirconia), LiAlO.sub.2,
LiGaO.sub.2, Li.sub.2SiO.sub.3, LiGeO.sub.3, NaAlO.sub.2,
NaGaO.sub.2, Na.sub.2GeO.sub.3, Na.sub.2SiO.sub.3,
Li.sub.3PO.sub.4, Li.sub.3AsO.sub.4, Li.sub.3VO.sub.4,
Li.sub.2MgGeO.sub.4, Li.sub.2ZnGeO.sub.4, Li.sub.2CdGeO.sub.4,
Li.sub.2MgSiO.sub.4, Li.sub.2ZnSiO.sub.4, Li.sub.2CdSiO.sub.4,
Na.sub.2MgGeO.sub.4, Na.sub.2ZnGeO.sub.4, Na.sub.2ZnSiO.sub.4, or
other commercial materials provided for epitaxy.
[0036] Next, the method according to the invention is to deposit a
poly-crystalline layer 12 of a material on the epitaxial surface
102 of the crystalline substrate 10, as shown in FIG. 2B. Also
shown in FIG. 2B, the poly-crystalline layer 12 has grain
boundaries 122.
[0037] In practical application, the material to form the
poly-crystalline layer 12 can be Ge, ZnO, ZnS, CdSe, CdTe, CdS,
ZnSe, InAs, InP, Si, or metal/silicide where the metal can be Al,
Ni, Fe or other metal, and the silicide can be SiAl, SiZn, SiNi or
other silicide.
[0038] In one embodiment, the poly-crystalline layer 12 can be
deposited on the epitaxial surface 102 of the crystalline substrate
10 by an LPCVD (low pressure chemical vapor deposition) process, an
PECVD (plasma-enhanced chemical vapor deposition) process, a
sputtering process, or a thermal evaporation process.
[0039] In one embodiment, the poly-crystalline layer 12 has a
thickness in a range from 20 nm to 2000 nm.
[0040] Then, the method according to the invention is to etch the
grain boundaries 122 of the poly-crystalline layer 12 by a first
wet etching process. The sectional view of the etched
poly-crystalline 12 is shown in FIG. 2C.
[0041] In a case, taking a sapphire as the substrate 10, various
etching solutions, which can be used to etch the grain boundaries
122 of poly-crystalline layer 12, and the compositions of these
etching solutions are listed in Table 1. Table 1 lists four etching
solutions including Secco solution, Sirtl solution, Wright
solution, and Seiter solution.
TABLE-US-00001 TABLE 1 composition (Mol %) etching solution solvent
.sup.1) HF oxizers .sup.2) Secco 67.6 32.2 0.17 Sirtl 71.2 26.3 2.5
Wright 78.5 16.1 5.4 Seiter 78.5 5.9 15.6 .sup.1) H.sub.2O +
CH.sub.3COOH(H.sub.Ac); .sup.2) CrO.sub.3 + HNO.sub.3
[0042] Furthermore, because the etching solutions listed in Table 1
cannot etch the sapphire substrate 10, these etching solutions can
etch the grain boundaries 122 of the poly-crystalline layer 12
until the epitaxial surface 102 of the sapphire substrate 10
underneath the grain boundaries 122 is exposed. Otherwise, as the
case, these etching solutions just etch the grain boundaries 122 of
the poly-crystalline layer 12 to certain depth where the epitaxial
surface 102 of the sapphire substrate 10 underneath the grain
boundaries 122 is not exposed.
[0043] Afterward, the method according to the invention is to take
the etched poly-crystalline layer 12 as a mask, and to etch the
regions within the grain boundaries 122 of the ploy-crystalline
layer 12 by a plasma etching process. Finally, the method according
to the invention is to remove the etched poly-crystalline layer 12
by a second wet etching process, where the epitaxial surface 102 of
the crystalline substrate 10 is nano-rugged and non-patterned.
[0044] In practice, the second wet etching process can use the
etching solution as the same as that used in the first wet etching
process.
[0045] In one embodiment, the epitaxial surface 102 of the
crystalline substrate 10 has an average surface roughness (Ra) in a
range from 100 nm to 400 nm.
[0046] In one embodiment, the epitaxial surface 102 of the
crystalline substrate 10 has a mean peak-to-valley height (Rz) in a
range from 50 nm to 350 nm.
[0047] In practice, the Ra and Rz values of the epitaxial surface
102 of the crystalline substrate 10 can be controlled by
controlling the thickness and grain size of the poly-crystalline
layer 12 and etching conditions.
[0048] Taking a sapphire substrate as an example, the morphology of
the sapphire substrate sample fabricated according to the invention
is shown in FIG. 3 that is an atomic force microscopy (AFM) image.
It is evident that the morphology of the epitaxial substrate
exhibits nano-rugged and non-patterned surface.
[0049] A transmission electron microscope (TEM) image of a sapphire
substrate sample (labeled as NRSS) fabricated according to the
invention is shown in FIG. 4, and an un-doped GaN layer (labeled as
u-GaN) grown on the epitaxial surface of the sapphire substrate is
also shown in FIG. 4. FIG. 4 evidently shows that the un-doped GaN
layer has low density of dislocations which are laterally extending
dislocations rather than threading dislocations.
[0050] An AFM image of an un-doped GaN layer grown on the aforesaid
NRSS sample is shown in FIG. 5A. The un-doped GaN layer grown on
the NRSS sample is etched at 180 .degree. C. for 1 minute in KOH
aqueous solution, an SEM image of the etched un-doped GaN layer is
shown in FIG. 5B. The etched pits shown in FIG. SB are just
evidence of threading dislocations. By statistical counting, the
density of threading dislocations of the un-doped GaN layer grown
on the NRSS sample is about 3.6.times.10.sup.6 cm.sup.-2. In
contrast, an AFM image of an un-doped GaN layer grown on a sapphire
substrate with smooth surface is shown in FIG. 5C. Obviously,
compared to FIG. 5A, FIG. 5C shows less smooth surface. By
statistical counting, the density of threading dislocations of the
un-doped GaN layer grown on the sapphire substrate with smooth
surface is about 1.times.10.sup.9 cm.sup.-2. Obviously, compared to
the epitaxial substrates with smooth epitaxial surface, the
epitaxial substrate according to the invention can reduce density
of dislocations, especially for density of threading
dislocations.
[0051] Similar to the epitaxial substrates with patterned surfaces
of the prior arts, the epitaxial substrate 1 with nano-rugged and
non-patterned surface according to the invention can also benefit
the compound semiconductor material in lateral epitaxy to reduce
density of defects and to enhance quality of epitaxial layers.
Table 2 lists measured photoelectric properties of sample labeled
as NRSS that the GaN layer is grown on the sapphire substrate with
nano-rugged and non-patterned surface fabricated according to the
invention. In contrast, Table 2 also lists measured photoelectric
properties of sample labeled as PSS that the GaN layer is grown on
the sapphire substrate with patterned surface, and measured
photoelectric properties of sample labeled as FSS that the GaN
layer is grown on the sapphire substrate with smooth surface.
TABLE-US-00002 TABLE 2 forward voltage peak emission wavelength
luminous intensity sample (Volt.) (nm) (a.u.) NRSS 3.71 457.21 5.71
.times. 10.sup.-7 PSS 3.60 450.30 5.50 .times. 10.sup.-7 FSS 3.69
459.51 3.33 .times. 10.sup.-7
[0052] With photoelectric properties listed in Table 2, it is
evident that the photoelectric properties of sample NRSS with
sapphire substrate according to the invention are close to those of
sample PSS with patterned sapphire substrate, and are better than
those of sample FSS with smooth sapphire substrate.
[0053] It is emphasized that different from the prior arts, the
method of fabricating the epitaxial substrate according to the
invention is not only without the need of a photolithography
process, and but also without the introduction of complicated
process. Therefore, it is obvious that the method according to the
invention has advantages of low manufacture cost and rapid
production speed.
[0054] With the example and explanations above, the features and
spirits of the invention will be hopefully well described. Those
skilled in the art will readily observe that numerous modifications
and alterations of the device may be made while retaining the
teaching of the invention. Accordingly, the above disclosure should
be construed as limited only by the metes and bounds of the
appended claims.
* * * * *