U.S. patent application number 14/175108 was filed with the patent office on 2014-08-07 for methods and systems for network address lookup engines.
This patent application is currently assigned to THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING / MCGILL UNIVERSITY. The applicant listed for this patent is THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING / MCGILL UNIVERSITY. Invention is credited to Warren Gross, Naoya Onizawa.
Application Number | 20140219279 14/175108 |
Document ID | / |
Family ID | 51259171 |
Filed Date | 2014-08-07 |
United States Patent
Application |
20140219279 |
Kind Code |
A1 |
Gross; Warren ; et
al. |
August 7, 2014 |
METHODS AND SYSTEMS FOR NETWORK ADDRESS LOOKUP ENGINES
Abstract
Internet routers are a key component in today's Internet. Each
router forwards received packets toward their final destinations
based upon a Longest Prefix Matching (LPM) algorithm select an
entry from a routing table that determines the closest location to
the final packet destination among several candidates. Prior art
solutions to LPM lookup offer different tradeoffs and that it would
be beneficial for a design methodology that provides for low power
large scale IP lookup engines addressing the limitations within the
prior art. According to embodiments of the invention a low-power
large-scale IP lookup engine may be implemented exploiting
clustered neural networks (CNNs). In addition to reduced power
consumption embodiments of the invention provide reduced transistor
count providing for reduced semiconductor die footprints and hence
reduced die cost.
Inventors: |
Gross; Warren; (Montreal,
CA) ; Onizawa; Naoya; (Montreal, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING / MCGILL
UNIVERSITY |
MONTREAL |
|
CA |
|
|
Assignee: |
THE ROYAL INSTITUTION FOR THE
ADVANCEMENT OF LEARNING / MCGILL UNIVERSITY
MONTREAL
CA
|
Family ID: |
51259171 |
Appl. No.: |
14/175108 |
Filed: |
February 7, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61761998 |
Feb 7, 2013 |
|
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Current U.S.
Class: |
370/392 ;
370/401 |
Current CPC
Class: |
H04L 1/1607 20130101;
H04L 5/005 20130101; H04L 5/006 20130101; H04J 13/12 20130101; H04L
5/0044 20130101; H04L 5/0057 20130101; H04L 5/0094 20130101; H04L
5/0053 20130101; H04L 5/0016 20130101; H04L 5/0048 20130101; H04L
1/0057 20130101; H04B 1/707 20130101; H04L 1/0029 20130101; H04J
11/00 20130101; H04L 45/745 20130101; H04L 45/46 20130101; H04L
5/0055 20130101; H04L 1/0026 20130101; H04J 13/0048 20130101; H04L
5/0007 20130101 |
Class at
Publication: |
370/392 ;
370/401 |
International
Class: |
H04L 12/741 20060101
H04L012/741; H04L 12/715 20060101 H04L012/715; H04L 29/12 20060101
H04L029/12 |
Claims
1. A device comprising; a clustered neural network processing
algorithms storing ternary data.
2. The device according to claim 1 wherein; the ternary data
comprises data having values of either 0, 1, or don't care.
3. The device according to claim 1; wherein the device only stores
data as binary weighted connections between clusters of the
clustered neural network.
4. The device according to claim 1 wherein; input data to the
device comprises a network address of a plurality of network
addresses according to a predetermined standard, each network
address relating to a destination of a packet of data received at a
system comprising at least the device; and output data from the
device comprises a rule for routing the packet of data; wherein the
plurality of addresses and their associated rules are stored as
associations within the device without the requirement for an
additional rule specific memory.
5. A device comprising: a first plurality of input clusters forming
a first predetermined portion of a clustered neural network, each
input cluster comprising of a first predetermined number of input
neurons; and a second plurality of output clusters forming a second
predetermined portion of the clustered neural network, each output
cluster comprising a second predetermined number of output neurons;
wherein, the clustered neural network stores a plurality of network
addresses and routing rules relating to the network addresses as
associations.
6. The device according to claim 5 wherein, the clustered neural
network operates using ternary data, the ternary data comprising
data having values of either 0, 1, or don't care.
7. The device according to claim 5; wherein the device only stores
data as binary weighted connections between clusters of the
clustered neural network.
8. A method comprising; providing an address lookup engine for a
routing device employing a clustered neural network capable of
processing ternary data; teaching the address lookup engine about a
plurality of addresses and their corresponding rules for routing
data packets received by the routing device in dependence upon at
least an address forming a predetermined portion of the data
packet; and routing data packets using the address lookup
engine.
9. The method according to claim 8 wherein, providing the address
lookup engine comprises: providing a first plurality of input
clusters forming a first predetermined portion of the clustered
neural network, each input cluster comprising of a first
predetermined number of input neurons; and providing a second
plurality of output clusters forming a second predetermined portion
of the clustered neural network, each output cluster comprising a
second predetermined number of output neurons; wherein, the
clustered neural network stores a plurality of network addresses
and routing rules relating to the network addresses as
associations.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This patent application claims the benefit of U.S.
Provisional Patent Application 61/761,998 filed on Feb. 7, 2013
entitled "Methods and Systems for Network Address Lookup
Engines."
FIELD OF THE INVENTION
[0002] This invention relates to address look-up engines and more
particularly to address look-up engines with low power, die area
efficiency, and compatibility with high speed packet datarates.
BACKGROUND OF THE INVENTION
[0003] In 2011 Cisco Systems 5.sup.th Annual Visual Networking
Index Forecast the networking giant forecast that global Internet
traffic will reach approximately 1 zettabyte a year by 2015
(966.times.10.sup.18). Breaking this down this equates to
approximately 80 exabytes per month in 2015, up from approximately
20 exabytes per month in 2010, or 245 terabytes per second. This
global Internet traffic will arise from approximately 3 billion
people using approximately 6 billion portable and fixed electronic
devices. At the same time average broadband access speeds will have
increased to nearly 30 megabits per second from the approximately 7
megabits per second in 2011. This Internet traffic and consumer
driven broadband access being supported through a variety of local,
metropolitan, and wide area networks together with long haul,
trunk, submarine, and backbone networks operating at OC-48 (2.5
Gb/s), OC-192 (10 Gb/s), OC-768 (40 Gb/s) with coarse and dense
wavelength division multiplexing to provide overall channel
capacities in some instances in excess of 1 Tb/s.
[0004] Dispersed between and within these networks are Internet
routers which have become key to the Internet backbone. Such
routers including, but not limited to, edge routers, subscriber
edge routers, inter-provider border routers, and core routers.
Accordingly, the overall data handled by these Internet routers by
2015 will be many times the approximately 1 zettabyte actually
provided to users who will have expectations not only of high
access speeds but low latency. Accordingly, Internet routers
require fast IP-lookup operations utilizing hundred thousands of
entries or more. Each router forwarding received packets toward
their final destinations based upon a Longest Prefix Matching (LPM)
algorithm to select an entry from a routing table that determines
the closest location to the final packet destination among several
candidates. As an entry in a routing table may be specify a
network, one destination address may match more than one routing
table entry. The most specific table entry, the one with the
highest subnet mask, being called the longest prefix match. With
the length of a packet being up to 32 bits for Internet Protocol
version 4 (IPv4) and 144 bits for Internet Protocol version 6
(IPv6) it is evident that even at OC-48 (2.5 Gb/s) with maximum
length IPv6 packets over 17 million packets are received per
second. These packets containing binary strings and wildcards.
[0005] The hardware of the LPM has been designed within the prior
art using several approaches including, but not limited to: [0006]
Ternary Content-Addressable Memory (TCAM), see for example Gamache
et. al. in "A fast ternary CAM design for IP networking
applications" (Proc. 12th IEEE ICCCN, pp. 434-439), Noda et. al. in
"A cost-efficient high-performance dynamic TCAM with pipelined
hierarchical searching and shift redundancy architecture" (IEEE
JSSC, Vol. 40, No. 1, pp. 245-253), Maurya et. al. in "A dynamic
longest prefix matching content addressable memory for IP routing"
(IEEE TVLSI, Vol. 19, No. 6, pp. 963-972), and Kuroda et. al. "A
200 Msps, 0.6 W eDRAM-based search engine applying full-route
capacity dedicated FIB application" (Proc. CICC 2012, pp. 1-4);
[0007] Trie-based schemes, see for example, Eatherton et al. "Tree
bitmap: hardware/software IP lookups with incremental updates"
(SIGCOMM Comput. Commun. Rev., Vol. 34, No. 2, pp. 97-122), and
Bando et al "Flashtrie: Beyond 100-Gb/s IP route lookup using
hash-based prefix-compressed trie" (IEEE/ACM Trans. Networking,
Vol. 20, No. 4, pp. 1262-1275); and [0008] Hash-based schemes, see
for example Hasan et. al. in "Chisel: A storage-efficient,
collision-free hash-based network processing architecture" (Proc.
33rd ISCA, pp. 203-215, June 2006) and Dharmapurikar et al. in
"Longest prefix matching using bloom filters" (IEEE/ACM Trans.
Networking 2006, Vol. 14, No. 2, pp. 397-409).
[0009] Unlike random access memory (RAM) which RAM returns the data
word stored at a supplied memory address a Content Addressable
Memory (CAM) searches its entire memory to see if a data word
supplied to it is stored anywhere within it. If the data word is
found, the CAM returns a list of the one or more storage addresses
where the word was found. A Ternary Content Addressable Memory
(TCAM) allows a third matching state of "X" (or "Don't Care") in
addition to "0" and "1" for one or more of the bits within the
stored data word, thus adding flexibility to the search.
Beneficially TCAMs perform the search of all entries stored in the
TCAM cells in parallel and allow therefore for high-speed lookup
operations. However, the large area of the cell, exploiting 16
transistors versus the 6 transistors in a static RAM (SRAM) cell
and the brute-force searching methodology result in large power
dissipation and inefficient hardware architectures for large
forwarding tables. In contrast trie-based schemes exploit ordered
tree data structures to store prefixes and locations based on this
binary-tree structure that is created based on portions of stored
Internet Protocol (IP) addresses. Searching is performed by
traversing the tree until an LPM is found and may be implemented in
hardware using SRAMs, rather than TCAMs, which potentially lowers
power dissipation. However, deep trees require multi-step lookups
slowing the determination of the LPM. Hash-based schemes use one or
more hash tables to store prefixes where the benefit is scalability
as table size is increased with length-independent searching speed.
However, hash-based schemes have a possibility of collisions that
requires post-processing to decide on only one output and requires
reading many hash tables for each length of stored strings thereby
slowing the process.
[0010] According, it would be evident that prior art solutions to
LPM lookup offer different tradeoffs and that it would be
beneficial for a design methodology that provides for low power
large scale IP lookup engines addressing the limitations within the
prior art. With carriers looking to add picocells, for example with
ranges of a few hundred metres, to augment microcells and base
stations in order to address capacity demands in dense urban
environments for example power consumption becomes an important
factor against conventional IP router deployment scenarios.
According to embodiments of the invention a low-power large-scale
IP lookup engine may be implemented exploiting clustered neural
networks (CNNs). In addition to reduced power consumption
embodiments of the invention provide reduced transistor count
providing for reduced semiconductor die footprints and hence
reduced die cost.
[0011] Beneficially low cost TCAMs would allow for their deployment
within a variety of other applications where to date they have not
been feasible due to cost as well as others where their deployment
had not been previously considered. For example, TCAMs would enable
routers to perform additional functions beyond address lookups,
including, but not limited to, virus detection and intrusion
detection.
[0012] Other aspects and features of the present invention will
become apparent to those ordinarily skilled in the art upon review
of the following description of specific embodiments of the
invention in conjunction with the accompanying figures.
SUMMARY OF THE INVENTION
[0013] It is an object of the present invention to address
limitations in the prior art for address look-up engines and more
particularly to providing address look-up engines with low power,
die area efficiency, and compatibility with high speed packet
datarates
[0014] In accordance with an embodiment of the invention there is
provided a device comprising a clustered neural network processing
algorithms storing ternary data.
[0015] In accordance with an embodiment of the invention there is
provided a device comprising: [0016] a first plurality of input
clusters forming a first predetermined portion of a clustered
neural network, each input cluster comprising of a first
predetermined number of input neurons; and [0017] a second
plurality of output clusters forming a second predetermined portion
of the clustered neural network, each output cluster comprising a
second predetermined number of output neurons; wherein, [0018] the
clustered neural network stores a plurality of network addresses
and routing rules relating to the network addresses as
associations.
[0019] In accordance with an embodiment of the invention there is
provided a method comprising: [0020] providing an address lookup
engine for a routing device employing a clustered neural network
capable of processing ternary data; [0021] teaching the address
lookup engine about a plurality of addresses and their
corresponding rules for routing data packets received by the
routing device in dependence upon at least an address forming a
predetermined portion of the data packet; and [0022] routing data
packets using the address lookup engine.
[0023] Other aspects and features of the present invention will
become apparent to those ordinarily skilled in the art upon review
of the following description of specific embodiments of the
invention in conjunction with the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Embodiments of the present invention will now be described,
by way of example only, with reference to the attached Figures,
wherein:
[0025] FIG. 1 depicts a prior art IP lookup engine exploiting
TCAMs;
[0026] FIGS. 2A and 2B depict an IP lookup engine exploiting CNNs
without wildcards in learning and retrieving processes;
[0027] FIGS. 3A to 3C depict an IP lookup engine according to an
embodiment of the invention exploiting wildcards in local storing,
dummy neuron activation, and global storing processes;
[0028] FIGS. 4A to 4C depict a retrieving process for use within an
IP lookup scheme with wildcards according to an embodiment of the
invention;
[0029] FIGS. 5A to 5D depict a retrieving process for use within an
IP lookup scheme with wildcards according to an embodiment of the
invention;
[0030] FIG. 6 depicts ambiguity probability versus number of learnt
messages for an IP engine according to an embodiment of the
invention;
[0031] FIG. 7 depicts a first implementation architecture for an IP
lookup engine according to an embodiment of the invention;
[0032] FIG. 8 depicts circuit schematics for a dummy generator and
input selection block forming portions of an IP lookup engine
according to the first implementation architecture in FIG. 7;
[0033] FIG. 9 depicts a circuit schematic for a decoding module
forming part of an IP lookup engine according to the first
implementation architecture in FIG. 7;
[0034] FIG. 10 depicts a second implementation architecture for an
IP lookup engine according to an embodiment of the invention;
[0035] FIGS. 11A and 11B depict circuits schematics for memory
blocks providing local storing (MLS) and global storing (MGS)
forming portions of an IP lookup engine according to the second
implementation architecture in FIG. 10;
[0036] FIGS. 12A and 12B depict circuits schematics for input
replacement based upon ILSW and dummy generator based upon MILSW
forming portions of IP lookup engines according to the second
implementation architecture in FIG. 10 for ILSW and MILSW
variants;
[0037] FIGS. 13A and 13B depict circuits schematics for decoding
modules based upon ILSW and MILSW respectively forming portions of
IP lookup engines according to the second implementation
architecture in FIG. 10 for ILSW and MILSW variants;
[0038] FIGS. 14A and 14B depict circuits schematics for ambiguity
elimination block and output selector forming portions of IP lookup
engines according to the second implementation architecture in FIG.
10;
[0039] FIG. 15 depicts the average and maximum number of ambiguous
entries versus the number of stored addresses for ILSW and MILSW IP
lookup engines according to embodiments of the invention;
[0040] FIG. 16 depicts the maximum N.sub.error versus number of
stored tables (N) with correlated table patterns for ILSW and MILSW
IP lookup engines according to embodiments of the invention;
DETAILED DESCRIPTION
[0041] The present invention is directed to address look-up engines
and more particularly to address look-up engines with low power,
die area efficiency, and compatibility with high speed packet
datarates.
[0042] The ensuing description provides exemplary embodiment(s)
only, and is not intended to limit the scope, applicability or
configuration of the disclosure. Rather, the ensuing description of
the exemplary embodiment(s) will provide those skilled in the art
with an enabling description for implementing an exemplary
embodiment. It being understood that various changes may be made in
the function and arrangement of elements without departing from the
spirit and scope as set forth in the appended claims.
[0043] Within the specification a variety of subscripts in respect
to mathematical descriptions of embodiments of the invention are
employed. Where possible the standard format of R.sub.s, where R is
a variable and S is an integer, is employed. However, where R.sub.S
is itself a subscript to another term then these are denoted as RS
for clarity to avoid multiple levels of subscripts which are
difficult to interpret in the published patent application.
[0044] 1. Background
[0045] As noted supra embodiments of the invention for low-power
large-scale IP lookup engines are implemented exploiting clustered
neural networks (CNNs). A CNN is a neural network which stores data
using only binary weighted connections between several clusters,
see for example Gripon et al. in "Sparse neural networks with large
learning diversity" (IEEE Trans. Neural Networks, Vol. 22, No. 7,
pp. 1087-1096). Compared with a classical Hopfield Neural Network
(HNN), see for example Hopfield in "Neural networks and physical
systems with emergent collective computational abilities" (Proc.
Nat. Academy of Sciences, Vol. 79, No. 8, pp. 2554-2558), the CNN
requires less complex functions while learning (storing) larger
number of messages. A hardware implementation for a CNN has been
reported by Jarollahi et. al. in "Architecture and implementation
of an associative memory using sparse clustered networks" (Proc.
ISCAS 2012, pp. 2901-2904).
[0046] However, within an IP lookup engine there is the requirement
for ternary not binary logic as LPM searching algorithms exploit
three values, namely "0", "1", "don't care", which would make them
incompatible with prior art CNNs. Accordingly, as described below
in respect of embodiments of the invention, the inventors have
extended the CNN concept to process ternary logic. Further, unlike
TCAMs that store IP addresses themselves, hardware embodiments of
the invention store the associations between IP addresses and
output rules, increasing memory efficiency. The output rule may, in
some embodiments of the invention, be determined through low
complexity hardware using associations read from SRAMs, thereby
reducing the search power dissipation compared with that of prior
art TCAMs that require brute-force searches. As both IP addresses
and their rules can be stored as associations in the proposed IP
lookup engine, the additional SRAM that stores rules within a
conventional TCAM-based IP lookup engine is not required.
[0047] 2. Prior Art TCAM Based IP Lookup Scheme
[0048] FIG. 1 depicts an IP lookup scheme using a TCAM and a SRAM
according to the prior art of Pagiamtzis et. al. in
"Content-addressable memory (CAM) circuits and architectures: a
tutorial and survey" (IEEE JSSC 2006, Vol. 41, No. 3, pp. 712-727).
Ternary content-addressable memories (TCAMs) contain large number
of entries from hundreds to several hundred thousand. Each entry
contains binary address information and a wildcard (X) in TCAMs,
while only binary information is stored in binary CAMs. The size of
the entry is several dozen to hundreds, e.g. 128, 144 bits for
IPv6, see for example Huang et al. in "A 65 nm 0.165 fJ/bit/search
256.times.144 TCAM macro design for IPv6 lookup tables" (IEEE JSSC
2011, Vol. 46, No. 2, pp. 507-519). In operation an input address
is broadcast onto all entries through search lines and one or more
entries are matched. A priority encoder finds the longest prefix
match among these matched entries and determines a matched location
that is an address of a SRAM containing rules. Since the matched
location in the TCAM corresponds to an address of the SRAM, the
corresponding rule is read.
[0049] As depicted in FIG. 1, an input address is 42.120.10.23 and
this matches two entries, 42.120.10.23 and 42.120.10.X as X is a
wildcard. Although two matched locations are activated, the matched
location corresponding to 42.120.10.23 is selected. Finally, a
"rule D" is read from the SRAM. TCAMs perform high-speed matching
based on one clock cycle with a small number of entries. However
there are some drawbacks when the number of entries is large, such
as network routing. Since the search lines are connected to all
entries, large search-line buffers are required, causing large
power dissipation. The power dissipation of the search lines is the
main portion of the overall power dissipation. In terms of die
footprint, the number of transistors in a TCAM cell is 16, while it
is 6 in a SRAM cell, resulting in an area inefficient hardware
implementation.
[0050] 3. IP Lookup Based on Clustered Neural Network
[0051] 3.1 IP Lookup Scheme without Wildcards
[0052] As noted supra IP lookup engines according to embodiments of
the invention are based upon extending the prior art binary CNN,
see for example Gripon. Referring to FIG. 2A there is depicted an
IP lookup scheme without wildcards (ILS) which provides the
functions of a TCAM and a SRAM by storing associations between the
IP addresses and their corresponding rules. There are c input
clusters and c' output clusters. Each input cluster consists of l
neurons and each output cluster consists of l' neurons. As depicted
in the example within FIG. 2, c=4 and l=16 are set in the input
cluster, while c'=1 and l'=16 are set in the output cluster. The
input address has 16(clog.sub.2 l) bits and the output port has
4(c'log.sub.2 l') bits.
[0053] 3.1.1 Learning Process:
[0054] In the learning process (also referred to as a storing
process), IP addresses and their corresponding rules (also referred
to as ports) are stored. Suppose that a k-th (1.ltoreq.k.ltoreq.N)
learning address m.sub.k is composed of c-sub-messages m.sub.k1 . .
. m.sub.kc and a k-th learning rule m'.sub.k is composed of
c'-sub-messages m'.sub.k1 . . . m'.sub.kc'. N is the number of
stored addresses. The length of the address is c*log.sub.2 l bits
and that of the rule is c'log.sub.2 l' bits. The address is
partitioned into c-sub-messages m.sub.kj (1.ltoreq.j.ltoreq.c),
whose size is .kappa.=log.sub.2 l bits. Each sub-message is
converted into a l-bit one-hot signal, which activates the
corresponding neuron in the input cluster, the l-bit one-hot signal
having one of the 1 bits "1" and the others are "0". The rule is
also partitioned into c'-sub-messages
m.sub.k'j'(1.ltoreq.j'.ltoreq.c'), whose size is .kappa.'=log.sub.2
l' bits. Each sub-message is converted into a l'-bit one-hot
signal, which activates the corresponding neuron in the output
cluster. During the learning process of M messages m.sub.1 . . .
m.sub.m that include input addresses and rules, the corresponding
patterns (activated neurons) C(m) are learnt. Depending on these
patterns, connections
w.sub.(i.sub.1.sub.,j.sub.1.sub.)(i.sub.2.sub.,j.sub.1.sub.)
between i.sub.1-th neuron of j.sub.1-th input cluster and
i.sub.2-th neuron of j.sub.2-th output cluster are stored according
to Equation (1).
w ( i 1 , j 1 ) ( i 2 , j 2 ) = { 1 , if { .E-backward. m .di-elect
cons. { m 1 m M } C ( m ) j 1 = i 1 C ( m ) j 2 = i 2 0 , otherwise
( 1 ) ##EQU00001##
where C(M) is a function that maps a message to a neuron.
[0055] This process is called "Global learning". Suppose that M
messages are uniformly distributed. An expected density d defined
as memory utilization for "Global learning" is given by Equation
(2).
d ' = 1 - ( 1 - 1 ll ' ) M ( 2 ) ##EQU00002##
[0056] For example, d'=0.3 means that stored bits of "1" are 30% of
the whole bits in the memory. The density is related to a
probability of ambiguity of output rules as described below.
[0057] 3.1.2 Retrieving Process:
[0058] Within the retrieving process, an output neuron (rule) is
retrieved using a c*k-bit input messages. The input message
m.sub.in is partitioned into c-sub-messages
m.sub.inj(1.ltoreq.j.ltoreq.c), which are converted into l-bit
one-hot signals. In each input cluster, one neuron that corresponds
to the l-bit one-hot signal is activated. The value of each neuron
v(n.sub.i1,j1)(i.sub.1<l, j.sub.1.ltoreq.c) in the input cluster
is given by Equation (3) below.
v ( n i 1 , j 1 ) = { = 1 , if m inf 1 = i 1 = 0 , otherwise ( 3 )
##EQU00003##
[0059] This process is called "Local decoding". Then, values of
neurons v(n'.sub.i2,j2) in the output cluster, where
v(n.sub.i1,j1)(i.sub.2<l', j.sub.2.ltoreq.c') is the j.sub.2-th
neuron of the i.sub.2-th input cluster, are updated using Equation
(4).
v ( n i 1 , j 1 ' ) = i 1 = 0 l - 1 j 1 = 1 c w ( i 1 , j 1 ) ( i 2
, j 2 ) v ( n i 1 , j 1 ) ( 4 ) ##EQU00004##
[0060] In each output neuron, the maximum value v.sub.Maxj.sub.2 is
found and then output neurons are activated using the Equations (5)
and (6) respectively.
v Maxj 2 = max v ( n i 2 , j 2 ' ) ( 5 ) v ( n i 2 , j 2 ' ) = { 1
, if v ( n i 2 , j 2 ' ) = v max j 2 0 , otherwise ( 6 )
##EQU00005##
[0061] The process described by processes covered by Equations (4)
through (6) are called "Global decoding". In the example shown in
FIG. 2B, the input message is 5.3.0.4. After applying Equation (4),
the value of the l-th neuron in the output cluster is 4 and becomes
the maximum value. Hence, the rule "1" is retrieved.
[0062] For learnt messages, there may be ambiguity in that more
than two neurons (rules) are retrieved in the output cluster after
"Global decoding". The probability of ambiguity P.sub.amb is given
by Equation (7).
P.sub.amb=1-(1-d.sup.c).sup.e'(l'-1) (7)
[0063] P.sub.amb is calculated based on learnt messages that are
uniformly distributed. If the learnt messages are correlated, then
the inventors through simulations described below have established
that these correlated patterns do not affect P.sub.amb
significantly.
[0064] If the number of stored addresses (M) is increased, an input
address might activate an output neuron that does not correspond to
the input address because of the multiplicity of stored
connections.
[0065] 3.2 IP Lookup Scheme with Wildcards
[0066] 3.2.1 Learning
[0067] As an IP routing table contains wildcards (X), the IP lookup
scheme is extended to store wildcards in the table. Referring to
FIGS. 3A to 3C there is depicted a learning process according to an
embodiment of the invention for an IP lookup scheme with wildcards
(ILSW). There are two different connections: w'.sub.(i,j)(i',j')
and w.sub.(i1,j1)(i2,j2). w'.sub.(i,j)(i',j') which represent
connections between activated neurons in the input clusters, while
w.sub.(i1,j1)(i2,j2) represents connections between activated
neurons in the input and output clusters. In the learning process
for w'.sub.(i1,j1)(i2,j2) (0.ltoreq.i.sub.1(i.sub.2)<l:
1.ltoreq.j.sub.1(j.sub.2).ltoreq.c) depicted in FIG. 3A, an address
learnt is partitioned into c-sub-messages with size
.kappa.=log.sub.2 l bits. If the sub-message is binary information,
it is converted into an l-bit one-hot signal, which activates the
corresponding neuron in the input cluster. If it is a wildcard, no
neuron is activated in the input cluster. The output neurons are
activated to store connections using the same, or comparable,
algorithm to that employed within the IP lookup scheme without
wildcards as depicted in FIG. 2. During the learning of M messages
M.sub.1', . . . , M.sub.M' that include only input connections and
depending on the corresponding patterns (activated neurons) C(m),
connections w.sub.(i,j)(i',j') between i-th neuron of j-th input
cluster and i'-th neuron of j'-th input cluster are stored based
upon Equation (8).
w ( i 1 , j 1 ) ( i 2 , j 2 ) = { 1 , if { .E-backward. m .di-elect
cons. { m 1 m M } j + 1 = j ' C ( m ) j = i C ( m ) j ' = i ' 0 ,
otherwise ( 8 ) ##EQU00006##
[0068] This process is called "Local learning".
[0069] FIG. 3B shows a process of a wildcard replacement for
connections between the input and the output clusters
w.sub.(i.sub.1.sub.,j.sub.1.sub.)(i.sub.2.sub.,j.sub.2.sub.)
(0.ltoreq.i.sub.1<l:0.ltoreq.i.sub.2<l':1.ltoreq.j.sub.1.ltoreq.c:1-
.ltoreq.j.sub.2.ltoreq.c') wherein dummy neurons are activated when
learnt messages include wildcards. Suppose that the last half of
learnt messages have wildcards distributed randomly. If a
sub-message is a wildcard, the wildcard is replaced by dummy
information that is binary one. The dummy information is determined
by a function using the first half of the learnt messages.
According to an embodiment of the invention, the function is
realized by XORing two sub-messages of the first half of learnt
messages. The k-th learning sub-messages m.sub.kj that contain
wildcards (X) are replaced as md.sub.kj according to Equation
(9).
md kj = { m k ( j - c 2 ) .sym. m k ( j - c 2 + 1 ) ( mod c 2 ) A ,
if { m kj = X and ( j > c b ) m kj . otherwise ( 9 )
##EQU00007##
[0070] Alternatively, this may be thought of that if a sub-address
is a wildcard the wildcard is replaced by a dummy sub-address
generated md.sub.kj, (1.ltoreq.j.ltoreq.c), where
1.ltoreq.k.ltoreq.N. Accordingly, if we suppose that the first
c.sub.b sub-addresses are known and the last (c-c.sub.b)
sub-addresses are either known or are wildcards. The dummy
sub-address is generated using a function that employs the first
c.sub.b sub-addresses.
[0071] In the example shown in FIG. 3B, the learnt message 1.9.10.X
has a wildcard. The wildcard is replaced by XORing 9.sym.1 that are
the two sub-messages in the first two input clusters, hence the
wildcard becomes 8. After making dummy neurons, process (1) is
performed by using md.sub.k instead of m.sub.k in order to make
connections between the input and output clusters and then these
connections are stored. For example, the dummy sub-message
(sub-address) is converted to an l-bit one-hot signal that
activates the corresponding dummy neuron in an input cluster
associated with the wildcard. Accordingly, the M stored messages
are now defined by M.sub.1, . . . , M.sub.M which include the
updated input addresses and output rule (port) and connections
between the input and the output activated neurons are stored as
shown in FIG. 3C and are given by Equation (10).
w ( i 1 , j 1 ) ( i 2 , j 2 ) = { 1 , if { .E-backward. M .di-elect
cons. { M 1 , , M M } and C ( M ) j 1 = i 1 and C ( M ) j 2 = i 2 0
, otherwise ( 10 ) ##EQU00008##
[0072] 3.2.2 Retrieving
[0073] In the retrieving process, the proposed IP lookup scheme
with wildcards (ILSW) checks whether input messages
m.sub.inj(1.ltoreq.j.ltoreq.C) are stored or not using stored
connections. If an activated neuron corresponding to an input
sub-message m.sub.inj1 in the j.sub.1-th input cluster doesn't have
a connection to an activated neuron in the precedent input cluster,
m.sub.inj1 can be decided as "non-stored messages". Hence, the
activated neuron is de-activated and alternatively a dummy neuron
is activated according to the rules in Equations (10) and (11).
This process initially partitions an input message m.sub.in into c
sub-messages which are themselves converted into l-bit one hot
signals and hence where an activate neuron corresponding to an
input sub-address m.sub.ini, in the j.sub.1-th input cluster has no
connection to an activated neuron in the (j.sub.1-1)-th input then
the cluster m.sub.inj1 may be treated as a non-stored message and
is not used but rather a dummy sub-messsage is generated according
to Equations (10) and (11) respectively. First, the number of
connections con.sub.j1 in the j.sub.1-th input cluster is given by
Equation (11).
con j 1 = j = 1 j 1 w ( m in ( j - 1 ) , j - 1 ) ( m inj , j ) ( 11
) ##EQU00009##
[0074] If con.sub.j1 is less than (j.sub.1-1), the input
sub-messages are not stored. Then, the input sub-messages
m.sub.inj1 are replaced as ms.sub.inj1 by dummy information as
determined by Equation (12).
ms inj 1 = { m in ( j 1 - c 2 ) .sym. m in ( j 1 - c 2 + 1 ) , if {
con j 1 < j 1 - 1 and ( j 1 > c b ) m inj 1 , otherwise ( 12
) ##EQU00010##
[0075] These rules in Equations (11) and (12) define processes are
referred to as "Input selection" or "Input replacement". Then,
v(n.sub.i1,j1) is obtained based on using Equation (3) by using
ms.sub.inj1 instead of m.sub.inj. In the example shown initially in
FIG. 4A an input message 5.3.10.6 is added with an output rule 5.
Subsequently as depicted in FIG. 4B an input message 1.9.10.6 is
input. Since the activated neuron "6" in the 4th input cluster
doesn't have a connection to the activated neuron "10" in the 3rd
input cluster, the activated neuron is de-activated. Instead, a
dummy neuron "4" in the 4th input cluster is activated.
[0076] The subsequent process is "Global decoding" based upon
exploiting the processes defined in Equations (4) through (6)
respectively. As the first-half input clusters have only binary
information, the summation of w.sub.(i1,j1)(i2,j2)v(n.sub.i1,j1)
from the first-half ones must be the half of the number of input
clusters, if output neurons are a candidate rule. In the IP lookup
scheme with wildcards (ILSW), Equation (4) is re-defined by
Equation (13).
ena i 2 , j 2 = i 1 = 0 l - 1 j 1 = 1 c b w ( i 1 , j 1 ) ( i 2 , j
2 ) v ( ni 1 , j 1 ) ( 13 ) ##EQU00011##
[0077] Accordingly, ena.sub.i2,j2 must be equal to c.sub.b if an
input address is stored by v(n.sub.i1,j1) being equal to 1. If
ena.sub.i2,j2 is less than c.sub.b the corresponding output neuron
is not related to the input address. Hence the summation in
Equation (4) is redefined by Equations (14) and (15).
sum i 2 , j 2 = i 1 = 0 l - 1 j 1 = c 2 + 1 c w ( i 1 , j 1 ) ( i 2
, j 2 ) v ( ni 1 , j 1 ) ( 14 ) v ( n i 2 , j 2 ' ) = { sum i 2 , j
2 , if_ena i 2 , j 2 = c 2 0 , otherwise ( 15 ) ##EQU00012##
[0078] After these processes are executed the processes established
by Equations (5) and (6) are executed. Referring to Table 1 the
learnt messages as a result of the "Local decoding" and "Global
decoding" processes described supra in respect of FIGS. 3 and 4 are
presented showing the IP address, IP address with dummy and the
associated rule.
TABLE-US-00001 TABLE 1 Learnt Messages from Process Depicted in
FIGS. 3 and 4 IP Address IP Address with Dummy Rule 5.3.0.6 5.3.0.6
1 1.9.10.12 1.9.10.12 14 1.9.10.X 1.9.10.8 8
[0079] 3.3 Global Decoding with Max Functions
[0080] 3.3.1 Learning
[0081] The proposed ILSW described supra in Section 3.2 requires a
max function in the Global decoding, which results in large
hardware overheads in terms of speed. The reason for a max function
being required is that the maximum value of v(n'.sub.i2,j2) is
varied depending on input messages, where v(n'.sub.i2,j2) can be up
to (c-c.sub.b). In the Input replacement, an input sub-message that
is not stored might be wrongly treated as a "stored sub-address",
especially when many addresses are stored. In this case, the input
sub-address activates the wrong neuron, which is not later replaced
by the dummy neuron. Once the wrong neuron is activated in the
input cluster, there may not exist a connection to an output
candidate. As a result, the maximum value of v(n'.sub.i2,j2) would
be less than (c-c.sub.b) that needs to be detected using the max
function.
[0082] To eliminate the max function, the maximum value has to be
stable. Referring to FIGS. 5A to 5D there is depicted a retrieving
process according to an embodiment of the invention exploiting a
modified proposed IP lookup scheme with wildcards (MILSW). In the
retrieving process, ms.sub.in which contains dummy sub-addresses is
generated using Equations (10) and (11). In addition, additional
dummy sub-addresses ma.sub.in (1.ltoreq.j.sub.1.ltoreq.c) are
generated using the processed defined by Equation (16).
ma inj 1 = { m in ( j 1 - c b ) .sym. m in ( j - c b + 1 ) ( mod c
b ) A , if ( j 1 > c b ) m inj 1 , otherwise ( 16 )
##EQU00013##
[0083] In Equation (16) all dummy sub-addresses related to an input
address are generated. Using ms.sub.in and ma.sub.in, input neurons
and all dummy neurons in the input clusters are activated based on
(3) instead of using m.sub.in. In this case, all the stored
connections for Global storing relating to the input address are
retrieved. Hence the maximum value of v(n'.sub.i2,j2) is
(c-c.sub.b) in Equation (15). The summation and max function are
replaced by an AND-OR function when the maximum value is fixed, see
for example the inventors in Ozinawa et al "Clockless Stochastic
Decoding of Low-Density Parity-Check Codes: Architecture and
Simulation Model" (J. Signal Processing Systems, pp. 2523-2526,
2013, hereinafter Ozinawa1). As a result the output neuron
v(n'.sub.i2,j2) is given by Equation (17).
v(n'.sub.i2,j2)=.LAMBDA..sub.j1=1.sup.cv
.sub.i1=0.sup.l.omega..sub.(i1,j1)(i2,j2)v(n.sub.i1,j1) (17)
[0084] In the example shown in FIGS. 5A to 5D one additional entry
is stored in Table 1 with an input address is 5.3.10.6 and its
output port is 5, where c.sub.b, is equal to 3. In FIGS. 5A to 5D
the solid lines indicate connections for Local storing and the
dashed lines indicate connections for Global storing. When an input
address is 1.9.10.6, a neuron "6" in the 4th input cluster is
wrongly activated because a connection between the neuron "6" in
the 4th input cluster and a neuron "I0" in the 3rd input cluster
exists as shown in FIG. 5B. Regardless of the activated neuron "6",
a dummy neuron "S" is activated following (16) using two
sub-addresses in the first two clusters shown in FIG. 5C. Using all
activated input neurons including the wrongly activated and the
dummy neurons, the output neuron is activated as shown in FIG. 5D.
In this case, the maximum value of v(n'.sub.i2,j2) is 4 that is the
number of input clusters (c). In contrast, when (12) is used, the
maximum value is 3 that cannot be detected using the AND-OR
function because the dummy neuron "8" in the 4th cluster is not
activated.
3.3.2 Probability of Generating Ambiguous Outputs
[0085] The MILSW also has a probability of generating ambiguous
outputs at each entry similar to that of the ILS in (7). For the
probability, an expected density for local storing is described. In
local storing, the density is different depending on positions of
stored sub-messages because the message lengths excluding wildcards
range from (c-c.sub.b)log.sub.2 l to log.sub.2 l bits. Now suppose
the number of sub-messages excluding wildcards are uniformly
distributed then the density from the j-th input cluster to the
(j+1)-th cluster for Local storing is given by the Equation
(18).
d j = 1 - ( 1 - 1 l 2 ) N ( c - j ) / ( c - c b + 1 ) ( 18 )
##EQU00014##
[0086] In the MILSW, there are two types of "wrongly" activated
neurons in the input clusters from (c-c.sub.b) to c. These two
types of the activated neurons affect the probability. In the first
type related to (12), when a sub-message that is not stored is
wrongly treated as a "stored sub-message", the corresponding neuron
is wrongly activated. The average number of wrongly activated
neurons per input cluster in the first type (.omega..sub.1) is
given by Equation (19).
.omega. 1 .apprxeq. 1 c - c b + 1 j = c b c - 1 k = 1 c - j ( k r =
j j + k + 1 d r ( 1 - d k + 1 ) ) ( 19 ) ##EQU00015##
[0087] In the second type related to (16), a dummy neuron is
activated even if a correct neuron that is actually stored is
activated in the same input cluster. In this case, the dummy neuron
is "wrongly" activated. The average number of wrongly activated
neurons per input cluster in the second type (.omega..sub.2) is
given by Equation (20).
.omega. 2 .apprxeq. 1 c - c b + 1 j = 1 c - c b j ( 20 )
##EQU00016##
[0088] Hence, the average number of activated neurons per input
cluster from c.sub.b to c(.omega..sub.a) as given by Equation (21).
As the activated neurons including "wrongly" activated neurons
affect the probability (p.sub.t) in MILWS, where p.sub.t is
obtained by modifying (7) to yield Equation (22) where c.sub.i is
the number of independent activated neurons in the input clusters,
which is affected by the function used in (9), (12) and (16).
[0089] 3.4 Ambiguity Analysis
[0090] The probability of generating ambiguous outputs at each
entry (P.sub.amb) is evaluated using a condition of l=512, c=16,
l'=1024, and c'=1. Suppose two different c.sub.b are used as 4 and
8. The functions of generating dummy sub-addresses in (16) are
designed using XOR functions and are summarized as an example in
Table 2. The functions are the same in (9), (12) and (16). As the
dummy sub-addresses are generated using the first c.sub.b
sub-addresses, some functions can be the same in c.sub.b=4.
Supposing the number of stored sub-addresses excluding wildcards
are uniformly distributed then c, is about 14.3 in the case of
c.sub.b=4.
TABLE-US-00002 TABLE 2 Example of Dummy Sub-Message Generation in
(16) f in c.sub.b = 8 f in c.sub.b = 4 ma.sub.in0 m.sub.in0
m.sub.in0 ma.sub.in1 m.sub.in1 m.sub.in1 ma.sub.in2 m.sub.in2
m.sub.in2 ma.sub.in3 m.sub.in3 m.sub.in3 ma.sub.in4 m.sub.in4
m.sub.in0 .sym. m.sub.in1 .sym. m.sub.in2 .sym. m.sub.in3
ma.sub.in5 m.sub.in5 m.sub.in1 .sym. m.sub.in2 .sym. m.sub.in3
.sym. m.sub.in0 ma.sub.in6 m.sub.in6 m.sub.in2 .sym. m.sub.in3
.sym. m.sub.in0 .sym. m.sub.in1 ma.sub.in7 m.sub.in7 m.sub.in3
.sym. m.sub.in0 .sym. m.sub.in1 .sym. m.sub.in2 ma.sub.in8
m.sub.in0 .sym. m.sub.in1 m.sub.in0 .sym. m.sub.in1 .sym. m.sub.in2
ma.sub.in9 m.sub.in1 .sym. m.sub.in2 m.sub.in1 .sym. m.sub.in2
.sym. m.sub.in3 ma.sub.in10 m.sub.in2 .sym. m.sub.in3 m.sub.in2
.sym. m.sub.in3 .sym. m.sub.in0 ma.sub.in11 m.sub.in3 .sym.
m.sub.in4 m.sub.in3 .sym. m.sub.in0 .sym. m.sub.in1 ma.sub.in12
m.sub.in4 .sym. m.sub.in5 m.sub.in0 .sym. m.sub.in1 ma.sub.in13
m.sub.in5 .sym. m.sub.in6 m.sub.in1 .sym. m.sub.in2 ma.sub.in14
m.sub.in6 .sym. m.sub.in7 m.sub.in2 .sym. m.sub.in3 ma.sub.in15
m.sub.in7 .sym. m.sub.in8 m.sub.in3 .sym. m.sub.in0
[0091] FIG. 6 shows the probability of ambiguity P.sub.amb versus
the number of learnt messages (M) in the IP lookup schemes (l=512,
c=16, l'=1024, c'=1). P.sub.amb is the probability that more than
two neurons are activated for learnt messages. In this condition,
the proposed IP lookup schemes store 144-bit (c*log.sub.2 l)
addresses (messages) for IPv6 headers. The maximum length is 36
bits for c.sub.b=4 and 72 bits for c.sub.b=8. Further when the
stored length is 36 bits, the wildcard length is 108 bits.
[0092] P.sub.amb without wildcards is defined by Equation (7).
P.sub.anib with wildcards was evaluated by simulations. Unlike
IPv4, since packet traces for the long prefix table are not
available to the public and the prefix table is still small, see
for example "Border Gateway Protocol (BGP)"
(http://bgp.potaroo.net), addresses were chosen randomly for the
evaluation. The stored addresses are uniformly distributed.
Random-length wildcards appear in the last half of addresses (72
bits). If the range of addresses that have wildcards is changed,
the prefix length can be changed.
[0093] It is evident from FIG. 6 that P.sub.amb is strongly
dependent of M. Within the IP lookup scheme according to
embodiments of the invention with wildcards, if a dummy neuron is
the same neuron as that already stored, then both outputs (rules)
might be retrieved, which slightly increases P.sub.amb compared
with that of the IP lookup scheme without wildcards. Adding dummy
neurons however as can be seen is very effective at lowering
P.sub.amb. This reduction is about five orders of magnitude
reduction of that without dummy neurons at M=78,643. As evident in
FIG. 5 the IP lookup scheme according to an embodiment of the
invention with wildcards can store 100,000 144-bit IP addresses
with a negligibly low probability of P.sub.amb (<10.sup.-8).
[0094] P.sub.amb was also simulated when the learnt messages are
correlated. The word length in the IP lookup scheme with wildcards
is 64 bits (l=256, c=8, l=1024, c'=1). The first 8 bits of the
learnt messages are selected from 64 fixed patterns of 256
(2.sup.8). The rest of the learnt messages are uniformly
distributed. Random-length wildcards appear in the last half of
addresses (32 bits). At M=10,000, P.sub.amb using the correlated
patterns was 5.30.times.10.sup.-7 while P.sub.amb using uniformly
distributed patterns is 1.69.times.10.sup.-7.
[0095] Unlearnt input messages are detected as "mismatch" via a
two-step process. In the first step, the number of local
connections con.sub.c/2 in Equation (10) is checked in "Input
selection". If it is not the same as ((c/2)-1), an unlearnt input
message can be detected as "mismatch" because all local connections
related to the input message are not stored ("Mismatch 1"). If an
unlearnt input message is detected as "match" by other stored
connections, the number of global connections ena.sub.t2,j2 is
checked at "Global decoding". If all ena.sub.i2,j2 are not the same
as (c/2), an unlearnt input message can be detected as "mismatch"
because all global connections between the input message and all
output rules are not stored ("Mismatch 2").
[0096] 4. Hardware Implementation
[0097] 4.1 Implementation 1
[0098] Referring to FIG. 7 there is depicted an overall structure
700 of an IP lookup engine according to an embodiment of the
invention with wildcards. The learning process is "Local learning"
using Equation (8) and "Global learning" as presented in respect of
Equations (9) and (1). The retrieving process employed exploits the
following process: [0099] 1) each input-sub message is replaced by
a dummy message if it is not stored ("Input selection") according
to Equations (10) and (11); [0100] 2) connections between c
activated neurons in the input clusters are read from a memory
block 1 ("Local decoding") established in dependence of Equation
(3); and [0101] 3) an output neuron is retrieved based on
connections between neurons of the input and the output clusters in
a memory block 2 in using processes established by Equations (12)
to (14), (5), and (6) respectively ("Global decoding").
[0102] There are ((c-1)l.sup.2)-bit SRAMs for "Local learning" and
c'll'-bit SRAMs for "Global learning". In "Local learning", a
sub-input k-th learning address I.sub.N and the subsequent one
m.sub.kj' are converted into one-hot l-bit signals at row and
column decoders, respectively. Then, a (w.sub.(i,j)(i',j')) is
stored in the memory block 1 if both are not a wildcard. In "Global
learning", the last half of an input address is replaced by dummy
information using a dummy generator that includes (c/2) sub-dummy
generators if each sub-input address is a wildcard. The
architecture of a sub-dummy generator being depicted by first
circuit 800 in FIG. 8. The sub-dummy generator contains l 2-input
XOR gates and multiplexors. Using the sub-input address with dummy
information md.sub.kj1 and the corresponding rule m'd.sub.kj2, a
(w.sub.(i1,j1)(i2,j2)) is stored in the memory block 2.
[0103] In the retrieving process, an input address m.sub.in is
partitioned into c-sub-messages and ((c-1)/l) connections
(w.sub.(i,j)(i',j')) are read from the memory block 1.
w.sub.(m.inj,j)(m.in(j+1),j+1) in Equation (10) are selected in a
multiplexor of an input-selection module. The input-selection
module being depicted by second circuit 850 in FIG. 8. Then, the
last half of the input address is replaced by dummy information if
these corresponding connections are not found. The output ms.sub.in
that contains the first half of the input address and the generated
last half of input address is sent to the memory block 2. The
one-hot decoder transforms ms.sub.in to v(n.sub.i1,j1). In the
memory block 2, (c'l') connections (w.sub.(i1,j1)(i2,j2)) are read
by ms.sub.in and are sent to a decoding module shown in FIG. 9. The
decoding module contains (c'l') global decoder, c' max-function
blocks and c' ambiguity checkers, where c' is set to 1 in FIG. 9.
In the global decoder, (c/2) 2-input AND gates and (c/2)-input AND
gate generate an enable signal to a (c/2)-input adder, where these
circuits are corresponding to (12)-(14). There are a l'-input
max-function block that decides an activated neuron
v(n.sub.i2,j2)=1. The ambiguity checker checks that two neurons are
activated simultaneously.
[0104] 4.2 Implementation 2
[0105] Referring to FIG. 10 there is depicted an overall structure
of another implementation of an IP lookup engine. A memory block
for local storing (MLS) stores connections in (8) and one for
global storing (MGS) stores connections in (10). These memory
modules are designed using SRAMs. A local decoding module in (3) is
a one-hot decoder included in the memory blocks. An ambiguity
elimination block includes a small TCAM that stores the ambiguous
entries in the ILSW (MILSW), wherein it should be noted that the
ambiguous entry generates more than one output port. If the ILSW
(MILSW) retrieves multiple output ports, the ambiguous entry is
matched to an input search address. In this case, the output of the
IP lookup engine is selected from the ambiguity elimination block
in an output selector. Otherwise, it is selected from the ILSW
(MILSW). The ILSW takes 2 clock cycles and the MILSW takes 3 clock
cycles for the retrieving process. The ambiguity elimination block
takes 2 clock cycles.
[0106] FIG. 11 shows the MLS contains (c-l) l.sup.2-bit sub-memory
blocks and the MGS contains c*c' ll'-bit sub-memory blocks. Both
the ILSW and the MILSW use the same memory block. In the storing
process, suppose that the stored connections are preliminarily
generated in an external processing unit (e.g. a central processing
unit (CPU) or microprocessor). In Local storing, l bits of
.omega.'.sub.(i,j)(i',j') are serially sent from the CPU and are
stored in the SRAM shown in FIG. 11A, where it takes at least/clock
cycles to store all .omega.'.sub.(i,j)(i',j') depending on the
number of inputs/outputs (I/Os) of the implemented semiconductor
circuit. In Global storing, it also takes at least l clock cycles
to store all .omega..sub.(i1,j1)(i2,j2)
[0107] In the retrieving process for the MLS, an input address
m.sub.in is partitioned into c sub-addresses and the corresponding
connections are read in (11). FIG. 12A depicts a circuit diagram of
the input-replacement module based on the ILSW. The updated input
address (ms.sub.in) is generated using the stored connections read
from the MLS in (12) at the first clock cycle. At the second clock
cycle, a flip-flop is enabled to store ms.sub.inj1 and transfers it
to the MGS. FIG. 12B depicts a circuit diagram of the dummy
generator for the MILSW. Accordingly, ma.sub.inj, is generated
before ms.sub.inj1 in (16) at the first clock cycle and is
transferred to the MGS using the same path of ms.sub.inj1 at the
second clock cycle. At the 3rd clock cycle, ms.sub.inj1 is
transferred to the MGS. Hence, .omega..sub.(i1,j1)(i2,j2) are read
twice from the MGS using ma.sub.inj1 and then ms.sub.inj1.
[0108] Now referring to FIG. 13A there is depicted the decoding
module based on the ILSW which operates at the 2nd clock cycle.
Using the connections read from the MGS, (13), (14) and (15) are
calculated using a c.sub.b-input AND gate and a (c-c.sub.b)-input
adder. Then, only activated output neuron or neurons are selected
using a max function in (5) and (6). FIG. 13B depicts the
corresponding decoding module based on the MILSW that operates at
the 2nd and the 3rd clock cycles. As .omega..sub.(i1,j1(i2,j2) is
read twice from the MGS, the word selected by ma.sub.inj1 is stored
in registers and then is ORed with the word selected by
ms.sub.inj1.
[0109] FIG. 14A depicts a circuit diagram of the ambiguity
elimination block. This block is identical for both the ILSW and
the MILSW and consists of q TCAM words (e.g. q=20) that contain the
ambiguous entries (m.sub.c). The value of q is larger than or equal
to the maximum number of ambiguous entries. In the storing process,
suppose that m.sub.c and the corresponding output ports (m'.sub.c)
are sent from a CPU and are stored in the TCAM and registers,
respectively. In the retrieving process, TCAM and registers,
respectively. In the retrieving process, m.sub.in is searched in
the TCAM and a matched word is found when the ILSW (MILSW)
generates multiple output ports. The matched word selects its
corresponding port from the registers through a one-hot encoder and
a multiplexer and then m.sub.out is transferred to an output
selector shown in FIG. 14B. The signal (mismatch) is low when the
matched word is found in the TCAM and high when it is not found. If
the matched word is found, m.sub.out is selected as an output port
in the output selector. Otherwise, the output port is selected from
the global decoding module.
[0110] 5. Evaluation
[0111] 5.1. Number of Ambiguous Entries
[0112] Depicted in FIG. 15 are the average (N.sub.amb) and the
maximum number (max(N.sub.amb)) of the ambiguous entries versus the
number of stored addresses (N) in the ILSW and the MILSW. Again it
is noted that an ambiguous entry activates more than one output
neuron. The same parameters as employed in FIG. 7 were used, where
c.sub.b=8. These results are obtained using simulations, where each
simulation point uses 12,000 trials to calculate N.sub.amb, and
max(N.sub.amb). N.sub.amb increases with increasing N because it
increases the density. The ILWS has lower N.sub.amb than that of
the MILWS. The reason for this being that the MILWS may "wrongly"
activate additional dummy neurons in (16).
[0113] Referring to FIG. 16 the max(N.sub.error) versus N is
plotted when stored addresses are correlated. P.sub.COR is the
number of correlated bits divided by the total number of bits at
the first two sub-addresses expressed as a percentage. The
simulation conditions are the same as the previous simulation. A
high P.sub.COR increases the number of shared connections among
stored entries. max(N.sub.amb) increases as the number of shared
connections is increased.
[0114] 5.2 Hardware Results and Performance Comparisons of
Embodiments of Invention
[0115] The proposed IP lookup engine described in respect of
Section 4.2 Implementation 2 and FIGS. 10 to 14 respectively was
designed based upon the Taiwan Semiconductor Manufacturing Company
Ltd. (TSMC) 65 nm CMOS technology. The MLS and the MGS both exploit
15 SRAM blocks (256 kb) and 32 SRAM blocks (256 kb), respectively.
The small TCAM in the compensation block has q=20 entries. For the
purpose of comparison, a reference TCAM was also designed. The TCAM
cell is designed using a NAND-type cell that consists of 16
transistors, as per Pagiamtzis et al in "Content-Addressable Memory
(CAM) Circuits and Architectures: A Tutorial and Survey" (IEEE J.
Solid State Circuits, Vol. 41, No. 3, pp. 712-727). Each entry has
144 TCAM cells and is designed based on a hierarchy design style
for high-speed matching operations, see for example Hanzawa et al
in "A Large-Scale and Low-Power CAM Architecture featuring a
One-Hotspot Block Code for IP-Address Lookup in a Network Router"
(IEEE J. Solid State Circuits, Vol. 40, No. 4, pp. 853-861).
Referring to Table III performance comparisons under HSPICE
simulation of the ILSW and MILSW with the reference TCAM design and
that of a previous design embodiment of the inventors are
presented, see Onizawa et al "Low-Power Area-Efficient Large-Scale
IP Lookup Engine based on Binary Weighted Clustered Networks"
(Proc. 50.sup.th IEEE Design Automation Conference, 2013,
hereinafter Ozinawa2). The reference TCAM is designed to store
100,000 144-bit entries and is divided into 20 sub-TCAMs that each
have 5,000 entries in order to achieve a power reduction for the
search lines. A priority encoder attached to the TCAM has 100,000
inputs and 17-bit outputs.
[0116] For storing process, the previous implementation of the
inventors, see Ozinawa2, and the IP lookup engines according to
embodiments of the invention l=512 clock cycles to store all tables
in the MLS and the MGS. The previous method has the probability of
generating ambiguous output ports (<10.sup.-8). The proposed
methods according to embodiments of the invention remove the
probability using the small TCAM. As the small TCAM can compensate
up to q=20 error entries, N is increased by 83.5% and 70.0% based
on the ILSW and the MILSW, respectively compared to the previous
method.
[0117] For the retrieving process, in the ILSW, the worst-case
delay is 1.31 ns in the block that includes the max-function block.
This delay is 89.1% of the previous method (Ozinawa2) that includes
an ambiguity checker after Global decoding. The delay of the
max-function block is 65.8% of the whole delay. In the MILWS, as
the max-function block is removed, the worst-case delay is 0.62 ns.
As throughput may be defined by (address length)/(worst-case
delay)/(retrieving clock cycles) the MILSW offers increased
throughput compared to the previous method (Ozinawa2) and the
ILSW.
[0118] However, the dynamic power dissipation of the MILSW is
increased compared to that of the ILSW because the MILSW reads
connections twice from the MGS. However, the energy dissipations of
the ILSW and the MILSW are 2.7% and 4.8% of that of the reference
TCAM which is significant. The main reason of the energy reduction
is the use of SRAMs instead of the power-hungry TCAM based on the
brute-force search. A lookup speed of the ILSW and the MILSW can be
229 Gb/s and 323 Gb/s over 40 Gb/s (OC-768) where the packet size
is supposed to be 75 bytes. In terms of die footprint a further
reduction is achieved as each TCAM cell contains 16 transistors
while each SRAM cell contains 6 transistors. Accordingly, the
required memory size of a CMOS implementation of a circuit
operating according to an embodiment of the invention is 11.75 Mb,
which 30.6% of the equivalent area of the reference TCAM design
TABLE-US-00003 TABLE 3 Performance Comparisons Reference TCAM
Ozinawa2 ILSW MILSW Number of Tables 100,000 100,000 183,500
170,000 Throughput (Gbps) 52.0 48.3 54.8 77.7 Dynamic Power (W)
3.030 0.140 0.156 0.363 Static Power (W) 0.240 0.090 0.090 0.090
Energy Metric (fJ/bit/search) 0.584 0.028 0.016 0.028 Probability
of Generating -- 10.sup.-8 -- -- Ambiguous Outputs q (number of
entries in TCAM) -- 0 20 20 Memory (Mb) 14.4 11.75 (SRAM) (TCAM)
Equivalent Size (SRAM) (Mb) 38.4 11.75 Number of Transistors 256M
77M
[0119] 5.3 Performance Comparison Relative to Prior Art
[0120] Referring to Table 4 there are presented performance
comparisons of embodiments of the invention with related works
within the prior art. The design of Gamache is a straightforward
implementation using TCAMs whilst Hayashi et al in "A 250-MHZ 18-Mb
Full Ternary CAM with Low-Voltage Matchline Sensing Scheme in 65-nm
CMOS" (IEEE J. Solid State Circuits, Vol. 48, No. 11, pp.
2671-2680) requires a very large (18 Mb) memory implementation
under a 65 nm CMOS technology. In contrast Noda employs eDRAMs to
reduce the size of TCAM cells for low power dissipation, however
this tends to be a complex process. In Maurya several entries are
shared using special-purpose CAM cells to reduce the number of
entries required whilst Kuroda realizes the prefix match by reading
candidates from eDRAMs, thereby yielding an energy metric which is
very small. However, as the memory size is O(2.sup.n) where n is
the word length, this leads to an unacceptably large memory of
1,039 Mb for long words (e.g. 144 bits). The trie-based method of
Bando (PC trie-4) realizes a memory-efficient IP lookup engine
using a prefix-compressed trie and also uses a hash function to
reduce memory accesses to off-chip memory in order to achieve high
throughput. Hasan exploits a hash-based method which reduces power
dissipation using a collision-free hash function compared with the
TCAM in Gamache. Compared with these methods, the IP lookup engines
ILSW and MILSW according to an embodiments of the invention realize
low energy metrics while dealing with large number of long entries
and also achieving high throughout and small die footprint through
a reasonable memory size.
[0121] It would be evident to one skilled in the art that small die
footprints equate to reduced die costs thereby reducing the cost of
an IP lookup engine according to an embodiment of the invention.
Beneficially low cost TCAMs and IP lookup engines implemented
according to embodiments of the invention would therefore not only
allow for their deployment within a variety of other applications
where to date they have not been feasible due to cost but also
others where their deployment had not been previously considered.
For example, low cost TCAMs would enable routers to perform
additional functions beyond address lookups, including, but not
limited to, virus detection and intrusion detection.
TABLE-US-00004 TABLE 4 Performance Comparison of Embodiment of the
Invention with Prior Art TCAM1 TCAM2 DTCAM IPCAM eDRAM Trie Hash
MILSW Length 512 72 144 32 (128) 23 63 32 144 (bits) (Note 1) No.
of 21,504 262,144 32,768 65,536 16 .times. 10.sup.6 318,043 524,288
170,000 Entries (Note 2) Throughput 76.8 18 20.6 32 4.6 12.6 6.4
77.7 (Gbps) e 12.26 9.6 2.0 7.33 0.6 -- 5.5 0.363 Energy 5.53 1.98
2.96 0.159 0.007 -- 1.64 0.028 Metric Memory 10.5 18 4.5 2 432
31.19 60 11.75 (Mb) Equiv. Size 28 48 -- 7.33 -- -- -- -- SRAM (Mb)
Equiv. Size 7.88 96 4.5 32.99 .sup. 10.sup.39 -- -- 11.75 for
144-bit Length (Mb) Technology 130 65 130 65 40 FPGA 130 65 (nm)
(Note 1): Method can be extended to 128 bits for IPv6 (Note 2):
1.38M - IPCAM word is approximately equivalent to 22 TCAM words.
Note 3: TCAMI - Gamache, TCAM2 - Hayashi, DTCAM - Noda, IPCAM -
Maurya, EDRAM - Kuroda, Trie - Bando, Hash - Hasan
[0122] Specific details are given in the above description to
provide a thorough understanding of the embodiments. However, it is
understood that the embodiments may be practiced without these
specific details. For example, circuits may be shown in block
diagrams in order not to obscure the embodiments in unnecessary
detail. In other instances, well-known circuits, processes,
algorithms, structures, and techniques may be shown without
unnecessary detail in order to avoid obscuring the embodiments.
[0123] In addition to the IP lookup search engines and context
driven search engines discussed supra other applications of
embodiments of the invention include, but are no limited, CPU fully
associative cache controllers and translation lookaside buffers,
database search engines, database engines, data compression,
artificial neural networks, and electronic intrusion prevention
system.
[0124] Implementation of the techniques, blocks, steps and means
described above may be done in various ways. For example, these
techniques, blocks, steps and means may be implemented in hardware,
software, or a combination thereof. For a hardware implementation,
the processing units may be implemented within one or more
application specific integrated circuits (ASICs), digital signal
processors (DSPs), digital signal processing devices (DSPDs),
programmable logic devices (PLDs), field programmable gate arrays
(FPGAs), processors, controllers, micro-controllers,
microprocessors, other electronic units designed to perform the
functions described above and/or a combination thereof.
[0125] Also, it is noted that the embodiments may be described as a
process which is depicted as a flowchart, a flow diagram, a data
flow diagram, a structure diagram, or a block diagram. Although a
flowchart may describe the operations as a sequential process, many
of the operations can be performed in parallel or concurrently. In
addition, the order of the operations may be rearranged. A process
is terminated when its operations are completed, but could have
additional steps not included in the figure. A process may
correspond to a method, a function, a procedure, a subroutine, a
subprogram, etc. When a process corresponds to a function, its
termination corresponds to a return of the function to the calling
function or the main function.
[0126] Furthermore, embodiments may be implemented by hardware,
software, scripting languages, firmware, middleware, microcode,
hardware description languages and/or any combination thereof. When
implemented in software, firmware, middleware, scripting language
and/or microcode, the program code or code segments to perform the
necessary tasks may be stored in a machine readable medium, such as
a storage medium. A code segment or machine-executable instruction
may represent a procedure, a function, a subprogram, a program, a
routine, a subroutine, a module, a software package, a script, a
class, or any combination of instructions, data structures and/or
program statements. A code segment may be coupled to another code
segment or a hardware circuit by passing and/or receiving
information, data, arguments, parameters and/or memory contents.
Information, arguments, parameters, data, etc. may be passed,
forwarded, or transmitted via any suitable means including memory
sharing, message passing, token passing, network transmission,
etc.
[0127] For a firmware and/or software implementation, the
methodologies may be implemented with modules (e.g., procedures,
functions, and so on) that perform the functions described herein.
Any machine-readable medium tangibly embodying instructions may be
used in implementing the methodologies described herein. For
example, software codes may be stored in a memory. Memory may be
implemented within the processor or external to the processor and
may vary in implementation where the memory is employed in storing
software codes for subsequent execution to that when the memory is
employed in executing the software codes. As used herein the term
"memory" refers to any type of long term, short term, volatile,
nonvolatile, or other storage medium and is not to be limited to
any particular type of memory or number of memories, or type of
media upon which memory is stored.
[0128] Moreover, as disclosed herein, the term "storage medium" may
represent one or more devices for storing data, including read only
memory (ROM), random access memory (RAM), magnetic RAM, core
memory, magnetic disk storage mediums, optical storage mediums,
flash memory devices and/or other machine readable mediums for
storing information. The term "machine-readable medium" includes,
but is not limited to portable or fixed storage devices, optical
storage devices, wireless channels and/or various other mediums
capable of storing, containing or carrying instruction(s) and/or
data.
[0129] The methodologies described herein are, in one or more
embodiments, performable by a machine which includes one or more
processors that accept code segments containing instructions. For
any of the methods described herein, when the instructions are
executed by the machine, the machine performs the method. Any
machine capable of executing a set of instructions (sequential or
otherwise) that specify actions to be taken by that machine are
included. Thus, a typical machine may be exemplified by a typical
processing system that includes one or more processors. Each
processor may include one or more of a CPU, a graphics-processing
unit, and a programmable DSP unit. The processing system further
may include a memory subsystem including main RAM and/or a static
RAM, and/or ROM. A bus subsystem may be included for communicating
between the components. If the processing system requires a
display, such a display may be included, e.g., a liquid crystal
display (LCD). If manual data entry is required, the processing
system also includes an input device such as one or more of an
alphanumeric input unit such as a keyboard, a pointing control
device such as a mouse, and so forth.
[0130] The memory includes machine-readable code segments (e.g.
software or software code) including instructions for performing,
when executed by the processing system, one of more of the methods
described herein. The software may reside entirely in the memory,
or may also reside, completely or at least partially, within the
RAM and/or within the processor during execution thereof by the
computer system. Thus, the memory and the processor also constitute
a system comprising machine-readable code.
[0131] In alternative embodiments, the machine operates as a
standalone device or may be connected, e.g., networked to other
machines, in a networked deployment, the machine may operate in the
capacity of a server or a client machine in server-client network
environment, or as a peer machine in a peer-to-peer or distributed
network environment. The machine may be, for example, a computer, a
server, a cluster of servers, a cluster of computers, a web
appliance, a distributed computing environment, a cloud computing
environment, or any machine capable of executing a set of
instructions (sequential or otherwise) that specify actions to be
taken by that machine. The term "machine" may also be taken to
include any collection of machines that individually or jointly
execute a set (or multiple sets) of instructions to perform any one
or more of the methodologies discussed herein.
[0132] The foregoing disclosure of the exemplary embodiments of the
present invention has been presented for purposes of illustration
and description. It is not intended to be exhaustive or to limit
the invention to the precise forms disclosed. Many variations and
modifications of the embodiments described herein will be apparent
to one of ordinary skill in the art in light of the above
disclosure. The scope of the invention is to be defined only by the
claims appended hereto, and by their equivalents.
[0133] Further, in describing representative embodiments of the
present invention, the specification may have presented the method
and/or process of the present invention as a particular sequence of
steps. However, to the extent that the method or process does not
rely on the particular order of steps set forth herein, the method
or process should not be limited to the particular sequence of
steps described. As one of ordinary skill in the art would
appreciate, other sequences of steps may be possible. Therefore,
the particular order of the steps set forth in the specification
should not be construed as limitations on the claims. In addition,
the claims directed to the method and/or process of the present
invention should not be limited to the performance of their steps
in the order written, and one skilled in the art can readily
appreciate that the sequences may be varied and still remain within
the spirit and scope of the present invention.
* * * * *
References