U.S. patent application number 13/989297 was filed with the patent office on 2014-08-07 for semiconductor device and method of manufacturing the same.
This patent application is currently assigned to Institute of Microelectronics, Chinese Academy of Sciences. The applicant listed for this patent is Changliang Qin, Huaxiang Yin. Invention is credited to Changliang Qin, Huaxiang Yin.
Application Number | 20140217519 13/989297 |
Document ID | / |
Family ID | 49948199 |
Filed Date | 2014-08-07 |
United States Patent
Application |
20140217519 |
Kind Code |
A1 |
Qin; Changliang ; et
al. |
August 7, 2014 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Abstract
A transistor device comprising epitaxial LDD and Halo regions
and a method of manufacturing the same are disclosed. According to
embodiments of the present disclosure, the method may comprise:
forming a gate stack on a semiconductor substrate; forming a gate
spacer which covers the top of the gate stack and sidewalls of the
gate stack; forming source/drain grooves; epitaxially growing a
Halo material layer in the source/drain grooves, wherein the Halo
material layer has a first doping element therein; epitaxially
growing source/drain regions which apply stress to a channel region
of the device, wherein the source/drain regions have a second
doping element, opposite in conductivity to the first doping
element, therein; isotropically etching the source/drain regions to
remove portions of the source/drain regions, wherein the etching
also removes portions of the Halo material layer directly under the
gate spacer and extends to the channel region to some extent,
wherein remaining portions of the Halo material layer constitute
Halo regions of the device; and epitaxially growing an LDD material
layer to form LDD regions of the device.
Inventors: |
Qin; Changliang; (Beijing,
CN) ; Yin; Huaxiang; (Beijing, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Qin; Changliang
Yin; Huaxiang |
Beijing
Beijing |
|
CN
CN |
|
|
Assignee: |
Institute of Microelectronics,
Chinese Academy of Sciences
Beijing
CN
|
Family ID: |
49948199 |
Appl. No.: |
13/989297 |
Filed: |
July 30, 2012 |
PCT Filed: |
July 30, 2012 |
PCT NO: |
PCT/CN2012/709352 |
371 Date: |
May 23, 2013 |
Current U.S.
Class: |
257/408 ;
438/300 |
Current CPC
Class: |
H01L 29/7848 20130101;
H01L 29/1045 20130101; H01L 29/66636 20130101; H01L 29/165
20130101; H01L 29/6659 20130101; H01L 29/7833 20130101; H01L
29/66628 20130101 |
Class at
Publication: |
257/408 ;
438/300 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/66 20060101 H01L029/66 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 16, 2012 |
CN |
201210246830.3 |
Claims
1. A method of manufacturing a semiconductor device, the method
comprising: forming a gate stack on a semiconductor substrate;
forming a gate spacer which covers the top of the gate stack and
sidewalls of the gate stack; forming source/drain grooves;
epitaxially growing a Halo material layer in the source/drain
grooves, wherein the Halo material layer has a first doping element
therein; epitaxially growing source/drain regions which apply
stress to a channel region of the device, wherein the source/drain
regions have a second doping element, opposite in conductivity to
the first doping element, therein; isotropically etching the
source/drain regions to remove portions of the source/drain
regions, wherein the etching also removes portions of the Halo
material layer directly under the gate spacer and extends to the
channel region to some extent, wherein remaining portions of the
Halo material layer constitute Halo regions of the device; and
epitaxially growing an LDD material layer to form LDD regions of
the device.
2-4. (canceled)
5. The method according to claim 1, wherein the LDD material layer
has a doping dose lower than that of the source/drain regions.
6-7. (canceled)
8. The method according to claim 1, wherein forming the LDD regions
comprises: anisotropically etching exposed portions of the LDD
material layer in a self-aligned manner after epitaxially growing
the LDD material layer, to reserve only portions of the LDD
material layer in the source/drain grooves directly under the gate
spacer, wherein the reserved portions constitute the LDD regions;
and further epitaxially growing the material for the source/drain
regions.
9. The method according to claim 1, further comprising: further
epitaxially growing the material for the source/drain regions on
the epitaxially grown LDD material layer, to raise the source/drain
regions.
10-12. (canceled)
13. A semiconductor device, comprising: a semiconductor substrate;
a gate stack formed on the semiconductor substrate; a gate spacer
covering the top of the gate stack and sidewalls of the gate stack;
source/drain grooves; epitaxially grown Halo regions located in the
source/drain grooves, wherein the Halo regions have a first doping
element therein; epitaxially grown source/drain regions which apply
stress to a channel region of the device, wherein the source/drain
regions have a second doping element, opposite in conductivity to
the first doping element, therein; and epitaxially grown LDD
regions at least partially located in the source/drain grooves
directly under the gate spacer, wherein the LDD regions have a
doping dose lower than that of the source/drain regions, and a
doping type same as that of the source/drain regions.
14. The device according to claim 13, wherein the Halo regions each
have a thickness of 1 nm-100 nm.
15. The device according to claim 13, wherein for a PMOS device,
the Halo regions comprise Si or SiGe and the first doping element
comprises an N-type doping element; and for an NMOS device, the
Halo regions comprise Si or Si:C and the first doping element
comprises a P-type doping element.
16. The device according to claim 13, wherein the Halo regions have
a doping concentration of 1E13-1E21 cm.sup.-3.
17. The device according to claim 13, wherein the doping dose of
the LDD regions is 1E13-1E15 cm.sup.-3, and the doping dose of the
source/drain regions is 1E15-1E20 cm.sup.-3.
18. The device according to claim 13, wherein for a PMOS device,
the LDD regions comprise Si or SiGe and are doped with a P-type
doping element; and for an NMOS device, the LDD regions comprise Si
or Si:C and are doped with an N-type doping element.
19. The device according to claim 14, wherein the Halo regions each
have a thickness of 1 nm-10 nm.
20. The device according to claim 15, wherein the N-type doping
element comprises P, and the P-type doping element comprises B.
21. The device according to claim 16, wherein the Halo regions have
a doping concentration of 1E13-1E15 cm.sup.-3.
22. The device according to claim 18, wherein the P-type doping
element comprises B, and the N-type doping element comprises P.
Description
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] The present application claims priority to Chinese
Application No. 201210246830.3, entitled "SEMICONDUCTOR DEVICE AND
METHOD OF MANUFACTURING THE SAME," filed on Jul. 16, 2012, which is
incorporated herein by reference in its entirety.
TECHNICAL FIELD
[0002] The present disclosure relates to the field of semiconductor
devices and manufacture thereof, and particularly, to a transistor
device comprising epitaxial LDD and Halo regions and a method of
manufacturing the same.
BACKGROUND
[0003] After the semiconductor integrated circuit technology
reaches the 90 nm node and beyond, it is becoming more and more
challenging to maintain or even improve performances of transistor
devices. At present, the strained silicon technology has become a
fundamental one, which improves performances of MOSFET devices by
suppressing short channel effects and enhancing the mobility of
carriers. For a PMOS device, it is common to form grooves in source
and drain regions and then epitaxially grow SiGe therein, which
applies compressive stress to press a channel region, so as to
improve the performances of the PMOS device. Likewise, for an NMOS
device, it is becoming popular to epitaxially grow Si:C in source
and drain regions, to achieve the same object. Specifically,
various stress applying techniques, such as STI (Shallow Trench
Isolation), SPT (Stress Proximity Technique), SiGe embedded source
and drain, stressed metallic gate, and Contact Etching Stop Layer
(CESL), have been proposed. Further, in small sized devices, it is
common to adopt the LDD and Halo processes to suppress hot carrier
effects and punch-through between the source and the drain. The LDD
and Halo are generally achieved by means of ion implantation
followed by annealing.
[0004] However, the ion implantation and annealing adopted in the
conventional LDD and Halo processes may cause some problems. If the
ion implantation is performed before the epitaxy in the source and
drain regions, the implantation may cause crystal structures at
surfaces of the source and drain grooves damaged, which has
negative impacts on the following epitaxy in the source and drain
regions. Otherwise, if the implantation is performed after the
epitaxy in the source and drain regions, the implantation may cause
the stress of the epitaxial layer released, resulting in reduced
stress applied by the source and drain regions and thus degraded
suppression of the SCE and DIBL effects. Further, a high
temperature adopted in the annealing process may crystallize an
amorphous layer formed by a pre-amorphization process. Furthermore,
there is still a possibility that the TED (Transient Enhanced
Diffusion) effect occurs and that doped elements cannot achieve a
relatively high activation state.
[0005] In view of the above, there is a need for a novel transistor
and a method of manufacturing the same, so as to more effectively
guarantee the performances of the transistor.
SUMMARY
[0006] The present disclosure aims to provide, among others, a
semiconductor device comprising epitaxial LDD and Halo regions and
a method of manufacturing the same, by which it is possible to
avoid problems in the prior art where the Halo and LDD regions are
formed by ion implantation and annealing.
[0007] According to an aspect of the present disclosure, there is
provided a method of manufacturing a semiconductor device, for
manufacturing a transistor comprising epitaxial LDD and Halo
regions, the method comprising: providing a semiconductor
substrate, forming STI arrangements on the semiconductor substrate,
and performing well implantation; forming a gate dielectric layer
and a gate electrode, and defining a gate pattern; forming a gate
spacer which covers the top of the gate electrode and sidewalls of
the gate electrode and the gate dielectric layer; forming
source/drain grooves; epitaxially growing a Halo material layer in
the source/drain grooves, wherein the Halo material layer has a
first doping element therein; epitaxially growing source/drain
regions which apply stress to a channel region of the transistor,
wherein the source/drain regions have a second doping element,
opposite in conductivity to the first doping element, therein;
isotropically etching the source/drain regions to remove portions
of the source/drain regions, wherein the etching also removes
portions of the Halo material layer directly under the gate spacer
and extends to the channel region to some extent, wherein remaining
portions of the Halo material layer constitute the Halo regions of
the transistor; epitaxially growing an LDD material layer to form
the LDD regions of the transistor; and forming source/drain
contacts.
[0008] In an example of the present disclosure, the Halo regions
each may have a thickness of 1 nm-100 nm, preferably 1 nm-10
nm.
[0009] In a further example of the present disclosure, for a PMOS
device, the Halo regions may comprise Si or SiGe and the first
doping element may comprise an N-type doping element, preferably P;
and for an NMOS device, the Halo regions may comprise Si or Si:C
and the first doping element may comprise a N-type doping element,
preferably B.
[0010] In a further example of the present disclosure, the Halo
regions may have a doping concentration of 1E13-1E21 cm.sup.-3,
preferably 1E13-1E15 cm.sup.-3.
[0011] In a further example of the present disclosure, the LDD
material layer may have a doping dose lower than that of the
source/drain regions. For example, the doping dose of the LDD
regions can be 1E13-1E15 cm.sup.-3, and the doping dose of the
source/drain regions can be 1E15-1E20 cm.sup.-3.
[0012] In a further example of the present disclosure, for a PMOS
device, the LDD regions may comprise Si or SiGe and can be doped
with a P-type doping element, preferably B; and for an NMOS device,
the LDD regions may comprise Si or Si:C and can be doped with an
N-type doping element, preferably P.
[0013] In a further example of the present disclosure, forming the
LDD regions may comprise: anisotropically etching exposed portions
of the LDD material layer in a self-aligned manner after
epitaxially growing the LDD material layer, to reserve only
portions of the LDD material layer in the source/drain grooves
directly under the gate spacer, wherein the reserved portions
constitute the LDD regions; and further epitaxially growing the
material for the source/drain regions, to compensate for loss of
the source/drain regions in the etching.
[0014] Alternatively, forming the LDD regions may comprise: leaving
the epitaxially grown LDD material layer as it is, without
anisotropically etching it in a self-aligned manner; and further
epitaxially growing the material for the source/drain regions, to
raise the source/drain regions.
[0015] According to a further example of the present disclosure,
the gate electrode may comprise polysilicon. Further, the gate last
process can be adopted. In this process, after formation of the
metal silicide, the gate electrode of polysilicon is removed to
form a gate void, into which metal is filled to form a metal gate.
Alternatively, the gate first process can be adopted. In this
process, the gate electrode may comprise metal. Further, the method
according to the present disclosure is applicable to the gate first
or last process of high-K/metal gate.
[0016] According to a further aspect of the present disclosure,
there is provided a semiconductor device, comprising a transistor
comprising epitaxial LDD and Halo regions, the device comprising: a
semiconductor substrate having STI arrangements and well regions
formed thereon; a gate stack comprising a gate dielectric layer and
a gate electrode; a gate spacer covering the top of the gate
electrode and sidewalls of the gate electrode and the gate
dielectric layer; source/drain grooves; epitaxially grown Halo
regions located in the source/drain grooves, wherein the Halo
regions have a first doping element therein; epitaxially grown
source/drain regions which apply stress to a channel region of the
transistor, wherein the source/drain regions have a second doping
element, opposite in conductivity to the first doping element,
therein; epitaxially grown LDD regions at least partially located
in the source/drain grooves directly under the gate spacer, wherein
the LDD regions have a doping dose lower than that of the
source/drain regions, and a doping type same as that of the
source/drain regions; and source/drain contacts.
[0017] In an example of the present disclosure, the Halo regions
each may have a thickness of 1 nm-100 nm, preferably 1 nm-10
nm.
[0018] In a further example of the present disclosure, for a PMOS
device, the Halo regions may comprise Si or SiGe and the first
doping element may comprise an N-type doping element, preferably P;
and for an NMOS device, the Halo regions may comprise Si or Si:C
and the first doping element may comprise a N-type doping element,
preferably B.
[0019] In a further example of the present disclosure, the Halo
regions may have a doping concentration of 1E13-1E21 cm.sup.-3,
preferably 1E13-1E15 cm.sup.-3.
[0020] In a further example of the present disclosure, the doping
dose of the LDD regions can be 1E13-1E15 cm.sup.-3, and the doping
dose of the source/drain regions can be 1E15-1E20 cm.sup.-3.
[0021] In a further example of the present disclosure, for a PMOS
device, the LDD regions may comprise Si or SiGe and can be doped
with a P-type doping element, preferably B; and for an NMOS device,
the LDD regions may comprise Si or Si:C and can be doped with an
N-type doping element, preferably P.
[0022] According to embodiments of the present disclosure,
formation of the Halo and LDD regions is achieved by the epitaxy
process and the self-aligned anisotropic etching process in
combination, and thus it is possible to avoid problems in the prior
art where the Halo and LDD regions are formed by ion implantation
and annealing. It is possible to completely eliminate damages on
crystal structures at surfaces of the source/drain grooves caused
by the ion implantation, and thus avoid impacts on the following
epitaxy of the material for the source/drain regions, without
increasing the amount of photolithography masks and the complexity.
Further, according to embodiments of the present disclosure, there
is no stress released due to the conventional ion implantation, so
the stress in the source/drain regions and thus suppression of the
SCE and DIBL effects thereby are guaranteed. Furthermore, according
to embodiments of the present disclosure, because there is no
annealing following the ion implantation, doped elements in the
transistor device can be placed in a relatively high activation
state. Also, it is possible to avoid potential crystallization of
an amorphous layer formed by a pre-amorphization process and
occurrence of the TED (Transient Enhanced Diffusion) effect.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIGS. 1-7 are schematic views showing a process of
manufacturing a transistor comprising epitaxial LDD and Halo
regions and structural aspects of the transistor.
DETAILED DESCRIPTION
[0024] Hereinafter, descriptions are given with reference to
embodiments shown in the attached drawings. However, it is to be
understood that these descriptions are illustrative and not
intended to limit the present disclosure. Further, in the
following, known structures and technologies are not described to
avoid obscuring the present disclosure unnecessarily.
[0025] According to embodiments of the present disclosure, there
are provided a semiconductor device and a method of manufacturing
the same, especially, a CMOS transistor device comprising epitaxial
LDD and Halo regions and a method of manufacturing the same.
Structural aspects of the device and a flow of the method will be
described in detail with reference to FIGS. 1-7, by way of
example.
[0026] FIG. 7 is a schematic view showing a semiconductor device
according to an embodiment of the present disclosure.
[0027] The semiconductor device comprises a semiconductor substrate
10 having STI arrangements 11 and well regions (not shown) formed
thereon; a gate stack comprising a gate dielectric layer 12 and a
gate electrode 13; a gate spacer 14 covering the top of the gate
electrode 13 and sidewalls of the gate electrode 13 and the gate
dielectric layer 12; source/drain grooves; epitaxially grown Halo
regions 15' located in the source/drain grooves, wherein the Halo
regions have a first doping element therein; epitaxially grown
source/drain regions 16 which apply stress to a channel region of
the transistor, wherein the source/drain regions 16 have a second
doping element, opposite in conductivity to the first doping
element, therein; epitaxially grown LDD regions 18 at least
partially located in the source/drain grooves directly under the
gate spacer 14, wherein the LDD regions 18 have a doping dose lower
than that of the source/drain regions, and a doping type same as
that of the source/drain regions; and source/drain contacts 19.
[0028] Hereinafter, an exemplary method of manufacturing the
semiconductor device will be described in detail.
[0029] Referring to FIG. 1, firstly, on a semiconductor substrate
10, STI (Shallow
[0030] Trench Isolation) arrangements 11, and also a gate
dielectric layer 12, a gate electrode 13, and a gate spacer 14 are
formed. Specifically, the semiconductor substrate 10, such as a
monocrystalline silicon substrate, is provided. Alternatively, the
semiconductor substrate 10 may comprise a Ge substrate or any other
suitable substrate. The STI arrangements 11 may be formed on the
semiconductor substrate 10 by, for example, applying a photoresist
layer on the semiconductor substrate 10 and patterning it into a
pattern corresponding to the STI arrangements 11, anisotropically
etching the semiconductor substrate 10 to form shallow trenches,
and then filling the shallow trenches with a dielectric material
such as commonly used SiO.sub.2. After formation of the STI
arrangements 11, well implantation (not shown) can be performed.
For a PMOS device, the well implantation is achieve by implanting
N-type impurities; while for an NMOS device, the well implantation
is achieved by implanting P-type impurities. To form a gate stack
comprising the gate dielectric layer 12 and the gate electrode 13,
a thin film layer of a high-K gate dielectric material may be
deposited on a surface of the substrate 10. The high-K gate
dielectric material has a higher relative permittivity than
SiO.sub.2, and thus is more beneficial to performances of the
transistor device. The high-K gate dielectric material may comprise
metal oxide, metal aluminate, and the like, such as HfO.sub.2,
ZrO.sub.2, LaAlO.sub.3. The gate dielectric layer 12 should be as
thin as possible, preferably with a thickness of about 0.5-10 nm,
while keeping its gate insulation property, and can be formed by
deposition such as CVD. After formation of the gate dielectric
layer 12, a material for the gate electrode 13 is deposited. The
gate electrode 13 may comprise polysilicon, metal, metal silicide,
and the like. In the gate first process, the gate electrode 13
generally comprises metal or metal silicide; while in the gate last
process, the gate electrode 13 generally comprises polysilicon,
which is replaced with metal or metal silicide after formation of
other parts of the transistor device. After that, a photoresist
layer is applied and then subjected to photolithography to define a
gate pattern. Then, the gate electrode 13 and the gate dielectric
layer 12 are sequentially etched according to the gate pattern.
Next, the gate spacer 14 is formed by, for example, depositing a
material for the spacer on the substrate 10, such as SiO.sub.2 and
Si.sub.3N.sub.4, by means of a deposition process with a good
conformality so that it covers the gate electrode 13 and the gate
dielectric layer 12 with a desired thickness, and then removing
portions of the spacer material on the surface of the substrate so
that the spacer material is left only on top of the gate electrode
13 and on sidewalls of the gate electrode 13 and the gate
dielectric layer 12. As a result, the gate spacer 14 surrounds the
entire gate stack. The gate spacer 14 may have a thickness of about
1 nm-100 nm, preferably 5 nm-50 nm. Subsequently, the semiconductor
substrate 10 is anisotropically etched in a self-aligned manner
with the STI arrangements 11, the gate electrode 13 and the gate
spacer 14 as a mask, to form source/drain grooves.
[0031] Next, referring to FIG. 2, a Halo material layer 15 is
epitaxially grown in the source/drain grooves. The Halo material
layer 15 may comprise Si or SiGe (for a PMOS device), or
alternatively Si or Si:C (for an NMOS device). The Halo material
layer 15 may have a first doping element doped therein, with a
doping concentration of about 1E13-1E21 cm.sup.-3, preferably
1E13-1E15 cm.sup.-3.
[0032] Then, source/drain regions 16 is epitaxially grown
selectively, as shown in FIG. 3. The source/drain regions 16 may
comprise Si or SiGe (for a PMOS device), or alternatively Si or
Si:C (for an NMOS device), to apply stress to a channel region of
the
[0033] MOS device so as to enhance the mobility of carriers. The
source/drain regions can be doped in-situ with, for example, B (for
a PMOS device) or P (for an NMOS device) into appropriate
source/drain doping, while being epitaxially grown. The
source/drain regions 16 may be configured to apply compressive
stress for a PMOS device, while tensile stress for an NMOS device.
Here, the source/drain regions 16 may have a second doping element
doped therein, which has a conductivity type opposite to the first
doping element. That is, if the source/drain regions 16 are doped
with P-type impurities (for a PMOS device), then the Halo material
layer 15 is be doped with N-type impurities such as P; or
otherwise, if the source/drain regions 16 are doped with N-type
impurities (for an NMOS device), then the Halo material layer 15 is
be doped with P-type impurities such as B.
[0034] Next, referring to FIG. 4, portions of the source/drain
regions 16 are removed by anisotropic etching. At the same time,
portions of the Halo material layer at SDE (Source Drain Extension)
regions (indicated by dashed-line circles in the drawing) are also
etched away. The etching drills towards the channel region
underlying the gate electrode to remove the portions of the Halo
material layer directly under the gate spacer 14, and extends to
the channel region to some extent. Here, removal of the portions of
the Halo material layer at the SDE regions will prevent a serial
resistance at the SDE regions from being too large. The Halo
material layer with the portions etched away constitutes Halo
regions 15' of the transistor device, with a thickness of about 1
nm-100 nm, preferably 1 nm-10 nm.
[0035] Then, referring to FIG. 5, an LDD material layer 17 is
epitaxially grown to form LDD regions of the transistor device.
Here, the LDD material layer 17 may have the same second doping
element as the source/drain regions 16. For example, for a PMOS
device, the LDD regions may comprise Si or SiGe, doped with B;
while for an NMOS device, the LDD regions may comprise Si or Si:C,
doped with P. However, the LDD material layer 17 may have a doping
dose lower than that of the source/drain regions 16. For example,
the doping dose in the source/drain regions 16 may be about
1E15-1E20 cm.sup.-3, and the doping dose in the LDD material layer
17 may be about 1E13-1E15 cm.sup.-3. The LDD regions may be formed
by directly epitaxially growing the LDD material layer 17 in the
source/drain grooves. That is, after epitaxy of the LDD material
layer, self-aligned anisotropic etching is not performed. After
that, the material for the source/drain regions is further
epitaxially grown to raise the source/drain regions, so as to
reduce a contact resistance. In this way, the LDD regions are
positioned at least partially in the source/drain grooves directly
under the gate spacer 14 (referring to the example shown in FIG.
5). Alternatively, the LDD regions may be formed as follows.
Referring to FIG. 6, after the LDD material layer 17 is epitaxially
grown, exposed portions thereof may be anisotropically etched in a
self-aligned manner. Due to presence of the gate spacer 14,
portions of the LDD material layer in the source/drain grooves
directly under the gate spacer 14 are reserved. The reserved
portions of the LDD material layer constitute the LDD regions 18 of
the transistor device. After that, the material for the
source/drain regions is further epitaxially grown in the
source/drain grooves, so as to compensate for loss of the
source/drain regions in the etching. In this way, the LDD regions
are entirely positioned in the source/drain grooves directly under
the gate spacer 14.
[0036] Thus, the Halo regions and the LDD regions are achieved by
means of epitaxy. Because formation of the Halo and LDD regions is
achieved by the epitaxy process and the self-aligned anisotropic
etching process in combination, it is possible to avoid problems in
the prior art where the Halo and LDD regions are formed by ion
implantation and annealing. It is possible to completely eliminate
damages on crystal structures at the surfaces of the source/drain
grooves caused by the ion implantation, and thus avoid impacts on
the following epitaxy of the material for the source/drain regions,
without increasing the amount of photolithography masks and the
complexity. Further, according to embodiments of the present
disclosure, there is no stress released due to the conventional ion
implantation, so the stress in the source/drain regions and thus
suppression of the SCE and DIBL effects thereby are guaranteed.
Furthermore, according to embodiments of the present disclosure,
because there is no annealing following the ion implantation, the
doped elements in the transistor device can be placed in a
relatively high activation state. Also, it is possible to avoid
potential crystallization of an amorphous layer formed by a
pre-amorphization process and occurrence of the TED (Transient
Enhanced Diffusion) effect.
[0037] After that, the manufacture of the transistor device can
continue conventionally. Referring to FIG. 7, source/drain contacts
of metal silicide 19 can be formed. The metal silicide may comprise
NiSi, NiSiGe, TiSi, TiSiGe, and the like.
[0038] After that, interconnection lines can be manufactured, if in
the gate first process. Alternatively, the already formed gate
electrode of polysilicon can be removed and a gate electrode of
metal or metal silicide can be formed instead, and then
interconnection lines can be manufactured, if in the gate last
process.
[0039] From the foregoing, it will be appreciated that specific
embodiments of the disclosure have been described herein for
purposes of illustration, but that various modifications may be
made without deviating from the disclosure. In addition, many of
the elements of one embodiment may be combined with other
embodiments in addition to or in lieu of the elements of the other
embodiments. Accordingly, the technology is not limited except as
by the appended claims.
* * * * *