U.S. patent application number 14/171455 was filed with the patent office on 2014-07-31 for method for using a photodetector having a bandwidth tuned honeycomb cell photodiode structure.
This patent application is currently assigned to VOLEX PLC. The applicant listed for this patent is APPLIED MICRO CIRCUITS CORPORATION, VOLEX PLC. Invention is credited to Subhash Roy, Sergey Vinogradov, Igor Zhovnirovsky.
Application Number | 20140209801 14/171455 |
Document ID | / |
Family ID | 50288825 |
Filed Date | 2014-07-31 |
United States Patent
Application |
20140209801 |
Kind Code |
A1 |
Roy; Subhash ; et
al. |
July 31, 2014 |
METHOD FOR USING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB
CELL PHOTODIODE STRUCTURE
Abstract
A photodetector with a bandwidth-tuned cell structure is
provided. The photodetector is fabricated from a semiconductor
substrate that is heavily doped with a first dopant. A plurality of
adjoining cavities is formed in the semiconductor substrate having
shared cell walls. A semiconductor well is formed in each cavity,
moderately doped with a second dopant opposite in polarity to the
first dopant. A layer of oxide is grown overlying the semiconductor
wells and an annealing process is performed. Then, metal pillars
are formed that extend into each semiconductor well having a
central axis aligned with an optical path. A first electrode is
connected to the metal pillar of each cell, and a second electrode
connected to the semiconductor substrate. The capacitance between
the first and second electrodes decreases in response to forming an
increased number of semiconductor wells with a reduced diameter,
and forming metal pillars with a reduced diameter.
Inventors: |
Roy; Subhash; (Lexington,
MA) ; Zhovnirovsky; Igor; (Newton, MA) ;
Vinogradov; Sergey; (Moscow, RU) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
VOLEX PLC
APPLIED MICRO CIRCUITS CORPORATION |
London
San Diego |
CA |
GB
US |
|
|
Assignee: |
VOLEX PLC
London
CA
APPLIED MICRO CIRCUITS CORPORATION
San Diego
|
Family ID: |
50288825 |
Appl. No.: |
14/171455 |
Filed: |
February 3, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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|
13355615 |
Jan 23, 2012 |
8680639 |
|
|
14171455 |
|
|
|
|
13278953 |
Oct 21, 2011 |
|
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13355615 |
|
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Current U.S.
Class: |
250/338.4 ;
250/200 |
Current CPC
Class: |
Y02E 10/50 20130101;
H01L 31/00 20130101; H01L 31/108 20130101; H01L 22/14 20130101;
H01L 31/1085 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; G01J 1/44 20130101; H01L 31/105 20130101; H01L 31/02019
20130101; H01L 31/022408 20130101; H01L 31/03529 20130101; H01L
27/1446 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
250/338.4 ;
250/200 |
International
Class: |
G01J 1/44 20060101
G01J001/44 |
Claims
1. A method for using a photodetector with a bandwidth-tuned cell
structure to measure optical signals, the method comprising:
providing a photodetector with a plurality of adjoining photodiode
cells formed in a bandwidth-tuned honeycomb structure, where each
cell comprises a metal pillar extending into a semiconductor well,
having a central axis aligned with an optical path; accepting a
bias voltage between first and second electrodes of the
photodetector; accepting an optical signal; measuring a higher
bandwidth response to forming an increased number of semiconductor
wells with a reduced diameter, and forming metal pillars with a
reduced diameter.
2. The method of claim 1 further comprising: measuring a higher
quantum efficiency (QE) in response to forming a decreased number
of semiconductor wells with an increased diameter, and forming
metal pillars with an increased diameter.
3. The method of claim 1 wherein providing the photodetector
includes providing a photodetector having silicon semiconductor
walls, metal pillars having an aspect ratio (L/d) of at least 7:1,
where L is defined as a length of the metal pillar and d is defined
as a metal pillar diameter at a top surface of the cell well, and a
ratio d/d0 of less than 10:1, where d0 is defined as a metal pillar
diameter at a bottom surface of the cell well; and, wherein
accepting the optical signal includes accepting an optical signal
having a wavelength in a range of about 815 to 875 nanometers (nm).
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 13/355,615, filed on Jan. 23, 2012, which is a
continuation-in-part of U.S. patent application Ser. No.
13/278,953, filed Oct. 21, 2011, the contents of each of which are
incorporated herein by reference in their entirety
TECHNICAL FIELD
[0002] This invention generally relates to solid state
photodetectors and, more particularly, to a cell structure of
photodiodes made using a vertical pillar aligned with the path of
light.
BACKGROUND
[0003] The most widely used semiconductor devices for light
detection are PN or PIN photodiodes. To enable the fastest
electrical output signal time response (highest bandwidth) using a
photodiode of a particular area, it is necessary to set an optimal
thickness of active layer to balance transit time and RC time
contributions to the bandwidth (BW). The optimal thickness of
active layer with respect to BW is insufficient for the detection
of light, as the absorption length in a thick active layer results
in low quantum efficiency (QE) of photodetection at longer
wavelengths. It is for this reason that silicon PN and PIN
photodiodes are typically too inefficient for high-speed optical
communications at wavelengths of 850 nanometers (nm) or
greater.
[0004] FIG. 1 is a diagram depicting a metal-semiconductor-metal
(MSM) photodetector (prior art). The MSM photodiode uses the
rectifying properties of Schottky contacts between metal and
semiconductor materials in a manner similar to PN junctions. The
trade-off between transit time and RC time contributions is
partially resolved in MSM photodetectors due to the low capacitance
of the interdigital electrodes, as compared to the capacitance of
PIN photodiodes having the same active area and active layer
thickness. Nevertheless, the thickness of the active layer in an
MSM device cannot be made too great due to inefficient and slow
collection of photoelectrons and holes generated at depths larger
than the spacing between fingers. Capacitance can be decreased, and
BW increased if the metal electrodes are moved closer together.
However, this results in greater shading of the absorption (active)
layer. Thus, MSM photodetectors typically use a very thin active
layer if high BWs are required, resulting in low QE for wavelengths
with an absorption depth longer than the active layer thickness.
Materials such Si, Ge, SiC, GaAs, InGaAs, and InP are typically
used as the active absorptive layer.
[0005] FIG. 2 is a partial cross-sectional view of lateral trench
detector (prior art). Improvement in the QE of a MSM photodetector
using a relatively thick absorption/active layer can be realized
using the so-called lateral trench detector (LTD). The main
drawback of the LTD is the high capacitance of parallel trench
electrodes, resulting in lower BW. The capacitance is proportional
to the length and height of the fingers.
[0006] It would be advantageous if a photodetector could be
fabricated with a reduced capacitance, to increase the signal
bandwidth at long wavelengths of light, without seriously degrading
the QE.
SUMMARY
[0007] Accordingly, a method is provided for fabricating a
photodetector with a bandwidth-tuned cell structure. A
semiconductor substrate is provided that is heavily doped with a
first dopant. A plurality of adjoining cavities is formed in the
semiconductor substrate having shared cell walls. A semiconductor
well is formed in each cavity, moderately doped with a second
dopant opposite in polarity to the first dopant. A layer of oxide
is grown overlying the semiconductor wells and an annealing process
is performed. Then, metal pillars are formed that extend into each
semiconductor well having a central axis aligned with an optical
path. A first electrode is connected to the metal pillar of each
cell, and a second electrode connected to the semiconductor
substrate. The capacitance between the first and second electrodes
decreases in response to forming an increased number of
semiconductor wells with a reduced diameter, and forming metal
pillars with a reduced diameter.
[0008] In one aspect, the photodetector operates at a wavelength in
a range of about 815 to 875nanometers (nm), and the semiconductor
well is silicon. Then, the metal pillars are formed by creating
openings in each semiconductor well having an aspect ratio (L/d) of
at least 7:1, where L is defined as a depth of the opening and d is
defined as the opening diameter at a top surface of the cell well.
Metal is deposited in each opening to form pillars. In another
aspect, each opening has a ratio d/d0 of less than 10:1, where d0
is defined as the opening diameter at a bottom surface of the cell
well.
[0009] Additional details of the above-described method and a
photodetector with a bandwidth-tuned cell structure are provided
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a diagram depicting a metal-semiconductor-metal
(MSM) photodetector (prior art).
[0011] FIG. 2 is a partial cross-sectional view of lateral trench
detector (prior art).
[0012] FIGS. 3A and 3B are, respectively, plan and partial
cross-sectional views of a photodiode with an optical path-aligned
electrode.
[0013] FIGS. 4A and 4B are, respectively, plan and cross-sectional
views depicting a cell structure photodiode with an optical
path-aligned electrode.
[0014] FIGS. 5A and 5B are, respectively, plan and partial
cross-sectional views of a photodetector with a bandwidth-tuned
cell structure.
[0015] FIG. 6 is a partial cross-sectional view of a variation of
the photodetector of FIG. 5B, depicting one cell in detail.
[0016] FIGS. 7A1, 7A2, 7A3, 7A4, 7A5, 7B5, 7A6, 7B6, 7A7, 7B7, 7A8,
7B8, 7A9, 7B9, and 7A10 depict steps in alternative processes for
fabricating a cell structure photodetector.
[0017] FIG. 8 is a partial cross-sectional view of a single cell
from the 19-cell design of FIG. 7A10 contrasting normal etched cell
walls with conic etched cell walls.
[0018] FIG. 9 is a graph depicting the parameter of capacitance vs.
various etch dimensions of W (microns), cross-referenced to cell
design.
[0019] FIG. 10 is a graph depicting the parameter of bandwidth vs.
W (microns) for various etch dimensions, cross-referenced to cell
design.
[0020] FIG. 11 is a graph depicting the parameter of bandwidth vs.
quantum efficiency (QE), cross-referenced to cell design.
[0021] FIG. 12 is a plan view of a 61-cell 5-layer
photodetector.
[0022] FIG. 13 is a graph depicting the parameter of bandwidth vs.
W, cross-referenced to the number of cells (Ncell).
[0023] FIG. 14 is a graph depicting the parameter of bandwidth vs.
QE, cross-referenced to the number of cells.
[0024] FIG. 15 is a graph depicting the parameter of bandwidth vs.
QE, cross-referenced to variations in pillar length (L).
[0025] FIG. 16 is a table describing the relationship between the
number of cell layers, W, bandwidth, QE, and cell area.
[0026] FIG. 17 is a flowchart illustrating a method for fabricating
a photodetector with a bandwidth-tuned cell structure.
[0027] FIG. 18 is a flowchart illustrating a method for using a
photodetector with a bandwidth-tuned cell structure to measure
optical signals.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT
[0028] FIGS. 3A and 3B are, respectively, plan and partial
cross-sectional views of a photodiode with an optical path-aligned
electrode. The photodiode 300 is referred to as a vertical pillar
photodiode (VPD). The photodiode 300 comprises a semiconductor
layer 302 and a first electrode 304. The first electrode 304 is a
vertical plane structure including at least one pillar 306
extending into the semiconductor layer 302, where the vertical
plane is aligned with an optical path 308 and where a central axis
310 of the pillar is aligned with vertical plane. Second electrode
configurations are presented below, with variations in the first
electrode structure. As is true for all the other variations
presented below, the semiconductor layer 302 may be silicon (Si),
for example, epitaxially grown Si (epi-Si), Ge, Ge--Si compounds,
GaAs, InGaAs, and other III-V Group compounds. However, the
photodiode is not limited to any particular type of semiconductor
material. The first electrode pillar 306 is typically a metal, but
may alternatively be a doped semiconductor in some aspects.
[0029] FIGS. 4A and 4B are, respectively, plan and cross-sectional
views depicting a cell structure photodiode with an optical
path-aligned electrode. In this aspect, the first electrode 304
further comprises a doped semiconductor substrate 400 underlying
the semiconductor layer 302. The semiconductor layer 302 is formed
in a well in the semiconductor substrate 1300. The second electrode
is a vertical plane structure wall 402 surrounding the first
electrode pillar 306. The second electrode further comprises an
electrically conductive contact perimeter 404 overlying and in
contact with the wall 402. A first electrical contact region 406
overlies the top surface of a doped semiconductor substrate 400. A
second electrical contact region 408 overlies the semiconductor
layer 302 top surface and is connected to the second electrode
contact perimeter 404.
[0030] FIGS. 5A and 5B are, respectively, plan and partial
cross-sectional views of a photodetector with a bandwidth-tuned
cell structure. The photodetector 500 comprises a semiconductor
substrate 502 heavily doped with a first dopant. A plurality of
adjoining photodiode cells 504 are formed in a bandwidth-tuned
honeycomb structure. Each photodiode cell 504 comprises a
semiconductor substrate cavity 506 having shared walls 508 with
adjacent cells 504. Each cell 504 has from 1 to 6 cell walls. As
shown, each cell is a 6-sided hexagonal. FIG. 4A depicts a 1-sided
wall shown as a circle, but that alternatively the single wall may
be an oval. Although not expressly shown, 2-sided cells may be an
eye-shape, 3-sided cells might be formed as triangles, and 4-sided
cells as squares or rectangles, etc. Cells with more than 6 walls
are possible.
[0031] A semiconductor well 510 is formed in the semiconductor
substrate cavity 506, moderately doped with a second dopant
opposite in polarity to the first dopant. A metal pillar 512
extends into the semiconductor well 510, having a central axis 514
aligned with (parallel to) the optical path 516. A first electrode
is connected to the metal pillar 512 of each cell 504. A second
electrode is connected to the semiconductor substrate 502. For
clarity, the first and second electrodes are not shown, see FIG.
7A9.
[0032] As explained in greater detail below, the capacitance
between the first electrode and second electrode decreases in
response to increasing the number of cells 504, while decreasing
the diameter 522 of each cell well 510, and decreasing the diameter
524 of each metal pillar 512. Alternately stated, the photodetector
500, under bias conditions, provides a higher bandwidth response to
an optical input signal in response to increasing the number of
cells 504, decreasing the diameter 522 of each cell well 510, and
decreasing the diameter 524 of each metal pillar 512. In another
aspect the photodetector 500, under bias conditions, provides a
higher quantum efficiency (QE) response to an optical input signal
in response to decreasing the number of cells 504, increasing the
diameter 522 of each cell well 510, and increasing the diameter 524
of each metal pillar 512.
[0033] FIG. 6 is a partial cross-sectional view of a variation of
the photodetector of FIG. 5B, depicting one cell in detail. In this
aspect, the photodetector 500 operates at a wavelength in the range
of about 815 to 875 nanometers (nm), and the semiconductor well 510
is silicon. Each metal pillar 512 has an aspect ratio (L/d) of at
least 7:1, where L 600 is defined as a length of the metal pillar
512 from the cell well top surface 604, and d 602 is defined as the
metal pillar diameter at the top surface 604 of the cell well 510.
Each metal pillar 512 has a ratio d/d0 of less than 10:1, where d0
606 is defined as a metal pillar diameter at a bottom surface 608
of the cell well 510.
[0034] The VPD design concept, which forms the basis of the
bandwidth-tuned cell structure design, has an inherently lower
capacitance of parallel wire conductors, in comparison to parallel
plate conductors. In another aspect, the design is based upon the
lower capacitance of coaxial conductors, as contrasted to parallel
plate conductors of the same length and with the same distance
between conductors. Their vertical orientation makes the pillars
normal to the active layer orientation and parallel to the
direction of incident light. As described above, the interfinger
structure might be formed as a plurality of cells where a central
pillar of one polarity is surrounded by peripheral pillars of
opposite polarity arranged in hexagonal symmetry.
[0035] In another aspect, the VPD design may be realized as a
plurality of vertical approximately coaxial conductors built-in
into a semiconductor active layer. A central conducting pillar
forms an inner electrode and a surrounding conductive wall forms
the outer electrode of a single cell. The outer electrodes of
neighboring cells may merge to form continuous wall structure over
the whole active area of VPD, for example, in a honeycomb
structure.
[0036] The VPD design concept provides approximately the same QE at
the same active layer thickness with considerable lower
capacitance, in comparison with a LTD design (see FIG. 2). The
capacitances of VPD and LTD can be compared, as expressed per
active illuminated area [F/cm.sup.2]. As the upper margin estimate
of VPD capacitance, the following expression may be applied for
coaxial conductors:
Cltd ( W , L , d , ) := L D W 1 ( W + d ) D ( 1 ) Cvpd_coax ( W , L
, d , ) := 2 .pi. L ln ( 1 + 2 W d ) 1 .pi. ( W + d ) 2 ( 2 )
##EQU00001##
[0037] Where W is the distance between trenches for the LTD
structure, and the distance between a central pillar and peripheral
walls for VPD. Where D is the trench length (about equal to the
length of the active area), d is width of trenches for LTD, and
diameter of central pillar and thickness of peripheral wall
(assuming the wall thickness is the same as the central pillar) for
VPD. Where L is height or depth of trenches and pillars/walls, and
.epsilon. is dielectric constant of semiconductor. Both expressions
are a product of elementary cell capacitance [F] to the density of
elementary cells [cm.sup.-2] (inversely equal to elementary cell
area):
Cltd ( W , L , d , ) Cvpd_coax ( W , L , d , ) = 1 2 ln ( 1 + 2 W d
) ( 1 + d W ) ( 3 ) ##EQU00002##
[0038] The ratio of equation (3) is more than 1 for any W/d, and it
increases with the increase of W/d. For example, it is equal to 2
at W/d .about.10, which is reasonable practical value in an example
where W .about.3.5 um and d .about.0.4 um for conventional LTD
samples.
[0039] FIGS. 7A1 through 7A10 depict steps in alternative processes
for fabricating a cell structure photodetector. Each figure shows
plan and cross-sectional views. In FIG. 7A1 both processes begin
with a heavily doped substrate. In this example, the substrate 502
is an n++Si (heavily n-doped) wafer with a conductivity of less
than or equal to 0.01 ohm-cm. Note: an equivalent design may be
enabled using a p++ (heavily p-doped) substrate and reversing the
doping polarities described below. In FIG. 7A2 both processes
photoresist mask a honeycomb cell pattern. In this example the 3
cells cover an area of about 25 microns, but structures of greater
than 40 cells are possible.
[0040] In FIG. 7A3 both processes anisotropically etch to form
cavities 506 for epitaxy. In this example, the cavities have a
depth of about 10 microns (.mu.m). In FIG. 7A4 both processes form
epitaxy (epi) in the cavities to create semiconductor wells 510. In
this example the epitaxy is p-doped Si with a conductivity of
greater than or equal to 10 ohm-cm. A chemical-mechanical polish
(CMP) process follows.
[0041] In FIG. 7A5 a thin layer of oxide growth 700 is followed by
a thick oxide layer 702. The oxide 700/702 is planarized and then
annealed. In FIG. 7B5 the substrate is conformally coated with
photoresist 704 except for the center of the wells 510, which is
anisotropically etched. In this example, the openings 706 have a
diameter of about 140 microns at the level of the photoresist.
[0042] In FIG. 7A6 the substrate is conformally (completely) coated
with photoresist 708 except for the center of the wells 510, which
is anisotropically etched. For example, a reactive ion etching
process may be used to form openings 710. In FIG. 7B6 metal 712 is
deposited in the previously formed openings to form a pillar. For
example, the metal may be Al. An ohmic contact is formed with the
p-Si epi.
[0043] In FIG. 7A7 metal 714 is deposited in the previously formed
openings to form a pillar. An ohmic contact is formed with the p-Si
epi. In FIG. 7B7 the n++ substrate 502 is covered with a thick
insulator 716 such as oxide. A p+Si layer 718 is formed at the top
surface of the well 510. For example, the n-Si in the well 510 may
be implanted with p dopants.
[0044] In FIG. 7A8 a metal is deposited to contact pillars 512,
forming an electrode 720. For example, the metal may have a width
in the range of 130 to 140 nanometers (nm). Plan view a) is
associated with the cross-section view, while plan view b) is a
variation, both with the goal of minimizing light blockage. In FIG.
7B8 a metal 722 (e.g., Al) is deposited on the p-Si layer 718 to
form an electrode.
[0045] In FIGS. 7A9 and 7B9 metal 724 is deposited on the n++
substrate 502 to form the other electrode. The cross-section view
of FIG. 7A9 continues the variation of FIG. 7A8. The plan view of
FIG. 7A9 continues the variation of FIG. 7A8.
[0046] FIG. 7A10 depicts to plan view of FIG. 7A9 extended to a
19-cell design.
[0047] FIG. 8 is a partial cross-sectional view of a single cell
from the 19-cell design of FIG. 7A10 contrasting normal etched cell
walls with conic etched cell walls. The cell is design to operate
at 25 gigahertz (GHz) with a pillar upper diameter (d) of 20
microns. The cell etching process may be used to create a pillar
with a lower diameter d0 that is less than d, which advantageously
minimizes optical response delay associated with photons collected
in the lower portion of the cell. "W" is the space between the
semiconductor etched wall and the metal pillar.
[0048] FIG. 9 is a graph depicting the parameter of capacitance vs.
various etch dimensions of W (microns), cross-referenced to cell
design. Cell C0 represents normally etched cell walls and a normal
pillar shape (d=d0). C1 represents normally etched wall with a
conical pillar, and C2 represents conically etched walls with
conical pillar. C.sub.MSM and C.sub.PIN represent, respectively,
equivalent metal-semiconductor-metal (MSM) and PIN diode designs.
N.sub.CELL is the number of cells, ES is the dielectric constant of
the semiconductor material, and .epsilon.i is the dielectric
constant of the passivation layer.
[0049] FIG. 10 is a graph depicting the parameter of bandwidth vs.
W (microns) for various etch dimensions, cross-referenced to cell
design. The "vertical etch" trace represents a cell with normal
walls and normal pillar (d=d0), where D is the diameter of the
entire structure (aggregating all the cells in the system) and R is
the resistivity of the pillar material.
[0050] FIG. 11 is a graph depicting the parameter of bandwidth vs.
quantum efficiency (QE), cross-referenced to cell design.
[0051] FIG. 12 is a plan view of a 61-cell 5-layer photodetector.
The accompanying chart describes parameters associated with 1
through 8-layer photodetectors. The parameters include cell
diameter (Ndiam), number of cells of the periphery (Nperif), the
total number of walls (Nwalls), and the cell surface area. Here,
the layers are shown as concentric circles.
[0052] In one aspect, the photodetector comprises a plurality of
selectively engagable layers, where each layer includes at least on
photodiode cell. For example, in the depicted S-layer design the
first layer (e.g., the center cell) may be selectively engaged
(biased) while the second layer (surrounding the center cell) is
not enabled. In this manner, the photodetector may "focused" with
layer combinations, power usage minimized, or bandwidth
characteristics modified. Alternatively, the layers need not be
organized as concentric circles. For example, a 2-layer design may
comprise top half (semi-circle) and bottom half (semi-circle) cell
layers. A 4-layer design may comprise layers organized as
quadrants, and a multi-layer design may comprise pie-shaped cell
sections. Other layering shapes are also possible.
[0053] FIG. 13 is a graph depicting the parameter of bandwidth vs.
W, cross-referenced to the number of cells (Ncell). For all
variations d=1 micron, dw=1 micron, the strip width of the
overlying metal electrode connection is 1 micron, and L=10
microns.
[0054] FIG. 14 is a graph depicting the parameter of bandwidth vs.
QE, cross-referenced to the number of cells.
[0055] FIG. 15 is a graph depicting the parameter of bandwidth vs.
QE, cross-referenced to variations in pillar length (L). The number
of cells for all variations is 19. The PIN photodiode (PD) has a
diameter of 20 microns.
[0056] FIG. 16 is a table describing the relationship between the
number of cell layers, W, bandwidth, QE, and cell area. For
example, a 19-cell design (3 layers) has a QE of 27% at a bandwidth
of 20 GHz using a pillar length (L) of 12 microns. These
calculations do not include the effects of stray capacitance and
resistance.
[0057] FIG. 17 is a flowchart illustrating a method for fabricating
a photodetector with a bandwidth-tuned cell structure. Although the
method is depicted as a sequence of numbered steps for clarity, the
numbering does not necessarily dictate the order of the steps. It
should be understood that some of these steps may be skipped,
performed in parallel, or performed without the requirement of
maintaining a strict order of sequence. Generally however, the
method follows the numeric order of the depicted steps. The method
starts at Step 1700.
[0058] Step 1702 provides a semiconductor substrate heavily doped
with a first dopant. Step 1704 forms a plurality of adjoining
cavities in the semiconductor substrate having shared cell walls.
The cavities may have any number of cell walls, although a number
from 1 to 6 is typical, where a 1-sided wall is defined by an oval
or circular shape. Step 1706 forms a semiconductor well in each
cavity, moderately doped with a second dopant opposite in polarity
to the first dopant. Step 1708 grows a layer of oxide overlying the
semiconductor wells. Step 1710 anneals the semiconductor wells.
Step 1712 forms a metal pillar extending into each semiconductor
well having a central axis aligned with an optical path. Step 1714
forms a first electrode connected to the metal pillar of each cell.
Step 1716 forms a second electrode connected to the semiconductor
substrate.
[0059] In one aspect, Step 1718 decreases capacitance between the
first and second electrodes in response to forming an increased
number of semiconductor wells with a reduced diameter, and forming
metal pillars with a reduced diameter. In another aspect, Step 1720
provides a bias voltage to the first and second electrodes. Step
1722 accepts an optical signal.
[0060] Step 1724 measures a higher bandwidth in response to forming
an increased number of semiconductor wells with a reduced diameter,
and forming metal pillars with a reduced diameter. Alternatively,
Step 1726 measures a higher quantum efficiency (QE) in response to
forming a decreased number of semiconductor wells with an increased
diameter, and forming metal pillars with an increases diameter.
[0061] In another aspect, Step 1722 supplies an optical signal at a
wavelength in a range of about 815 to 875 nanometers (nm), and Step
1706 forms semiconductor wells of silicon. Then, forming the metal
pillars in Step 1712 includes substeps. Step 1712a forms an opening
in each semiconductor well having an aspect ratio (L/d) of at least
7:1, where L is defined as a depth of the opening and d is defined
as the opening diameter at a top surface of the cell well. Step
1712b deposits metal in the opening. In one aspect, Step 1712a
forms openings having a ratio d/d0 of less than 10:1, where d0 is
defined as the opening diameter at a bottom surface of the cell
well.
[0062] FIG. 18 is a flowchart illustrating a method for using a
photodetector with a bandwidth-tuned cell structure to measure
optical signals. The method starts at Step 1800. Step 1802 provides
a photodetector with a plurality of adjoining photodiode cells
formed in a bandwidth-tuned honeycomb structure, where each cell
comprises a metal pillar extending into a semiconductor well,
having a central axis aligned with an optical path. Step 1804
accepts a bias voltage between first and second electrodes of the
photodetector. Step 1806 accepts an optical signal. Step 1808
measures a higher bandwidth response to forming an increased number
of semiconductor wells with a reduced diameter, and forming metal
pillars with a reduced diameter. In one aspect, Step 1810 measures
a higher quantum efficiency (QE) in response to forming a decreased
number of semiconductor wells with an increased diameter, and
forming metal pillars with an increases diameter.
[0063] In another aspect, Step 1802 provides a photodetector having
silicon semiconductor walls, metal pillars having an aspect ratio
(L/d) of at least 7:1, where L is defined as a length of the metal
pillar and d is defined as a metal pillar diameter at a top surface
of the cell well. The metal pillars have a ratio d/d0 of less than
10:1, where d0 is defined as a metal pillar diameter at a bottom
surface of the cell well. Step 1806 accepts an optical signal
having a wavelength in a range of about 815 to 875 nm.
[0064] A photodetector has been presented with a bandwidth-tuned
cell structure. Examples of particular topologies, geometries,
materials, and process steps have been presented to illustrate the
invention. However, the invention is not limited to merely these
examples. Other variations and embodiments of the invention will
occur to those skilled in the art.
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