U.S. patent application number 13/827475 was filed with the patent office on 2014-07-17 for programming technique for reducing program disturb in stacked memory structures.
This patent application is currently assigned to MACRONIX INTERNATIONAL CO, LTD.. The applicant listed for this patent is KUO-PIN CHANG, TI-WEN CHEN, CHIH-CHANG HSIEH, SHIH-LIN HUANG, CHUN-HSIUNG HUNG, Shuo-Nan Hung, HANG-TING LUE. Invention is credited to KUO-PIN CHANG, TI-WEN CHEN, CHIH-CHANG HSIEH, SHIH-LIN HUANG, CHUN-HSIUNG HUNG, Shuo-Nan Hung, HANG-TING LUE.
Application Number | 20140198576 13/827475 |
Document ID | / |
Family ID | 51146239 |
Filed Date | 2014-07-17 |
United States Patent
Application |
20140198576 |
Kind Code |
A1 |
Hung; Shuo-Nan ; et
al. |
July 17, 2014 |
PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED
MEMORY STRUCTURES
Abstract
A programming bias technique is described for programming a
stacked memory structure with a plurality of layers of memory
cells. The technique includes the controller circuitry responsive
to a program instruction to program data in target cells in a stack
of cells at a particular multibit address. The circuitry is
configured to use an assignment of cells in the stack of cells to a
plurality of sets of cells, and to iteratively execute a set
program operation selecting each of the plurality of sets in
sequence. Each iteration includes applying inhibit voltages to all
of the cells in others of the plurality of sets. Also, each set of
layers includes subsets of one or two, and there are at least two
layers from other sets separating each of the subsets in one
set.
Inventors: |
Hung; Shuo-Nan; (HSINCHU,
TW) ; LUE; HANG-TING; (HSINCHU, TW) ; CHEN;
TI-WEN; (TAINAN, TW) ; HUANG; SHIH-LIN;
(PENGHU, TW) ; CHANG; KUO-PIN; (MIAOLI, TW)
; HSIEH; CHIH-CHANG; (HSINCHU, TW) ; HUNG;
CHUN-HSIUNG; (HSINCHU, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Hung; Shuo-Nan
LUE; HANG-TING
CHEN; TI-WEN
HUANG; SHIH-LIN
CHANG; KUO-PIN
HSIEH; CHIH-CHANG
HUNG; CHUN-HSIUNG |
HSINCHU
HSINCHU
TAINAN
PENGHU
MIAOLI
HSINCHU
HSINCHU |
|
TW
TW
TW
TW
TW
TW
TW |
|
|
Assignee: |
MACRONIX INTERNATIONAL CO,
LTD.
Hsinchu
TW
|
Family ID: |
51146239 |
Appl. No.: |
13/827475 |
Filed: |
March 14, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61752985 |
Jan 16, 2013 |
|
|
|
Current U.S.
Class: |
365/185.18 |
Current CPC
Class: |
G11C 11/5628 20130101;
G11C 16/10 20130101; G11C 2211/5621 20130101; H01L 27/11578
20130101; G11C 16/0483 20130101; G11C 16/3459 20130101; G11C
2216/14 20130101; H01L 27/11551 20130101 |
Class at
Publication: |
365/185.18 |
International
Class: |
G11C 16/10 20060101
G11C016/10 |
Claims
1. A method of operating a memory including a stacked memory
structure, wherein multibit addresses map to corresponding memory
cells disposed in a plurality of layers, comprising: responsive to
a program instruction to store data in a set of memory cells
corresponding to a particular multibit address, executing a program
operation limited to memory cells in a first set of layers that
include memory cells in said set of memory cells, said first set
including subsets of one or more of the layers in said first set of
layers, where the subsets of the first set are separated from other
subsets of the first set by at least two layers that are not
members of the first set, and then completing programming if
necessary of remaining memory cells in said set of memory
cells.
2. The method of claim 1, wherein the program operation causes one
or more memory cells in the first set of layers to change to a
programmed state and to inhibit changes in state in memory cells to
memory cells in a second set of layers that include memory cells in
said set of memory cells; the program operation including applying
a bias arrangement that includes: (i) a program voltage applied to
the one or more of the memory cells in the first set of layers, and
(ii) an inhibit voltage applied to all memory cells in the second
set of layers; and if data to be stored requires a change of state
of memory cells in the second set of layers, then executing another
program operation, to cause one or more memory cells in the second
set of layers to change to a programmed state.
3. The method of claim 2, wherein said another program operation
includes applying a second bias arrangement that includes: (i) a
program voltage applied to the one or more of the memory cells in
the second set, and (ii) an inhibit voltage applied to all memory
cells in the first set of the plurality of layers.
4. The method of claim 2, wherein said first mentioned program
operation is configured so that the first set includes a first
subset including a first pair of layers and a third subset
including a third pair of layers and the second set includes a
first subset including a second pair of layers, and wherein the
first pair of layers and the third pair of layers are separated by
the second pair of layers.
5. The method of claim 4, wherein at least one memory cell in the
first pair of layers and at least one memory cell in the third pair
of layers are programmed during the first mentioned program
operation.
6. The method of claim 4, wherein the second set includes a second
subset including a fourth pair of layers, the second pair of layers
and the fourth pair of layers being separated by the third pair of
layers, and in which at least one memory cell in the second pair of
layers and at least one memory cell in the fourth pair of layers
are programmed during the second mentioned another program
operation.
7. The method of claim 1, wherein the program bias arrangement
includes the inhibit voltage applied to memory cells in the
corresponding memory cells in the first set of the plurality of
layers for which no change in state is needed to store the
data.
8. The method of claim 1, further including identifying memory
cells in the corresponding memory cells for which a change in state
is needed to store the data, and if possible assigning memory cells
to the first set of the plurality of layers so that it includes all
of the identified memory cells.
9. The method of claim 1, wherein the plurality of layers includes
said first set of layers, a second set of layers and a third set of
layers, the layers in the second set of layers being separated by
one layer in the third set of layers and one layer in the first
set, and including: after applying said first mentioned program
operation, applying a second program operation for cells in the
second set, and then applying a third program operation for cells
in the third set.
10. A memory comprising: a stacked memory structure with layers of
memory cells, wherein multibit addresses map to corresponding
memory cells disposed in a plurality of layers; circuitry coupled
to the stacked memory structure, the logic and control circuitry
configured to: respond to a program instruction to store data in a
set of memory cells corresponding to a particular multibit address,
by executing a program operation limited to memory cells in a first
set of layers that include memory cells in said set of memory
cells, said first set including subsets of one or more of the
layers in said first set of layers, where the subsets of the first
set are separated from other subsets of the first set by at least
two layers that are not members of the first set, and then
completing programming if necessary of remaining memory cells in
said set of memory cells
11. The memory of claim 10, wherein the program operation causes
one or more memory cells in the first set of layers to change to a
programmed state and to inhibit changes in state in memory cells in
a second set of layers in the plurality of layers; the program
operation including applying a bias arrangement that includes: (i)
a program voltage applied to the one or more of the memory cells in
the first set of layers, and (ii) an inhibit voltage applied to all
memory cells in the second set of layers; and the logic and control
circuitry responsive to the program instruction to program data at
the particular multibit address being configured to, if data to be
stored requires a change of state of memory cells in the second set
of layers, then executing another program operation, to cause one
or more memory cells in the second set of layers to change to a
programmed state.
12. The memory of claim 11, wherein said another program operation
includes applying a second bias arrangement that includes: (i) a
program voltage applied to the one or more of the memory cells in
the second set, and (ii) an inhibit voltage applied to all memory
cells in the first set of the plurality of layers.
13. The memory of claim 12, wherein said first mentioned program
operation is configured so that the first set includes a first
subset including a first pair of layers and a third subset
including a third pair of layers and the second set includes a
first subset including a second pair of layers, and wherein the
first pair of layers and the third pair of layers are separated by
the second pair of layers.
14. The memory of claim 13, wherein at least one memory cell in the
first pair of layers and at least one memory cell in the third pair
of layers are programmed during the first mentioned program
operation.
15. The memory of claim 13, wherein the second set includes a
second subset including a fourth pair of layers, the second pair of
layers and the fourth pair of layers being separated by the third
pair of layers, and in which at least one memory cell in the second
pair of layers and at least one memory cell in the fourth pair of
layers are programmed during said another program operation.
16. The memory of claim 11, wherein the program bias arrangement
includes the inhibit voltage applied to memory cells in the set of
corresponding memory cells in the first set of the plurality of
layers for which no change in state is needed to store the
data.
17. The memory of claim 11, the logic and control circuitry
responsive to the program instruction to program data at the
particular multibit address being configured to identify memory
cells in the corresponding memory cells for which a change in state
is needed to store the data, and if possible assign memory cells to
the first set of the plurality of layers so that it includes all of
the identified memory cells.
18. The memory of claim 11, wherein the plurality of layers
includes said first set of layers, a second set of layers and a
third set of layers, the layers in the second set of layers being
separated by one layer in the third set of layers and one layer in
the first set, and including: the logic and control circuitry
responsive to the program instruction to program data at the
particular multibit address being configured to, after applying
said first mentioned program operation, apply a second program
operation for cells in the second set, and then apply a third
program operation for cells in the third set.
19. A memory comprising: a stacked memory structure with layers of
memory cells; circuitry coupled to the stacked memory structure,
the circuitry responsive to a program instruction to program data
in target cells in a stack of cells at a particular multibit
address, the circuitry configured to use an assignment of cells in
the stack of cells to a plurality of sets of cells, and to
iteratively execute a set program operation selecting each of the
plurality of sets in sequence, where each iteration includes
applying program voltages to target cells in a selected one of the
plurality of sets, inhibit voltages to remaining cells in said
selected one of the plurality of sets, and inhibit voltages to all
of the cells in others of the plurality of sets.
20. The memory of claim 19, wherein the sets in the plurality of
sets include subsets of cells in the stack, including a first
subset in a given set and a second subset in the given set, where
assignment of cells to the first and second subsets insures that no
cells in the first subset are disposed in layers separated by only
one layer from layers including a cell in the second subset.
21. The memory of claim 19, wherein assignment groups cells in sets
so no cell having inhibit voltages applied is in a layer of the
stack between two layers in which cells are having programming
applied.
22. The memory of claim 19, wherein assignment groups cells in sets
so no cell having programming voltages applied is in a layer of the
stack adjacent any layer including a cell that is having
programming voltages applied.
23. The memory of claim 22, wherein assignment groups cells in sets
so no cell having inhibit voltages applied is in a layer of the
stack between two layers in which cells are having programming
applied.
24. The memory of claim 19, wherein the group program operation
includes logic to skip a selected set if there are no target cells
in the set.
Description
RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Patent Application No. 61/752,985 filed on 16 Jan. 2013, which
application is incorporated by reference as if fully set forth
herein.
BACKGROUND
[0002] 1. Field of the Invention
[0003] The present invention relates to high density memory
devices, and particularly the operation of devices using stacked
memory structures.
[0004] 2. Description of Related Art
[0005] As critical dimensions of devices in integrated circuits
shrink, designers have been looking to techniques for stacking
multiple planes of memory cells to achieve greater storage
capacity, and to achieve lower costs per bit. For example, thin
film transistor techniques are applied to charge trapping memory
technologies in Lai, et al., "A Multi-Layer Stackable Thin-Film
Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron
Devices Meeting, 11-13 Dec. 2006; and in Jung et al., "Three
Dimensionally Stacked NAND Flash Memory Technology Using Stacking
Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30
nm Node," IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
[0006] Also, cross-point array techniques have been applied for
anti-fuse memory in Johnson et al., "512-Mb PROM With a
Three-Dimensional Array of Diode/Anti-fuse Memory Cells," IEEE J.
of Solid-State Circuits, vol. 38, no. 11, November 2003. In the
design described in Johnson et al., multiple layers of word lines
and bit lines are provided, with memory elements at the
cross-points.
[0007] Another structure that provides vertical NAND cells in a
charge trapping memory technology is described in Tanaka et al.,
"Bit Cost Scalable Technology with Punch and Plug Process for Ultra
High Density Flash Memory," 2007 Symposium on VLSI Technology
Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15. The
structure described in Tanaka et al. includes a multi-gate field
effect transistor structure having a vertical channel which
operates like a NAND gate, using
silicon-oxide-nitride-oxide-silicon SONOS charge trapping
technology to create a storage site at each gate/vertical channel
interface.
[0008] 3D memory structures are very dense, but the density can
lead to problems with data retention. For example, a programming
operation for a selected cell can disturb the data stored in other
cells. Thus, it is desirable to provide for a technology for
programming 3D memories with improved data retention.
SUMMARY
[0009] Technology for programming data in a stacked memory
structure is described. The technology can mitigate program disturb
conditions, and thereby improve endurance of memory devices. A
program operation is initiated when a memory device receives a
program instruction to program data to a particular multibit
address which is mapped to a set of memory cells in a plurality of
layers of the stacked memory structure. The set of memory cells, to
which the multibit address is mapped, are organized for the
purposes of the programming into those in a first set of layers and
those in a second set of layers. The layers are organized so that
no two layers in the first set are separated by only one layer in
the second set. Thus, for example, the layers in the first set can
be separated by two or more layers in the second set, or can be
adjacent only layers in the first set (i.e. not separated by a
layer in the second set). Also, the layers are assigned so that the
first set includes a plurality of subsets of one or more layers,
where each of the subsets is separated from other subsets of the
first set by at least two layers.
[0010] According to this technique, responsive to a program
instruction to store data at the particular multibit address, a
program operation is executed that is limited to memory cells in a
first set of subsets of layers in the plurality of layers, where
the subsets of layers in the first set are separated from other
subsets in the first set by at least two layers, and then
completing programming if necessary of remaining memory cells for
the multibit address. As a result of the first program operation,
one or more of the memory cells in the first subset for the
corresponding multibit address are programmed.
[0011] According to this technique a second program operation can
be applied that includes applying program voltage to one or more of
the corresponding memory cells in the second set and an inhibit
voltage to the memory cells in the first set.
[0012] In one alternative, a set of memory cells corresponding to
the multibit address can include some cells that do not need to be
changed and some that do need to be changed to a programmed state,
as can be identified based upon the data to be programmed and upon
which of the corresponding memory cells are already in a programmed
state. The first set of layers can be selected when possible for
each program instruction, so that the first programming operation
is able to complete the programming operations in some instances,
so that the second programming operation is not needed. In this
case, and also when the first and second sets are statically
configured, the second program operation can be applied only if the
state of at least one memory cell in the second set needs to be
changed to a programmed state.
[0013] In another aspect, the technology described herein provides
a memory device including stacked memory cells which is configured
to use an assignment of cells in the stack of cells to a plurality
of sets of cells, and to iteratively execute a group program
operation selecting each of the plurality of sets in sequence. In
each iteration, the group program operation includes applying
program voltages to target cells in a selected one of the plurality
of sets, inhibit voltages to remaining cells in said selected one
of the plurality of sets, and inhibit voltages to all of the cells
in others of the plurality of sets.
[0014] Other aspects and advantages of the present invention can be
seen on review of the drawings, the detailed description and the
claims, which follow.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a perspective illustration of a 3D NAND-flash
memory array structure.
[0016] FIG. 2 is a layout view of the 3D NAND-flash memory array
structure of FIG. 1 showing an example of a programming bias
arrangement.
[0017] FIGS. 3A-3C show a stacked memory structure made up of three
bit lines and the various voltage levels that can exist on the bit
lines during a program operation.
[0018] FIG. 3D is a graph of voltage levels shown in FIGS.
3A-3C.
[0019] FIG. 4 shows voltages on the bit lines in a stacked memory
structure during a programming technique.
[0020] FIG. 5 is a flowchart of steps executed by a controller in
an alternate programming technique.
[0021] FIG. 6 shows an example organization of memory cells in the
stacked memory structure.
[0022] FIGS. 7 and 8 show the stacked memory structure with the
organization of FIG. 6 with voltage levels in bit lines during the
performance of corresponding first and second programming
operations of the programming technique shown in FIG. 5.
[0023] FIG. 9 is a flowchart of steps executed by a controller in
another alternate programming technique.
[0024] FIGS. 10A-10C show a stacked memory structure made up of two
bit lines and the various voltage levels that can exist on the bit
lines during a program operation.
[0025] FIG. 11 is a graph of the threshold voltage (Vt) of the
memory cells formed with the structure and applied voltages of FIG.
10A as a function of an increasing voltage level of the voltage
applied to the word line through ISPP.
[0026] FIG. 12 shows another example organization of memory cells
in the stacked memory structure during programming.
[0027] FIG. 13 is a flowchart of steps executed by a controller in
yet another programming technique.
[0028] FIG. 14 is a block diagram of an integrated circuit memory
employing memory cells and bias circuitry according to embodiments
of the present invention with a stacked memory structure having
modified programming logic as described herein.
DETAILED DESCRIPTION
[0029] A detailed description of embodiments is provided with
reference to the FIGS. 1-14.
[0030] FIG. 1 is a perspective illustration of a 3D NAND-flash
memory array structure. The 3D NAND-flash memory array structure is
described in commonly owned U.S. patent application Ser. No.
13/078,311 filed 1 Apr. 2011, entitled "Memory Architecture of 3D
Array With Alternating Memory String Orientation and String Select
Structures," now Publication No. US-2012-0182806, (MXIC 1960-2)
which is hereby incorporated by reference as if fully set forth
herein. It is appreciated that alternative 3D NAND-flash memory
array structures exist as are described in Chen et al. Insulating
material is removed from the drawing to expose additional
structure. For example, insulating layers are removed between the
semiconductor strips, in the ridge-shaped stacks, and are removed
between the ridge-shaped stacks of semiconductor strips. The 3D
NAND-flash memory array structure includes stacked memory
structures resulting in the array having a plurality of memory
cells disposed in a dense configuration. As a result of the
plurality of memory cells being disposed in a dense configuration,
problems with data retention are observed in the 3D-NAND flash
memory array shown in FIG. 1.
[0031] The multilayer array is formed on an insulating layer, and
includes a plurality of word lines 125-1, . . . , 125-N. The
plurality of ridge-shaped stacks includes semiconductor strips 112,
113, 114, 115. Semiconductor strips in the same plane are
electrically coupled together by pads 102B, 103B, 104B, 105B, which
are connected to overlying metal lines in ML3 using stairstep
structures.
[0032] The shown word line numbering, ascending from 1 to N going
from the back to the front of the overall structure, applies to
even memory pages. For odd memory pages, the word line numbering
descends from N to 1 going from the back to the front of the
overall structure.
[0033] Stairstep pads 112A, 113A, 114A, 115A terminate
semiconductor strips, such as semiconductor strips 112, 113, 114,
115. As illustrated, these stairstep pads 112A, 113A, 114A, 115A
are electrically connected to different bit lines for connection to
decoding circuitry to select planes within the array. These
stairstep pads 112A, 113A, 114A, 115A can be patterned at the same
time that the plurality of ridge-shaped stacks are defined.
[0034] Stairstep pads 102B, 103B, 104B, 105B terminate
semiconductor strips, such as semiconductor strips 102, 103, 104,
105. As illustrated, these stairstep pads 102B, 103B, 104B, 105B
are electrically connected to different bit lines for connection to
decoding circuitry to select planes within the array. These
stairstep pads 102B, 103B, 104B, 105B can be patterned at the same
time that the plurality of ridge-shaped stacks are defined.
[0035] Any given stack of semiconductor strips is coupled to either
the stairstep pads 112A, 113A, 114A, 115A, or the stairstep pads
102B, 103B, 104B, 105B, but not both. A stack of semiconductor
strips has one of the two opposite orientations of bit line
end-to-source line end orientation, or source line end-to-bit line
end orientation. For example, the stack of semiconductor strips
112, 113, 114, 115 has bit line end-to-source line end orientation,
and the stack of semiconductor strips 102, 103, 104, 105 has source
line end-to-bit line end orientation.
[0036] The stack of semiconductor strips 112, 113, 114, 115 is
terminated at one end by the stairstep pads 112A, 113A, 114A, 115A,
and passes through SSL gate structure 119, gate select line GSL
126, word lines 125-1 WL through 125-N WL, gate select line GSL
127, and terminates at the other end by source line 128. The stack
of semiconductor strips 112, 113, 114, 115 does not reach the
stairstep pads 102B, 103B, 104B, 105B.
[0037] The stack of semiconductor strips 102, 103, 104, 105 is
terminated at one end by the stairstep pads 102B, 103B, 104B, 105B,
and passes through SSL gate structure 109, gate select line GSL
127, word lines 125-N WL through 125-1 WL, gate select line GSL
126, and terminates at the other end by a source line (obscured by
other parts of the figure). The stack of semiconductor strips 102,
103, 104, 105 does not reach the stairstep pads 112A, 113A, 114A,
115A.
[0038] A layer of memory material separates the word lines 125-1
through 125-n, from the semiconductor strips 112-115 and 102-105.
Ground select lines GSL 126 and GSL 127 are conformal with the
plurality of ridge-shaped stacks, similar to the word lines.
[0039] Every stack of semiconductor strips is terminated at one end
by a set of stairstep pads, and at the other end by a source line.
For example, the stack of semiconductor strips 112, 113, 114, 115
is terminated at one end by stairstep pads 112A, 113A, 114A, 115A,
and terminated on the other end by source line 128. At the near end
of the figure, every other stack of semiconductor strips is
terminated by the stairstep pads 102B, 103B, 104B, 105B, and every
other stack of semiconductor strips is terminated by a separate
source line. At the far end of the figure, every other stack of
semiconductor strips is terminated by the stairstep pads 112A,
113A, 114A, 115A, and every other stack of semiconductor strips is
terminated by a separate source line.
[0040] Bit lines and string select lines are formed at the metals
layers ML1, ML2, and ML3. Local bit lines for each string of memory
cells are formed by the semiconductor strips.
[0041] Transistors are formed between the stairstep pads 112A,
113A, 114A and the word line 125-1. In the transistors, the
semiconductor strip (e.g. 113) acts as the channel region of the
device. SSL gate structures (e.g. 119, 109) are patterned during
the same step that the word lines 125-1 through 125-n are defined.
A layer of silicide can be formed along the top surface of the word
lines, the ground select lines, and over the gate structures. A
layer of memory material can act as the gate dielectric for the
transistors. These transistors act as string select gates coupled
to decoding circuitry for selecting particular ridge-shaped stacks
in the array.
[0042] FIG. 2 is a layout view of the 3D NAND-flash memory array
structure of FIG. 1 showing an example of a programming bias
arrangement.
[0043] In the layout view of FIG. 2, the stacks of semiconductor
strips are shown as vertical strips with dot-dash borders. Adjacent
stacks of semiconductor strips alternate between the opposite
orientations, of bit line end-to-source line end orientation, and
source line end-to-bit line end orientation. Every other stack of
semiconductor strips runs from the bit line structure at the top to
the source line at the bottom. Every other stack of semiconductor
strips runs from the source line at the top to the bit line
structure at the bottom.
[0044] Overlying the stacks of semiconductor strips, are the
horizontal word lines and the horizontal ground select lines GSL
(even) and GSL (odd). Also overlying the stacks of semiconductor
strips, are the SSL gate structures. The SSL gate structures
overlie every other stack of semiconductor strips at the top end of
the semiconductor strips, and overlie every other stack of
semiconductor strips at the bottom end of the semiconductor strips.
In either case, the SSL gate structures control electrical
connection between any stack of semiconductor strips and the
stack's corresponding bit line contact pads.
[0045] The shown word line numbering, ascending from 1 to N going
from the top of the figure to the bottom of the figure, applies to
even memory pages. For odd memory pages, the word line numbering
descends from N to 1 going from the top of the figure to the bottom
of the figure.
[0046] Overlying the word lines, ground select lines, and SSL gate
structures, are the ML1 SSL string select lines running vertically.
Overlying the ML1 SSL string select lines are the ML2 SSL string
select lines running horizontally. Although the ML2 SSL string
select lines are shown as terminating at corresponding ML1 SSL
string select lines for ease of viewing the structure, the ML2 SSL
string select lines may run longer horizontally. The ML2 SSL string
select lines carry signals from the decoder, and the ML1 SSL string
select lines couple these decoder signals to particular SSL gate
structures to select particular stacks of semiconductor strips.
[0047] Also overlying the ML1 SSL string select lines are the
source lines, even and odd.
[0048] Further, overlying the ML2 SSL string select lines are the
ML3 bit lines (not shown) which connect to the stepped contact
structures at the top and the bottom. Through the stepped contact
structures, the bit lines select particular planes of semiconductor
strips.
[0049] Particular bit lines are electrically connected to different
planes of semiconductor strips that form local bit lines. Under the
programming bias arrangement shown, the particular bit lines, are
biased at either Vcc (inhibit) or 0V (program), which voltage
levels are representative of inhibit set up and program voltages
that can have other values. The SSL of the selected stack of
semiconductor strips is at Vcc, and all other SSLs are 0V. For this
semiconductor strip in an "odd" stack being programmed, the GSL
(even) is turned on at Vcc to allow the bit line bias to pass, and
the GSL (odd) is turned off at 0V to disconnect the source line
(odd). Source line (even) is at Vcc for self-boosting to avoid
disturb of adjacent even pages. The word lines are at Vpass
voltages, except for the selected word line which undergoes
incremental step pulsed programming ISPP in which pulses are
applied having stepped voltages, which can include pulses having
voltage levels on the order of 21V for example.
[0050] The shown memory unit is repeated above and below, sharing
the same bit lines. These repeated units can also be programmed at
the same time.
[0051] If, instead, a semiconductor strip in an "even" stack is
being programmed, then the odd and even signals are switched.
[0052] FIGS. 3A-3C show a stacked memory structure made up of three
bit lines and the various voltage levels that can exist on the bit
lines during a program operation. The stacked memory structure 300
includes first bit line 302, a second bit line 304 and a third bit
line 306. Insulating layers 308 and 310 are disposed between the
first, second and third bit lines 302, 304 and 306. The bit lines
are electrically coupled to corresponding memory cells in first,
second and third layers of memory cells in the stacked memory
structure 300. The first, second and third layers of memory cells
correspond to the first, second and third bit lines. For purposes
of illustration, the memory material layers and the surrounding
word line are not shown.
[0053] The various voltage levels in the bit lines that are shown
in FIGS. 3A-3C are the voltage levels that occur as a result of the
unselected bit line being connected to a positive voltage like Vcc
to set up for inhibit voltages, and the selected bit line being
coupled to a lower voltage line OV. During a program pulse on a
word line targeting a selected bit line, the unselected bit lines
are boosted by coupling to the word line. FIG. 3D is a graph of
voltage levels shown in FIGS. 3A-3C.
[0054] For the stacked memory structure shown in FIG. 3A, during a
first interval of a program operation a voltage at an inhibit set
up voltage level, is set up on the first, second and third bit
lines 302, 304 and 306. The inhibit set up voltage level can be,
for example, Vcc between 2.5 and 3.6V. At the end of the first
interval, the string select switches and ground select switches
that are coupled to the first, second and third bit lines are
opened. As a result, during a second interval after the first
interval, the first, second and third bit lines 302, 304 and 306
are left floating with a voltage at the inhibit set upvoltage
level. During the second interval, a voltage is set up through ISPP
on the word line (not shown) that is electrically coupled to
corresponding memory cells in the first, second and third layers of
memory cells of the stacked memory structure 300.
[0055] As all three of the bit lines are left floating during the
second interval, the setting up of the voltage through ISPP on the
word line causes boosting of the voltages on all three of the
first, second and third bit lines 302, 304 and 306 to a Vinhibit1
voltage level. This boosting is caused by capacitive coupling
between the word lines and the bit lines. The Vinhibit1 voltage
level is roughly equal to the sum of the inhibit set up voltage
level and the amount that the voltage on the bit lines is increased
as a result of the boosting, depending on the coupling
efficiency.
[0056] For the stacked memory structure shown in FIG. 3B, during a
first interval of a program operation a voltage with the inhibit
set upvoltage level isset up on the second and third bit lines 304
and 306. Also during the first interval, a voltage with a
programming (Vpgm) voltage level is set up on the first bit line
302. The Vpgm voltage level is less than the inhibit set up voltage
level. For example, the Vpgm voltage level can be 0V. At the end of
the first interval, the string select switches and ground select
switches that are coupled to the second and third bit lines 304 and
406 are open. As a result, during a second interval after the first
interval, the second and third bit lines are left floating with a
voltage at the inhibit set up voltage level. The string select
switch and the ground select switch that are coupled to the first
bit line 302 remain closed during the second interval. As a result,
the first bit line is not left floating and remains at a voltage at
the Vpgm voltage level during the second interval.
[0057] Also during the second interval, a word line voltage pulse
with a voltage level up to 21V is set up, for example using ISPP
techniques, on the word line that is electrically coupled to the
corresponding memory cells in the first, second and third layers of
the stacked memory structure 300. The word line voltage pulse
causes boosting of the voltage on the third bit line 306 up to the
Vinhibit1 voltage level, in the same manner as was discussed with
respect to FIG. 3A.
[0058] The second bit line 304 is capacitively coupled to both the
word line and the first bit line 302. The word line voltage pulse
causes the voltage on the second bit line to be boosted up as a
result of capacitive coupling with the word line. However, the
amount the voltage on the second bit line is boosted is reduced as
a result of the voltage on the first bit line 302 at a Vpgm voltage
level. As a result, the voltage on the second bit line is boosted
to a Vinhibit2 voltage level that is different than the Vinhibit1
voltage level. As shown in FIG. 3D, the Vinhibit2 voltage level is
less than the Vinhibit1 voltage level. The lower Vinhibit2 can
increase the likelihood that a memory cell will be disturbed on the
unselected line. However, using the technology described herein,
the programming bias arrangement can be configured to account for
this voltage shift, so that program disturb in this situation can
be suppressed.
[0059] For the stacked memory structure shown in FIG. 3C, during a
first interval of a program operation, a voltage with an inhibit
set up voltage level is set up on the second bit line 304. Also,
during the first interval, a voltage with a Vpgm voltage level is
set up on the first and third bit lines 302 and 306. At the end of
the first interval, the string select switch and the ground select
switch that are coupled to the second bit line 304 are open. As a
result, during a second interval after the first interval, the
second bit line 304 is left floating with a voltage at the inhibit
set up voltage level (e.g. Vcc).
[0060] During the second interval, word line voltage pulse is
applied to the word line that is electrically coupled to the
corresponding memory cells in the first, second and third layers of
memory cells of the stacked memory structure 300. Meanwhile, during
the second interval, the string select and ground select switches
that are coupled to the first and third bit lines 302 and 306
remain closed. As a result, the first and third bit lines are left
non-floating with a voltage at the Vpgm voltage level during the
second interval. The second bit line 304 is capacitively coupled to
both the word line and the first and third bit lines 302 and 306.
The voltage on the second bit line is boosted upward as a result of
capacitive coupling with the word line. Meanwhile, the amount the
voltage is boosted is reduced as a result of the voltages on both
the first and third bit lines. As a result, the voltage on the
second bit line is boosted to a Vinhibit3 voltage level, which can
be lower than Vinhibit1 and Vinhibit2. As shown in FIG. 3D, the
Vinhibit3 voltage level is less than both the Vinhibit1 and
Vinhibit2 voltage levels. The decreased voltage level of Vinhibit3
increases the chances that unwanted charge tunneling will occur in
unselected memory cells of the stacked memory structure 300.
Specifically, such unwanted charge tunneling will occur in
unselected memory cells that have a voltage at the Vinhibit3
voltage level on them during a performed programming operation.
This unwanted charge tunneling can lead to disturbing of unselected
cells during a programming operation through either the disrupting
of already stored data or the creation of false data. As described
herein, the programming bias arrangement can be configured to
reduce or prevent this voltage shift to a level of Vinhibit3, so
that program disturb in this situation can be suppressed. The
memory structure can be configured so that Vinhibit1 and Vinhibit2
can be encountered while data retention performance remains within
operating specifications. Vinhibit3 on the other hand may cause too
much program disturbance in unselected cells, leading to poor data
retention performance.
[0061] FIG. 4 shows voltages on the bit lines in a stacked memory
structure during a programming technique. The stacked memory
structure 400 includes eight bit lines 402, 404, 406, 408, 410,
412, 414 and 416 separated by insulating layers 418 between the bit
lines. The eight bit lines 402, 404, 406, 408, 410, 412, 414 and
416 are electrically coupled to memory cells in the corresponding
eight layers, and share a common word line structure (not shown).
Then, if any memory cell in the stack is selected for programming,
all of them are exposed to the high voltage in the common word
line. The stacked memory structure can include any number of layers
containing corresponding memory cells. While FIG. 4 shows a single
vertical column of cells disposed in the eight bit lines, the
stacked memory structure includes multiple vertical columns of
cells that are formed by the eight bit lines and can simultaneously
have the same or different voltages on them during performance of a
programming operation according to the programming technique. In
FIG. 4, the layers that include memory cells target of a change of
state in a single program command, that is the layers at which
there are selected memory cells to be programmed, are marked as
target layers "TGT" for an example. The programming technique used
to program the stacked memory structure shown in FIG. 4 includes
programming all of the selected memory cells through a single
programming bias arrangement, regardless of where the selected
memory cells are disposed in the stacked structure.
[0062] As a result, voltages at the Vinhibit3 voltage level can be
encountered in bit lines in the stacked memory structure, thereby
leading to disturbing. In the shown example, the third bit line
406, fourth bit line 408, sixth bit line 412 and eighth bit line
416 have voltages at the Vpgm voltage level, while the others have
voltage variously at the Vinhibit1, Vinhibit2 and Vinhibit3 voltage
levels.
[0063] Specifically, the programming technique includes, during a
first interval, setting up a voltage with a Vpgm voltage level on
the third, fourth, sixth and eighth bit lines 406, 408, 412 and
416. Also, during the first interval, an inhibit set up voltage is
set up on the first, second, fifth and seventh bit lines 402, 404,
410 and 414.
[0064] During a second interval, after the first interval, the
string select switches and the ground select switches that are
coupled to the first, second, fifth and seventh bit lines 402, 404,
410 and 414 are open. As a result, the first, second, fifth and
seventh bit lines 402, 404, 410 and 414 are left floating with a
voltage at the inhibit set up voltage level during the second
interval. Conversely, during the second interval, the string select
switches and ground select switches that are coupled to the third,
fourth, sixth and eighth bit lines 406, 408, 412 and 416 remain
closed (on). As a result, the third, fourth, sixth and eighth bit
lines are left non-floating and remain with a voltage at the Vpgm
voltage level throughout the second interval. Additionally, during
the second interval, a voltage is set up through ISPP on the word
line that is electrically coupled to the memory cells in the
stacked memory structure 400.
[0065] The first bit line 402 is capacitively coupled to the word
line. Therefore, the charging of the word line through ISPP causes
the voltage on the first bit line to transition to the Vinhibit1
voltage level. The second bit line 404 is adjacent the third bit
line 406 which is at target level. Therefore, both the charging of
the word line and the non-floating voltage at the Vpgm voltage
level on the third bit line 406 cause the voltage on the second bit
line 404 to transition to the Vinhibit2 voltage level.
[0066] The fifth bit line 410 is capacitively coupled to the word
line and between the fourth bit line 408 and the sixth bit line
412. Therefore, the charging of the word line and the continued
application of non-floating voltages at the Vpgm voltage level on
the fourth bit line 408 and the sixth bit line 412 causes the
voltage on the fifth bit line to transition to the Vinhibit3
voltage level. The seventh bit line 414 is capacitively coupled to
the word line and between the sixth bit line 412 and the eighth bit
line 416. Therefore, the charging of the word line and the
non-floating voltages at the Vpgm voltage level on both the sixth
bit line and the eighth bit line causes the voltage on the seventh
bit line 414 to transition to the Vinhibit3 voltage level. The
Vinhibit3 level can lead to program disturb conditions.
[0067] FIG. 5 is a flowchart of the steps executed by the
controller in performing a programming technique that includes
iteratively performing group programming operations over cells
disposed in first and second sets of the layers. Specifically, at
step 510, the controller receives a program instruction to program
data to memory cells corresponding to a particular multibit address
in a stacked memory structure having a plurality of layers. At step
512, the controller executes a first program operation on the
corresponding memory cells. The first programming operation
includes applying program voltages via bit lines to cells to be
changed to a programmed state in a first set of the layers, inhibit
voltages to remaining cells in the first set, and inhibit voltages
via bit lines to all of the cells in a second set of the layers,
even if some of the cells in the second set are target of
programming by the program instruction being executed. The layers
are assigned to the first and second sets of the layers so that no
two layers in the first set are separated by only one layer in the
second set. In an alternate embodiment, the first and second sets
of the layers are assigned so that not only is the above true, but
also so that no two layers in the second set are separated by only
one layer in the first set. As a result, no cells in the first or
second sets can be exposed to conditions like those of layer 410 in
FIG. 4, which causes a Vinhibit3 level.
[0068] At step 514, if memory cells disposed in the second set of
the layers need to be changed to a programmed state, the controller
executes a second programming operation. The second programming
operation includes applying program voltages to the cells to be
changed to the programmed state in the second set of the layers,
inhibit voltages to remaining cells in the second set, and inhibit
voltages to all the cells in the first set of the layers.
[0069] FIG. 6 shows an example organization of memory cells in the
stacked memory structure. The organization is based on the physical
locations of the memory cells in the layers of the stacked memory
structure 600. The stacked memory structure 600 includes a first,
second, third, fourth, fifth, sixth, seventh and eighth bit line
602, 604, 606, 608, 610, 612, 614 and 616. The bit lines are
separated by insulating layers (e.g., 618, 628). The bit lines
correspond to first, second, third, fourth, fifth, sixth, seventh
and eighth layers in the stacked memory structure, with each layer
including memory cells.
[0070] The organization includes a set of memory cells for a
particular multibit address disposed in a first set of layers 630
and a second set of layers 632. The first set of layers 630
includes the layers in a first subset including a pair of layers
620 and a third subset including a pair of layers 624. The second
set of layers 632 includes layers that are in a second subset
including a pair of layers 622 and a fourth subset including a pair
of layers 626. The first pair of layers 620 includes the first and
second layers that correspond to the first and second bit lines 602
and 604. The second pair of layers 622 includes the third and
fourth layers that correspond to the third and fourth bit lines 606
and 608. The third pair of layers 624 includes the fifth and sixth
layers that correspond to the fifth and sixth bit lines 610 and
612. The fourth pair of layers 626 includes the seventh and eighth
layers that correspond to the seventh and eighth bit lines 614 and
616. It is appreciated that the stack of memory cells can include
any number of levels so that each set can include any number of
pairs of layers. As a result of this organization, no layer
receiving the inhibit condition can be between two adjacent layers
receiving the programming condition on the bit line. Also, every
layer receiving an inhibit condition, even if it is in the set
being programmed, will have at least one adjacent layer that is
also in the inhibit condition.
[0071] FIGS. 7 and 8 show the stacked memory structure with the
organization of FIG. 7 with voltage levels in the bit lines during
the performing of corresponding first and second programming
operations of the programming technique shown in FIG. 5. For
comparative purposes, the device receives the same multibit address
and maps the address to the same corresponding cells as was
illustrated for the stacked memory structure shown in FIG. 4. As a
result, the selected cells of the corresponding memory cells target
of programming are in the third 606, fourth 608, sixth 612 and
eighth 616 layers of the stacked memory structure, the same as in
FIG. 4.
[0072] With respect to the stack of memory cells that is shown in
FIG. 7, under the first programming operation of the present
programming technique, the controller applies a first program bias
arrangement to the corresponding memory cells in a first set of the
stacked memory structure. Under the first programming bias
arrangement, during a first interval, a voltage at the Vpgm level
is applied to the selected memory cell in the first set of layers.
The memory cells in the first set of layers include the memory
cells in the first pair of layers 620 and the third pair of layers
624. Specifically, a voltage at the Vpgm voltage level is set up
only on the sixth bit line 612 that is part of the third pair of
layers 624. Other target cells in layers 606, 608 and 161 are in
the second set. It is appreciated that in alternative embodiments,
in response to different multibit addresses, the first program bias
arrangement can include applying voltages at the Vpgm level to any
combination of the corresponding memory cells in the first set of
layers. Specifically, this can include applying voltages at the
Vpgm voltage level to one memory cell or both memory cells in the
first pair of layers 620 and one memory cell or both memory cells
in the third pair of layers 624.
[0073] Also, during the first interval of the first programming
bias arrangement, voltages at the Vcc voltage level are applied to
the unselected memory cells in the first set of layers. The
unselected memory cells in the first set of layers include the
corresponding memory cells in the first, second and fifth layers of
the stacked memory structure 600. Specifically, voltages at the Vcc
level are set up on the first bit line 602, the second bit line 604
and the sixth bit line 610. Additionally, during the first interval
of the first programming bias arrangement, inhibit voltages are
applied to the memory cells in the second set of layers. The memory
cells in the second set of layers include the memory cells in the
corresponding second and fourth pairs of layers 622 and 626.
Specifically, voltages at the Vcc voltage level are set up on the
third bit line 606, the fourth bit line 608, the seventh bit line
614 and the eighth bit line 616.
[0074] During a second interval, after the first interval, of the
first programming bias arrangement, the string select switches and
the ground select switches that are coupled to the bit lines upon
which voltages at the Vcc voltage level were set up on during the
first interval, are opened (off). As a result, the first bit line
602, the second bit line 604, the third bit line 606, the fourth
bit line 608, the fifth bit line 610, the seventh bit line 614 and
the eighth bit line 616 are all left floating with a voltage at the
Vcc voltage level. The string select switches and the ground
selected switches that are coupled to the selected bit line upon
which the voltage at the Vpgm voltage level (e.g. O V) was set up
to remain closed (on) throughout the second interval. As a result,
during the second interval, the sixth bit line 612 is non-floating
with a voltage at the Vpgm voltage level.
[0075] Also, during the second interval, a voltage is set up
through ISPP on the word line that is electrically coupled to the
corresponding memory cells in the stacked memory structure 600. The
first bit line 602, the second bit line 604, the third bit line
606, the fourth bit line 608 and the eighth bit line 616 are
adjacent only other bit lines set up for inhibit. As a result,
during the second interval, the voltages on such bit lines
transition to a voltage at the Vinhibit1 voltage level. The fifth
bit line 610 and the seventh bit line 614 are adjacent to one bit
line (608 and 616, respectively) set up for inhibit, and to the
selected bit line 612 The selected bit line 612 that has a
non-floating voltage at the Vpgm voltage level set up on it. As a
result, the voltages on the fifth bit line and the seventh bit line
transition to the Vinhibit2 voltage level during the second
interval. None of the voltages on the bit lines transition to the
Vinhibit3 voltage level throughout the application of the first
programming bias arrangement.
[0076] With respect to the stack of memory cells as shown in FIG.
8, the controller applies a second program bias arrangement to the
corresponding memory cells in the stacked memory structure to
program cells in layers 606 and 608. Under the second programming
bias arrangement, during a first interval, a voltage at the Vpgm
level is applied to the selected memory cells in the second set of
layers. The selected memory cells in the second set of layers
include the corresponding memory cells in the third, fourth, and
eighth layers of the stacked memory structure 600. Specifically, a
voltage at the Vpgm voltage level is set up on the third bit line
606 and the fourth bit line 608, that are part of the second pair
of layers 622, and the eighth bit line 616 that is part of the
fourth pair of layers 626. It is appreciated that in alternative
embodiments, in response to different multibit addresses, the
second program bias arrangement can include applying voltages at
the Vpgm level to any combination of the corresponding memory cells
in the second set of layers. Specifically, this can include
applying voltages at the Vpgm voltage level to one memory cell in
the second pair of layers 622 and one memory cell in the fourth
pair of layers 626.
[0077] Also, during the first interval of the second programming
bias arrangement, voltages at the Vcc voltage level are applied to
the unselected memory cells in the second set of layers. The
unselected memory cell in the second set of layers includes the
corresponding memory cell in the seventh layer of the stacked
memory structure. Specifically, a voltage at the Vcc level is set
up on the seventh bit line 614. Additionally, during the first
interval of the second programming bias arrangement, inhibit
voltages are applied to the memory cells in the first set of
layers. Specifically, voltages at the Vcc voltage level are set up
on the first bit line 602, the second bit line 604, the fifth bit
line 610 and the sixth bit line 612.
[0078] During a second interval of the second programming bias
arrangement, after the first interval, the string select switches
and the ground select switches that are coupled to the bit lines
upon which voltages at the Vcc voltage level were set upon during
the first interval, are opened. As a result, the first bit line
602, the second bit line 604, the fifth bit line 610, the sixth bit
line 612 and the seventh bit line 614 are all left floating with an
inhibit set up voltage at for example the Vcc voltage level. The
string select switches and the ground select switches that are
coupled to the bit lines upon which voltages at the Vpgm voltage
level were set upon during the first interval remain closed (on)
during the second interval. As a result, during the second
interval, the third bit line 606, the fourth bit line 608 and the
eighth bit line 616 are left non-floating with voltages at the Vpgm
voltage level.
[0079] Also, during the second interval of the second programming
bias arrangement, a voltage is set up through ISPP on the word line
that is electrically coupled to the corresponding memory cells of
the stacked memory structure 600. The first bit line 602 and the
sixth bit line 612 are adjacent only layers receiving the inhibit
bias. As a result, during the second interval, the voltages on the
first bit line and the sixth bit line transition to a voltage at
the Vinhibit1 voltage level. The second bit line 604, the fifth bit
line 610 and the seventh bit line 614 are adjacent one of the bit
lines that have voltages at the Vpgm voltage level set upon them,
and to one bit line set up for inhibit. As a result, the voltages
on the second bit line, the fifth bit line and the seventh bit line
transition to the Vinhibit2 voltage level during the second
interval. None of the voltages on the semiconductor layers in the
stack of memory cells transition to the Vinhibit3 voltage
level.
[0080] In the examples described with reference to FIGS. 5-8, the
sets of layers are statically assigned. So the controller
automatically performs the first and second program operation in
response to the single program command, skipping one or the other
only when a pre-verify step for example, determines that there are
no cells that need to be changed in the corresponding set of
layers. In the example of FIG. 10, the control logic is altered so
that the sets are not statically assigned, but rather can be
assigned for each program command in an attempt to include all
target cells in the first set, so that no programming operation
would be required for the second set. This can could be used for
example referring to FIG. 6, if the target layers included the
third layer 606 (which is in the second set in the static
assignment) and the eighth layer 616 (which is in the first set in
the static assignment) only. In this case, the controller can
determine that there are no layers which would be subject of the
inhibit set up adjacent to two layers that would be subject of the
program bias, even if cells in both target layers are programmed in
one operation. So, the controller can assign layer 3 and 8 to the
first set for the current program command. Also, it is noted that
the Figures show that the cells in the set of cells that maps to
the multibit address are aligned in a vertical stack. In other
alternatives, the cells in the set of cells may be disposed in
other configurations, such as disposed in the plurality of layers
but not vertically aligned.
[0081] FIG. 9 is a flowchart of the steps executed by the
controller in performing an alternate programming technique that
includes iteratively performing group programming operations over
first and second sets of the cells. Specifically, at step 520, the
controller receives a program instruction to program data to memory
cells corresponding to a particular multibit address in a stacked
memory structure having a plurality of layers. Next, at step 522,
the controller determines which of the corresponding memory cells
are to be changed to the programmed state. The controller
determines which of the corresponding memory cells to change based
on the received programming instructions and optionally whether or
not the corresponding memory cells are already in the programmed
state, such as can be determined by a pre-verify step.
[0082] At step 524, the controller, if possible, defines a first
set of the layers to include all of the corresponding memory cells
to be changed to a programmed state. The first set of the layers
includes corresponding layers of the plurality of layers so that no
two layers in the first set are separated by only one layer in a
second set of the layers. In an alternate embodiment, the first and
second sets of layers includes corresponding layers of the
plurality of layers so that not only is the above true, but also so
that no two layers in the second set are separated by only one
layer in the first set.
[0083] Next at step 526, the controller executes a first program
operation on the corresponding memory cells. The first programming
operation includes applying program voltages to cells to be changed
to a programmed state in the first set of the layers, inhibit
voltages to remaining cells in the first set, and inhibit voltages
to all cells in the second set of the layers. Then, at step 528, if
corresponding memory cells in the second set of the layers still
need to be changed to the programmed state, the controller executes
a second program operation on the corresponding memory cells. The
second programming operation includes applying program voltages to
the cells to be changed to the programmed state in the second set
of the layers, inhibit voltages to remaining cells in the second
set, and inhibit voltages to all cells in the first set of the
layers. Because of the selection of a first set based on the cells
to be programmed, the second program operation may be required less
often.
[0084] FIGS. 10A-10C show a stacked memory structure made up of two
bit lines and various voltage levels that can exist on the bit
lines during a program operation for the purposes of illustrating a
program disturb phenomenon that can occur in stacked memory
structures. The stacked memory structure 700 includes first bit
line 702 and a second bit line 704. An insulating layer 706 is
disposed between the first and second bit lines 702 and 704. The
bit lines are electrically coupled to corresponding memory cells in
first and second layers of memory cells in the stacked memory
structure 700. The first and second layers of memory cells
correspond to the first and second bit lines. For purposes of
illustration, the memory material layers and the surrounding word
line are not shown.
[0085] For the stacked memory structure 700 shown in FIG. 10A,
during a programming operation, a voltage at the Vpgm voltage level
is set up on the first and second bit lines 702 and 704. As with
the stacked memory structures discussed previously, the string
select switches and the ground select switches that are coupled to
the bit lines upon which a voltage at the Vpgm voltage level are
set upon remain closed as long as a voltage at the Vpgm voltage
level remains on the bit lines. As a result, the voltages on the
first and second bit lines, for the stacked memory structure shown
in FIG. 10A, remain at the Vpgm voltage level during the
programming operation. Such voltage levels on the bit lines of the
stacked memory structure are in a "00" programming pattern. The
"00" programming pattern is a programming biasing arrangement in
which a memory cell formed with the first bit line and a memory
cell formed with the second bit line are programmed during the
programming operation.
[0086] For the stacked memory structure 700 shown in FIG. 10B,
during a first interval of a programming operation, a voltage at
the Vpgm voltage level is set up on the first bit line 702. Also
during the first interval, a voltage at the Vcc voltage level is
set up on the second bit line 704. Such voltage levels on the bit
lines of the stacked memory structure are in a "01" programming
pattern. The "01" programming pattern is a programming biasing
arrangement in which one memory cell coupled to the first bit line
is programmed and one memory cell coupled to the second bit line is
not programmed during the programming operation. During a second
interval of the programming operation, the string select switches
and the source select switches that are coupled to the bit lines
upon which a voltage at the Vpgm voltage level are set upon remain
closed.
[0087] Conversely, during the second interval of the programming
operation, the string select switches and the source select
switches that are coupled to the bit lines upon which a voltage at
the Vcc voltage level are set upon are opened. As a result, during
the second interval the voltage on the first bit line is
non-floating at the Vpgm voltage level, while the voltage on the
second bit line is floating. The voltage on a word line coupled to
corresponding memory cells that are coupled to the first bit line
and the second bit line is increased through ISPP to a voltage with
a voltage level up to 21V. As the voltage on the second bit line is
left floating during the second interval, the voltage level on the
second bit line increases through capacitive coupling with the word
line. As a result, the voltage level of the voltage on the second
bit line is boosted up to Vinhibit2.
[0088] For the stacked memory structure 700 shown in FIG. 10C,
during a first interval of a programming operation, a voltage at
the Vpgm voltage level is set up on the second bit line 704. Also
during the first interval, a voltage at the Vcc voltage level is
set up on the first bit line 702. Such voltage levels on the bit
lines of the stacked memory structure are in a "10" programming
pattern. The "10" programming pattern is a programming biasing
arrangement in which at least one memory cell coupled to the second
bit line is programmed, and at least one memory cell coupled to the
first bit line is not programmed during the programming
operation.
[0089] The string select switches and ground select switches are
closed and open based upon the voltage level that is set up on each
bit line as for the programming operation performed on the stacked
memory structure shown in FIG. 10C. As a result, during the second
interval, the voltage on the second bit line is non-floating at the
Vpgm voltage level, while the voltage on the first bit line is
floating. The voltage on a word line that is coupled to
corresponding memory cells that are coupled to the first bit line
and the second bit line is increased through ISPP to a voltage with
a voltage level up to 21V. As the voltage on the first bit line is
left floating during the second interval, the voltage level on the
first bit line increases through capacitive coupling with the word
line. As a result, the voltage level of the voltage on the first
bit line is boosted up to Vinhibit2.
[0090] Memory cells in a stacked memory structure that are
programmed according to either the "10" or "01" programming
patterns are programmed faster than memory cells in a stack of
memory cells that are programmed according to the "00" programming
pattern. This increase in programming speed in either the "10" or
"01" programming pattern can be understood because the bit lines
upon which the voltage is boosted up can act as a "back gate" for
the memory cells formed with an adjacent bit line upon which a
voltage at the Vpgm level is maintained during the programming
process. The voltage on the boosted bit lines can act like a gate
voltage on a field effect transistor, in which the bit lines
selected for programming can act like the field effect transistor
channel in which the carrier concentrations are boosted by a gate
voltage. For example, in the stacked memory structure shown in FIG.
10B that is programmed according to the "01" programming pattern,
the second bit line 704 serves as the back gate for the memory
cells formed with the adjacent first bit line 702. Similarly, for
the stacked memory structure shown in FIG. 10C that is programmed
according to the "10" programming pattern, the first bit line 702
serves as the back gate for the memory cells formed with the
adjacent second bit line 704.
[0091] The increase in the voltage level of the voltage on the bit
lines that serve as the back gate causes an increase, during
programming, of the carrier concentration within the inversion
layers of the memory cells that are formed with an adjacent bit
line. Such increase of the charge density in the inversion layers
can cause charge to tunnel from the inversion layer at a lower word
line voltage than memory cells with inversion layers that have a
lower charge density.
[0092] FIG. 11 is a graph of the threshold voltage (Vt) of the
memory cells formed with the structure and applied voltages of FIG.
10A as a function of an increasing voltage level of the voltage
applied to the word line through ISPP. Specifically, FIG. 11
illustrates over-programming that can occur in the stacked memory
structure that are programmed in the "00" programming pattern. Line
710 is the threshold voltage in the memory cells formed with the
first, upper bit line 702 shown in FIG. 10A. Line 708 is the
threshold voltage in the memory cells formed with the second, lower
bit line 704 shown in FIG. 10A. The threshold voltage of the memory
cells in the first bit line and the second bit line increase
roughly linearly with each pulse until the memory cell in the
second bit line passes program verify, shown at point 712. After
point 712, the threshold voltage on trace 710 for the memory cells
on upper bit line 702 levels off in region 714 because the bit line
is set to the inhibit condition As the voltage on the second bit
line drops to an inhibit voltage level after point 712, the stacked
memory structure transitions from being programmed in a "00"
programming pattern to being programmed in a "01" programming
pattern, such as is applied to the memory structure shown in FIG.
10B. The programming rate is faster for memory cells in a stacked
memory structure that are programmed according to the "01"
programming pattern. As a result, Vt changes in the bottom layer as
indicated by the arrow 716 by a larger amount in the next ISPP
pulse after point 712. The increase in the amount that Vt changes
after point 712 can lead to over-programming of the memory cells in
the bottom layer in this example.
[0093] FIG. 12 shows another example organization of memory cells
in the stacked memory structure during programming, which can
suppress disturb and prevent over-programming. The stacked memory
structure 720 includes first, second, third, fourth, fifth, sixth,
seventh and eighth stacked bit lines 722, 724, 726, 728, 730, 732,
734 and 736. The stacked bit lines are separated by insulating
layers 738. The stacked bit lines correspond to first, second,
third, fourth, fifth, sixth, seventh and eighth layers in the
stacked memory structure, with each layer including memory
cells.
[0094] The organization can be characterized as including three
sets of layers. In this organization, the first set of layers 740
includes the memory cells formed with the first, fourth and seventh
bit lines 722, 728 and 734. The second set of layers 742 includes
the memory cells formed with the second, fifth and eighth bit lines
724, 730 and 736. The third set of layers 744 includes the memory
cells formed with the third and sixth bit lines 726 and 732. In the
organization based on these sets of layers, the bit lines in each
set of layers are separated by at least two other bit lines in two
different sets of layers. As compared to the embodiment of FIG. 8,
the sets in FIG. 12 include subsets of only one layer. The
organization can be applied to a stacked memory structure that
includes three or more bit lines, so that each group of layers
includes any number of bit lines.
[0095] The organization of FIG. 12 is applied during a programming
operation to prevent over-programming while decreasing the amount
of disturbing that occurs in unselected memory cells in the stacked
memory structure 720.
[0096] In programming the memory cells in the stacked memory
structure that are organized through the arrangement of FIG. 12, a
first program operation is executed. The first programming
operation includes applying a first programming bias to a first set
(any one of the three sets) in a stacked memory structure. The
first programming bias also includes applying voltages to the
stacked memory structure to inhibit changes in the state of memory
cells in the corresponding memory cells in the second and third
sets of layers.
[0097] After the first programming operation is performed, if the
data to be stored requires memory cells in the second set of layers
to change state, then a second program operation is executed. If
one or more cells in the second set of layers requires a change to
a programmed state, the second programming operation includes
applying a bias to cause such cells to change state. The bias also
includes applying voltages to the stacked memory structure to
inhibit changes in the state of memory cells in the set of
corresponding memory cells in the first set and the third set of
layers. Then, if one or more cells in the third set of layers
requires a change in state, then a third programming operation is
applied that includes applying a bias to cause such cells to change
state. The bias also includes applying voltages to the stacked
memory structure to inhibit changes in the state of memory cells in
the set of corresponding memory cells in the first set and the
second set of layers. As a result of this organization, no layer
set up for inhibit is between two layers set up for programming.
Also, no layer set up for programming is adjacent any layer that is
also set up for programming. This prevents the over-programming
that can occur in the "01" and "10" program conditions shown in
FIG. 10A.
[0098] The grouping can be static, applied for every program
command, or dynamic so that the grouping is selected each time to
reduce the need for second and third programming operations.
[0099] FIG. 13 is a flowchart of the steps executed by the
controller in performing an alternate programming technique that
can prevent program disturb and over programming, that includes
iteratively performing group programming operations over first,
second and third sets of the cells. Specifically, at step 1302, the
controller receives a program instruction to program data to memory
cells corresponding to a particular multibit address in a stacked
memory structure having a plurality of layers. At step 1304, the
controller executes a first program operation on the corresponding
memory cells. The first programming operation includes applying
program voltages via bit lines to cells to be changed to a
programmed state disposed in a first set of the layers, inhibit
voltages to remaining cells disposed in the first set, and inhibit
voltages to all of the cells disposed in a second set and a third
set. The cells are assigned to the sets so that there are no
adjacent layers in any one set, and the layers in any one set are
separated by two layers, including one layer in each of the other
two sets.
[0100] As a result, no cells in the first set can be exposed to
conditions like those of layer 410 in FIG. 4, which causes a
Vinhibit3 level.
[0101] At step 1306, if memory cells in the second set of the
layers need to be changed to a programmed state, the controller
executes a second programming operation. The second programming
operation includes applying program voltages to the cells to be
changed to the programmed state in the second set of the layers,
inhibit voltages to remaining cells in the second set, and inhibit
set up voltages to all the cells in the first and third sets.
[0102] At step 1308, if memory cells in the third set of the layers
need to be changed to a programmed state, the controller executes a
third programming operation. The third programming operation
includes applying program voltages to the cells to be changed to
the programmed state in the third set of the layers, inhibit
voltages to remaining cells in the third set, and inhibit set up
voltages to all the cells in the first and second sets.
[0103] FIG. 14 is a block diagram of an integrated circuit memory
900 employing memory cells and bias circuitry according to
embodiments of the present invention with a stacked memory
structure 902 having modified programming logic as described
herein. In some embodiments, the stacked memory structure 902
includes multiple levels of cells arranged in multiple NAND
strings. A row decoder (block 904) is coupled to a plurality of
word lines 906 arranged along rows in the stacked memory structure
902. Column decoders in block 908 are coupled to a set of page
buffers 910, in this example via data bus 912. The global bit lines
914 are coupled to local bit lines (not shown) arranged along
columns in the stacked memory structure 902. Addresses are supplied
on bus 916 to column decoders (block 908) and row and level decoder
(block 904). Data is supplied via the data-in line 918 from other
circuitry 920 (including for example input/output ports) on the
integrated circuit, such as a general purpose processor or special
purpose application circuitry, or a combination of modules
providing system-on-a-chip functionality supported by the stacked
memory structure 902. Data is supplied via the line 918 to
input/output ports or to other data destinations internal or
external to the integrated circuit memory 900.
[0104] A controller 922, implemented for example as a state
machine, provides signals to control the application of bias
arrangement supply voltages generated or provided through the
voltage supply or supplies in block 924 to carry out the various
operations described herein. The controller can use programming
techniques like those shown in FIGS. 6, and 9, where the controller
includes logic for first and second program sequences to the
stacked memory structure 902 to suppress disturb. Also, the
controller can include logic for first, second and third program
sequences to prevent over-programming like those shown in FIG. 13.
The controller can be implemented using special-purpose logic
circuitry as known in the art. In alternative embodiments, the
controller comprises a general purpose processor, which may be
implemented on the same integrated circuit, which executes a
computer program to control the operations of the device. In yet
other embodiments, a combination of special purpose logic circuitry
and a general purpose processor may be utilized for implementation
of the controller.
[0105] A memory device is described therefore, including a stacked
memory structure with layers of memory cells. The device includes
circuitry coupled to the stacked memory structure, responsive to a
program instruction to program data in target cells in a stack of
cells at a particular multibit address. As described above, the
circuitry is configured to use an assignment of cells in the stack
of cells to a plurality of sets of cells, and to iteratively
execute a group program operation selecting each of the plurality
of sets in sequence. In each iteration, the group program operation
includes applying program voltages to target cells in a selected
one of the plurality of sets, inhibit voltages to remaining cells
in said selected one of the plurality of sets, and inhibit voltages
to all of the cells in others of the plurality of sets. In one
example, the plurality of sets includes a first set and a second
set, where assignment of cells to the first and second sets insures
that no cells in the first set are disposed in layers separated by
only one layer from layers including cells in the second set.
[0106] In another example, the assignment groups cells so no cell
having inhibit voltages applied is in a layer of the stack between
two layers in which cells are having programming voltages
applied.
[0107] In another example, the assignment groups cells so no cell
having programming voltages applied is in a layer of the stack
adjacent any layer including a cell that is also having programming
voltages applied.
[0108] In another example, the assignment groups cells so no cell
having inhibit voltages applied is in a layer of the stack between
two layers in which cells are having programming applied.
[0109] The device is configured in one example, so that the group
program operation includes logic to skip a selected set if there
are no target cells in the set.
[0110] While the present invention is disclosed by reference to the
preferred embodiments and examples detailed above, it is understood
that these examples are intended in an illustrative rather than in
a limiting sense. It is contemplated that modifications and
combinations will readily occur to those skilled in the art, which
modifications and combinations will be within the spirit of the
invention and the scope of the following claims.
* * * * *