U.S. patent application number 13/741010 was filed with the patent office on 2014-07-17 for frequency multiplier.
This patent application is currently assigned to Texas Instruments Incorporated. The applicant listed for this patent is TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Hassan Ali, Brian B. Ginsburg, Baher Haroun, Bradley A. Kramer, Srinath M. Ramaswamy, Vijaya B. Rentala, Swaminathan Sankaran, Eunyoung Seok, Nirmal C. Warke.
Application Number | 20140198550 13/741010 |
Document ID | / |
Family ID | 50944105 |
Filed Date | 2014-07-17 |
United States Patent
Application |
20140198550 |
Kind Code |
A1 |
Sankaran; Swaminathan ; et
al. |
July 17, 2014 |
FREQUENCY MULTIPLIER
Abstract
An apparatus is provided. A differential pair of transistors is
configured to receive a first differential signal having a first
frequency, and a transformer, having a primary side and a secondary
side is provided. The primary side of the transformer is coupled to
the differential pair of transistors, and the secondary side of the
transformer is configured to output a second differential signal
having a second frequency, where the second frequency is greater
than the first frequency. A first transistor is coupled to the
first supply rail, the primary side of the transformer, and the
differential pair of transistors, where the first transistor is of
a first conduction type. A second transistor is coupled to the
second supply rail, the primary side of the transformer, and the
differential pair of transistors, where the second transistor is of
a second conduction type.
Inventors: |
Sankaran; Swaminathan;
(Allen, TX) ; Rentala; Vijaya B.; (Plano, TX)
; Ginsburg; Brian B.; (Allen, TX) ; Ramaswamy;
Srinath M.; (Murphy, TX) ; Seok; Eunyoung;
(Plano, TX) ; Haroun; Baher; (Allen, TX) ;
Kramer; Bradley A.; (Plano, TX) ; Ali; Hassan;
(Murphy, TX) ; Warke; Nirmal C.; (Irving,
TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TEXAS INSTRUMENTS INCORPORATED |
Dallas |
TX |
US |
|
|
Assignee: |
Texas Instruments
Incorporated
Dallas
TX
|
Family ID: |
50944105 |
Appl. No.: |
13/741010 |
Filed: |
January 14, 2013 |
Current U.S.
Class: |
363/163 |
Current CPC
Class: |
H03B 19/14 20130101;
H02M 5/297 20130101; H02M 5/16 20130101 |
Class at
Publication: |
363/163 |
International
Class: |
H02M 5/16 20060101
H02M005/16; H02M 5/297 20060101 H02M005/297 |
Claims
1. An apparatus comprising: a first supply rail; a second supply
rail; a differential pair of transistors that are configured to
receive a first differential signal having a first frequency; a
transformer having a primary side and a secondary side, wherein the
primary side of the transformer is coupled to the differential pair
of transistors, and wherein the secondary side of the transformer
is configured to output a second differential signal having a
second frequency, wherein the second frequency is greater than the
first frequency; a first transistor that is coupled to the first
supply rail, the primary side of the transformer, and the
differential pair of transistors, and wherein the first transistor
is of a first conduction type; and a second transistor that is
coupled to the second supply rail, the primary side of the
transformer, and the differential pair of transistors, and wherein
the second transistor is of a second conduction type.
2. The apparatus of claim 1, wherein the first transistor has a
first passive electrode, a second passive electrode, and a control
electrode, wherein the first passive electrode of the first
transistor is coupled to the primary side of the transformer,
wherein the second passive electrode of the first transistor is
coupled to the first supply rail, and wherein the control electrode
of the first transistor is coupled to the differential pair of
transistors.
3. The apparatus of claim 2, wherein the second transistor has a
first passive electrode, a second passive electrode, and a control
electrode, wherein the first passive electrode of the first
transistor is coupled to the primary side of the transformer,
wherein second passive electrode of the first transistor is coupled
to the second supply rail, and wherein the control electrode of the
first transistor is coupled to the differential pair of
transistors.
4. The apparatus of claim 3, wherein the first supply rail is
ground.
5. The apparatus of claim 4, wherein the first transistor is a
N-type transistor, and wherein the second transistor is a P-type
transistor.
6. The apparatus of claim 5, wherein the first transistor is a NMOS
transistor and wherein the second transistor is a PMOS
transistor.
7. An apparatus comprising: a first supply rail; a second supply
rail; a first MOS transistor that is coupled between a common node
and the first supply rail, wherein the first MOS transistor is
configured to receive a first portion of a first differential
signal at its gate, and wherein the first differential signal has a
second frequency; a second MOS transistor that is coupled between
the common node and the second supply rail, wherein the second MOS
transistor is configured to receive a second portion of the first
differential signal at its gate; a transformer having: a primary
side with a first terminal, a second terminal, and a center tap,
wherein the first terminal of the primary side of the transformer
is coupled to the common node, and wherein the center tap of the
primary side of the transformer is configured to receive a common
mode voltage; and a secondary side with a first terminal, a second
terminal, and a center tap, wherein the first terminal of the
secondary side of the transformer is configured to output a first
portion of a second differential signal, and wherein the center tap
of the secondary side of the transformer is configured to receive a
common mode voltage, and wherein the second terminal of the
secondary side of the transformer is configured to output a second
portion of the second differential signal, wherein the second
differential signal has a second frequency, and wherein the second
frequency is greater than the first frequency; a third MOS
transistor that is coupled between the second terminal of the
primary side of the transformer and the second supply rail and that
is coupled to the common node at its gate, wherein the third MOS
transistor is of a first conduction type; a fourth MOS transistor
that is coupled between the second terminal of the primary side of
the transformer and the first supply rail and that is coupled to
the common node at its gate, and wherein the fourth MOS transistor
is of a second conduction type.
8. The apparatus of claim 7, wherein the first, second, and third
MOS transistors are NMOS transistors, and wherein the fourth
transistor is a PMOS transistor.
9. The apparatus of claim 8, wherein the second supply rail is
ground.
10. The apparatus of claim 8, wherein the second frequency is twice
the first frequency.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to U.S. patent application Ser.
No. 13/683,735 (U.S. Pat. No. ______), entitled "BALUN WITH
INTEGRATED DECOUPLING AS GROUND SHIELD," filed on Nov. 21, 2012,
which is incorporated by reference herein for all purposes.
TECHNICAL FIELD
[0002] The invention relates generally to a frequency multiplier
and, more particularly, to a frequency multiplier having lower
direct current (DC) power consumption at radio frequency (RF) and
millimeter-wave frequencies (e.g., wavelengths between about 0.1 mm
and 10 mm).
BACKGROUND
[0003] Frequency multipliers have been used in a variety of
applications, including RF applications. In FIG. 1, an example of a
frequency multiplier 100 with positive feedback can be seen. As
shown, this multiplier 100 operates to generate a differential
output signal 2f.sub.LO+ and 2f.sub.LO+ that has twice the
frequency of the input differential signal f.sub.LO+ and f.sub.LO-.
In this example, the differential output signal 2f.sub.LO+ and
2f.sub.LO+ can function as a local oscillator signal for a
modulator. The input differential signal f.sub.LO+ and f.sub.LO-,
in the example of FIG. 1, is provided to the gates of transistors
Q1 and Q2. Transistors Q1 and Q2 (which, as shown are NMOS
transistors) are arranged to form a differential pair of
transistors that are coupled between a common node and a supply
rail (e.g., ground). Inductor L (which is coupled to a supply rail
VDD at its center tap) is coupled to the common node of the
differential pair Q1/Q2, along with the gate of transistor Q3
(which, as shown, is an NMOS transistor). The source of transistor
Q3 is also coupled to the inductor L.
[0004] There are, however, some problems with this arrangement.
First, the DC power consumption at RF and millimeter-wave
frequencies can be high because of a finite transconductance
density. Second there is a lack of biasing flexibility at the
output of multiplier 100 due to the existence of a single common
mode inductor tap (which, in the example of FIG. 1, is coupled to
supply rail VDD). Therefore, a frequency multiplier with improved
characteristics is needed.
SUMMARY
[0005] In accordance with the present invention, an apparatus is
provided. The apparatus comprises a first supply rail; a second
supply rail; a differential pair of transistors that are configured
to receive a first differential signal having a first frequency; a
transformer having a primary side and a secondary side, wherein the
primary side of the transformer is coupled to the differential pair
of transistors, and wherein the secondary side of the transformer
is configured to output a second differential signal having a
second frequency, wherein the second frequency is greater than the
first frequency; a first transistor that is coupled to the first
supply rail, the primary side of the transformer, and the
differential pair of transistors, and wherein the first transistor
is of a first conduction type; and a second transistor that is
coupled to the second supply rail, the primary side of the
transformer, and the differential pair of transistors, and wherein
the second transistor is of a second conduction type.
[0006] In accordance with the present invention, the first
transistor has a first passive electrode, a second passive
electrode, and a control electrode, wherein the first passive
electrode of the first transistor is coupled to the primary side of
the transformer, wherein the second passive electrode of the first
transistor is coupled to the first supply rail, and wherein the
control electrode of the first transistor is coupled to the
differential pair of transistors.
[0007] In accordance with the present invention, the second
transistor has a first passive electrode, a second passive
electrode, and a control electrode, wherein the first passive
electrode of the first transistor is coupled to the primary side of
the transformer, wherein the second passive electrode of the first
transistor is coupled to the second supply rail, and wherein the
control electrode of the first transistor is coupled to the
differential pair of transistors.
[0008] In accordance with the present invention, the first supply
rail is ground.
[0009] In accordance with the present invention, the first
transistor is a N-type transistor, and wherein the second
transistor is a P-type transistor.
[0010] In accordance with the present invention, the first
transistor is a NMOS transistor and wherein the second transistor
is a PMOS transistor.
[0011] In accordance with the present invention, an apparatus is
provided. The apparatus comprises a first supply rail; a second
supply rail; a first MOS transistor that is coupled between a
common node and the first supply rail, wherein the first MOS
transistor is configured to receive a first portion of a first
differential signal at its gate, and wherein the first differential
signal has a second frequency; a second MOS transistor that is
coupled between the common node and the second supply rail, wherein
the second MOS transistor is configured to receive a second portion
of the first differential signal at its gate; a transformer having:
a primary side with a first terminal, a second terminal, and a
center tap, wherein the first terminal of the primary side of the
transformer is coupled to the common node, and wherein the center
tap of the primary side of the transformer is configured to receive
a common mode voltage; and a secondary side with a first terminal,
a second terminal, and a center tap, wherein the first terminal of
the secondary side of the transformer is configured to output a
first portion of a second differential signal, and wherein the
center tap of the secondary side of the transformer is configured
to receive a common mode voltage, and wherein the second terminal
of the secondary side of the transformer is configured to output a
second portion of the second differential signal, wherein the
second differential signal has a second frequency, and wherein the
second frequency is greater than the first frequency; a third MOS
transistor that is coupled between the second terminal of the
primary side of the transformer and the second supply rail and that
is coupled to the common node at its gate, wherein the third MOS
transistor is of a first conduction type; a fourth MOS transistor
that is coupled between the second terminal of the primary side of
the transformer and the first supply rail and that is coupled to
the common node at its gate, and wherein the fourth MOS transistor
is of a second conduction type.
[0012] In accordance with the present invention, the first, second,
and third MOS transistors are NMOS transistors, and wherein the
fourth transistor is a PMOS transistor.
[0013] In accordance with the present invention, the second
frequency is twice the first frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] For a more complete understanding of the present invention,
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0015] FIG. 1 is a diagram of an example of a conventional
frequency multiplier with positive feedback; and
[0016] FIG. 2 is a diagram of an example of a frequency multiplier
with positive feedback in accordance with the present
invention.
DETAILED DESCRIPTION
[0017] Refer now to the drawings wherein depicted elements are, for
the sake of clarity, not necessarily shown to scale and wherein
like or similar elements are designated by the same reference
numeral through the several views.
[0018] Turning to FIG. 2, an example of a frequency multiplier 200
can be seen. Similar to multiplier 100, multiplier 200 can, for
example, generate a differential output signal 2f.sub.LO+ and
2f.sub.LO+ that has twice the frequency of the input differential
signal f.sub.LO+ and f.sub.LO-. There are, however, some
differences in topology. Namely, inductor L has been replaced by
transformer TR, and transistor Q4 (which can, for example, be a
PMOS transistor) has been added. In this configuration, transistors
Q3 and Q4 are arranged to be of opposite conduction types; for
example, transistors Q3 and Q4 are shown to be NMOS and PMOS
transistors, respectively. These transistors Q3 and Q4 are also
coupled between supply rails (e.g., supply rail VDD and ground).
Because these transistors Q3 and Q4 are commonly coupled to a
terminal of the primary side of the transformer TR and because the
gates of transistors Q3 and Q4 are coupled to the common node of
differential pair Q1/Q2, these transistors Q3 and Q4 operate as
"stacked" transconductance devices. By having this stacked
arrangement (e.g., source of transistor Q4 being coupled to the
drain of transistor Q3), current reuse between these
transconductance devices (e.g., transistors Q3 and Q4) is
permitted, which can, for example, double the transconductance
density.
[0019] Better bias can also be achieved. As shown, the transformer
TR has replaced the inductor L in this example with the primary
side being coupled to the common node of differential pair Q1/Q2
and the drain and source of transistors Q3 and Q4, respectively,
and with the secondary side providing differential output signal
2f.sub.LO+ and 2f.sub.LO+. Because the transformer TR can offer at
least two center taps (e.g., one on the primary side and one of the
secondary side), a common mode voltage VCM can be applied to these
center taps. This common mode voltage VCM can be selected to allow
for improved (e.g., optimized) biasing for transistors Q3 and
Q4.
[0020] Having thus described the present invention by reference to
certain of its preferred embodiments, it is noted that the
embodiments disclosed are illustrative rather than limiting in
nature and that a wide range of variations, modifications, changes,
and substitutions are contemplated in the foregoing disclosure and,
in some instances, some features of the present invention may be
employed without a corresponding use of the other features.
Accordingly, it is appropriate that the appended claims be
construed broadly and in a manner consistent with the scope of the
invention.
* * * * *