U.S. patent application number 13/938225 was filed with the patent office on 2014-06-26 for data control circuit.
The applicant listed for this patent is Novatek Microelectronics Corp.. Invention is credited to Chia-Wei Su, Chao-Kai Tu, Tse-Hung Wu.
Application Number | 20140176227 13/938225 |
Document ID | / |
Family ID | 50973957 |
Filed Date | 2014-06-26 |
United States Patent
Application |
20140176227 |
Kind Code |
A1 |
Wu; Tse-Hung ; et
al. |
June 26, 2014 |
DATA CONTROL CIRCUIT
Abstract
A data control circuit includes an output stage circuit, a
switch circuit, and an impedance module. The output stage circuit
outputs a data signal. An input terminal of the switch circuit is
coupled to an output terminal of the output stage circuit, and an
output terminal of the switch circuit is coupled to a post-stage
circuit. According to a control of a control signal, the switch
circuit determines whether to transmit the data signal of the
output stage circuit to the post-stage circuit. The impedance
module is configured in the output stage circuit, configured
between the output stage circuit and the switch circuit, or
configured in the switch circuit. Here, the impedance module
reduces noise flowing from the switch circuit to the output stage
circuit.
Inventors: |
Wu; Tse-Hung; (New Taipei
City, TW) ; Tu; Chao-Kai; (Hsinchu City, TW) ;
Su; Chia-Wei; (Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Novatek Microelectronics Corp. |
Hsinchu |
|
TW |
|
|
Family ID: |
50973957 |
Appl. No.: |
13/938225 |
Filed: |
July 9, 2013 |
Current U.S.
Class: |
327/437 ;
327/365 |
Current CPC
Class: |
H03K 17/162 20130101;
H03K 2217/0054 20130101; H03K 19/017509 20130101 |
Class at
Publication: |
327/437 ;
327/365 |
International
Class: |
H03K 17/16 20060101
H03K017/16 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 24, 2012 |
TW |
101149597 |
Claims
1. A data control circuit comprising: an output stage circuit
outputting a data signal; a switch circuit, an input terminal of
the switch circuit being coupled to an output terminal of the
output stage circuit, an output terminal of the switch circuit
being coupled to a post-stage circuit, wherein the switch circuit
determines whether to transmit the data signal of the output stage
circuit to the post-stage circuit according to a control of a
control signal; and an impedance module configured in the output
stage circuit, configured between the output stage circuit and the
switch circuit, or configured in the switch circuit, wherein the
impedance module reduces noise flowing from the switch circuit to
the output stage circuit.
2. The data control circuit as recited in claim 1, wherein the
output stage circuit comprises: a first inverter circuit, an input
terminal of the first inverter circuit being coupled to an input
terminal of the output stage circuit, an output terminal of the
first inverter circuit being coupled to the output terminal of the
output stage circuit.
3. The data control circuit as recited in claim 2, wherein the
first inverter circuit comprises: a first n-type transistor, a
source terminal of the first n-type transistor being coupled to a
ground voltage, a drain terminal of the first n-type transistor
being coupled to the output terminal of the output stage circuit, a
gate terminal of the first n-type transistor being coupled to the
input terminal of the output stage circuit; and a first p-type
transistor, a gate terminal of the first p-type transistor being
coupled to the gate terminal of the first n-type transistor, a
drain terminal of the first p-type transistor being coupled to the
drain terminal of the first n-type transistor, a source terminal of
the first p-type transistor being coupled to a system voltage.
4. The data control circuit as recited in claim 3, wherein the
impedance module is coupled between the source terminal of the
first n-type transistor and the ground voltage.
5. The data control circuit as recited in claim 3, wherein the
impedance module is coupled between the source terminal of the
first p-type transistor and the system voltage.
6. The data control circuit as recited in claim 3, wherein the
impedance module is coupled between the drain terminal of the first
n-type transistor and the output terminal of the output stage
circuit.
7. The data control circuit as recited in claim 3, wherein the
impedance module is coupled between the drain terminal of the first
p-type transistor and the output terminal of the output stage
circuit.
8. The data control circuit as recited in claim 2, wherein the
output stage circuit further comprises: a second inverter circuit,
an input terminal of the second inverter circuit being coupled to
the output terminal of the first inverter circuit, an output
terminal of the second inverter circuit being coupled to the input
terminal of the first inverter circuit.
9. The data control circuit as recited in claim 8, wherein the
second inverter circuit comprises: a second p-type transistor, a
source terminal of the second p-type transistor being coupled to a
system voltage, a gate terminal of the second p-type transistor
being coupled to the input terminal of the second inverter circuit,
a drain terminal of the second p-type transistor being coupled to
the output terminal of the second inverter circuit; and a second
n-type transistor, a drain terminal of the second n-type transistor
being coupled to the drain terminal of the second p-type
transistor, a source terminal of the second n-type transistor being
coupled to a ground voltage, a gate terminal of the second n-type
transistor being coupled to the input terminal of the second
inverter circuit.
10. The data control circuit as recited in claim 8, wherein the
second inverter circuit comprises: a second p-type transistor, a
source terminal of the second p-type transistor being coupled to a
system voltage, a gate terminal of the second p-type transistor
being coupled to the input terminal of the second inverter circuit;
a third p-type transistor, a source terminal of the third p-type
transistor being coupled to a drain terminal of the second p-type
transistor, a drain terminal of the third p-type transistor being
coupled to the output terminal of the second inverter circuit, a
gate terminal of the third p-type transistor being controlled by a
clock signal; a second n-type transistor, a drain terminal of the
second n-type transistor being coupled to the drain terminal of the
third p-type transistor, a gate terminal of the second n-type
transistor being controlled by an inverting signal of the clock
signal; and a third n-type transistor, a drain terminal of the
third n-type transistor being coupled to a source terminal of the
second n-type transistor, a source terminal of the third n-type
transistor being coupled to a ground voltage, a gate terminal of
the third n-type transistor being coupled to the input terminal of
the second inverter circuit.
11. The data control circuit as recited in claim 1, wherein the
switch circuit comprises: a second n-type transistor, a source
terminal of the second n-type transistor being coupled to the
output terminal of the switch circuit, a drain terminal of the
second n-type transistor being coupled to the input terminal of the
switch circuit, a gate terminal of the second n-type transistor
being controlled by the control signal.
12. The data control circuit as recited in claim 11, wherein the
impedance module is coupled between the drain terminal of the
second n-type transistor and the input terminal of the switch
circuit.
13. The data control circuit as recited in claim 11, wherein the
switch circuit further comprises: a second p-type transistor, a
source terminal of the second p-type transistor being coupled to
the input terminal of the switch circuit, a drain terminal of the
second p-type transistor being coupled to the output terminal of
the switch circuit, a gate terminal of the second p-type transistor
being controlled by an inverting signal of the control signal.
14. The data control circuit as recited in claim 1, wherein the
switch circuit comprises: a second p-type transistor, a source
terminal of the second p-type transistor being coupled to the input
terminal of the switch circuit, a drain terminal of the second
p-type transistor being coupled to the output terminal of the
switch circuit, a gate terminal of the second p-type transistor
being controlled by the control signal.
15. The data control circuit as recited in claim 14, wherein the
impedance module is coupled between the source terminal of the
second p-type transistor and the input terminal of the switch
circuit.
16. The data control circuit as recited in claim 1, wherein the
impedance module is coupled between the output terminal of the
output stage circuit and the input terminal of the switch
circuit.
17. The data control circuit as recited in claim 1, wherein the
impedance module is at least one resistor, an n-type transistor, or
a p-type transistor.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan
application serial no. 101149597, filed on Dec. 24, 2012. The
entirety of the above-mentioned patent application is hereby
incorporated by reference herein and made a part of this
specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to an electronic circuit, and more
particularly to a data control circuit capable of reducing
switching noise.
[0004] 2. Description of Related Art
[0005] When data transmission technologies are applied, a switch
device or a switch circuit is often configured on a transmission
path in a circuitry system, so as to control transmission of data
and information in the circuitry system. Nonetheless, a pre-stage
circuit coupled to the switch circuit may be interfered by the
noise generated by the switch circuit, such that data of the
pre-stage circuit cannot be correctly processed. Therefore, how to
effectively eliminate or reduce the switching noise in a data
control circuit and prevent the noise from affecting the correct
transmission of signals is one of the topics worth discussing.
SUMMARY OF THE INVENTION
[0006] The invention is directed to a data control circuit for
reducing noise flowing from a switch circuit to an output stage
circuit (a pre-stage circuit), so as to prevent the operation of
the pre-stage circuit from being interfered.
[0007] In an embodiment of the invention, a data control circuit
that includes an output stage circuit, a switch circuit, and an
impedance module is provided. The output stage circuit outputs a
data signal. An input terminal of the switch circuit is coupled to
an output terminal of the output stage circuit, and an output
terminal of the switch circuit is coupled to a post-stage circuit.
According to a control of a control signal, the switch circuit
determines whether to transmit the data signal of the output stage
circuit to the post-stage circuit. The impedance module is
configured in the output stage circuit, configured between the
output stage circuit and the switch circuit, or configured in the
switch circuit. Here, the impedance module reduces noise flowing
from the switch circuit to the output stage circuit.
[0008] According to an embodiment of the invention, the output
stage circuit includes a first inverter circuit. An input terminal
of the first inverter circuit is coupled to an input terminal of
the output stage circuit, and an output terminal of the first
inverter circuit is coupled to the output terminal of the output
stage circuit.
[0009] According to an embodiment of the invention, the first
inverter circuit includes a first n-type transistor and a first
p-type transistor. A source terminal of the first n-type transistor
is coupled to a ground voltage, a drain terminal of the first
n-type transistor is coupled to the output terminal of the output
stage circuit, and a gate terminal of the first n-type transistor
is coupled to the input terminal of the output stage circuit. A
gate terminal of the first p-type transistor is coupled to the gate
terminal of the first n-type transistor, a drain terminal of the
first p-type transistor is coupled to the drain terminal of the
first n-type transistor, and a source terminal of the first p-type
transistor is coupled to a system voltage.
[0010] According to an embodiment of the invention, the impedance
module is coupled between the source terminal of the first n-type
transistor and the ground voltage.
[0011] According to an embodiment of the invention, the impedance
module is coupled between the source terminal of the first p-type
transistor and the system voltage.
[0012] According to an embodiment of the invention, the impedance
module is coupled between the drain terminal of the first n-type
transistor and the output terminal of the output stage circuit.
[0013] According to an embodiment of the invention, the impedance
module is coupled between the drain terminal of the first p-type
transistor and the output terminal of the output stage circuit.
[0014] According to an embodiment of the invention, the output
stage circuit further includes a second inverter circuit. An input
terminal of the second inverter circuit is coupled to the output
terminal of the first inverter circuit, and an output terminal of
the second inverter circuit is coupled to the input terminal of the
first inverter circuit.
[0015] According to an embodiment of the invention, the second
inverter circuit includes a second p-type transistor and a second
n-type transistor. A source terminal of the second p-type
transistor is coupled to a system voltage, a gate terminal of the
second p-type transistor is coupled to the input terminal of the
second inverter circuit, and a drain terminal of the second p-type
transistor is coupled to the output terminal of the second inverter
circuit. A drain terminal of the second n-type transistor is
coupled to the drain terminal of the second p-type transistor, a
source terminal of the second n-type transistor is coupled to a
ground voltage, and a gate terminal of the second n-type transistor
is coupled to the input terminal of the second inverter
circuit.
[0016] According to an embodiment of the invention, the second
inverter circuit includes a second p-type transistor, a third
p-type transistor, a second n-type transistor, and a third n-type
transistor. A source terminal of the second p-type transistor is
coupled to a system voltage, and a gate terminal of the second
p-type transistor is coupled to the input terminal of the second
inverter circuit. A source terminal of the third p-type transistor
is coupled to a drain terminal of the second p-type transistor, a
drain terminal of the third p-type transistor is coupled to the
output terminal of the second inverter circuit, and a gate terminal
of the third p-type transistor is controlled by a clock signal. A
drain terminal of the second n-type transistor is coupled to the
drain terminal of the third p-type transistor, and a gate terminal
of the second n-type transistor is controlled by an inverting
signal of the clock signal. A drain terminal of the third n-type
transistor is coupled to a source terminal of the second n-type
transistor, a source terminal of the third n-type transistor is
coupled to a ground voltage, and a gate terminal of the third
n-type transistor is coupled to the input terminal of the second
inverter circuit.
[0017] According to an embodiment of the invention, the switch
circuit includes a second n-type transistor. A source terminal of
the second n-type transistor is coupled to an output terminal of
the switch circuit, a drain terminal of the second n-type
transistor is coupled to an input terminal of the switch circuit,
and a gate terminal of the second n-type transistor is controlled
by the control signal.
[0018] According to an embodiment of the invention, the impedance
module is coupled between the drain terminal of the second n-type
transistor and the input terminal of the switch circuit.
[0019] According to an embodiment of the invention, the switch
circuit further includes a second p-type transistor. A source
terminal of the second p-type transistor is coupled to the input
terminal of the switch circuit, a drain terminal of the second
p-type transistor is coupled to the output terminal of the switch
circuit, and a gate terminal of the second p-type transistor is
controlled by an inverting signal of the control signal.
[0020] According to an embodiment of the invention, the impedance
module is coupled between the source terminal of the second p-type
transistor and the input terminal of the switch circuit.
[0021] According to an embodiment of the invention, the impedance
module is coupled between the output terminal of the output stage
circuit and the input terminal of the switch circuit.
[0022] According to an embodiment of the invention, the impedance
module is at least one resistor, an n-type transistor, or a p-type
transistor.
[0023] In view of the above, the impedance module is additionally
configured on a path where the noise flows, so as to effectively
reduce noise interference caused by the switch circuit in the data
control circuit.
[0024] In order to make the aforementioned and other features and
advantages of the invention comprehensible, embodiments accompanied
with figures are described in detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a schematic block diagram illustrating a data
control circuit according to an embodiment of the invention.
[0026] FIG. 2 is a schematic diagram illustrating a data control
circuit according to a first embodiment of the invention.
[0027] FIG. 3 is a schematic diagram illustrating a data control
circuit according to a second embodiment of the invention.
[0028] FIG. 4 is a schematic diagram illustrating a data control
circuit according to a third embodiment of the invention.
[0029] FIG. 5 is a schematic diagram illustrating a data control
circuit according to a fourth embodiment of the invention.
[0030] FIG. 6 is a schematic diagram illustrating a data control
circuit according to a fifth embodiment of the invention.
[0031] FIG. 7 is a schematic diagram illustrating a data control
circuit according to a sixth embodiment of the invention.
[0032] FIG. 8 is a schematic diagram illustrating a data control
circuit according to a seventh embodiment of the invention.
[0033] FIG. 9 is a schematic diagram illustrating a data control
circuit according to an eighth embodiment of the invention.
[0034] FIG. 10 is a schematic diagram illustrating a data control
circuit according to a ninth embodiment of the invention.
[0035] FIG. 11 is a schematic diagram illustrating a data control
circuit according to a tenth embodiment of the invention.
[0036] FIG. 12 is a schematic diagram illustrating a data control
circuit according to an eleventh embodiment of the invention.
[0037] FIG. 13 is a schematic diagram illustrating a data control
circuit according to a twelfth embodiment of the invention.
[0038] FIG. 14 is a schematic diagram illustrating a data control
circuit according to a thirteenth embodiment of the invention.
[0039] FIG. 15 is a schematic diagram illustrating a data control
circuit according to a fourteenth embodiment of the invention.
[0040] FIG. 16 is a schematic diagram illustrating a data control
circuit according to a fifteenth embodiment of the invention.
DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS
[0041] FIG. 1 is a schematic block diagram illustrating a data
control circuit according to an embodiment of the invention. With
reference to FIG. 1, a data control circuit 100 includes an output
stage circuit 60 and a switch circuit 80. An output terminal of the
output stage circuit 60 is coupled to an input terminal of the
switch circuit 80, so as to output a data signal. An output
terminal of the switch circuit 80 is coupled to a post-stage
circuit 10. In different embodiments, the output stage circuit 60
may include an inverter circuit, a latch, a buffer, or any other
signal output circuit. The switch circuit 80 determines whether to
transmit the data signal of the output stage circuit 60 to the
post-stage circuit 10 according to a control of a control
signal.
[0042] In the present embodiment, the data control circuit 100
further includes an impedance module which is not shown in FIG. 1
but will be elaborated hereinafter. The impedance module is
configured in the output stage circuit 60, configured between the
output stage circuit 60 and the switch circuit 80, or configured in
the switch circuit 80. Since the impedance module is configured on
a path where noise flows, the impedance module is able to
effectively reduce the noise flowing from the switch circuit 80 to
the output stage circuit 60. Here, the impedance module may be at
least one resistor, an n-type transistor (i.e., an n-channel
transistor), a p-type transistor (i.e., a p-channel transistor), or
any other circuit that may provide impedance.
[0043] FIG. 2 is a schematic diagram illustrating a data control
circuit according to a first embodiment of the invention. With
reference to FIG. 1 and FIG. 2, a data control circuit 100 includes
an output stage circuit 60, a switch circuit 80, and an impedance
module 110. In the present embodiment, the output stage circuit 60
includes a first inverter circuit. An input terminal of the first
inverter circuit is coupled to an input terminal of the output
stage circuit 60, and an output terminal of the first inverter
circuit is coupled to the output terminal of the output stage
circuit 60. The first inverter circuit may be implemented in
different manner according to different embodiments. For instance,
the first inverter circuit may include an n-type transistor N1 and
a p-type transistor P1. As shown in FIG. 2, a source terminal of
the n-type transistor N1 is coupled to a ground voltage Vss through
the impedance module 110, a drain terminal of the n-type transistor
N1 is coupled to the drain terminal of the p-type transistor P1,
and a gate terminal of the n-type transistor N1 is coupled to a
gate terminal of the p-type transistor P1. The gate terminal of the
p-type transistor P1 is coupled to the input terminal of the output
stage circuit 60, the drain terminal of the p-type transistor P1 is
coupled to the output terminal of the output stage circuit 60, and
a source terminal of the p-type transistor P1 is coupled to a
system voltage Vdd.
[0044] The switch circuit 80 includes an n-type transistor N2 and a
p-type transistor P2. As shown in FIG. 2, a source terminal of the
n-type transistor N2 is coupled to an output terminal of the switch
circuit 80, a drain terminal of the n-type transistor N2 is coupled
to an input terminal of the switch circuit 80, and a gate terminal
of the n-type transistor N2 is controlled by a control signal V4. A
source terminal of the p-type transistor P2 is coupled to the input
terminal of the switch circuit 80, a drain terminal of the p-type
transistor P2 is coupled to the output terminal of the switch
circuit 80, and a gate terminal of the p-type transistor P2 is
controlled by a control signal V3. Here, the control signal V3 and
the control signal V4 are inverted.
[0045] In the present embodiment, the data control circuit 100 is
configured in a p-type substrate of an integrated circuit. Since
the n-type transistor N2 is located in the p-type substrate, the
switching noise (or the substrate noise) flows to the ground
voltage Vss through the drain terminal of the n-type transistor N2,
the drain terminal of the n-type transistor N1, a bulk of the
n-type transistor N1, and the source terminal of the n-type
transistor N1. Accordingly, all circuits coupled to the ground
voltage Vss are interfered by the noise generated by the switch
circuit 80. The impedance module 110 is located between the source
terminal of the n-type transistor N1 and the ground voltage Vss,
i.e., on the path where the noise flows, such that the amount of
noise flowing to the ground voltage Vss may be significantly
reduced. Here, the impedance module 110 may be an n-type
transistor, for instance. A drain terminal of the n-type transistor
is coupled to the source terminal of the n-type transistor N1, a
source terminal of the n-type transistor is coupled to the ground
voltage Vss, and a gate terminal of the n-type transistor is
coupled to a fixed control voltage, for instance, so as to reduce
the amount of noise energy. Accordingly, the noise interference
caused by the switch circuit 80 may be effectively reduced by the
data control circuit 100.
[0046] However, the way to implement the data control circuit 100
shown in FIG. 1 should not be limited to that shown in FIG. 2. FIG.
3 is a schematic diagram illustrating a data control circuit
according to a second embodiment of the invention. With reference
to FIG. 1 and FIG. 3, a data control circuit 100 includes an output
stage circuit 60, a switch circuit 80, and an impedance module 110.
The description of the embodiment depicted in FIG. 3 may be deduced
from the description of the embodiment shown in FIG. 2. Different
from FIG. 2, FIG. 3 shows that the impedance module 110 is located
between the source terminal of the p-type transistor P1 and the
system voltage Vdd.
[0047] In the present embodiment, the data control circuit 100 is
configured in an n-type substrate of an integrated circuit. Since
the p-type transistor P2 is located in the n-type substrate, the
switching noise (or the substrate noise) flows to the system
voltage Vdd through the source terminal of the p-type transistor
P2, the drain terminal of the p-type transistor P1, a bulk of the
p-type transistor P1, and the source terminal of the p-type
transistor P1. Accordingly, all circuits coupled to the system
voltage Vdd are interfered by the noise generated by the switch
circuit 80. The impedance module 110 is located between the source
terminal of the p-type transistor P1 and the system voltage Vdd,
i.e., on the path where the noise flows, such that the amount of
noise flowing to the system voltage Vdd may be significantly
reduced. Accordingly, the noise interference caused by the switch
circuit 80 may be effectively reduced by the data control circuit
100.
[0048] FIG. 4 is a schematic diagram illustrating a data control
circuit according to a third embodiment of the invention. With
reference to FIG. 1 and FIG. 4, a data control circuit 100 includes
an output stage circuit 60, a switch circuit 80, and an impedance
module 110. The description of the embodiment depicted in FIG. 4
may be deduced from the description of the embodiment shown in FIG.
2. Different from FIG. 2, FIG. 4 shows that the impedance module
110 is located between the drain terminal of the n-type transistor
N1 and the output terminal of the output stage circuit 60.
[0049] In the present embodiment, the data control circuit 100 is
configured in a p-type substrate of an integrated circuit. Since
the n-type transistor N2 is located in the p-type substrate, the
switching noise (or the substrate noise) flows to the ground
voltage Vss through the drain terminal of the n-type transistor N2,
the drain terminal of the n-type transistor N1, the bulk of the
n-type transistor N1, and the source terminal of the n-type
transistor N1. The impedance module 110 is located between the
drain terminal of the n-type transistor N1 and the output terminal
of the output stage circuit 60, i.e., on the path where the noise
flows, such that the amount of noise flowing to the ground voltage
Vss may be significantly reduced. Here, the impedance module 110
may be a n-type transistor, for instance. A source terminal of the
n-type transistor of the impedance module 110 is coupled to the
drain terminal of the n-type transistor N1, a drain terminal of the
n-type transistor of the impedance module 110 is coupled to the
output terminal of the output stage circuit 60, and a gate terminal
of the n-type transistor of the impedance module 110 is coupled to
a fixed control voltage, for instance, so as to reduce the amount
of noise energy. Accordingly, the noise interference caused by the
switch circuit 80 may be effectively reduced by the data control
circuit 100.
[0050] FIG. 5 is a schematic diagram illustrating a data control
circuit according to a fourth embodiment of the invention. With
reference to FIG. 1 and FIG. 5, a data control circuit 100 includes
an output stage circuit 60, a switch circuit 80, and an impedance
module 110. The description of the embodiment depicted in FIG. 5
may be deduced from the description of the embodiment shown in FIG.
3. Different from FIG. 3, FIG. 5 shows that the impedance module
110 is located between the drain terminal of the p-type transistor
P1 and the output terminal of the output stage circuit 60.
[0051] In the present embodiment, the data control circuit 100 is
configured in an n-type substrate of an integrated circuit. Since
the p-type transistor P2 is located in the n-type substrate, the
switching noise (or the substrate noise) flows to the system
voltage Vdd through the source terminal of the p-type transistor
P2, the drain terminal of the p-type transistor P1, a bulk of the
p-type transistor P1, and the source terminal of the p-type
transistor P1. The impedance module 110 is located between the
drain terminal of the p-type transistor P1 and the output terminal
of the output stage circuit 60, i.e., on the path where the noise
flows, such that the amount of noise flowing to the system voltage
Vdd may be significantly reduced. Accordingly, the noise
interference caused by the switch circuit 80 may be effectively
reduced by the data control circuit 100.
[0052] FIG. 6 is a schematic diagram illustrating a data control
circuit according to a fifth embodiment of the invention. With
reference to FIG. 1 and FIG. 6, a data control circuit 100 includes
an output stage circuit 60, a switch circuit 80, and an impedance
module 110. The description of the embodiment depicted in FIG. 6
may be deduced from the descriptions of the embodiments shown in
FIG. 2 to FIG. 5. Different from FIG. 2 to FIG. 5, FIG. 6 shows
that the impedance module 110 is coupled to a transmission path
between the output terminal of the output stage circuit 60 and the
input terminal of the switch circuit 80.
[0053] In some embodiments of the invention, the switching noise
(or the substrate noise) flows to the system voltage Vdd through
the source terminal of the p-type transistor P2, the drain terminal
of the p-type transistor P1, the bulk of the p-type transistor P1,
and the source terminal of the p-type transistor P1. In other
embodiments of the invention, the switching noise (or the substrate
noise) flows to the ground voltage Vss through the drain terminal
of the n-type transistor N2, the drain terminal of the n-type
transistor N1, the bulk of the n-type transistor N1, and the source
terminal of the n-type transistor N1. The impedance module 110 is
located between the output terminal of the output stage circuit 60
and the input terminal of the switch circuit 80, i.e., on the path
where the noise flows, such that the amount of noise flowing to the
system voltage Vdd and the ground voltage Vss may be significantly
reduced. Accordingly, the noise interference caused by the switch
circuit 80 may be effectively reduced by the data control circuit
100.
[0054] FIG. 7 is a schematic diagram illustrating a data control
circuit according to a sixth embodiment of the invention. With
reference to FIG. 1 and FIG. 7, a data control circuit 100 includes
an output stage circuit 60, a switch circuit 80, and an impedance
module 110. The description of the embodiment depicted in FIG. 7
may be deduced from the description of the embodiment shown in FIG.
2. Different from FIG. 2, FIG. 7 shows that the impedance module
110 is coupled between the drain terminal of the n-type transistor
N2 and the input terminal of the switch circuit 80.
[0055] In the present embodiment, the data control circuit 100 is
configured in a p-type substrate of an integrated circuit. Since
the n-type transistor N2 is located in the p-type substrate, the
switching noise (or the substrate noise) flows to the ground
voltage Vss through the drain terminal of the n-type transistor N2,
the drain terminal of the n-type transistor N1, the bulk of the
n-type transistor N1, and the source terminal of the n-type
transistor N1. The impedance module 110 is located between the
drain terminal of the n-type transistor N2 and the input terminal
of the switch circuit 80, i.e., on the path where the noise flows,
such that the amount of noise flowing to the ground voltage Vss may
be significantly reduced. Accordingly, the noise interference
caused by the switch circuit 80 may be effectively reduced by the
data control circuit 100.
[0056] FIG. 8 is a schematic diagram illustrating a data control
circuit according to a seventh embodiment of the invention. With
reference to FIG. 1 and FIG. 7, a data control circuit 100 includes
an output stage circuit 60, a switch circuit 80, and an impedance
module 110. The description of the embodiment depicted in FIG. 8
may be deduced from the description of the embodiment shown in FIG.
3. Different from FIG. 3, FIG. 8 shows that the impedance module
110 is coupled between the input terminal of the switch circuit 80
and the source terminal of the p-type transistor P2.
[0057] In the present embodiment, the data control circuit 100 is
configured in an n-type substrate of an integrated circuit. Since
the p-type transistor P2 is located in the n-type substrate, the
switching noise (or the substrate noise) flows to the system
voltage Vdd through the source terminal of the p-type transistor
P2, the drain terminal of the p-type transistor P1, a bulk of the
p-type transistor P1, and the source terminal of the p-type
transistor P1. The impedance module 110 is located between the
input terminal of the switch circuit 80 and the source terminal of
the p-type transistor P2, i.e., on the path where the noise flows,
such that the amount of noise flowing to the system voltage Vdd may
be significantly reduced. Accordingly, the noise interference
caused by the switch circuit 80 may be effectively reduced by the
data control circuit 100.
[0058] However, the way to implement the output stage circuit 60
shown in FIG. 1 should not be limited to those shown in FIG. 2 to
FIG. 8. FIG. 9 is a schematic diagram illustrating a data control
circuit according to an eighth embodiment of the invention. With
reference to FIG. 1 and FIG. 9, the data control circuit 200 shown
in FIG. 9 may be deduced from the descriptions of the data control
circuit 100 shown in FIG. 1 to FIG. 8. The data control circuit 200
includes an output stage circuit 60, a switch circuit 80, and an
impedance module 110. Different from FIG. 2, FIG. 9 shows that the
output stage circuit 60 includes a first inverter circuit and a
second inverter circuit. An input terminal of the first inverter
circuit is coupled to an input terminal of the output stage circuit
60, and an output terminal of the first inverter circuit is coupled
to the output terminal of the output stage circuit 60. An input
terminal of the second inverter circuit is coupled to the output
terminal of the first inverter circuit, and an output terminal of
the second inverter circuit is coupled to the input terminal of the
first inverter circuit. The first inverter circuit and the second
inverter circuit may be implemented in different manner according
to different embodiments. The first inverter circuit includes the
n-type transistor N1 and the p-type transistor P1, and the second
inverter circuit includes an n-type transistor N4 and a p-type
transistor P3, for instance.
[0059] As shown in FIG. 9, a source terminal of the n-type
transistor N1 is coupled to the ground voltage Vss through the
impedance module 110, a drain terminal of the n-type transistor N1
and a drain terminal of the p-type transistor P1 are collectively
coupled to the output terminal of the output stage circuit 60, a
gate terminal of the n-type transistor N1 and a gate terminal of
the p-type transistor P1 are collectively coupled to the input
terminal of the output stage circuit 60, and a source terminal of
the p-type transistor P1 is coupled to the system voltage Vdd.
Besides, a source terminal of the p-type transistor P3 is coupled
to the system voltage Vdd, a drain terminal of the n-type
transistor N4 and a drain terminal of the p-type transistor P3 are
collectively coupled to the input terminal of the output stage
circuit 60, a gate terminal of the n-type transistor N4 and a gate
terminal of the p-type transistor P3 are collectively coupled to
the output terminal of the output stage circuit 60, and a source
terminal of the n-type transistor N4 is coupled to the ground
voltage Vss.
[0060] In the present embodiment, the data control circuit 200 is
configured in a p-type substrate of an integrated circuit. The
switching noise (or the substrate noise) flows to the ground
voltage Vss through the drain terminal of the n-type transistor N2,
the drain terminal of the n-type transistor N1, the bulk of the
n-type transistor N1, and the source terminal of the n-type
transistor N1. The impedance module 110 is located between the
source terminal of the n-type transistor N1 and the ground voltage
Vss, i.e., on the path where the noise flows, such that the amount
of noise flowing to the ground voltage Vss may be significantly
reduced. Accordingly, the noise interference caused by the switch
circuit 80 may be effectively reduced by the data control circuit
200.
[0061] FIG. 10 is a schematic diagram illustrating a data control
circuit according to a ninth embodiment of the invention. The data
control circuit 200 includes an output stage circuit 60, a switch
circuit 80, and an impedance module 110. The description of the
embodiment depicted in FIG. 10 may be deduced from the descriptions
of the embodiments shown in FIG. 3 and FIG. 9. Different from FIG.
9, FIG. 10 shows that the impedance module 110 is located between
the source terminal of the p-type transistor P1 and the system
voltage Vdd.
[0062] In the present embodiment, the data control circuit 200 is
configured in an n-type substrate of an integrated circuit. The
switching noise (or the substrate noise) flows to the system
voltage Vdd through the source terminal of the p-type transistor
P2, the drain terminal of the p-type transistor P1, the bulk of the
p-type transistor P1, and the source terminal of the p-type
transistor P1. The impedance module 110 is located between the
source terminal of the p-type transistor P1 and the system voltage
Vdd, i.e., on the path where the noise flows, such that the amount
of noise flowing to the system voltage Vdd may be significantly
reduced. Accordingly, the noise interference caused by the switch
circuit 80 may be effectively reduced by the data control circuit
200.
[0063] FIG. 11 is a schematic diagram illustrating a data control
circuit according to a tenth embodiment of the invention. The data
control circuit 200 includes an output stage circuit 60, a switch
circuit 80, and an impedance module 110. The description of the
embodiment depicted in FIG. 11 may be deduced from the descriptions
of the embodiments shown in FIG. 4 and FIG. 9. Different from FIG.
9, FIG. 11 shows that the impedance module 110 is located between
the drain terminal of the n-type transistor N1 and the output
terminal of the output stage circuit 60.
[0064] In the present embodiment, the data control circuit 200 is
configured in a p-type substrate of an integrated circuit. The
switching noise (or the substrate noise) flows to the ground
voltage Vss through the drain terminal of the n-type transistor N2,
the drain terminal of the n-type transistor N1, the bulk of the
n-type transistor N1, and the source terminal of the n-type
transistor N1. The impedance module 110 is located between the
drain terminal of the n-type transistor N1 and the output terminal
of the output stage circuit 60, i.e., on the path where the noise
flows, such that the amount of noise flowing to the ground voltage
Vss may be significantly reduced. Accordingly, the noise
interference caused by the switch circuit 80 may be effectively
reduced by the data control circuit 200.
[0065] FIG. 12 is a schematic diagram illustrating a data control
circuit according to an eleventh embodiment of the invention. The
data control circuit 200 includes an output stage circuit 60, a
switch circuit 80, and an impedance module 110. The description of
the embodiment depicted in FIG. 12 may be deduced from the
descriptions of the embodiments shown in FIG. 5 and FIG. 10.
Different from FIG. 10, FIG. 12 shows that the impedance module 110
is located between the drain terminal of the p-type transistor P1
and the output terminal of the output stage circuit 60.
[0066] In the present embodiment, the data control circuit 200 is
configured in an n-type substrate of an integrated circuit. The
switching noise (or the substrate noise) flows to the system
voltage Vdd through the source terminal of the p-type transistor
P2, the drain terminal of the p-type transistor P1, the bulk of the
p-type transistor P1, and the source terminal of the p-type
transistor P1. The impedance module 110 is located between the
drain terminal of the p-type transistor P1 and the output terminal
of the output stage circuit 60, i.e., on the path where the noise
flows, such that the amount of noise flowing to the system voltage
Vdd may be significantly reduced. Accordingly, the noise
interference caused by the switch circuit 80 may be effectively
reduced by the data control circuit 200.
[0067] FIG. 13 is a schematic diagram illustrating a data control
circuit according to a twelfth embodiment of the invention. The
data control circuit 200 includes an output stage circuit 60, a
switch circuit 80, and an impedance module 110. The description of
the embodiment depicted in FIG. 13 may be deduced from the
descriptions of the embodiments shown in FIG. 6 and FIG. 9 to FIG.
12. Different from FIG. 9 to FIG. 12, FIG. 13 shows that the
impedance module 110 is coupled to a transmission path between the
output terminal of the output stage circuit 60 and the input
terminal of the switch circuit 80.
[0068] In some embodiments of the invention, the switching noise
(or the substrate noise) flows to the system voltage Vdd through
the source terminal of the p-type transistor P2, the drain terminal
of the p-type transistor P1, the bulk of the p-type transistor P1,
and the source terminal of the p-type transistor P1. In other
embodiments of the invention, the switching noise (or the substrate
noise) flows to the ground voltage Vss through the drain terminal
of the n-type transistor N2, the drain terminal of the n-type
transistor N1, the bulk of the n-type transistor N1, and the source
terminal of the n-type transistor N1. The impedance module 110 is
located between the output terminal of the output stage circuit 60
and the input terminal of the switch circuit 80, i.e., on the path
where the noise flows, such that the amount of noise flowing to the
system voltage Vdd and the ground voltage Vss may be significantly
reduced. Accordingly, the noise interference caused by the switch
circuit 80 may be effectively reduced by the data control circuit
200.
[0069] FIG. 14 is a schematic diagram illustrating a data control
circuit according to a thirteenth embodiment of the invention. The
data control circuit 200 includes an output stage circuit 60, a
switch circuit 80, and an impedance module 110. The description of
the embodiment depicted in FIG. 14 may be deduced from the
descriptions of the embodiments shown in FIG. 7 and FIG. 9.
Different from FIG. 9, FIG. 14 shows that the impedance module 110
is coupled between the drain terminal of the n-type transistor N2
and the input terminal of the switch circuit 80.
[0070] In the present embodiment, the data control circuit 200 is
configured in a p-type substrate of an integrated circuit. The
switching noise (or the substrate noise) flows to the ground
voltage Vss through the drain terminal of the n-type transistor N2,
the drain terminal of the n-type transistor N1, the bulk of the
n-type transistor N1, and the source terminal of the n-type
transistor N1. The impedance module 110 is located between the
drain terminal of the n-type transistor N2 and the input terminal
of the switch circuit 80, i.e., on the path where the noise flows,
such that the amount of noise flowing to the ground voltage Vss may
be significantly reduced. Accordingly, the noise interference
caused by the switch circuit 80 may be effectively reduced by the
data control circuit 200.
[0071] FIG. 15 is a schematic diagram illustrating a data control
circuit according to a fourteenth embodiment of the invention. The
data control circuit 200 includes an output stage circuit 60, a
switch circuit 80, and an impedance module 110. The description of
the embodiment depicted in FIG. 15 may be deduced from the
descriptions of the embodiments shown in FIG. 8 and FIG. 10.
Different from FIG. 10, FIG. 15 shows that the impedance module 110
is coupled between the source terminal of the p-type transistor P2
and the input terminal of the switch circuit 80.
[0072] In the present embodiment, the data control circuit 200 is
configured in an n-type substrate of an integrated circuit. The
switching noise (or the substrate noise) flows to the system
voltage Vdd through the source terminal of the p-type transistor
P2, the drain terminal of the p-type transistor P1, the bulk of the
p-type transistor P1, and the source terminal of the p-type
transistor P1. The impedance module 110 is located between the
input terminal of the switch circuit 80 and the source terminal of
the p-type transistor P2, i.e., on the path where the noise flows,
such that the amount of noise flowing to the system voltage Vdd may
be significantly reduced. Accordingly, the noise interference
caused by the switch circuit 80 may be effectively reduced by the
data control circuit 200.
[0073] In addition to the above-mentioned manner to implement the
output stage circuit 60 in the data control circuit 200, as
provided in the eight embodiment to the fourteenth embodiment, the
output stage circuit 60 in other embodiments may also be equipped
with an n-type transistor N3 and a p-type transistor P4 which are
controlled by a clock signal CLK and an inverting clock signal
CLK.
[0074] FIG. 16 is a schematic diagram illustrating a data control
circuit according to a fifteenth embodiment of the invention. With
reference to FIG. 16, a data control circuit 200 includes an output
stage circuit 60 and a switch circuit 80. The description of the
embodiment depicted in FIG. 16 may be deduced from the descriptions
of the embodiments shown in FIG. 9 to FIG. 15. Different from FIG.
9 to FIG. 15, FIG. 16 shows that the output stage circuit 60
further includes an n-type transistor N3 and a p-type transistor
P4. As shown in FIG. 16, the source terminal of the p-type
transistor P3 is coupled to the system voltage Vdd, and the drain
terminal of the p-type transistor P3 is coupled to the source
terminal of the p-type transistor P4. The drain terminal of the
p-type transistor P4 and the drain terminal of the n-type
transistor N3 are collectively coupled to the input terminal of the
output stage circuit 60. The gate terminal of the n-type transistor
N4 and the gate terminal of the p-type transistor P3 are
collectively coupled to the output terminal of the output stage
circuit 60. The gate terminal of the n-type transistor N3 and the
gate terminal of the p-type transistor P4 are respectively coupled
to the clock signal CLK and the inverting clock signal CLK. The
source terminal of the n-type transistor N3 is coupled to the drain
terminal of the n-type transistor N4, and the source terminal of
the n-type transistor N4 is coupled to the ground voltage Vss.
[0075] Note that the descriptions of the data control circuit 200
as shown in FIG. 16 may also be deduced from the descriptions of
the impedance module 110 provided in the eighth embodiment to the
fourteenth embodiment above, and therefore no further descriptions
are provided hereinafter. The impedance module (not shown in FIG.
16) is configured in the output stage circuit 60, configured
between the output stage circuit 60 and the switch circuit 80, or
configured in the switch circuit 80. Thereby, the impedance module
may effectively reduce noise flowing from the switch circuit 80 to
the output stage circuit 60.
[0076] To sum up, in an embodiment of the invention, the impedance
module is additionally configured on the noise-coupling
transmission path in the data control circuit, e.g., configured in
the output stage circuit, configured in the switch circuit, or
configured between the output stage circuit and the switch circuit.
Thereby, the noise generated by the pose-stage switch circuit may
be effectively reduced, the pre-stage circuit may be protected from
the noise interference, and errors resulting from the noise
interference do not occur.
[0077] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
disclosed embodiments without departing from the scope or spirit of
the invention. In view of the foregoing, it is intended that the
invention cover modifications and variations of this invention
provided they fall within the scope of the following claims and
their equivalents.
* * * * *