U.S. patent application number 13/957382 was filed with the patent office on 2014-06-19 for power on reset (por) circuit.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. The applicant listed for this patent is Samsung Electro-Mechanics Co., Ltd.. Invention is credited to Joo Yul Ko, Hyun Paek.
Application Number | 20140167823 13/957382 |
Document ID | / |
Family ID | 50930184 |
Filed Date | 2014-06-19 |
United States Patent
Application |
20140167823 |
Kind Code |
A1 |
Paek; Hyun ; et al. |
June 19, 2014 |
POWER ON RESET (POR) CIRCUIT
Abstract
Disclosed herein is a power on reset (POR) circuit, including: a
current mirror circuit adjusting ratio of current flowing in a
circuit according to voltage supplied from power; an inverter
driven according to output of the current mirror circuit to output
a POR signal; a brown out detection (BOD) comparator electrically
connected to the current mirror circuit and comparing the voltage
supplied from the power with reference voltage to output a
corresponding voltage signal according to the comparison result; a
BOD controlling switch driven when the output of the BOD comparator
is zero voltage (0V) to again operate a POR; and a current
controlling switch installed in the current mirror circuit and
driven when the output of the BOD comparator is zero voltage (0V)
to control and supply current of the POR.
Inventors: |
Paek; Hyun; (Gyeonggi-do,
KR) ; Ko; Joo Yul; (Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Samsung Electro-Mechanics Co., Ltd. |
Gyeonggi-do |
|
KR |
|
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Gyeonggi-do
KR
|
Family ID: |
50930184 |
Appl. No.: |
13/957382 |
Filed: |
August 1, 2013 |
Current U.S.
Class: |
327/143 |
Current CPC
Class: |
H03K 17/223 20130101;
H03L 5/00 20130101 |
Class at
Publication: |
327/143 |
International
Class: |
H03L 5/00 20060101
H03L005/00 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 18, 2012 |
KR |
10-2012-0148432 |
Claims
1. A power on reset (POR) circuit, comprising: a current mirror
circuit adjusting ratio of current flowing in a circuit according
to voltage supplied from power; an inverter electrically connected
to the current mirror circuit and driven according to output of the
current mirror circuit to output a POR signal; a brown out
detection (BOD) comparator electrically connected to the current
mirror circuit and comparing the voltage supplied from the power
with reference voltage to output a corresponding voltage signal
according to the comparison result; a BOD controlling switch
electrically connected to an output terminal of the BOD comparator
and driven when the output of the BOD comparator is zero voltage
(0V) to again operate a POR; and a current controlling switch
installed in the current mirror circuit and driven when the output
of the BOD comparator is zero voltage (0V) to control and supply
current of the POR.
2. The POR circuit according to claim 1, wherein the BOD comparator
is configured of an operational amplifier (OP AMP).
3. The POR circuit according to claim 1, wherein the BOD comparator
is configured so that an input terminal of one side thereof is
input with reference voltage of bandgap reference (BGR) and an
input terminal of the other side thereof is input with voltage from
a supplying power VDD.
4. The POR circuit according to claim 3, wherein the BOD comparator
is configured so that the input terminal of the other side is input
with the voltage from the supplying power VDD, the voltage from the
supplying power VDD being divided by a resistor.
5. The POR circuit according to claim 3, wherein the BOD comparator
is configured so as to output zero voltage (0V) in the case in
which the input voltage from the supplying power VDD is lower than
the reference voltage of the bandgap reference (BGR).
6. The POR circuit according to claim 3, wherein the BOD comparator
is configured so as to maintain high voltage as output thereof in
the case in which the input voltage from the supplying power VDD is
the reference voltage or more of the bandgap reference (BGR).
7. The POR circuit according to claim 1, wherein the BOD
controlling switch is configured of a semiconductor switching
element.
8. The POR circuit according to claim 7, wherein the semiconductor
switching element is a p-channel type Metal Oxide Semiconductor
Field Effect Transistor (MOSFET).
9. The POR circuit according to claim 1, wherein the current
controlling switch is configured of a semiconductor switching
element.
10. The POR circuit according to claim 9, wherein the semiconductor
switching element is a p-channel type MOSFET.
Description
CROSS REFERENCE(S) TO RELATED APPLICATIONS
[0001] This application claims the benefit under 35 U.S.C. Section
119 of Korean Patent Application Serial No. 10-2012-0148432,
entitled "Power On Reset (POR) Circuit" filed on Dec. 18, 2012,
which is hereby incorporated by reference in its entirety into this
application.
BACKGROUND OF THE INVENTION
[0002] 1. Technical Field
[0003] The present invention relates to a power on reset circuit
employed in an integrated chip (IC) and the like, and particularly,
to a power on reset circuit capable of even being in a circuit
requiring a sleep mode or the IC requiring low power
consumption.
[0004] 2. Description of the Related Art
[0005] A power on reset (hereinafter, abbreviated as `POR`) circuit
is a circuit necessary for an integrated chip (IC) including a
digital circuit. A digital block needs a structure in which the
digital block is not automatically turned on while power VDD is
applied thereto but data stored in the digital block is reset by
input of a predetermined pulse. To this end, after the power VDD is
applied and a predetermined time is delayed, the input of the pulse
is required. However, the POR always needs to consume current.
Therefore, it is difficult to use the POR in a circuit requiring a
sleep mode or a circuit needed to have small power consumption.
[0006] FIG. 1 is a view showing an example of a POR circuit
according to the related art.
[0007] Referring to FIG. 1, the POR circuit according to related
art is configured of a current mirror circuit 110, an inverter 120,
and a delay capacitor 130.
[0008] When the VDD is applied as the power, current ratio is
adjusted by the current mirror circuit 110 so as to mirror current
IA to be smaller. In addition, the small IA current charges the
delay capacitor and voltage of a "point A" obtains voltage delayed
as compared to the VDD. This may obtain more delayed pulse than the
VDD through the inverter 120. FIG. 2 is a view showing a simulation
result for the POR circuit as described above.
[0009] However, in the case of the POR circuit according to related
art as described above, since the current mirror circuit 110 always
operates, it consumes significantly large power. In addition, since
the current mirror circuit 110 always operates as described above,
it is difficult to use in the case requiring the sleep mode or in
the case of the IC requiring low power.
RELATED ART DOCUMENT
Patent Document
[0010] (Patent Document 1) Korean Patent Laid-Open Publication No.
10-2010-0071603
[0011] (Patent Document 2) Japanese Patent Laid-Open Publication
No. 2007-228095
SUMMARY OF THE INVENTION
[0012] An object of the present invention is to provide a power on
reset (POR) circuit capable of being used even in a circuit
requiring a sleep mode or an integrate chip (IC) requiring low
power consumption by adding a brown out detection (BOD) circuit to
a general POR circuit to implement a POR circuit having small power
consumption.
[0013] According to an exemplary embodiment of the present
invention, there is provided a power on reset (POR) circuit,
including: a current mirror circuit adjusting ratio of current
flowing in a circuit according to voltage supplied from power; an
inverter electrically connected to the current mirror circuit and
driven according to output of the current mirror circuit to output
a POR signal; a brown out detection (BOD) comparator electrically
connected to the current mirror circuit and comparing the voltage
supplied from the power with reference voltage to output a
corresponding voltage signal according to the comparison result; a
BOD controlling switch electrically connected to an output terminal
of the BOD comparator and driven when the output of the BOD
comparator is zero voltage (0V) to again operate a POR; and a
current controlling switch installed in the current mirror circuit
and driven when the output of the BOD comparator is zero voltage
(0V) to control and supply current of the POR.
[0014] The BOD comparator may be configured of an operational
amplifier (OP AMP).
[0015] The BOD comparator may be configured so that an input
terminal of one side thereof is input with reference voltage of
bandgap reference (BGR) and an input terminal of the other side
thereof is input with voltage from a supplying power VDD.
[0016] The BOD comparator may be configured so that the input
terminal of the other side is input with the voltage from the
supplying power VDD, the voltage from the supplying power VDD being
divided by a resistor.
[0017] The BOD comparator may be configured so as to output zero
voltage (0V) in the case in which the input voltage from the
supplying power VDD is lower than the reference voltage of the
bandgap reference (BGR).
[0018] The BOD comparator may be configured so as to maintain high
voltage as output thereof in the case in which the input voltage
from the supplying power VDD is the reference voltage or more of
the bandgap reference (BGR).
[0019] The BOD controlling switch may be configured of a
semiconductor switching element.
[0020] The semiconductor switching element may be a p-channel type
Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
[0021] The current controlling switch may be configured of a
semiconductor switching element.
[0022] The semiconductor switching element may be a p-channel type
MOSFET.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a view showing an example of a POR circuit
according to the related art;
[0024] FIG. 2 a view showing a simulation result of current for
power VDD and POR output in the POR circuit of FIG. 1;
[0025] FIG. 3 is a view showing a configuration of a power on reset
(POR) circuit according to an exemplary embodiment of the present
invention;
[0026] FIG. 4 is a view showing a simulation result of POR output
and current when the POR circuit according to the exemplary
embodiment of the present invention is constantly supplied with
VDD;
[0027] FIG. 5 is a view showing a simulation result of POR output
and current when VDD drops to a predetermined value or less in the
POR circuit according to the exemplary embodiment of the present
invention; and
[0028] FIG. 6 is a view showing a simulation result of current
consumed in the POR circuit according to the related art and the
POR circuit according to the exemplary embodiment of the present
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0029] The terms and words used in the present specification and
claims should not be interpreted as being limited to typical
meanings or dictionary definitions, but should be interpreted as
having meanings and concepts relevant to the technical scope of the
present invention based on the rule according to which an inventor
can appropriately define the concept of the term to describe most
appropriately the best method he or she knows for carrying out the
invention.
[0030] Through the present specification, unless explicitly
described otherwise, "comprising" any components will be understood
to imply the inclusion of other components but not the exclusion of
any other components. The terms "unit", "module", "device" or the
like means a unit processing at least one function or operation,
which may be implemented by hardware, software, or combinations of
the hardware and the software.
[0031] Hereinafter, embodiments of the present invention will be
described in detail with reference to the accompanying
drawings.
[0032] FIG. 3 is a view showing a configuration of a power on reset
(POR) circuit according to an exemplary embodiment of the present
invention.
[0033] Referring to FIG. 3, the POR circuit according to the
exemplary circuit of the present invention includes a current
mirror circuit 310, an inverter 320, a brown out detection (BOD)
comparator 330, a BOD controlling switch 340, and a current
controlling switch 350.
[0034] The current mirror circuit 310 adjusts current ratio flowing
in a circuit according to voltage supplied from power VDD.
[0035] The inverter 320 is electrically connected to the current
mirror circuit 310, and is driven according to output of the
current mirror circuit 310 to thereby output a POR signal.
[0036] The brown out detection (BOD) comparator 330 is electrically
connected to the current mirror circuit 310, and compares supply
voltage from the power VDD with reference voltage to thereby output
a corresponding voltage signal according to the compared
result.
[0037] Here, the BOD comparator 330 may be configured of an
operational amplifier (OP-AMP).
[0038] In addition, the BOD comparator 330 may be configured so
that an input terminal of one side thereof is input with reference
voltage of bandgap reference BGR and an input terminal of the other
side thereof is input with voltage from supplying power VDD.
[0039] In this configuration, the BOD comparator 330 may be
configured so that the input terminal of the other side thereof is
input with the voltage from the supplying power VDD, the voltage
from the supplying power VDD being divided (distributed) by a
resistor, as shown in FIG. 3.
[0040] In addition, the BOD comparator 330 may be configured so as
to output zero voltage (0V) in the case in which the input voltage
from the supplying power VDD is lower than the reference voltage of
the BGR.
[0041] In addition, the BOD comparator 330 may be configured so as
to maintain high voltage as output thereof in the case in which the
input voltage from the supplying power VDD is the reference voltage
or more of the BGR.
[0042] The BOD controlling switch 340 is electrically connected to
an output terminal of the BOD comparator 330 and is driven when
output of the BOD comparator 330 is zero voltage (0V) to thereby
serve to again operate the POR. Here, the above-mentioned BOD
controlling switch 340 may be configured of a semiconductor
switching element. In this case, the semiconductor switching
element may be configured of a p-channel type Metal Oxide
Semiconductor Field Effect Transistor (MOSFET).
[0043] The current controlling switch 350 is installed in the
current mirror circuit 310 and is driven when the output of the BOD
comparator 330 is zero voltage (0V) to thereby serve to control and
supply current of the POR. Here, the current controlling switch 350
may be configured of a semiconductor switching element similar to
the BOD controlling switch 340. In this case, the semiconductor
switching element may also be configured of a p-channel type
MOSFET.
[0044] Next, operations of a POR circuit having the configuration
as described above according the exemplary embodiment of the
present invention will be briefly described.
[0045] As described above, the POR circuit according to the
exemplary embodiment of the present invention is mainly configured
of a power on reset circuit part and a brown out detection circuit
part. The POR circuit part is a circuit operated when the power is
applied and the BOD circuit part is a circuit capable of being
forcedly reset when unstable power is input during the operation.
The BOD circuit part is configured of the BOD comparator 330 using
the operational amplifier (OP AMP) as described above, wherein the
input terminal of one side of the BOD comparator 330 is input with
the reference voltage of the BGR and the input terminal of the
other side thereof is input with the voltage that the VDD is
distributed by the resistor.
[0046] In the above-mentioned situation, if the VDD is input to the
BOD comparator 330 in a state it is lower than the reference
voltage of the BGR while fluctuating, the BOD comparator 330
outputs zero voltage (0V) through the output terminal. Therefore,
the BOD controlling switch 340 (PMOS) having a gate terminal
connected to the output terminal of the BOD comparator 330 is
forcedly driven (that is, switched on) to again operate the
POR.
[0047] In the case in which the VDD voltage is constantly supplied,
the BOD comparator 330 is not operated and the output of the BOD
comparator 300 is maintained at high voltage. Therefore, the
current controlling switch 350 (PMOS) installed in the current
mirror circuit 310 is maintained in a switch off state. As a
result, current flow in the current mirror circuit 310 is blocked,
thereby preventing power consumption during the operation of the
current mirror circuit 310. This eventually means that it is
possible to design the POR consuming low power using the output of
the BOD.
[0048] When the VDD voltage that is a predetermined value or less
(that is, the reference voltage or less of the BGR) is supplied, 0V
is output through the output terminal of the BOD comparator 330.
Therefore, the current controlling switch 350 (PMOS) in the current
mirror circuit 310 is driven (that is, switched on) to thereby
supply current to the current mirror circuit 310.
[0049] Meanwhile, FIG. 4 is a view showing a simulation result of
POR output and current when the POR circuit according to the
exemplary embodiment of the present invention is constantly
supplied with VDD and FIG. 5 is a view showing a simulation result
of POR output and current when VDD drops to a predetermined value
or less in the POR circuit according to the exemplary embodiment of
the present invention.
[0050] As shown in FIG. 4, in the POR circuit according to the
exemplary embodiment of the present invention, it may be
appreciated that when the VDD is constantly supplied, the output of
the BOD comparator 330 is maintained in the high voltage state as
described above, such that both the BOD controlling switch 340 and
the current controlling switch 350 are maintained in the switch off
state and thus current does not flow in the current mirror circuit
310 to thereby represent a current value of 0 and also represent
the POR output of 0 value.
[0051] However, as shown in FIG. 5, it may be appreciated that when
the VDD drops to a predetermined value or less, the BOD comparator
330 outputs 0V as described above, such that both the BOD
controlling switch 340 and the current controlling switch 350 are
switched on to thereby immediately represent the current value and
the POR output having a predetermined magnitude value. Thereafter,
it may be appreciated that when the VDD is again constantly
supplied, the current value and the POR output also represent 0
value.
[0052] In addition, FIG. 6 is a view showing a simulation result of
current consumed in the POR circuit according to related art and
the POR circuit according to the exemplary embodiment of the
present invention.
[0053] As shown in FIG. 6, it may be appreciated that the POR
circuit according to related art continuously consumes the current
having a predetermined magnitude regardless of whether or not the
supplying voltage is uniform, but the POR circuit according to the
present invention does not consume the current as long as the
voltage is uniformly supplied.
[0054] According to the exemplary embodiment of the present
invention as described above, power consumed in a power on reset
(POR) may be minimized by adding a brown out detection (BOD)
circuit to a general POR circuit to implement the POR circuit
having small power consumption, thereby making it possible to
design a low power integrated chip (IC).
[0055] Although the preferred embodiments of the present invention
have been disclosed, the present invention is not limited thereto,
but those skilled in the art will appreciated that various
modifications, additions, and substitutions are possible, without
departing from the scope and sprit of the invention as disclosed in
the accompanying claims. Therefore, the true scope of the present
invention should be construed by the following claims, and all of
the technical spirit of the present invention within the equivalent
range thereof are included in scope of the present invention.
* * * * *