U.S. patent application number 14/182799 was filed with the patent office on 2014-06-12 for enhanced transconductance circuit.
This patent application is currently assigned to ANALOG DEVICES, INC.. The applicant listed for this patent is Sandro HERRERA. Invention is credited to Sandro HERRERA.
Application Number | 20140159813 14/182799 |
Document ID | / |
Family ID | 49211225 |
Filed Date | 2014-06-12 |
United States Patent
Application |
20140159813 |
Kind Code |
A1 |
HERRERA; Sandro |
June 12, 2014 |
ENHANCED TRANSCONDUCTANCE CIRCUIT
Abstract
A transconductance circuit that improves linearity and output
current over a wider range of input voltages than prior designs.
The transconductance circuit may include first and second sets of
paired differential transistors. In each set, emitters of the
paired transistors may be commonly coupled to corresponding nodes
of a common impedance, and collectors may be coupled to output
terminals of the transconductance circuit. The circuit may further
include first and second sets of doublet differential transistor
pairs, each doublet pair having transistors of different sizes.
Each doublet pair may have current sources coupled between commonly
coupled emitters and a source potential. Respective collectors for
each doublet pair may be coupled to the output terminals of the
transconductance circuit. A pair of voltage followers may be
provided to replicate corresponding input voltages across
corresponding bases of the differential transistor pairs and the
doublet transistor pairs.
Inventors: |
HERRERA; Sandro; (Medford,
MA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
HERRERA; Sandro |
Medford |
MA |
US |
|
|
Assignee: |
ANALOG DEVICES, INC.
Norwood
MA
|
Family ID: |
49211225 |
Appl. No.: |
14/182799 |
Filed: |
February 18, 2014 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
13424961 |
Mar 20, 2012 |
8692615 |
|
|
14182799 |
|
|
|
|
Current U.S.
Class: |
330/252 |
Current CPC
Class: |
H03F 3/45071 20130101;
H03F 3/4508 20130101; H03F 2203/45236 20130101; H03F 2203/45366
20130101; H03F 1/3211 20130101; H03F 3/45085 20130101; H03F
2203/45352 20130101 |
Class at
Publication: |
330/252 |
International
Class: |
H03F 3/45 20060101
H03F003/45 |
Claims
1. A transconductance circuit, comprising: first and second sets of
differential transistor pairs, wherein within the first set,
emitters of the transistors are coupled to a first common node and
collectors of the transistors are coupled to a first pair of output
terminals of the transconductance circuit, and wherein within the
second set, emitters of the transistors are coupled to a second
common node, and collectors of the transistors are coupled to a
second pair of output terminals of the transconductance circuit,
and wherein each set has a first transistor to receive a first
input voltage at its base, and a second transistor to receive a
second input voltage at its base; and an impedance coupled between
the first and second common nodes.
2. The transconductance circuit of claim 1, further comprising: a
first voltage follower to receive the first input voltage at a
first input terminal and replicate the first input voltages across
the bases of the first transistors of each set; and a second
voltage follower to receive the second input voltage at a second
input terminal and replicate the second input voltage across the
bases of the second transistors of each set.
3. The transconductance circuit of claim 2, wherein the circuit is
configured to generate output currents from each output terminal
that track changes for the first and second input voltages across a
predetermined voltage range.
Description
RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 13/424,961, filed on Mar. 20, 2012, the entirety of which is
incorporated by reference herein.
BACKGROUND
[0002] Transconductance is a property of certain electronic
circuits which relates to a ratio of a change in the output current
generated by a circuit versus the change in input voltage supplied
to the circuit. Transconductance may be referred to herein as
"G.sub.M," and can be represented mathematically as:
G M = .DELTA. I OUT .DELTA. V IN Eqn . 1 ##EQU00001##
[0003] A transconductance circuit may be referred to as a "GM
circuit." Ideally, the transconductance of a G.sub.M circuit should
remain linear with corresponding input voltage changes. Further,
the output current of a G.sub.M circuit should track corresponding
input voltage changes.
[0004] In application, however, linear transconductance and output
current tracking is difficult to achieve. A G.sub.M circuit is
often implemented using a differential pair of transistors as shown
in the differential pair transconductance circuit 100 of FIG. 1,
but this type of circuit suffers from known disadvantages.
[0005] The differential pair circuit 100 includes a pair of
transistors Q1, Q2 having common emitter couplings. A current
source I.sub.SOURCE is coupled to the common emitters of Q1, Q2 to
bias the circuit. Output currents I.sub.OUTP, I.sub.OUTM are
obtained from collectors of Q1 and Q2. A differential input signal
V.sub.IN, is represented by the difference of voltages V.sub.INP,
V.sub.INM, which are applied to the corresponding bases of Q1 and
Q2. The circuit 100 generates a differential output current
I.sub.OUT represented by the difference of output currents
I.sub.OUTP, I.sub.OUTM.
[0006] As the input voltages V.sub.INP, V.sub.INM vary, the
differential pair generates corresponding output currents
I.sub.OUTP, I.sub.OUTM, which relate to the input voltages. FIG. 2
is a graph 200 illustrating a simulated transconductance and
differential output current I.sub.OUT for the differential pair
circuit 100 of FIG. 1. The simulated transconductance and
differential output current I.sub.OUT are normalized for
illustrative purposes.
[0007] As shown in FIG. 2, as a differential input voltage V.sub.IN
is applied across the bases of Q1 and Q2 from -160 mV to 160 mV,
transconductance (G.sub.M) of the circuit 100 is linear only for a
small range of differential input voltages near 0V. As the
differential input voltage V.sub.IN, varies away from 0V, the
transconductance varies in a non-linear manner.
[0008] Further, the output current I.sub.OUT does not track changes
of the differential input voltage V.sub.IN. Rather, I.sub.OUT only
tracks changes in the differential input voltage V.sub.IN from
approximately -20 mV to 20 mV, and then begins to saturate. The
output current for the differential pair circuit 100 is limited by
the output current from the current source I.sub.SOURCE.
[0009] The differential pair circuit 100 generates an undesirable
output error for input voltages V.sub.INP, V.sub.INM that are
supplied at common mode voltage levels. The error is a consequence
of the finite output impedance for the current source I.sub.SOURCE.
The output error exhibits rectification which also degrades the
transconductance linearity for the differential pair circuit
100.
[0010] FIG. 3 illustrates a doublet transconductance circuit 300
(referred to as a "doublet circuit" herein). The doublet circuit
300 includes complementary sets of area-offset differential
transistor pairs. A first set includes transistors, QU.sub.1.1,
QU.sub.1.2 having a current source I.sub.U.1 coupled between
emitters of each transistor and a first source potential VSS. A
complementary transistor pair QL.sub.1.1, QL.sub.1.2 have a current
source I.sub.U.2 coupled between emitters of each transistor and a
second source potential VDD. A second set includes transistors
QU.sub.2.1, QU.sub.2.2 having a current source I.sub.U.2 coupled
between emitters of each transistor and the first source potential
VSS. A complementary transistor pair QL.sub.2.1, QL.sub.2.2 have a
current source I.sub.L.2 coupled between emitters of each
transistor and the second source potential VDD.
[0011] A first input voltage V.sub.INP is applied to the bases of
transistors QU.sub.1.1, QU.sub.2.1, QL.sub.1.1, and QL.sub.2.1. A
second input voltage V.sub.INM is applied to the bases of
transistors QU.sub.1.2, QU.sub.2.2, QL.sub.1.2, and QL.sub.2.2.
Output currents I.sub.OUTP.1 and I.sub.OUTM.1 are obtained from the
collectors of QU.sub.1.1-QU.sub.2.2 and represent half of an
overall output current I.sub.OUT1 for the doublet circuit 300.
Output currents I.sub.OUTP.2 and I.sub.OUTM.2 are obtained from the
collectors of QL.sub.1.1-QL.sub.2.2 and represent half of an
overall output current I.sub.OUT2 for the doublet circuit 300.
[0012] The transistors QU.sub.1.1-QU.sub.2.2 and
QL.sub.1.1-QL.sub.2.2 have area offsets as represented by
A.sub.OFF:1 where A.sub.OFF corresponds to an offset area factor
among the transistors. Transistors QU.sub.1.2, QU.sub.2.1,
QL.sub.1.2, and QL.sub.2.1 are larger than the other transistors by
the offset factor A.sub.OFF. When activated, the area offset
transistors conduct a correspondingly higher current than the
smaller transistors.
[0013] FIG. 4 is a graph 400 simulating transconductance for the
doublet circuit of FIG. 3 for various area offset factors. As
illustrated in FIG. 4, the transconductance for the doublet circuit
is flattened or "spread" for various area offset factors including
A.sub.OFF=4 and A.sub.OFF=6. For an area offset factor of
A.sub.OFF=1, the transconductance is similar to that of the
differential pair circuit 100 of FIG. 1. As the area offset is
increased to A.sub.OFF=4, the transconductance linearity is
improved for differential input voltages V.sub.IN from
approximately -20 mV to 20 mV. As the area offset is increased to
A.sub.OFF=6, transconductance continues to spread but linearity is
degraded.
[0014] Although the doublet circuit 300 provides improvements for
transconductance linearity, the output current is limited similar
to that of the differential pair circuit 100. The output current of
the doublet circuit 300 is limited by the currents from the current
sources I.sub.U.1, I.sub.U.2, I.sub.L.1, and I.sub.L.2.
[0015] Accordingly, there is a need in the art for a
transconductance circuit that improves transconductance linearity
and output current.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 illustrates a differential pair transconductance
circuit.
[0017] FIG. 2 is a graph simulating transconductance and
differential output current for the differential pair circuit of
FIG. 1.
[0018] FIG. 3 illustrates a doublet transconductance circuit.
[0019] FIG. 4 is a graph simulating transconductance for the
doublet circuit of FIG. 3 for various area offset factors.
[0020] FIG. 5 illustrates a transconductance circuit according to
an embodiment of the present invention.
[0021] FIG. 6 is a graph simulating transconductance and
differential output current for the transconductance circuit of
FIG. 5 versus that of the differential pair circuit of FIG. 1.
[0022] FIG. 7 illustrates an enhanced transconductance circuit
according to an embodiment of the present invention.
[0023] FIG. 8 is a graph simulating transconductance and
differential output current for the enhanced transconductance
circuit of FIG. 7 versus that of the differential pair circuit of
FIG. 1.
[0024] FIG. 9 is a method for generating a pair of output currents
from a transconductance circuit which track voltage changes for a
first predetermined range of input voltages according to an
embodiment of the present invention.
[0025] FIG. 10 is a diagram of a differential amplifier for use
with embodiments of the present invention.
DETAILED DESCRIPTION
[0026] Embodiments of the present invention provide a
transconductance circuit that improves transconductance linearity
and output current over a wider range of input voltages than prior
designs. The transconductance circuit may include first and second
sets of paired differential transistors, where, in each set,
emitters of the paired transistors may be commonly coupled to
corresponding nodes of a common impedance, and collectors may be
coupled to output terminals of the transconductance circuit. The
circuit may further include first and second sets of doublet
differential transistor pairs, each doublet pair having transistors
of different sizes. Each doublet transistor pair may have current
sources coupled between commonly coupled emitters and a source
potential. Respective collectors for each doublet transistor pair
may be coupled to the output terminals of the transconductance
circuit. A pair of voltage followers may be provided to replicate
corresponding input voltages across corresponding bases of the
complementary set of differential transistor pairs and the
complementary sets of doublet transistor pairs.
[0027] As noted, the transconductance of a single differential pair
is non-linear over a wide range of input voltages and the doublet
circuit, while providing improvements for transconductance
linearity, has limited output current. In the configuration of the
embodiments described herein, non-linear behavior is mitigated in
large part because non-linearities in the sets of differential
transistor pairs are counter-acted by non-linearities in the sets
of doublet transistor pairs. This phenomenon is discussed in
greater detail herein below. Output current is also improved in the
configuration of the embodiments described herein.
[0028] FIG. 5 illustrates a transconductance circuit 500 according
to an embodiment of the present invention (referred to as an
"I-bridge circuit" herein). The I-bridge circuit 500 may include
complementary sets of differential transistor pairs. A first
differential pair may include a first pair of transistors
QU.sub.1.1, QU.sub.1.2, having emitters commonly coupled to a first
node N1, and collectors coupled to corresponding output terminals
I.sub.OUTP.1, I.sub.OUTM.1. A second differential pair may include
a second pair of transistors QL.sub.1.1, QL.sub.1.2, having
emitters commonly coupled to a second node N2, and collectors
coupled to corresponding output terminals I.sub.OUTM.2,
I.sub.OUTP.2. A common impedance R1 may be coupled between the
first and second node N1, N2.
[0029] A pair of voltage followers FOLR.1, FOLR.2 may be coupled to
bases of corresponding transistors QU.sub.1.1, QL.sub.1.1 and
QU.sub.1.2, QL1.2. The voltage followers FOLR.1, FOLR.2 may
replicate input voltages V.sub.INP, V.sub.INM at bases of the
corresponding transistors. A first follower FOLR.1 may include a
complementary pair of transistors QC.sub.1.1, QC.sub.1.2. Current
sources I.sub.UB.1, I.sub.LB.1 may be coupled respectively to
transistors QU.sub.1.1 and QL.sub.1.1. The first follower FOLR.1
may receive a first input voltage V.sub.INP and replicate
corresponding voltages at bases of the transistors QU.sub.1.1, and
QL.sub.1.1. A second follower FOLR.2 may include a complementary
pair of transistors QC.sub.2.1, QC.sub.2.2. Current sources
I.sub.UB.2, I.sub.LB.2 may be coupled to respective bases for
transistors QU.sub.1.2, QL.sub.1.2. The second voltage follower
FOLR.2 may receive a second input voltage V.sub.INM and replicate
corresponding voltages at bases of the transistors QU.sub.1.2 and
QL.sub.1.2.
[0030] Currents generated at outputs I.sub.OUTP.1 and I.sub.OUTM.1
each may represent one-half of an overall output current I.sub.OUT1
for the I-bridge circuit 500. Similarly, currents generated at
outputs I.sub.OUTP.2 and I.sub.OUTM.2 each may represent one-half
of an overall output current I.sub.OUT2 for the I-bridge circuit
500.
[0031] During operation, each follower FOLR.1, FOLR.2 may replicate
corresponding voltages for driving the bases of each set of paired
transistors from input voltage V.sub.INP, V.sub.INM. As the input
voltages V.sub.INP, V.sub.INM may vary, each of the first pair of
transistors QU.sub.1.1, QU.sub.1.2 may generate corresponding
output currents I.sub.OUTP.1, I.sub.OUTM.1, which may relate to
input voltage variations. Similarly, each of the second pair of
transistors QL.sub.1.1, QL.sub.1.2 may generate corresponding
output currents I.sub.OUTP.2, and I.sub.OUTM.2 which may relate to
the input voltage variations.
[0032] The I-bridge circuit 500 improves transconductance linearity
and output current over the differential pair of FIG. 1. FIG. 6 is
a graph 600 simulating a transconductance and differential output
current response I.sub.OUT for the I-bridge circuit 500 of FIG. 5
versus that of the differential pair of FIG. 1. FIG. 6(a) compares
the transconductance linearity for both circuits for a range of
differential input voltages V.sub.IN from -200 mV to 200 mV. FIG.
6(b) compares the differential output current response I.sub.OUT
for both circuits across the voltage range. The output of each
circuit type is normalized for comparative purposes.
[0033] As illustrated, transconductance linearity of the I-bridge
circuit 500 is improved over that of the differential pair circuit
100 of FIG. 1. Coupling the resistor R1 between the first and
second pairs of transistors may flatten the overall
transconductance for the I-bridge circuit 500 (solid line). In
contrast, the overall transconductance for differential pair
circuit 100 (dashed line) varies greatly over the range of input
voltages V.sub.IN.
[0034] The output current I.sub.OUT of the I-bridge circuit 500 is
improved over that of the differential pair circuit. As
illustrated, the output current of the I-bridge circuit 500 may
track changes for differential input voltages V.sub.IN from
approximately -200 mV to 200 mV without saturation. The output
current of the I-bridge circuit 500 should not saturate because the
first and second transistor pairs are not limited by the output
current of a current source. In contrast, the output current of the
differential pair circuit 100 is limited by the output current of
current source I.sub.SOURCE and therefore begins to saturate as the
differential input voltages V.sub.IN begin to diverge from 0 mV. In
various embodiments, the output current for the I-bridge circuit
500 may be configured to track predetermined ranges of differential
input voltages V.sub.IN by changing the value of the common
impedance R1.
[0035] The I-bridge circuit 500 may also reduce output error
current over the differential pair circuit of FIG. 1 for common
mode input voltages. The complementary configuration of the first
and second transistor pairs QU.sub.1.1, QU.sub.1.2, QL.sub.1.1, and
QL.sub.1.2 and complementary current sources I.sub.UB.1,
I.sub.UB.2, and I.sub.LB.1, I.sub.LB.2 may minimize the output
error current. Although each transistor of the first and second
transistor pairs individually may develop output error currents for
common mode input voltages, the complementary configuration of each
pair in the I-bridge circuit 500 may cause the respective error
currents from each pair to effectively cancel each other out. Thus,
the overall output error current of the I-bridge circuit 500 may be
minimized for common mode voltages.
[0036] Noise levels for the I-bridge circuit 500 may also be
minimized even with the addition of the impedance R1 coupled
between the upper and lower transistor pairs. Typically, adding
resistances into a transconductance circuit increases differential
noise for the circuit. However, by coupling the impedance R1
between the upper and lower transistor pairs, noise that may be
generated across the impedance R1 may be common mode noise shared
by each of the first and second sets of paired transistors. Thus,
no noise should be contributed by the impedance R1.
[0037] FIG. 7 illustrates an enhanced transconductance circuit 700,
according to an embodiment of the present invention that combines
the I-bridge circuit and the doublet circuit. By combining the
I-bridge circuit and the doublet circuit, this embodiment improves
transconductance linearity even further.
[0038] The enhanced transconductance circuit 700 of this embodiment
may include two sets of differential transistor pairs QU.sub.1.1,
QU.sub.1.2 and QL.sub.1.1, QL.sub.1.2, an impedance R1, and voltage
followers FOLR.1, FOLR.2 of an I-bridge circuit. The circuit 700
also may include two sets of area offset differential transistor
pairs QU.sub.2.1, QU.sub.3.1 and QU.sub.2.2, QU.sub.3.2;
QL.sub.2.1, QL.sub.3.1 and QL.sub.2.2, QL.sub.3.2 of a doublet
circuit. As illustrated, bases of the doublet transistors
QU.sub.2.1, QU.sub.3.1, QL2.1, and QL.sub.3.1 may be coupled to
outputs of the voltage follower FOLR.1. Similarly, bases of the
doublet transistors QU.sub.2.2, QU.sub.3.2, QL2.2, and QL.sub.3.2
may be coupled to outputs of the voltage follower FOLR.2.
[0039] The doublet circuit may include current sources I.sub.U.1,
I.sub.U.2, I.sub.L.1, I.sub.L.2 coupled between corresponding sets
of doublet transistor emitters and source potentials VDD and VSS.
The enhanced transconductance circuit 700 may have output terminals
I.sub.OUTP.1, I.sub.OUTM.1, I.sub.OUTP.2, and I.sub.OUTM.2 coupled
to collectors of transistors of each of the combined I-bridge
circuit and the doublet circuit.
[0040] During operation, the enhanced transconductance circuit 700
improves linearity by combining the transconductance of the
I-bridge circuit and doublet circuit. FIG. 8 is a graph 800
simulating a transconductance and differential output current
I.sub.OUT for the enhanced transconductance circuit 700 having an
area offset factor A.sub.OFF=6 versus the differential pair circuit
100 of FIG. 1. The output of each circuit type is normalized for
comparative purposes. As illustrated in FIG. 8(a), the simulated
transconductance linearity for the enhanced transconductance
circuit 700 is improved over that of the differential pair circuit
100 over a range of differential input voltages V.sub.IN from
approximately -50 mV to 50 mV.
[0041] The enhanced transconductance circuit 700 improves
differential output current I.sub.OUT over that of the differential
pair circuit 100. As illustrated in FIG. 8(b), the enhanced
transconductance circuit 700 may generate an output current
I.sub.OUT that tracks changes for the differential input voltage
V.sub.IN without saturation. For example, the output current of the
enhanced transconductance circuit 700 may track changes for
differential input voltages V.sub.IN from approximately -200 mV to
200 mV without saturation. In contrast, the output current of the
differential pair circuit 100, which is limited by the output
current of the current source I.sub.SOURCE, begins to saturate as
the differential input voltages V.sub.IN begin to diverge from 0
mV.
[0042] The enhanced transconductance circuit 700 also minimizes
output error currents for common mode input voltages. In various
embodiments, the output current may be configured to correspond to
various ranges of differential input voltages V.sub.IN by changing
the value of the common impedance R1. In various embodiments, the
area offset factor A.sub.OFF may be configured to adjust the
transconductance linearity for the enhanced transconductance
circuit 700 for predetermined ranges of differential input voltages
V.sub.IN.
[0043] FIG. 9 is a method 900 for generating a pair of output
currents from a transconductance circuit which track voltage
changes for a predetermined range of input voltages according to an
embodiment of the present invention. As illustrated in block 910,
the method 900 may apply one of a pair of input voltages across
bases of a corresponding set of complementary I-bridge differential
transistor pairs and corresponding sets of complementary doublet
differential transistor pairs. The method 900 may apply the other
of the pair of input voltages across opposite bases of the
corresponding set complementary I-bridge differential transistor
pairs and the corresponding sets of complementary doublet
differential transistor pairs (block 920). The method 900 may
generate the pair of output currents from a first and second pair
of outputs of the transconductance circuit, wherein each output of
each pair may represent one-half of one of the pair of output
currents for the transconductance circuit (block 930).
[0044] In an embodiment, the method 900 may configure area offsets
for the complementary sets of doublet differential transistor pairs
to generate an approximately linear transconductance across the
predetermined range of input voltages (block 902). In an
embodiment, the method may configure a common impedance value for
the I-bridge differential transistor pairs to generate the output
current for the predetermined range of input voltages (block
904).
[0045] FIG. 10 is a diagram of a fully differential amplifier for
use with embodiments of the present invention. FIG. 10A illustrates
a fully differential op-amp 1010 symbolically. The op-amp 1010 may
generate a pair of output voltages V.sub.OUTP, V.sub.OUTM based on
a difference between a pair of input voltages V.sub.INP, V.sub.INM
(e.g., (V.sub.OUTP-V.sub.OUTM)=A*(V.sub.INP-V.sub.INM), where `A`
may be the open loop gain of the op-amp 1010).
[0046] FIG. 10B provides a block diagram for the fully differential
op-amp 1010. As illustrated, a G.sub.M circuit 1020 may generate
differential output currents I.sub.OUTP1, I.sub.OUT1 in response to
input voltages V.sub.INP, V.sub.INM (e.g.,
(I.sub.OUTP1-I.sub.OUTM1)=G.sub.M*(V.sub.INP-V.sub.INM)). Signal
current mirrors 1030 may generate output currents I.sub.OUTP2,
I.sub.OUTM2 corresponding to the currents I.sub.OUTP1, I.sub.OUTM1
received from the G.sub.M circuit 1020. The output currents
I.sub.OUTP2, I.sub.OUTM2 may pass through impedance blocks 1040.1,
1040.2, which may create corresponding output voltages having
magnitude G.sub.M*Z*(V.sub.INP-V.sub.INM). Amplifier buffers
1050.1, 1050.2 may generate output voltages V.sub.OUTP=-V.sub.OUTM
(e.g., (V.sub.OUT-V.sub.OUTM)=G.sub.M*Z*(V.sub.INP-V.sub.INM)).
[0047] FIG. 10C illustrates application of the G.sub.M circuit 1020
as an input stage for the op-amp 1010. As illustrated, the G.sub.M
circuit 1020 may generate complementary pairs of output currents
I.sub.OUTP1/2 and I.sub.OUTM1/2, each representing half of the
overall current for I.sub.OUTP1, I.sub.OUTM1. The signal current
mirrors 1030 may be represented as complementary sets of mirrors
1030.1-1030.4, each receiving a respective input current signal and
generating corresponding mirrored output currents. A first pair of
output currents I.sub.OUTP2/2, I.sub.OUTM2/2 may be summed at an
output node to generate the output current I.sub.OUTP and a second
pair of output currents I.sub.OUTM2/2, I.sub.OUTP2/2 may be summed
at an output node to generate the output current I.sub.OUTM.
[0048] Several embodiments of the present invention are
specifically illustrated and described herein. However, it will be
appreciated that modifications and variations of the present
invention are covered by the above teachings. In other instances,
well-known operations, components and circuits have not been
described in detail so as not to obscure the embodiments. It can be
appreciated that the specific structural and functional details
disclosed herein may be representative and do not necessarily limit
the scope of the embodiments.
[0049] Those skilled in the art may appreciate from the foregoing
description that the present invention may be implemented in a
variety of forms, and that the various embodiments may be
implemented alone or in combination. Therefore, while the
embodiments of the present invention have been described in
connection with particular examples thereof, the true scope of the
embodiments and/or methods of the present invention should not be
so limited since other modifications will become apparent to the
skilled practitioner upon a study of the drawings, specification,
and following claims.
* * * * *