U.S. patent application number 13/707426 was filed with the patent office on 2014-06-12 for non-volatile memory and manufacturing method thereof.
This patent application is currently assigned to MACRONIX INTERNATIONAL CO., LTD.. The applicant listed for this patent is MACRONIX INTERNATIONAL CO., LTD.. Invention is credited to Yao-Wen Chang, Tao-Cheng Lu, Guan-Wei Wu, I-Chen Yang.
Application Number | 20140159134 13/707426 |
Document ID | / |
Family ID | 50845408 |
Filed Date | 2014-06-12 |
United States Patent
Application |
20140159134 |
Kind Code |
A1 |
Wu; Guan-Wei ; et
al. |
June 12, 2014 |
NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF
Abstract
A non-volatile memory and a manufacturing method thereof are
provided. The non-volatile memory including a gate structure
disposed on a substrate, doped regions, charge storage layers, and
a first dielectric layer. There are recesses in the substrate at
two sides of the gate structure. The gate structure includes a gate
dielectric layer disposed on the substrate and a gate disposed on
the gate dielectric layer. There is an interface between the gate
dielectric layer and the substrate. The doped regions are disposed
in the substrate around the recesses. The charge storage layers are
disposed in the recesses, and a top surface of each of the charge
storage layers is higher than the interface. The first dielectric
layer is disposed between the charge storage layers and the
substrate, and between the charge storage layers and the gate
structure.
Inventors: |
Wu; Guan-Wei; (Hsinchu,
TW) ; Yang; I-Chen; (Hsinchu, TW) ; Chang;
Yao-Wen; (Hsinchu, TW) ; Lu; Tao-Cheng;
(Hsinchu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MACRONIX INTERNATIONAL CO., LTD. |
Hsinchu |
|
TW |
|
|
Assignee: |
MACRONIX INTERNATIONAL CO.,
LTD.
Hsinchu
TW
|
Family ID: |
50845408 |
Appl. No.: |
13/707426 |
Filed: |
December 6, 2012 |
Current U.S.
Class: |
257/324 ;
438/589 |
Current CPC
Class: |
H01L 29/42352 20130101;
H01L 29/66833 20130101; H01L 29/792 20130101 |
Class at
Publication: |
257/324 ;
438/589 |
International
Class: |
H01L 29/792 20060101
H01L029/792; H01L 29/66 20060101 H01L029/66 |
Claims
1. A non-volatile memory, comprising: a gate structure, disposed on
a substrate, wherein there are recesses in the substrate at two
sides of the gate structure, the gate structure comprising: a gate
dielectric layer, disposed on the substrate, wherein there is an
interface between the gate dielectric layer and the substrate; and
a gate, disposed on the gate dielectric layer; doped regions,
disposed in the substrate around the recesses; charge storage
layers, disposed in the recesses, and a top surface of each of the
charge storage layers is higher than the interface; and a first
dielectric layer, disposed between the charge storage layers and
the substrate, and between the charge storage layers and the gate
structure.
2. The non-volatile memory as claimed in claim 1, wherein the
distance is between 0.005 .mu.m and 0.01 .mu.m.
3. The non-volatile memory as claimed in claim 1, wherein a
thickness of the charge storage layers is between 100 .ANG. to 150
.ANG..
4. The non-volatile memory as claimed in claim 1, wherein the
recesses have a tilting sidewall.
5. The non-volatile memory as claimed in claim 1, wherein a
material of the charge storage layers comprises nitride or a high
dielectric constant material.
6. The non-volatile memory as claimed in claim 1, further
comprising second dielectric layers disposed on the charge storage
layers, wherein a top surface of each of the second dielectric
layers is coplanar with a top surface of the gate structure.
7. The non-volatile memory as claimed in claim 6, further
comprising a conductive layer disposed on the second dielectric
layers and the gate structure.
8. The non-volatile memory as claimed in claim 1, wherein the doped
regions are kept a distance from the interface, each of the
recesses has a bottom surface and at least a sidewall, and each of
the doped regions is disposed in the substrate under the bottom
surface and surrounds a part of the sidewall.
9. A method of manufacturing a non-volatile memory, comprising:
forming a gate structure on a substrate, the gate structure
comprising: a gate dielectric layer, located on the substrate,
wherein there is an interface between the gate dielectric layer and
the substrate; and a gate, located on the gate dielectric layer;
forming recesses in the substrate at two sides of the gate
structure; forming a first dielectric layer on the substrate and
the gate structure; forming doped regions in the substrate around
the recesses, wherein the doped regions are kept a distance from
the interface; forming charge storage layers in the recesses,
wherein a top surface of each of the charge storage layer is higher
than the interface.
10. The method of manufacturing the non-volatile memory as claimed
in claim 9, wherein the distance is between 0.005 .mu.m and 0.01
.mu.m.
11. The method of manufacturing the non-volatile memory as claimed
in claim 9, wherein a thickness of the charge storage layers is
between 100 .ANG. to 150 .ANG..
12. The method of manufacturing the non-volatile memory as claimed
in claim 9, wherein the recesses have a tilting sidewall.
13. The method of manufacturing the non-volatile memory as claimed
in claim 9, wherein a material of the charge storage layers
comprises nitride or a high dielectric constant material.
14. The method of manufacturing the non-volatile memory as claimed
in claim 9, further comprising forming second dielectric layers on
the charge storage layers after the charge storage layers are
formed.
15. The method of manufacturing the non-volatile memory as claimed
in claim 14, further comprising performing a planarization process
to remove a portion of the first dielectric layer and a portion of
the second dielectric layers until the gate is exposed after the
second dielectric layers are formed.
16. The method of manufacturing the non-volatile memory as claimed
in claim 15, further comprising forming a conductive layer on the
second dielectric layers and the gate structure after the
planarization process is performed.
17. The method of manufacturing the non-volatile memory as claimed
in claim 9, wherein the doped regions are kept a distance from the
interface, each of the recesses has a bottom surface and at least a
sidewall, and each of the doped regions is formed in the substrate
under the bottom surface and surrounds a part of the sidewall.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical Field
[0002] The disclosure relates to a non-volatile memory and a
manufacturing method thereof, and particularly relates to a
non-volatile memory that prevents a second bit effect and a
manufacturing method thereof.
[0003] 2. Related Art
[0004] The non-volatile memory is characterized by maintaining the
stored data even when the power is down, and has thus become a
mandatory device in many electronic products for providing normal
operation of the electronic products when booted. In particular,
flash memory is a type of non-volatile memory that allows multiple
times of programming, reading and erasing operations. With these
advantages, flash memory has become one of the most widely adopted
memory devices for personal computers and electronic
equipments.
[0005] Nitride-based flash memory is a common non-volatile memory
nowadays. In a nitride-based flash memory, a two-bit data is stored
by using a charge trapping structure formed of an
oxide-nitride-oxide layer (the well-known ONO layer). Generally
speaking, the two-bit data may be respectively stored at the left
side (left bit) and the right side (right bit) of the nitride layer
in the charge trapping structure.
[0006] However, there is a second bit effect in the nitride-based
flash memory. Namely, a reading operation to the left bit is
influenced by the right bit, whereas a reading operation to the
right bit is influenced by the left bit. In addition, as the memory
size reduces, the channel length is reduced accordingly, rendering
an even more significant influence of the second bit effect.
Therefore, the operation window and device performance of the
memory are influenced.
SUMMARY
[0007] An embodiment of the disclosure provides a non-volatile
memory adapted for preventing the second bit effect during
operation.
[0008] An embodiment of the disclosure additionally provides a
method of manufacturing a non-volatile memory adapted for
manufacturing a non-volatile memory with a larger operation
window.
[0009] An embodiment of the disclosure provides a non-volatile
memory including a gate structure, doped regions, charge storage
layers, and a first dielectric layer. The gate structure is
disposed on a substrate. There are recesses in the substrate at two
sides of the gate structure. The gate structure includes a gate
dielectric layer and a gate. The gate dielectric layer is disposed
on the substrate, wherein there is an interface between the gate
dielectric layer and the substrate. The gate is disposed on the
gate dielectric layer. The doped regions are disposed in the
substrate around the recesses. The charge storage layers are
disposed in the recesses, and a top surface of each of the charge
storage layers is higher than the interface. The first dielectric
layer is disposed between the charge storage layers and the
substrate, and between the charge storage layers and the gate
structure.
[0010] According to the non-volatile memory in an embodiment of the
disclosure, the distance is between 0.005 .mu.m and 0.01 .mu.m, for
example.
[0011] According to the non-volatile memory in an embodiment of the
disclosure, a thickness of the charge storage layers is between 100
.ANG. to 150 .ANG., for example.
[0012] According to the non-volatile memory in an embodiment of the
disclosure, the recesses have a tilting sidewall, for example.
[0013] According to the non-volatile memory in an embodiment of the
disclosure, a material of the charge storage layers is nitride or a
high dielectric constant material, for example.
[0014] According to the non-volatile memory in an embodiment of the
disclosure, second dielectric layers disposed on the charge storage
layers are further included, wherein a top surface of each of the
second dielectric layers is coplanar with a top surface of the gate
structure.
[0015] According to the non-volatile memory in an embodiment of the
disclosure, a conductive layer disposed on the second dielectric
layers and the gate structure is further included.
[0016] According to the non-volatile memory in an embodiment of the
disclosure, the doped regions are kept a distance from the
interface, each of the recesses has a bottom surface and at least a
sidewall, and each of the doped regions is disposed in the
substrate under the bottom surface and surrounds a part of the
sidewall, for example.
[0017] An embodiment of the disclosure also provides a method of
manufacturing a non-volatile memory, wherein a gate structure is
formed on a substrate. The gate structure includes a gate
dielectric layer and a gate. The gate dielectric layer is located
on the substrate, wherein there is an interface between the gate
dielectric layer and the substrate. The gate is located on the gate
dielectric layer. Then recesses are formed in the substrate at two
sides of the gate structure. Afterwards, a first dielectric layer
is formed on the substrate and the gate structure. Then doped
regions are formed in the substrate around the recesses.
Afterwards, charge storage layers are formed in the recesses,
wherein a top surface of each of the charge storage layer is higher
than the interface.
[0018] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, the distance is between
0.005 .mu.m and 0.01 .mu.m, for example.
[0019] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, a thickness of the
charge storage layers is between 100 .ANG. to 150 .ANG., for
example.
[0020] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, the recesses have a
tilting sidewall, for example.
[0021] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, a material of the charge
storage layers is nitride or a high dielectric constant material,
for example.
[0022] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, forming second
dielectric layers on the charge storage layers is further included
after the charge storage layers are formed.
[0023] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, performing a
planarization process to remove a portion of the first dielectric
layer and a portion of the second dielectric layers until the gate
is exposed is further included after the second dielectric layers
are formed.
[0024] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, forming a conductive
layer on the second dielectric layers and the gate structure is
further included after the planarization process is performed.
[0025] According to the method of manufacturing the non-volatile
memory in an embodiment of the disclosure, the doped regions are
kept a distance from the interface, each of the recesses has a
bottom surface and at least a sidewall, and each of the doped
regions is formed in the substrate under the bottom surface and
surrounds a part of the sidewall, for example.
[0026] In view of the foregoing, in the non-volatile memory in the
embodiments of the disclosure, the charge storage layers storing
charges are respectively disposed at the two opposite sides of the
gate structure, such that the channel length of memory increases to
avoid the second bit effect during operation, and the operation
window increases as well.
[0027] It should be noted that the descriptions above and
hereinafter are only exemplary only, instead of serving as
limitations of the disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are included to provide a further
understanding of the disclosure, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the disclosure and, together with the description,
serve to explain the principles of the disclosure.
[0029] FIGS. 1A through 1D are cross-sectional views illustrating a
process of manufacturing a non-volatile memory according to an
embodiment of the disclosure.
DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS
[0030] Reference will now be made in detail to the present
preferred embodiments of the disclosure, examples of which are
illustrated in the accompanying drawings. Wherever possible, the
same reference numbers are used in the drawings and the description
to refer to the same or like parts.
[0031] FIGS. 1A through 1D are cross-sectional views illustrating a
process of manufacturing a non-volatile memory according to an
embodiment of the disclosure. First, referring to FIG. 1A, a
substrate 100 is provided. The substrate 100 is, for example, a
silicon substrate, or a silicon-on-insulator (SOI) substrate. Then,
a gate dielectric material layer (not shown) and a gate material
layer (now shown) are formed in sequence on the substrate 100. The
gate dielectric material layer is, for example, an oxide layer with
a thickness between, for example, 170 .ANG. to 190.ANG., and is
formed by, for example, a thermal oxidation process or a chemical
vapor deposition process. The gate material layer is, for example,
a polysilicon layer, formed by a chemical vapor deposition process.
Then the gate material layer and the gate dielectric material layer
are patterned to form a gate 104 and a gate dielectric layer 102. A
width W1 of the gate 104 is, for example, between 0.05 .mu.m to 0.1
.mu.m The gate dielectric layer 102 and the gate 104 form a gate
structure 104.
[0032] Afterwards, referring to FIG. 1B, recesses 108 are formed in
the substrate 100 at two sides of the gate structure 106. The
recesses 108 are formed by, for example, performing an anisotropic
etching process to remove a portion of the substrate 100. In this
embodiment, the recesses 108 have a tilting sidewall. However, the
disclosure is not limited thereto. In other embodiments, the
recesses 108 may also have a vertical sidewall. Then, a dielectric
layer 110 is formed on the substrate 100 and the gate structure
106. The dielectric layer 110 is, for example, an oxide layer with
a thickness between, for example, 50 .ANG. and 100 .ANG., and
formed by, for example, a thermal oxidation process or a chemical
vapor deposition process.
[0033] Then, referring to FIG. 1C, doped regions 112 are formed in
the substrate 100 around the recesses 108. Specifically, each of
the recesses 108 has a bottom surface 108a and at least a sidewall
108b, and each of the doped regions 112 is formed in the substrate
100 under the bottom surface 108a and surrounds a part of the
sidewall 108b.
[0034] The doped regions 112 are formed by performing an ion
implantation process, for example. A depth of the doped regions 112
is, for example, between 0.05 .mu.m to 0.09 .mu.m. It should be
noted that an interface 113 is between the gate dielectric layer
102 and the substrate 100, and the doped regions 112 do not contact
the interface 113. Namely, there is a distance D1 between each of
the doped regions 112 and the interface 113. The distance D1 is,
for example, between 0.005 .mu.m to 0.01 .mu.m. The doped regions
112 at the two sides of the gate structure 106 respectively serve
as a source region and a drain region of a non-volatile memory.
Then, charge storage layers 114 are formed in the recesses 108 to
complete manufacture of a non-volatile memory 10 of this
embodiment. The dielectric layer 110 disposed between the charge
storage layers 114 and the substrate 100 serves as a tunneling
dielectric layer. A top surface of each of the charge storage
layers 114 is higher than the interface 113. A material of the
charge storage layers 114 is, for example, nitride or a high
dielectric constant material. A thickness of the charge storage
layers 114 is, for example, between 100 .ANG. to 150 .ANG.. The
charge storage layer 114 is formed by depositing a charge storage
material layer in the recesses 108, and then performing an
etch-back process to remove a portion of the charge storage
material layer.
[0035] Then, referring to FIG. 1D, after forming the charge storage
layers 114, dielectric layers 116 may be further formed on the
charge storage layers 114. The dielectric layers 116 are oxide
layers, for example. The dielectric layers 116 are, for example,
formed by depositing a dielectric material layer on the charge
storage layers 114 and then performing a planarization process to
remove a portion of the dielectric layer 116 and the dielectric
layers 110 until the gate 104 is exposed. Then, a conductive layer
118 is formed on the dielectric layers 116 and 110 and the gate
structure 106. The conductive layer 118 is used to connect the gate
104 of the non-volatile memory 10 with a gate of an adjacent
non-volatile memory (now shown). Namely, the conductive layer
serves as a word line.
[0036] In the non-volatile memory 10, the charge storage layers 114
storing charges are respectively disposed at the two opposite sides
of the gate structure 106, such that the second bit effect during
operation caused by a short channel length of memory is effectively
prevented and an operation window is increased.
[0037] In addition, in the non-volatile memory 10, the doped
regions 112 and the interface 113 are kept the distance D1 instead
of being connected to each other. Therefore, when the non-volatile
memory 10 is operated, the charges may be effectively injected into
the charge storage layers 114.
[0038] In addition, since the top surface of each of the charge
storage layers 114 is higher than the interface 113, direct
penetration of charges through the dielectric layer 110 into the
dielectric layers 116 on the charge storage layers 114 may be
prevented.
[0039] Although the disclosure has been described with reference to
the above embodiments, it will be apparent to one of the ordinary
skill in the art that modifications to the described embodiment may
be made without departing from the spirit of the disclosure.
Accordingly, the scope of the disclosure will be defined by the
attached claims not by the above detailed descriptions.
* * * * *