U.S. patent application number 14/168407 was filed with the patent office on 2014-05-29 for memory system with user configurable density/performance option.
This patent application is currently assigned to MICRON TECHNOLOGY, INC.. The applicant listed for this patent is MICRON TECHNOLOGY, INC.. Invention is credited to Frankie F. Roohparvar.
Application Number | 20140149648 14/168407 |
Document ID | / |
Family ID | 35450279 |
Filed Date | 2014-05-29 |
United States Patent
Application |
20140149648 |
Kind Code |
A1 |
Roohparvar; Frankie F. |
May 29, 2014 |
MEMORY SYSTEM WITH USER CONFIGURABLE DENSITY/PERFORMANCE OPTION
Abstract
The memory system has one or more memory dies coupled to a
processor or other system controller. Each die has a separate
memory array organized into multiple memory blocks. The different
memory blocks of each die can be assigned a different memory
density by the end user, depending on the desired memory
performance and/or memory density. The user configurable
density/performance option can be adjusted with special read/write
operations or a configuration register having a memory density
configuration bit for each memory block.
Inventors: |
Roohparvar; Frankie F.;
(Monte Sereno, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MICRON TECHNOLOGY, INC. |
Boise |
ID |
US |
|
|
Assignee: |
MICRON TECHNOLOGY, INC.
Boise
ID
|
Family ID: |
35450279 |
Appl. No.: |
14/168407 |
Filed: |
January 30, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12434371 |
May 1, 2009 |
8644065 |
|
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14168407 |
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10861645 |
Jun 4, 2004 |
7535759 |
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12434371 |
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Current U.S.
Class: |
711/103 |
Current CPC
Class: |
G11C 2211/5641 20130101;
G11C 16/0483 20130101; G11C 11/5621 20130101; G06F 12/0246
20130101 |
Class at
Publication: |
711/103 |
International
Class: |
G06F 12/02 20060101
G06F012/02 |
Claims
1. An apparatus comprising: a memory array comprising a block of
memory cells; control circuitry configured to control operations on
the memory array; and a configuration register coupled to the
control circuitry and configured to store a density configuration
bit, wherein the density configuration bit is assigned to a
sub-block of the block of memory cells and wherein the block of
memory cells is assigned multiple configuration bits.
2. The apparatus of claim 1, wherein a memory device includes the
memory array, the control circuitry and the configuration register,
and wherein the apparatus further comprises a processor coupled to
the memory device.
3. The apparatus of claim 2, further comprising a random access
memory (RAM) to store memory density configuration data that is
read from the memory array.
4. The apparatus of claim 1, wherein the configuration register is
configured to also store at least one of trimming data, memory
block lock data, and record keeping data.
5. The apparatus of claim 1, wherein the configuration register is
further configured to store another density configuration bit,
wherein the other density configuration bit is assigned to more
than one block of memory cells.
6. The apparatus of claim 1, wherein the control circuitry is
configured to load configuration data from the memory array into
the configuration register.
7. The apparatus of claim 1, wherein the control circuitry is
configured to load configuration data from the memory array into
the configuration register at initialization of a device including
the memory array, the control circuitry and the configuration
register.
8. The apparatus of claim 1, wherein the control circuitry is
configured to load configuration data from the memory array into
the configuration register at power-tip of a device including the
memory array, the control circuitry and the configuration
register.
9. The apparatus of claim 1, wherein the control circuitry is
configured to check the configuration register to determine a
configuration assignment of the block.
10. The apparatus of claim 1, wherein the control circuitry is
configured to copy data in the configuration register to the memory
array in relation to powering down of a device including the memory
array, the control circuitry and the configuration register.
11. An apparatus comprising: a memory array comprising a block of
memory cells; control circuitry configured to control operations on
the memory array, the control circuitry configured to set memory
blocks of the memory to one of a high density configuration or a
low density configuration to achieve a desired reliability
indicator.
12. The apparatus of claim 11, wherein a memory device includes the
memory array, the control circuitry and the configuration register,
and wherein the apparatus further comprises a processor coupled to
the memory device.
13. The apparatus of claim 11, wherein the desired reliability
indicator is a mean time before failure.
14. The apparatus of claim 11, wherein the desired reliability
indicator is a range mean times before failure.
15. The apparatus of claim 11, and further comprising a table
stored in the memory, the table configured to contain entries
indicating a quantity of memory blocks that are to be set to the
high density configuration and the low density configuration in
order to achieve the desired reliability indicator.
16. The apparatus of claim 11, and further comprising a table
stored in the memory, the table configured to store density
configuration bits for memory blocks of the memory having the high
density configuration and the low density configuration.
17. The apparatus of claim 11, and further comprising a
configuration register coupled to the control circuitry, the
configuration register configured to store a configuration bit
indicating an operating mode for each memory block of the
memory.
18. The apparatus of claim 11, and further comprising a
configuration register coupled to the control circuitry, the
configuration register configured to store a plurality of
configuration bits, and wherein a configuration bit of the
configuration register is configured to store density configuration
information for more than one block of memory cells of the memory
array.
19. An apparatus comprising: a memory array comprising a block of
memory cells; control circuitry configured to control operations on
the memory array; and a configuration register coupled to the
control circuitry and configured to store density configuration
bits to set memory blocks of the memory to one of a high density
configuration or a low density configuration to achieve a desired
reliability indicator.
20. The apparatus of claim 19, wherein a memory device includes the
memory array, the control circuitry and the configuration register,
and wherein the apparatus further comprises a processor coupled to
the memory device.
Description
RELATED APPLICATIONS
[0001] This is a continuation of U.S. application Ser. No.
12/434,371, titled "MEMORY SYSTEM WITH USER CONFIGURABLE
DENSITY/PERFORMANCE OPTION", filed May 1, 2009 (allowed), which is
a continuation of U.S. application Ser. No. 10/861,645, filed Jun.
4, 2004, now U.S. Pat. No. 7,535,759 issued on May 19, 2009, which
are assigned to the assignee of the present invention and the
entire contents of which are incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
[0002] The present invention relates generally to memory devices
and in particular the present invention relates to non-volatile
memory devices.
BACKGROUND OF THE INVENTION
[0003] Memory devices are typically provided as internal,
semiconductor, integrated circuits in computers or other electronic
devices. There are many different types of memory including
random-access memory (RAM), read only memory (ROM), dynamic random
access memory (DRAM), synchronous dynamic random access memory
(SDRAM), and flash memory.
[0004] Flash memory devices have developed into a popular source of
non-volatile memory for a wide range of electronic applications.
Flash memory devices typically use a one-transistor memory cell
that allows for high memory densities, high reliability, and low
power consumption. Common uses for flash memory include personal
computers, personal digital assistants (PDAs), digital cameras, and
cellular telephones. Program code and system data such as a basic
input/output system (BIOS) are typically stored in flash memory
devices for use in personal computer systems.
[0005] The present trend of electronic devices is increased
performance at reduced cost. The component manufacturers,
therefore, must continue to increase the performance of their
devices while decreasing the cost to manufacture them.
[0006] One way to increase a flash memory device's density while
lowering its manufacturing cost is to use multiple level cells
(MLC). Such a device stores two logical bits per physical cell.
This reduces the overall cost of the memory. NAND flash memory
devices are designed to operate in either one of two configurations
on the same die: single bit per cell (SBC) or MLC. The selection of
the configuration is done at the factory when the die is
manufactured through a metal mask or a programmable fuse
option.
[0007] However, an MLC die, while having improved cost versus
density, has drawbacks relative to performance. Both the
programming and read operations can become slower for an MLC die.
Therefore, the user typically has to choose between having high
memory density at low cost and lower memory density with higher
performance.
[0008] For the reasons stated above, and for other reasons stated
below which will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for a memory system that combines the attributes of
both MLC and SBC.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 shows a diagram of one embodiment of a NAND flash
memory array of the present invention.
[0010] FIG. 2 shows a block diagram of one embodiment of a flash
memory system of the present invention that incorporates the memory
array of FIG. 1.
[0011] FIG. 3 shows a flowchart of one embodiment of a method for
determining the desired density/performance configuration of the
flash memory system.
[0012] FIG. 4 shows a flowchart of one embodiment of a method for
configuring the density/performance of the flash memory system.
[0013] FIG. 5 shows a flowchart of another embodiment of a method
for configuring the density/performance of the flash memory
system.
DETAILED DESCRIPTION
[0014] In the following detailed description of the invention,
reference is made to the accompanying drawings that form a part
hereof and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present invention is defined only by the appended
claims and equivalents thereof.
[0015] FIG. 1 illustrates a NAND flash array is comprised of an
array of floating gate cells 101 arranged in series strings 104,
105. Each of the floating gate cells are coupled drain to source in
the series chain 104, 105. Word lines (WL0-WL31) that span across
multiple series strings 104, 105 are coupled to the control gates
of every floating gate cell in order to control their operation.
The memory array is arranged in row and column form such that the
word lines (WL0-WL31) form the rows and the bit lines (BL1-BL2)
form the columns.
[0016] In operation, the word lines (WL0-WL31) select the
individual floating gate memory cells in the series chain 104, 105
to be written to or read from and operate the remaining floating
gate memory cells in each series string 104, 105 in a pass through
mode. Each series string 104, 105 of floating gate memory cells is
coupled to a source line 106 by a source select gate 116, 117 and
to an individual bit line (BL1-BL2) by a drain select gate 112,
113. The source select gates 116, 117 are controlled by a source
select gate control line SG(S) 118 coupled to their control gates.
The drain select gates 112, 113 are controlled by a drain select
gate control line SG(D) 114.
[0017] The memory cells illustrated in FIG. 1 can be operated as
either single bit cells (SBC) or multilevel cells (MLC). Multilevel
cells greatly increase the density of a flash memory device. Such
cells enable storage of multiple bits per memory cell by charging
the floating gate of the transistor to different levels. MLC
technology takes advantage of the analog nature of a traditional
flash cell by assigning a bit pattern to a specific voltage range
stored on the cell. This technology permits the storage of two or
more bits per cell, depending on the quantity of voltage ranges
assigned to the cell.
[0018] For example, a cell may be assigned four different voltage
ranges of 200 mV for each range. Typically, a dead space or guard
band of 0.2V to 0.4V is between each range. If the voltage stored
on the cell is within the first range, the cell is storing a 00. If
the voltage is within the second range, the cell is storing a 01.
This continues for as many ranges are used for the cell.
[0019] The embodiments of the present invention may refer to the
MLC as a high density configuration. The embodiments of the present
invention are not limited to two bits per cell. Some embodiments
may store more than two bits per cell, depending on the quantity of
different voltage ranges that can be differentiated on the cell.
Therefore, the term high density generally refers to any density
beyond single bit cells.
[0020] FIG. 2 illustrates a block diagram of one embodiment of a
flash memory system 220 of the present invention that incorporates
the memory array illustrated in FIG. 1. The memory device 200 has
been simplified to focus on features of the memory that are helpful
in understanding the present invention. A more detailed
understanding of internal circuitry and functions of flash memories
are known to those skilled in the art.
[0021] A processor 210 controls the operation of the flash memory
system. The processor 210 may be a microprocessor, a
microcontroller, or some other type of control circuitry that
generates the memory control, data, and address signals required by
the memory device 200.
[0022] The memory device 200 includes an array of flash memory
cells 230 as discussed previously. An address buffer circuit 240 is
provided to latch address signals provided on address input
connections A0-Ax 242. Address signals are received and decoded by
a row decoder 244 and a column decoder 246 to access the memory
array 230. It will be appreciated by those skilled in the art, with
the benefit of the present description, that the number of address
input connections depends on the density and architecture of the
memory array 230. That is, the number of addresses increases with
both increased memory cell counts and increased bank and block
counts.
[0023] The memory device 200 reads data in the memory array 230 by
sensing voltage or current changes in the memory array columns
using sense amplifier/buffer circuitry 250. The sense
amplifier/buffer circuitry, in one embodiment, is coupled to read
and latch a row of data from the memory array 230. Data input and
output buffer circuitry 260 is included for bi-directional data
communication over a plurality of data connections 262 with the
controller 210. Write circuitry 255 is provided to write data to
the memory array.
[0024] Control circuitry 270 decodes signals provided on a control
bus 272. These signals are used to control the operations on the
memory array 230, including data read, data write, and erase
operations. The control circuitry 270 may be a state machine, a
sequencer, or some other type of controller. The control circuitry
270, in one embodiment, is responsible for executing the
embodiments of the methods of the present invention for configuring
the memory blocks as high or single density.
[0025] The control circuitry 270 can also program the configuration
registers 280 in which, in one embodiment, the high/single density
memory configuration bits of the present invention can reside. This
register may be a non-volatile, programmable fuse apparatus, a
volatile memory array, or both. The configuration register 280 can
also hold other data such as trimming data, memory block lock data,
record keeping data for the memory device, and other data required
for operation of the memory device.
[0026] In one embodiment, random access memory (RAM) 290 is
included in the system 220 for volatile storage of data. The RAM
290 might be used to store memory density configuration data that
is read from the non-volatile memory array 230 during
initialization. In an embodiment where the system 220 is a memory
card, the RAM 290 might be included on the card or coupled to the
card through a back plane or other bus transmission structure.
[0027] The flash memory system illustrated in FIG. 2 can be
implemented on a memory card, as a computer system, or any other
type of non-volatile memory system requiring a system controller
and non-volatile memory. Additional embodiments may include more
than one memory device coupled to the processor. In such an
embodiment, the processor could determine which blocks in the
different flash memory devices would be assigned to have
information stored in SBC or MLC. Such a system allows the end user
to optimize for best performance, cost, and memory density
depending on system use.
[0028] FIG. 3 illustrates a flowchart of one embodiment of a method
for determining the desired density/performance configuration of
the memory system of FIG. 2. In one embodiment, the method begins
when the system is powered up or otherwise initialized. As part of
the initialization process or after the initialization process has
been completed, the desired density/performance configurations for
the flash memory in the system are obtained 301.
[0029] The desired density/performance configurations can be
obtained in various ways, depending on the embodiment. A user can
input some type of performance parameter that is used by the system
to generate the memory block configurations of the present
invention.
[0030] In one embodiment, the user provides the system with a
desired average memory access speed performance parameter and the
system determines the memory density required to obtain or come
closest to that speed. For example, the processor may have an
algorithm or table stored in memory (i.e., RAM or flash) that lists
or determines the quantity of memory blocks that should be set to
SBC and/or MLC in order to achieve an average access speed. Such an
embodiment may require different flash memory dies of the system to
have different quantities of memory blocks set to different
densities. In the alternative, the user may just input that high
access speed is desired. In this case, the system processor can set
all of the flash memories to SBC.
[0031] In another embodiment, the user may input that a high
reliability performance parameter is important. In this case, the
processor can set the flash memories to SBC in order to get the
highest reliability possible. The processor can also set only
certain blocks of each flash memory die or a certain quantity of
entire flash memory dies to obtain the desired mean time before
failure (MTBF) or other reliability indicator. The processor can
access a table stored in non-volatile memory or RAM that indicates
the required quantity of memory blocks that are set to SBC and/or
MLC in order to achieve a predetermined MTBF or range of MTBFs. An
algorithm or other means can also be used to determine the quantity
of SBC/MLC blocks are required to achieve certain MTBFs.
[0032] In yet another embodiment, the user may input the planned
use of the memory system and the system processor determines the
best memory density necessary to meet that need. For example, if
the memory system is a memory card and the user inputs that the
card is to be used to store photographs, reliability is not as
important as memory density and a predetermined quantity or all of
the flash memory dies may be set to MLC. If the user is to use the
memory card to store code, reliability is more important than
density and all or a predetermined quantity of the flash memory
dies are set to SBC.
[0033] After the memory density/performance configurations have
been generated 301, the memory blocks of the flash memory die or
dies are then configured 305. The configuration can be accomplished
in many ways. Two embodiments for configuring the
density/performance of flash memory are illustrated in FIGS. 4 and
5.
[0034] FIG. 4 illustrates a flowchart of one embodiment of a method
for configuring the density/performance of a memory device 305.
This embodiment uses special write and read commands to perform
high density program and read operations. This embodiment puts the
burden on the memory control circuitry to determine the
density/performance configuration for a particular block. By having
the control circuitry perform this task, the memory device does not
require any extra hardware in order to switch blocks between high
density and single density. The controller tracks the
density/performance level.
[0035] This embodiment uses two sets of algorithms--one for SBC
reading and writing and another for MLC reading and writing. A
higher level routine determines which set of algorithms to use
depending on the received command. In this embodiment, the erase
operation is substantially similar for each memory density.
[0036] The method determines if the received command is a read or
write command 401. If a write command was received, it is
determined 403 whether the command is a single density write
command or a special high density write command. A high density
write command 407 causes the controller circuitry to program the
specified memory block with two or more bits per cell. A single
density write command 409 causes the controller circuitry to
program the specified memory block with one bit per cell.
[0037] If the received command is a read command, it is determined
405 whether the command is a single density read command or a high
density read command. If the command is a high density read command
411, the memory block was previously programmed as an MLC cell and
is, therefore, read with a high density read operation. A single
density configuration read command causes the memory block to be
read 413 assuming it was programmed as an SBC.
[0038] FIG. 5 illustrates another embodiment for configuring the
density/performance of a memory device 305. In this embodiment, the
SBC or MLC configuration is pre-assigned to blocks of memory using
a configuration register. This could occur during or after system
initialization. This embodiment uses flash memory read and write
commands. Additionally, an existing register could be used to store
the configuration data so that additional hardware is not required
or, in another embodiment, a dedicated configuration register could
be added to the memory device.
[0039] In one embodiment, the register of the present invention has
a bit for every memory block for indicating the operating mode
(e.g., MLC or SBC) of that particular block. For example, a logical
1 stored in the memory block 0 configuration bit would indicate
that the block is an SBC block while a logical 0 would indicate the
block is operating as an MLC block. In another embodiment, these
logic levels are reversed.
[0040] Alternate embodiments can assign different quantities of
blocks to each bit of the configuration register. For example, the
register may have a configuration bit assigned to more than one
memory block. Additionally, a configuration bit may be assigned to
the sub-block level such that each block has multiple configuration
bits.
[0041] In one embodiment, row 0 of the flash memory device of the
present invention is a configuration row. At initialization and/or
power-up of the device, the configuration data from row 0 is loaded
into the configuration register 501.
[0042] When a command is received, it is determined whether it is a
read or write command 503. For a read command, the configuration
register is checked prior to the read operation to determine if the
memory block has been assigned a high density or single density
configuration 507. In a single density configuration 511, a single
density read operation is performed 519. In a high density
configuration 511, a high density read operation is performed
517.
[0043] If a write command was received, the configuration register
is checked prior to write operation to determine if the memory
block has been assigned a high density or a single density
configuration 509. In a single density configuration 509, a single
density write operation is performed 515. In a high density
configuration 509, a high density write operation is performed
513.
[0044] In the embodiment of FIG. 5, the user determines the
configuration of each block, or other memory cell grouping, and
stores this data into the configuration register. When the memory
device is powered down, the data in the configuration register is
copied to row 0 for more permanent storage in non-volatile memory.
In another embodiment, the user can store the configuration
directly to the non-volatile, configuration row of the memory
device.
[0045] The flash memory of the present invention is comprised of
memory blocks that can each be configured to store data in
different densities. For example, one use of a single memory device
might be to store both pictures and code. The picture data is more
tolerant of corrupted data than the storage of code. Therefore,
since the SBC configuration has a higher reliability than the MLC
configuration, the user would typically choose the SBC
configuration for the code storage and the MLC configuration for
the picture storage.
[0046] Similarly, since the MLC configuration might be eight to
nine times slower in read and programming performance as compared
to the SBC configuration, the user might choose the MLC
configuration for memory blocks requiring faster read/write times.
This could be useful in a system having fast bus speeds requiring
fast storage and retrieval times.
CONCLUSION
[0047] In summary, the embodiments of the present invention enable
a memory system user to select between an MLC and an SBC
configuration. Different configurations can be set up for different
memory blocks over multiple flash memory dies in the memory system.
Additionally, the density/performance configuration changes can be
performed dynamically with configuration commands.
[0048] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement that is calculated to achieve the
same purpose may be substituted for the specific embodiments shown.
Many adaptations of the invention will be apparent to those of
ordinary skill in the art. Accordingly, this application is
intended to cover any adaptations or variations of the invention.
It is manifestly intended that this invention be limited only by
the following claims and equivalents thereof.
* * * * *