U.S. patent application number 14/143107 was filed with the patent office on 2014-05-15 for monolithic ceramic electronic component.
This patent application is currently assigned to Murata Manufacturing Co., Ltd.. The applicant listed for this patent is Murata Manufacturing Co., Ltd.. Invention is credited to Teppei AKAZAWA, Masahiro SAKURATANI.
Application Number | 20140133063 14/143107 |
Document ID | / |
Family ID | 47614167 |
Filed Date | 2014-05-15 |
United States Patent
Application |
20140133063 |
Kind Code |
A1 |
SAKURATANI; Masahiro ; et
al. |
May 15, 2014 |
MONOLITHIC CERAMIC ELECTRONIC COMPONENT
Abstract
In a monolithic ceramic electronic component, given that an
interval between outer-layer dummy conductors adjacent to each
other in an outer layer portion is d1, and that an interval between
first and second inner electrodes adjacent to each other in an
inner layer portion is d2, 1.7d2.ltoreq.d1 is satisfied. By
reducing a density of the outer-layer dummy conductors in the outer
layer portion on that condition, pressing of the inner electrodes
through the outer-layer dummy conductors is relieved in a pressing
step before firing. As a result, a distance between the inner
electrodes can be prevented from being locally shortened. It is
hence possible to effectively reduce and prevent degradation of
reliability of the monolithic ceramic electronic component, e.g., a
reduction of BDV.
Inventors: |
SAKURATANI; Masahiro;
(Nagaokakyo-shi, JP) ; AKAZAWA; Teppei;
(Nagaokakyo-shi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Murata Manufacturing Co., Ltd. |
Nagaokakyo-shi |
|
JP |
|
|
Assignee: |
Murata Manufacturing Co.,
Ltd.
Nagaokakyo-shi
JP
|
Family ID: |
47614167 |
Appl. No.: |
14/143107 |
Filed: |
December 30, 2013 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
13561285 |
Jul 30, 2012 |
8654504 |
|
|
14143107 |
|
|
|
|
Current U.S.
Class: |
361/301.4 |
Current CPC
Class: |
H01C 1/148 20130101;
H01C 7/18 20130101; H01G 4/232 20130101; H01G 4/30 20130101; H01G
4/005 20130101; H01G 4/012 20130101; H01L 41/0471 20130101 |
Class at
Publication: |
361/301.4 |
International
Class: |
H01G 4/005 20060101
H01G004/005; H01G 4/30 20060101 H01G004/30 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 2, 2011 |
JP |
2011-168869 |
Mar 30, 2012 |
JP |
2012-079714 |
Claims
1. A monolithic ceramic electronic component comprising: a ceramic
base element including a plurality of stacked ceramic layers and
outer surfaces defined by a pair of principal surfaces opposed to
each other, a pair of lateral surfaces opposed to each other, and a
pair of end surfaces opposed to each other, the lateral surfaces
extending in a lengthwise direction interconnecting the pair of end
surfaces and having a size longer than that of the end surfaces
extending in a widthwise direction interconnecting the pair of
lateral surfaces; first inner electrodes disposed inside the
ceramic base element and each including a first opposing portion,
which is substantially rectangular and including a longer side and
a shorter side, and a first lead-out portion led out from the
longer side of the first opposing portion to the lateral surface of
the ceramic base element; second inner electrodes disposed inside
the ceramic base element and each including a second opposing
portion, which is opposed to the first opposing portion, and a
second lead-out portion led out from the second opposing portion to
the outer surface of the ceramic base element; a first outer
electrode disposed on the lateral surface of the ceramic base
element and including a plated film that directly covers an exposed
portion of the first lead-out portion; and a second outer electrode
disposed on the outer surface of the ceramic base element,
electrically connected to the exposed portion of the second
lead-out portion, and connected to a different potential from that
of the first outer electrode; wherein given that a region where the
first inner electrodes and the second inner electrodes are present
in a height direction interconnecting the pair of principal
surfaces is defined as an inner layer portion; and that a region
where the first inner electrodes and the second inner electrodes
are both not present in the height direction is defined as an outer
layer portion; a plurality of outer-layer dummy conductors are
disposed in the outer layer portion to be stacked in the height
direction such that the outer-layer dummy conductors are each led
out to the lateral surface in overlapped relation to the first
lead-out portion when the ceramic base element is viewed through
projection in the height direction, the outer-layer dummy
conductors being connected to the plated film of the first outer
electrode; and given that an interval between the outer-layer dummy
conductors adjacent to each other in the outer layer portion is d1,
and that an interval between the first and second inner electrodes
adjacent to each other in the inner layer portion is d2,
1.7d2.ltoreq.d1 is satisfied.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a monolithic ceramic
electronic component, and more particularly to a monolithic ceramic
electronic component provided with outer electrodes including
plated films that are disposed and formed directly on outer
surfaces of a ceramic base element.
[0003] 2. Description of the Related Art
[0004] Recently, the sizes of electronic devices, such as cellular
phones, notebook personal computers, digital cameras, and digital
audio devices, have been reduced more and more. Monolithic ceramic
electronic components capable of being manufactured with smaller
sizes and higher performance have been used in many of these
electronic devices.
[0005] The monolithic ceramic electronic component usually includes
a ceramic base element including a plurality of stacked ceramic
layers, inner electrodes formed inside the ceramic base element,
and outer electrodes formed on outer surfaces of the ceramic base
element. Further, the monolithic ceramic electronic component is
placed on conductive lands of a mounting board and is mounted to
the board by using a conductive bonding material, e.g., a
solder.
[0006] There are still now continuing demands for further size
reduction of monolithic ceramic electronic components.
[0007] However, when the size of the monolithic ceramic electronic
component is reduced, an effective area where the inner electrodes
are opposed to each other is also reduced. As a result,
characteristics of the monolithic ceramic electronic component
generally tend to degrade.
[0008] Further, in a multi-terminal monolithic ceramic electronic
component, it is required to arrange a plurality of stripe-shaped
outer electrodes at a narrow pitch. However, a known method of
baking a thick film paste has a limit in accuracy of applying the
paste and has a difficulty in forming the outer electrodes with
high accuracy.
[0009] In view of such a situation, a method of forming the outer
electrodes directly by plating is proposed. With that method, thin
and flat outer electrodes can be formed, and hence the effective
area of the inner electrodes can be increased. Moreover, because
plated metals are deposited on the exposed portions of the inner
electrodes, the outer electrodes can be formed with high accuracy
even at a narrow pitch.
[0010] To realize more reliable growth of the plated metals when
the outer electrodes are formed directly by plating, Japanese
Unexamined Patent Application Publication No. 2004-327983, for
example, proposes the use of dummy conductors (anchor tabs).
According to the technique disclosed in Japanese Unexamined Patent
Application Publication No. 2004-327983, plated metals can be
deposited on not only the exposed portions of the inner electrodes,
but also on the exposed portions of the dummy conductors.
Therefore, growth of the plated metals can be more reliably
ensured.
[0011] With the method disclosed in Japanese Unexamined Patent
Application Publication No. 2004-327983, however, reliability,
e.g., BDV (breakdown voltage), of the monolithic ceramic electronic
component may degrade in some cases.
[0012] The inventors of the invention described and claimed in the
present application have conducted intensive studies to find the
cause of the degradation of reliability. As a result, it has been
discovered that the degradation of reliability (BDV) is
attributable to the presence of the dummy conductors. In more
detail, it has been discovered that, when the dummy conductors are
present in an outer layer portion where there are no inner
electrodes, the inner electrodes positioned in overlapped relation
to the dummy conductors are excessively pressed in a pressing step
before firing due to the presence of the dummy conductors, and the
distance between the inner electrodes adjacent to each other is
locally shortened.
SUMMARY OF THE INVENTION
[0013] Accordingly, preferred embodiments of the present invention
provide a monolithic ceramic electronic component having a
structure that can solve the problem mentioned above.
[0014] According to a preferred embodiment of the present
invention, a monolithic ceramic electronic component includes a
ceramic base element including a plurality of stacked ceramic
layers; outer surfaces defined by a pair of principal surfaces
opposed to each other, a pair of lateral surfaces opposed to each
other, and a pair of end surfaces opposed to each other, the
lateral surfaces extending in a lengthwise direction
interconnecting the pair of end surfaces and having a size longer
than that of the end surfaces extending in a widthwise direction
interconnecting the pair of lateral surfaces; first inner
electrodes disposed inside the ceramic base element and each
including a first opposing portion, which has a substantially
rectangular shape including a longer side and a shorter side, and a
first lead-out portion led out from the longer side of the first
opposing portion to the lateral surface of the ceramic base
element; second inner electrodes disposed inside the ceramic base
element and each including a second opposing portion, which is
opposed to the first opposing portion, and a second lead-out
portion led out from the second opposing portion to the outer
surface of the ceramic base element; a first outer electrode
disposed on the lateral surface of the ceramic base element and
including a plated film that directly covers an exposed portion of
the first lead-out portion; and a second outer electrode disposed
on the outer surface of the ceramic base element, electrically
connected to the exposed portion of the second lead-out portion,
and connected to a different potential from that of the first outer
electrode.
[0015] Given that a region where the first inner electrodes and the
second inner electrodes are present in a height direction
interconnecting the pair of principal surfaces is defined as an
inner layer portion, and that a region where the first inner
electrodes and the second inner electrodes are both not present in
the height direction is defined as an outer layer portion, a
plurality of outer-layer dummy conductors are disposed in the outer
layer portion to be stacked in the height direction such that the
outer-layer dummy conductors are each led out to the lateral
surface in overlapped relation to the first lead-out portion when
the ceramic base element is viewed through projection in the height
direction, the outer-layer dummy conductors being connected to the
plated film of the first outer electrode.
[0016] Given that an interval between the outer-layer dummy
conductors adjacent to each other in the outer layer portion is d1,
and that an interval between the first and second inner electrodes
adjacent to each other in the inner layer portion is d2,
1.7d2.ltoreq.d1 is preferably satisfied.
[0017] Preferably, d1.ltoreq.about 6 .mu.m is further
satisfied.
[0018] In a monolithic ceramic electronic component according to
another preferred embodiment of the present invention, the first
lead-out portion is led out to be positioned across a center of at
least one of the pair of lateral surfaces in the lengthwise
direction.
[0019] As described above, when the outer-layer dummy conductors
are present in the outer layer portion, the inner electrodes
positioned in overlapped relation to the outer-layer dummy
conductors are excessively pressed in the pressing step before
firing due to the presence of the outer-layer dummy conductors, and
the distance between the inner electrodes adjacent to each other is
locally shortened. This may degrade reliability of the monolithic
ceramic electronic component, e.g., BDV (breakdown voltage) in some
cases.
[0020] With the findings resulting from the intensive studies
described above, the degradation of reliability is attributable to
the fact that, during the pressing step, the outer-layer dummy
conductors act to press the first lead-out portion, thus causing
the pressed first lead-out portion to drag in the first opposing
portion such that a root portion of the first lead-out portion
sinks.
[0021] Further, the inventors have discovered that such a sinking
phenomenon is apt to more easily occur in particular when the first
lead-out portion is led out from the longer side of the first
opposing portion.
[0022] With the preferred embodiments of the present invention, in
the monolithic ceramic electronic component including the inner
electrodes each of which has the first lead-out portion led out
from the longer side of the first opposing portion, a density of
the outer-layer dummy conductors in the outer layer portion is
reduced. Therefore, the pressing of the inner electrodes through
the outer-layer dummy conductors is relieved in the pressing step
before firing such that the distance between the inner electrodes
can be prevented from being locally shortened. It is hence possible
to effectively reduce and prevent degradation of reliability of the
monolithic ceramic electronic component, e.g., a reduction of BDV,
which may be caused by the local shortening of the distance between
the inner electrodes.
[0023] In relation to the preferred embodiments of the present
invention, from the viewpoint of reducing and preventing the
degradation of reliability, the interval d1 between the outer-layer
dummy conductors adjacent to each other is preferably longer.
However, the longer the interval d1, the stronger a tendency to
impede growth of the plated film for the first outer electrode.
Stated another way, a risk that plated films growing with the
exposed portions of the outer-layer dummy conductors being nuclei
may become hard to continuously join with each other in the height
direction is increased. For that reason, the interval d1 is
preferably set so as to satisfy d1.ltoreq.about 6 .mu.m. By
satisfying that condition, the growth of the plated film for the
first outer electrode can be more reliably ensured.
[0024] The above and other elements, features, steps,
characteristics and advantages of the present invention will become
more apparent from the following detailed description of the
preferred embodiments with reference to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a perspective view illustrating an external
appearance of a monolithic ceramic capacitor as a monolithic
ceramic electronic component according to a first preferred
embodiment of the present invention.
[0026] FIG. 2 is a sectional view taken along a plane parallel to
lateral surfaces of a ceramic base element in the monolithic
ceramic capacitor illustrated in FIG. 1.
[0027] FIG. 3 is a sectional view taken along a plane parallel to
end surfaces of the ceramic base element in the monolithic ceramic
capacitor illustrated in FIG. 1.
[0028] FIG. 4 is a sectional view taken along a plane parallel to
principal surfaces of the ceramic base element in the monolithic
ceramic capacitor illustrated in FIG. 1, the plane including a
first inner electrode that extends therein.
[0029] FIG. 5 is a sectional view taken along a plane parallel to
the principal surfaces of the ceramic base element in the
monolithic ceramic capacitor illustrated in FIG. 1, the plane
including a second inner electrode that extends therein.
[0030] FIG. 6 is a sectional view taken along a plane parallel to
the principal surfaces of the ceramic base element in the
monolithic ceramic capacitor illustrated in FIG. 1, the plane
including an outer-layer dummy conductor that extends therein.
[0031] FIG. 7 is an enlarged view of a portion of the ceramic base
element, illustrated in FIG. 3, to explain the feature of a
preferred embodiment of the present invention.
[0032] FIG. 8 is a sectional view taken along a plane parallel to
end surfaces of a ceramic base element in a monolithic ceramic
capacitor as a monolithic ceramic electronic component according to
a second preferred embodiment of the present invention.
[0033] FIG. 9 is a perspective view illustrating an external
appearance of a monolithic ceramic capacitor as a monolithic
ceramic electronic component according to a third preferred
embodiment of the present invention.
[0034] FIG. 10 is a sectional view taken along a plane parallel to
end surfaces of a ceramic base element in the monolithic ceramic
capacitor illustrated in FIG. 9.
[0035] FIG. 11 is a sectional view taken along a plane parallel to
lateral surfaces of a ceramic base element in a monolithic ceramic
capacitor as a monolithic ceramic electronic component according to
a fourth preferred embodiment of the present invention.
[0036] FIG. 12 is a sectional view taken along a plane parallel to
principal surfaces of the ceramic base element in the monolithic
ceramic capacitor illustrated in FIG. 11, the plane including
outer-layer dummy conductors that extend therein.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0037] Preferred embodiments of the present invention will be
described below in connection with a monolithic ceramic capacitor
as one example of a monolithic ceramic electronic component.
First Preferred Embodiment
[0038] A first preferred embodiment of the present invention will
be described below with reference to FIGS. 1 to 7. A monolithic
ceramic capacitor 1 according to the first preferred embodiment
includes a ceramic base element 2. The monolithic ceramic capacitor
1 further includes first and second inner electrodes 3 and 4, first
and second inner-layer dummy conductors 5 and 6, and outer-layer
dummy conductors 7, which are all disposed inside the ceramic base
element 2, as well as first and second outer electrodes 9 and 10,
which are disposed on outer surfaces of the ceramic base element 2.
Details of the structure of the monolithic ceramic capacitor 1 will
be described below followed by a description of a manufacturing
method.
[0039] The ceramic base element 2 preferably is substantially
parallelepiped, and includes outer surfaces defined by a pair of
first and second principal surfaces 11 and 12 opposed to each
other, a pair of lateral surfaces 13 and 14 opposed to each other,
and a pair of end surfaces 15 and 16 opposed to each other.
[0040] A direction interconnecting the principal surfaces 11 and 12
is defined as a height direction, a direction interconnecting the
lateral surfaces 13 and 14 is defined as a widthwise direction, and
a direction interconnecting the end surfaces 15 and 16 is defined
as a lengthwise direction. In this preferred embodiment, a size of
the ceramic base element 2 in the lengthwise direction is longer
than that in the widthwise direction, and the size in the
lengthwise direction is about twice that in the widthwise
direction.
[0041] The ceramic base element 2 is preferably rounded at corners
and ridges thereof.
[0042] As illustrated in FIGS. 2 and 3, the ceramic base element 2
has a multilayer structure including a plurality of ceramic layers
17, which extend in a direction parallel or substantially parallel
to the principal surfaces 11 and 12 and which are stacked in the
height direction. A thickness of each of the ceramic layers 17 is
preferably about 0.5 .mu.m to about 10 .mu.m and in particular
preferably about 0.7 .mu.m to about 3.0 .mu.m, for example. A
ceramic material constituting the ceramic layer 17 can be, for
example, a dielectric ceramic containing BaTiO.sub.3, CaTiO.sub.3,
SrTiO.sub.3, CaZrO.sub.3, or the like as a main component. The
dielectric ceramic may further contain, in addition to the main
component, auxiliary components, e.g., a Mn compound, a Mg
compound, a Si compound, a Co compound, a Ni compound, and a
rare-earth element compound.
[0043] The inner electrode includes a plurality of first inner
electrodes 3 each illustrated in FIG. 4, and a plurality of second
inner electrodes 4 each illustrated in FIG. 5. The plurality of
first inner electrodes 3 and the plurality of second inner
electrodes 4 are alternately arranged in the height direction
(stacking direction) of the ceramic base element 2, as illustrated
in FIGS. 2 and 3.
[0044] As illustrated in FIG. 4, the first inner electrode 3
includes a first opposing portion 19 opposed to the second inner
electrode 4 that is positioned adjacent to the relevant first inner
electrode 3, and two first lead-out portions 20 each led out from
the first opposing portion 19 to the outer surface of the ceramic
base element 2. In this preferred embodiment, the first inner
electrode 3 preferably has a crisscross shape. One and the other of
the two first lead-out portions 20 are led out respectively to the
first and second lateral surfaces 13 and 14. In other words, the
first inner electrode 3 is disposed so as to extend from the first
lateral surface 13 to the second lateral surface 14. The first
opposing portion 19 preferably has a substantially rectangular
shape having a longer side extending in the lengthwise direction
and a shorter side extending in the widthwise direction. The first
lead-out portions 20 are led out from the longer sides of the first
opposing portion 19 to be positioned across respective centers of
the lateral surfaces 13 and 14.
[0045] As illustrated in FIG. 5, the second inner electrode 4
includes a second opposing portion 21 opposed to the first inner
electrode 3 that is positioned adjacent to the relevant second
inner electrode 4, and two second lead-out portions 22 each led out
from the second opposing portion 21 to the outer surface of the
ceramic base element 2. In FIG. 5, a boundary between the second
opposing portion 21 and the second lead-out portion 22 in the
second inner electrode 4 is denoted by a dotted line. In this
preferred embodiment, the second inner electrode 4 preferably has a
substantially rectangular shape. Further, one and the other of the
two second lead-out portions 22 of the second inner electrode 4 are
led out respectively to the first and second end surfaces 15 and
16. In other words, the second inner electrode 4 is disposed so as
to extend from the first end surface 15 to the second end surface
16.
[0046] For example, Ni, Cu, Ag, Pd, an Ag--Pd alloy, Au, etc. can
be optionally used as conductive materials constituting the inner
electrodes 3 and 4.
[0047] A thickness of each of the inner electrodes 3 and 4 is
preferably about 0.3 .mu.m to about 2.0 .mu.m, for example.
[0048] An electrostatic capacity is generated in a region where the
first opposing portion 19 of the first inner electrode and the
second opposing portion 21 of the second inner electrode 4 are
opposed to each other with the ceramic layer 17 interposed
therebetween. A region where the first and second inner electrode 3
and 4 are present along the height direction, the region including
the above-mentioned region generating the electrostatic capacity,
is defined as an inner layer portion 23.
[0049] On the other hand, a region where the first and second inner
electrode 3 and 4 are both not present along the height direction
is defined as an outer layer portion 24. There are two outer layer
portions 24 on both sides of the inner layer portion 23, i.e., on
one side closer to the first principal surface 11 and on the other
side closer to the second principal surface 12.
[0050] The inner-layer dummy conductor is disposed in the inner
layer portion 23, and it includes a plurality of first inner-layer
dummy conductors 5 each illustrated in FIG. 5 and a plurality of
second inner-layer dummy conductors 6 each illustrated in FIG.
4.
[0051] In this preferred embodiment, as illustrated in FIG. 5, the
first inner-layer dummy conductor 5 is flush with the second inner
electrode 4. The first inner-layer dummy conductor 5 is connected
to the first outer electrode 9.
[0052] In this preferred embodiment, as illustrated in FIG. 4, the
second inner-layer dummy conductor 6 is flush with the first inner
electrode 3. The second inner-layer dummy conductor 6 is connected
to the second outer electrode 10.
[0053] The inner-layer dummy conductors 5 and 6 function as
deposition points for plated films that constitute respective
underling layers of the first and second outer electrodes 9 and 10,
thereby increasing current-carrying efficiency. Further, the
inner-layer dummy conductors 5 and 6 contribute to increasing the
strength of the ceramic base element 2.
[0054] Preferable conditions for materials and thicknesses of the
inner-layer dummy conductors 5 and 6 are similar to those for the
inner electrodes 3 and 4. Thus, the inner-layer dummy conductors 5
and 6 are preferably made of the same material in the same
thickness as in the case of the inner electrodes 3 and 4.
[0055] It is to be noted that the inner-layer dummy conductors 5
and 6 may be not formed in some cases.
[0056] As illustrated in FIGS. 2 and 3, the outer-layer dummy
conductor 7 is disposed in the outer layer portion 24.
[0057] The outer-layer dummy conductor 7 is preferably led out to
at least two positions in the outer surfaces of the ceramic base
element 2. In this preferred embodiment, as illustrated in FIG. 6,
the outer-layer dummy conductor 7 preferably has a substantially
rectangular shape and is led out to two positions in the outer
surfaces of the ceramic base element 2, i.e., to the first lateral
surface 13 and the second lateral surface 14. In other words, the
outer-layer dummy conductor 7 is disposed so as to extend from the
first lateral surface 13 to the second lateral surface 14.
[0058] The outer-layer dummy conductor 7 functions as a deposition
point for a plated film that constitutes an underling layer of the
first outer electrode 9. Because of the outer-layer dummy conductor
7 being led out to two positions as described above, when media
such as steel balls come into contact with one of the exposed
portions of the outer-layer dummy conductor 7 during plating, an
electric current is supplied to the other exposed portion of the
outer-layer dummy conductor 7 as well. Thus, when the outer-layer
dummy conductor 7 includes two or more exposed portions, a
probability of contact between the exposed portions of the
outer-layer dummy conductor 7 and the media is increased and the
current-carrying efficiency is increased. As a result, a plating
time necessary to form the plated films, which serve as the
underlying layers of the first outer electrodes 9 described later,
is shortened.
[0059] As illustrated in FIGS. 2 and 3, the outer-layer dummy
conductor 7 is successively stacked in plural number in the
stacking direction of the ceramic layers 17. The outer-layer dummy
conductor 7 is preferably disposed in number of 10 to 100 in each
of the outer layer portions 24.
[0060] The outer-layer dummy conductors 7 are each arranged in
overlapped relation to the first lead-out portion 20 when the
ceramic base element 2 is viewed through projection in the height
direction. With such an arrangement, the exposed portions of the
outer-layer dummy conductors 7 form an exposed portion group in the
form of a row, together with the exposed portions of the first
lead-out portions 20, in the outer surface of the ceramic base
element 2. In this preferred embodiment, the exposed portion group
is formed in each of the first and second lateral surfaces 13 and
14.
[0061] Given that, as illustrated in FIG. 7, an interval between
the outer-layer dummy conductors 7 adjacent to each other in the
outer layer portion 24 is d1, and that an interval between the
first and second inner electrodes 3 and 4 adjacent to each other in
the inner layer portion 23 is d2, 1.7d2.ltoreq.d1 is preferably
satisfied.
[0062] Thus, by reducing a density of the outer-layer dummy
conductors 7 in the outer layer portion 24 on that condition,
pressing of the inner electrodes 3 and 4 through the outer-layer
dummy conductors 7 is relieved when the ceramic base element is
pressed before firing such that the distance between the inner
electrodes can be prevented from being locally shortened. It is
hence possible to effectively reduce and prevent degradation of
reliability of the monolithic ceramic electronic component, e.g., a
reduction of BDV.
[0063] As seen from EXPERIMENTAL EXAMPLES described later, if d1 is
smaller than about 1.7d2, there is a risk that the reliability may
degrade.
[0064] When the first lead-out portion is led out to be positioned
across the center of at least one of the pair of lateral surfaces
13 and 14 in the lengthwise direction as in this preferred
embodiment, a root portion of the first lead-out portion 20 is
caused to sink to a larger extent. In such a situation, the
above-mentioned advantageous effect is more effectively
expected.
[0065] From the viewpoint of reducing and preventing the
degradation of reliability, the interval d1 is preferably longer.
However, the longer the interval d1, the stronger a tendency to
impede growth of the plated film that serves as the underlying
layer of the first outer electrode 9. Stated another way, a risk
that plated films growing with the exposed portions of the
outer-layer dummy conductors 7 being nuclei may become hard to
continuously join with each other in the height direction is
increased. For that reason, d1.ltoreq.about 6 .mu.m is preferably
satisfied.
[0066] The outer-layer dummy conductor 7 is preferably made of the
same material as that of the inner electrodes 3 and 4. For example,
Ni, Cu, Ag, Pd, an Ag--Pd alloy, Au, etc., mentioned above, can
also be optionally used as a conductive material of the outer-layer
dummy conductor 7.
[0067] A thickness of the outer-layer dummy conductor 7 is
preferably about 0.3 .mu.m to about 2.0 .mu.m, for example.
[0068] As specifically illustrated in FIG. 3, the first outer
electrode 9 is disposed on each of the first and second lateral
surfaces 13 and 14 of the ceramic base element 2. In this preferred
embodiment, the first outer electrode 9 is disposed to extend up to
over respective portions of the first and second principal surfaces
11 and 12.
[0069] The first outer electrode 9 is electrically connected to the
first inner electrodes 3. As illustrated in FIGS. 3 to 6, the first
outer electrode 9 includes an underlying layer 25 and an overlying
layer 26, the overlying layer 26 being formed on the underlying
layer 25 as required.
[0070] The underlying layer 25 of the first outer electrode 9 is
constituted as a plated film. The plated film constituting the
underlying layer 25 of the first outer electrode 9 directly covers
not only the exposed portions of the first lead-out portions 20 of
the first inner electrodes 3 and the exposed portions of the first
inner-layer dummy conductors 5, but also the exposed portions of
the outer-layer dummy conductors 7. For example, Cu, Ni, Ag, Pd, an
Ag--Pd alloy, Au, Sn, Pb, Bi, Zn, etc. can be optionally used as a
metal constituting the plated film that serves as the underlying
layer 25. The plated film preferably does not contain glass
ingredients. Further, a metal proportion of the plated film per
unit volume is preferably about 99% by volume or more. A thickness
of the plated film is preferably about 1 .mu.m to about 15 .mu.mm,
for example, in its thickest portion. The first inner-layer dummy
conductor 5 and the outer-layer dummy conductor 7 act to promote
deposition and growth of the plated film that serves as the
underlying layer 25.
[0071] When the overlying layer 26 is formed in the first outer
electrode 9, the overlying layer 26 is constituted as, e.g., a
plated film. For example, Cu, Ni, Ag, Pd, an Ag--Pd alloy, Au, Sn,
Pb, Bi, Zn, etc. can be optionally used as a metal constituting the
plated film that serves as the overlying layer 26. The plated film
for the overlying layer 26 may include plural layers. A thickness
of the plated film for the overlying layer 26 is preferably about 1
.mu.m to about 10 .mu.m per layer, for example.
[0072] When the overlying layer 26 is provided in the first outer
electrode 9, it is preferable that the underlying layer 25 is
constituted as a Ni plated film and the overlying layer 26 is
constituted as a Sn plated film. Alternatively, when the overlying
layer 26 includes plural layers, the overlying layer 26 preferably
has a two-layer structure including a Ni plated layer and a Sn
plated layer provided on the Ni plated layer.
[0073] The second outer electrode 10 is connected to a different
potential from that of the first outer electrode 9 and is disposed
on each of the first and second end surfaces 15 and 16 of the
ceramic base element 2. In this preferred embodiment, the second
outer electrode 10 is disposed to extend up to over respective
portions of the first and second principal surfaces 11 and 12 and
respective portions of the first and second lateral surfaces 13 and
14.
[0074] The second outer electrode 10 covers the exposed portions of
the second lead-out portions 22 in such a state that the second
outer electrode 10 is electrically connected to the second inner
electrodes 4. As illustrated in FIGS. 2 and 4 to 6, the second
outer electrode 10 includes an underlying layer 27, which is
contacted with the exposed portions of the second lead-out portions
22 of the second inner electrodes 4, and an overlying layer 28,
which is disposed on the underlying layer 27 as desired. The
underlying layer 27 can be constituted as, e.g., a plated film, a
sintered metal film, and/or a conductive resin film.
[0075] When the plated film is selected as a film constituting the
underlying layer 27, Cu, Ni, Ag, Pd, an Ag--Pd alloy, Au, Sn, Pb,
Bi, Zn, etc. can be optionally used, for example, as a metal
constituting the plated film. The plated film preferably does not
contain glass ingredients. A thickness of the underlying layer 27
is preferably about 1 .mu.m to about 20 .mu.m in its thickest
portion. The second inner-layer dummy conductor 6 acts to promote
deposition and growth of the plated film that serves as the
underlying layer 27.
[0076] When the sintered metal film is selected as a film
constituting the underlying layer 27, Cu, Ni, Ag, Pd, an Ag--Pd
alloy, Au, etc. can be optionally used, for example, as a metal
constituting the sintered metal film. The sintered metal film may
contain glass ingredients. Further, the sintered metal film may be
fired at the same time as the ceramic base element 2 and the inner
electrodes 3 and 4. As an alternative, the sintered metal film may
be formed by coating a conductive paste over the ceramic base
element 2 after the firing, and then baking the conductive
paste.
[0077] When the conductive resin film is selected as a film
constituting the underlying layer 27, the conductive resin film can
be formed by using a thermosetting resin alone or in a state mixed
with a metal filler.
[0078] When the sintered metal film or the conductive resin film is
selected, a thickness of the underlying layer 27 is preferably
about 10 .mu.m to about 50 .mu.m in its thickest portion, for
example.
[0079] In the illustrated preferred embodiment, the underlying
layer 27 preferably includes a plated film 29, which is contacted
with the respective exposed portions of the second inner electrodes
4 and the second inner-layer dummy conductors 6, and a sintered
metal film 30 provided on the plated film 29.
[0080] When the overlying layer 28 is to be further provided on the
underlying layer 27 in the second outer electrode 10, the overlying
layer 28 is constituted as, e.g., a plated film. For example, Cu,
Ni, Ag, Pd, an Ag--Pd alloy, Au, Sn, Pb, Bi, Zn, etc. can be
optionally used as a metal constituting the plated film that serves
as the overlying layer 28. The plated film for the overlying layer
28 may include plural layers. In that case, the overlying layer 28
preferably has a two-layer structure including a Ni plated layer
and a Sn plated layer formed on the Ni plated layer. A thickness of
the plated film for the overlying layer 28 is preferably about 1
.mu.m to about 10 .mu.m per layer, for example.
[0081] A non-limiting example of a method for manufacturing the
monolithic ceramic capacitor 1 will now be described.
[0082] A ceramic green sheet to be used as the ceramic layer 17, a
conductive paste for the inner electrode, and a conductive paste
for the outer electrode are prepared. The conductive paste for the
inner electrode is also used as a conductive paste for the
inner-layer dummy conductor and a conductive paste for the
outer-layer dummy conductor. The ceramic green sheet and the
conductive pastes for the inner electrode and the outer electrode
contain a binder and a solvent. The binder and the solvent can be
known organic ones, respectively.
[0083] On ceramic green sheets, the conductive paste is printed in
predetermined patterns by screen printing, for example, to form an
inner electrode pattern, an inner-layer dummy conductor pattern,
and an outer-layer dummy conductor pattern.
[0084] An outer-layer ceramic green sheet on which neither the
inner electrode pattern nor the outer-layer dummy conductor pattern
are printed, the ceramic green sheet on which the outer-layer dummy
conductor pattern is printed, and the ceramic green sheet on which
the inner electrode and the inner-layer dummy conductor pattern are
printed are stacked in predetermined order in respective
predetermined numbers of sheets such that a mother laminate is
fabricated.
[0085] Here, in the outer layer portion, the above-mentioned
interval d1 can be adjusted by adjusting the number of the stacked
outer-layer ceramic green sheets on each of which the outer-layer
dummy conductor pattern is not printed. As an alternative, the
interval d1 may be adjusted by adjusting the thickness of each of
the outer-layer ceramic green sheets.
[0086] Furthermore, in the inner layer portion, the interval d2 can
be adjusted by adjusting the number of stacked inner-layer ceramic
green sheets on each of which neither the inner electrode pattern
nor the inner-layer dummy conductor pattern are printed. As an
alternative, the interval d2 may be adjusted by adjusting the
thickness of each of the inner-layer ceramic green sheets.
[0087] The mother laminate is pressed in the stacking
direction.
[0088] The mother laminate is cut into a predetermined size,
whereby a green ceramic base element is cut out.
[0089] The green ceramic base element is fired. The ceramic base
element 2 illustrated in the drawings is thereby obtained. A firing
temperature is preferably about 900.degree. C. to about
1300.degree. C., though depending on the materials of the ceramic
sheet and the inner electrode.
[0090] Thereafter, barrel polishing is preferably performed on the
ceramic base element 2 when necessary. With the barrel polishing,
corners and ridges of the ceramic base element 2 are rounded.
[0091] The ceramic base element 2 after the barrel polishing is
subjected to a plating process.
[0092] With the plating process, plated films constituting the
underlying layers 25 of the first outer electrodes 9 are formed. At
that time, as illustrated in FIG. 3, not only the first inner
electrodes 3, but also the first inner-layer dummy conductors 5 and
the outer-layer dummy conductors 7 are exposed to the lateral
surfaces 13 and 14, and the plated films are deposited on those
exposed portions that serve as start points for the deposition.
Therefore, the underlying layers 25 of the first outer electrodes 9
can be efficiently formed.
[0093] The plating process is preferably performed by electrolytic
plating based on a rotating barrel method. Thus, a plating method
is preferably performed as rotating barrel plating. Conductive
media, such as steel balls, are used in the plating process.
[0094] Because of the outer-layer dummy conductor 7 including two
exposed portions, when the conductive media come into contact with
one of the exposed portions in the plating step, an electric
current is supplied to the other exposed portion as well.
Therefore, a probability of contact between the exposed portions of
the outer-layer dummy conductor 7 and the conductive media is
increased and the current-carrying efficiency is increased. As a
result, a plating time required to form the underlying layers 25 is
shortened.
[0095] In the above-described plating process, the plated films 29
for the underlying layers 27 of the second outer electrodes 10 can
also be simultaneously formed while the respective exposed portions
of the second inner electrodes 4 and the second inner-layer dummy
conductors 6 serve as start points for the deposition of the plated
films.
[0096] After the plating process, heat treatment is preferably
performed at temperature of about 600.degree. C. to about
900.degree. C., for example. The heat treatment increases the
fixing strength of the plated films with respect to the ceramic
base element 2.
[0097] The sintered metal film 30 in the underlying layer 27 of
each second outer electrode 10 is formed by coating a conductive
paste and baking the conductive paste. A baking temperature is
preferably about 700.degree. C. to about 900.degree. C., for
example.
[0098] The overlying layer 26 of the first outer electrode 9 and
the overlying layer 28 of the second outer electrode 10 are formed
by a plating process.
[0099] The monolithic ceramic capacitor 1 is thus completed.
Second Preferred Embodiment
[0100] A second preferred embodiment of the present invention is
illustrated in FIG. 8. FIG. 8 is a sectional view corresponding to
FIG. 3. Equivalent elements in FIG. 8 to those in FIG. 3 are
denoted by the same reference symbols and duplicate descriptions of
those elements are omitted here.
[0101] In a monolithic ceramic capacitor 1a according to the second
preferred embodiment, an outer-layer dummy conductor 7a is arranged
such that the outer-layer dummy conductor 7a does not penetrate
through the ceramic base element 2 in the widthwise direction and
it is separated in the widthwise direction.
Third Preferred Embodiment
[0102] A third preferred embodiment of the present invention is
illustrated in FIGS. 9 and 10. FIG. 9 is a perspective view
corresponding to FIG. 1, and FIG. 10 is a sectional view
corresponding to FIG. 3. Equivalent elements in FIGS. 9 and 10 to
those in FIGS. 1 and 3 are denoted by the same reference symbols
and duplicate descriptions of those elements are omitted here.
[0103] A monolithic ceramic capacitor 1b according to the third
preferred embodiment is characterized in that a first outer
electrode 9b, including an underlying layer 25 and an overlying
layer 26 thereof, is disposed to extend over the first and second
lateral surfaces 13 and 14 and the first and second principal
surfaces 11 and 12 of the ceramic base element 2 in a fully
surrounding state.
[0104] In this preferred embodiment, the outer-layer dummy
conductors 7 are preferably exposed in at least respective portions
of the principal surfaces 11 and 12 by chipping off the ceramic
layers 17, which define the principal surfaces 11 and 12, in the
above-described polishing step after the firing. This operation
adds plating deposition points on the principal surfaces 11 and 12,
and hence enables the plated film for the underlying layer 25 of
the first outer electrode 9b to be more easily formed in the fully
surrounding state.
[0105] The outer-layer dummy conductor 7 is not always required to
be exposed in its entirety at each of the principal surfaces 11 and
12, and it may be exposed in a discontinuously distributed form
(e.g., in a mottled pattern). However, the exposed portions of the
outer-layer dummy conductor 7 in each of the principal surfaces 11
and 12 of the outer-layer dummy conductor 7 are preferably evenly
distributed over a region spanning from the first lateral surface
13 to the second lateral surface 14. Further, those exposed
portions of the outer-layer dummy conductor 7 are desirably exposed
without a break over the region spanning from the first lateral
surface 13 to the second lateral surface 14. Thus, even when a
portion where the outer-layer dummy conductor 7 is continuously
exposed from the first lateral surface 13 to the second lateral
surface 14 is small, a current-carrying area is arranged to
continuously extend over the principal surfaces 11 and 12 from the
first lateral surface 13 to the second lateral surface 14. Hence
the current-carrying efficiency is maximized.
[0106] According to the third preferred embodiment, the plated film
is continuously formed so as to fully extend around the ceramic
base element 2 in a plating growth process that is developed in the
plating step to form the underlying layer 25 of the first outer
electrode 9b, whereby an electrode area serving as the plating
deposition point is increased. Therefore, the current-carrying
efficiency is increased from the time at which the plated film has
been continuously formed, and a thickness of the plated film
formable per unit time is increased. In other words, with this
preferred embodiment, a time required to form a film for the
underlying layer 25 of the first outer electrode 9b in a
predetermined thickness is shortened, and a cost is reduced.
[0107] In the first preferred embodiment described above, distal
end portions of the first outer electrode 9 are present on the
principal surfaces 11 and 12 of the ceramic base element 2. When
stress is applied to the distal end portions of the first outer
electrode 9 upon flexing of the board on which the monolithic
ceramic capacitor 1 is mounted, the underlying layer 25 may be
peeled off starting from those distal end portions with a
relatively high possibility. According to the third preferred
embodiment, however, the first outer electrode 9b is formed in an
endless manner such that there are no distal end portions of the
first outer electrode. For that reason, peeling-off of the
underlying layer 25 is very difficult and thus, prevented.
[0108] Further, in the first preferred embodiment described above,
a plating solution used in the step of forming the overlying layer
26 by plating may intrude through the distal end portions of the
underlying layer 25 of the first outer electrode 9, which portions
are present on the principal surfaces 11 and 12, thus causing a
possibility that reliability may degrade. With the third preferred
embodiment, however, the underlying layer 25 of the first outer
electrode 9b has no distal end portions, and hence degradation of
reliability is hard to occur.
[0109] Moreover, since the first outer electrode 9b is defined by
the plated film fully extending around the ceramic base element 2,
the first outer electrode 9b can be formed in a state smoothly
covering the outer surfaces of the ceramic base element 2.
Therefore, the monolithic ceramic capacitor 1b is less apt to roll
unintentionally and it can maintain a stable posture when
mounted.
Fourth Preferred Embodiment
[0110] A fourth preferred embodiment of the present invention is
illustrated in FIGS. 11 and 12. FIG. 11 is a sectional view
corresponding to FIG. 2, and FIG. 12 is a sectional view
corresponding to FIG. 6. Equivalent elements in FIGS. 11 and 12 to
those in FIGS. 2 and 6 are denoted by the same reference symbols
and duplicate descriptions of those elements are omitted here.
[0111] A monolithic ceramic capacitor 1c according to the fourth
preferred embodiment is characterized in that a second outer-layer
dummy electrode 8 is flush with the outer-layer dummy conductor
7.
[0112] Further, an underlying layer 27 of a second outer electrode
10c is entirely constituted as a plated film. Therefore, the
underlying layers 25 and 27 of the first and second outer
electrodes 9 and 10c can be formed at the same time.
[0113] The second outer-layer dummy conductor 8 functions as a
deposition point for the plated film that constitutes the
underlying layer 27 of the second outer electrode 10c, thereby
increasing current-carrying efficiency.
Other Preferred Embodiments
[0114] The dummy conductor, particularly the outer-layer dummy
conductor, may contribute to development of electric
characteristics. Further, the dummy conductor may have any desired
shape. For example, the outer-layer dummy conductor may have the
same shape as the inner electrode.
Experimental Examples
[0115] In accordance with the first preferred embodiment,
non-limiting samples of the monolithic ceramic capacitor were
fabricated as follows.
(1) Size in the lengthwise direction.times.size in the widthwise
direction.times.size in the height direction of the ceramic base
element: 1.6 mm.times.0.8 mm.times.0.8 mm
(2) First Outer Electrode
[0116] Underlying layer: Cu plated film having a thickness of 10
.mu.m
[0117] Overlying layer: Ni plated film having a thickness of 3
.mu.m and Sn plated film having a thickness of 3 .mu.m, the latter
being coated on the former
(3) Second Outer Electrode
[0118] Underlying layer: Cu plated film having a thickness of 10
.mu.m and Cu sintered metal film having a thickness of 15 .mu.m,
the latter being coated on the former Overlying layer: Ni plated
film having a thickness of 3 .mu.m and Sn plated film having a
thickness of 3 .mu.m, the latter being coated on the former
(4) Inner Electrode
[0119] Interval d2 between the inner electrodes: as listed in the
Table Thickness of the inner electrode: 0.56 .mu.m Number of the
inner electrodes: 345
(5) Inner-Layer Dummy Conductor
[0120] Parameter values are the same as those for the inner
electrode
(6) Outer-Layer Dummy Conductor
[0121] Interval d1 between the outer-layer dummy conductors: as
listed in the Table Thickness of the outer-layer dummy conductor:
0.56 .mu.m Number of the outer-layer dummy conductors: 56 in each
of the upper and lower outer layer portions
[0122] As indicated in the Table, BDV and a plating failure were
evaluated for each of the samples with d1 and d2 each set to
different values from one another.
[0123] The measurement of d1 and d2 was carried out by preparing
three capacitors per sample type, and grinding the ceramic base
element of each capacitor to about 1/2 in the widthwise direction
such that a cross-section defined by a certain size in the
lengthwise direction and a certain size in the thickness direction
was exposed to the ground surface.
[0124] Further, the interval d1 was obtained by measuring, in the
above-mentioned cross-section, respective intervals between
adjacent twos of all the outer-layer dummy conductors, which were
present in the outer layer portion on the side closer to the first
principal surface and which were positioned at about 1/2 of the
size in the lengthwise direction, with an electron microscope, and
by calculating an average value of the intervals measured for the
three samples.
[0125] The interval d2 was obtained by measuring, in the
above-mentioned cross-section, respective distances between
adjacent pairs of fifteen inner electrodes, which were positioned
in an uppermost region of the inner layer portion and which were
positioned at about 1/2 of the size in the lengthwise direction,
with the same electron microscope, and by calculating an average
value of the intervals measured for the three samples.
[0126] BDV was measured by preparing 10 capacitors per sample type,
and carrying out a measurement under condition of voltage boosting
rate of 100 V/sec with a DC voltage breakdown testing device.
[0127] The plating failure was evaluated by preparing 1500
capacitors per sample type, the capacitors being each in a stage
where the Cu plated film serving as the underlying layer of the
first outer electrode was formed, confirming a state of the Cu
plated film between the outer layer portion and the inner layer
portion with an optical microscope, determining the capacitor, in
which the plated film was disconnected, to be defective for the
reason of a plating failure, and counting the number of samples,
which exhibited the plating failure, among the 1500 capacitors.
[0128] The Cu plated film serving as the underlying layer of the
first outer electrode was formed as follows. First, strike Cu
plating was carried out on condition of a current density of 0.1
A/dm.sup.2 for 60 minutes with the rotating barrel plating by using
a plating bath with pH of 8.5 and a bath temperature of 25.degree.
C., the plating bath containing 14 g/L of copper pyrophosphate, 120
g/L of potassium pyrophosphate, and 10 g/L of potassium oxalate.
Then, thick Cu plating was carried out on condition of a current
density of 0.3 A/dm.sup.2 for 60 minutes with the rotating barrel
plating by using a Pyrobright processing bath, available from
Uyemura & CO., LTD., with pH of 8.8 and a bath temperature of
55.degree. C. As a result, the Cu plated film was formed.
TABLE-US-00001 TABLE Plating d1 (.mu.m) d2 (.mu.m) d1/d2 BDV (V)
Failure Sample 1 1.24 1.24 1.0 96.1 0/1500 Sample 2 1.48 1.23 1.2
98.1 0/1500 Sample 3 2.09 1.23 1.7 102.6 0/1500 Sample 4 2.46 1.23
2.0 104.4 0/1500 Sample 5 3.63 1.21 3.0 105.6 0/1500 Sample 6 4.88
1.22 4.0 106.3 0/1500 Sample 7 6.00 1.20 5.0 106.0 0/1500 Sample 8
7.20 1.20 6.0 105.8 1/1500 Sample 9 8.68 1.24 7.0 106.0 5/1500
[0129] As seen from the Table above, BDV of 100 V or higher was
achieved with Samples 3 to 9 each satisfying 1.7d2.ltoreq.d1.
[0130] Among Samples 3 to 9, good adhesion of the plated film was
further obtained with, in particular, Samples 3 to 6 each
satisfying d1.ltoreq.about 6 .mu.m.
[0131] On the other hand, in Samples 1 and 2, good adhesion of the
plated film was obtained, but BDV was less than 100 V because of
not satisfying 1.7d2.ltoreq.d1.
[0132] Though not listed in the Table, it is also confirmed that,
as a result of conducting similar experiments in which, among the
above-described conditions for EXPERIMENTAL EXAMPLES, the interval
d2 between the inner electrodes were changed to about 3.0 .mu.m or
about 0.7 .mu.m, similar advantageous effects to those in the
above-described experimental results can be obtained.
[0133] The present invention is not limited to the above-described
monolithic ceramic capacitor, and it can also be applied to another
type of monolithic ceramic electronic component. For example, when
the ceramic base element is made of a piezoelectric ceramic, a
monolithic ceramic electronic component functioning as a
piezoelectric component can be provided. When the ceramic base
element is made of a semiconductor ceramic, e.g., a spinel ceramic,
a monolithic ceramic electronic component functioning as a
thermistor can be provided.
[0134] While preferred embodiments of the present invention have
been described above, it is to be understood that variations and
modifications will be apparent to those skilled in the art without
departing from the scope and spirit of the present invention. The
scope of the present invention, therefore, is to be determined
solely by the following claims.
* * * * *