U.S. patent application number 14/157914 was filed with the patent office on 2014-05-15 for semiconductor device.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. The applicant listed for this patent is Samsung Electronics Co., Ltd.. Invention is credited to Yoon-Hae Kim, O Sung Kwon, Oh-Jung Kwon, Bong-Seok Suh, Dong-Hee Yu.
Application Number | 20140131815 14/157914 |
Document ID | / |
Family ID | 45972283 |
Filed Date | 2014-05-15 |
United States Patent
Application |
20140131815 |
Kind Code |
A1 |
Yu; Dong-Hee ; et
al. |
May 15, 2014 |
SEMICONDUCTOR DEVICE
Abstract
A semiconductor device is provided. The semiconductor device
includes: a substrate; device isolation regions formed in the
substrate; an impurity region formed in a region of the substrate
between every two adjacent ones of the device isolation regions; a
gate electrode formed on the substrate; first and second interlayer
insulating films sequentially formed on the substrate; a metal
interlayer insulating film formed on the second interlayer
insulating film and comprising metal wiring layers; a first contact
plug electrically connecting each of the metal wiring layers and
the impurity region; and a second contact plug electrically
connecting each of the metal wiring layers and the gate electrode,
wherein the first contact plug is formed in the first and second
interlayer insulating films, and the second contact plug is formed
in the second interlayer insulating film.
Inventors: |
Yu; Dong-Hee; (Hwaseong-si,
KR) ; Suh; Bong-Seok; (Hwaseong-si, KR) ; Kim;
Yoon-Hae; (Yongin-si, KR) ; Kwon; O Sung;
(Wappingers Falls, NY) ; Kwon; Oh-Jung; (Hopewell
Junction, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Samsung Electronics Co., Ltd. |
Suwon-si |
|
KR |
|
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Suwon-si
NY
International Business Machines Corporation
Armonk
Infineon Technologies AG
Bavaria
|
Family ID: |
45972283 |
Appl. No.: |
14/157914 |
Filed: |
January 17, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12909002 |
Oct 21, 2010 |
8633520 |
|
|
14157914 |
|
|
|
|
Current U.S.
Class: |
257/401 |
Current CPC
Class: |
H01L 21/76895 20130101;
H01L 23/535 20130101; H01L 21/76813 20130101; H01L 2924/0002
20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101; H01L
23/485 20130101; H01L 21/76802 20130101 |
Class at
Publication: |
257/401 |
International
Class: |
H01L 23/535 20060101
H01L023/535 |
Claims
1. A semiconductor device comprising: a substrate; device isolation
regions formed in the substrate; an impurity region formed in a
region of the substrate between every two adjacent ones of the
device isolation regions; a gate electrode formed on the substrate;
metal wiring layers formed on the substrate; a first contact plug
electrically connecting each of the metal wiring layers and the
impurity region and comprising first and second sub contact plugs
which are sequentially formed on the impurity region; and a second
contact plug electrically connecting each of the metal wiring
layers and the gate electrode, wherein the first contact plug and
the second contact plug are made of different conductive materials,
and the second contact plug and the second sub contact plug are
made of the same conductive material.
2. The semiconductor of claim 1, wherein the conductive material
that forms the second sub contact plug and the second contact plug
has a lower resistance than the conductive material that forms the
first sub contact plug.
3. The semiconductor device of claim 2, wherein the conductive
material that forms the first sub contact plug comprises
tungsten.
4. The semiconductor device of claim 3, wherein the conductive
material that forms the second sub contact plug and the second
contact plug comprises copper.
5. The semiconductor device of claim 4, wherein the metal wiring
layers comprise copper.
6. The semiconductor device of claim 1, further comprising a
silicide film formed on the impurity region.
7. The semiconductor device of claim 6, wherein the gate electrode
comprises a polysilicon film and a silicide film which is formed on
the polysilicon film.
8. The semiconductor device of claim 1, wherein the gate electrode
is formed on each of the device isolation regions.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional application of U.S. patent
application Ser. No. 12/909,002, filed Oct. 21, 2010, the
disclosure of which is hereby incorporated herein by reference in
its entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to a semiconductor device.
BACKGROUND
[0003] The ongoing technological development in the field of
semiconductor fabrication is resulting in integrated circuits with
higher device density, lower power consumption, and higher
operation speed. Generally, a highly integrated circuit is designed
using a multi-layer wiring structure that includes an embedded
metal wiring layer and a contact plug.
[0004] In addition, an embedded metal wiring layer and a contact
plug are formed by forming a contact hole in an insulating film and
filling the contact hole with a conductive material.
[0005] As the thickness of an insulating film in which a contact
hole is formed increases, it becomes difficult to secure the
contact area and to completely fill the contact hole to a bottom
surface thereof with a conductive material, thereby causing open
defects.
SUMMARY
[0006] Aspects of the present invention provide a semiconductor
device with reduced contact resistance between a contact plug and a
structure thereunder, the contact plug having enhanced resistance
characteristics.
[0007] However, aspects of the present invention are not restricted
to the one set forth herein. The above and other aspects of the
present invention will become more apparent to one of ordinary
skill in the art to which the present invention pertains by
referencing the detailed description of the present invention given
below.
[0008] According to an aspect of the present invention, there is
provided a semiconductor device including: a substrate; device
isolation regions formed in the substrate; an impurity region
formed in a region of the substrate between two adjacent ones of
the device isolation regions; a gate electrode formed on the
substrate; first and second interlayer insulating films
sequentially formed on the substrate; a metal interlayer insulating
film formed on the second interlayer insulating film and comprising
metal wiring layers; a first contact plug electrically connecting
each of the metal wiring layers and the impurity region; and a
second contact plug electrically connecting each of the metal
wiring layers and the gate electrode, wherein the first contact
plug is formed in the first and second interlayer insulating films,
and the second contact plug is formed in the second interlayer
insulating film.
[0009] According to another aspect of the present invention, there
is provided a semiconductor device including: a substrate; device
isolation regions formed in the substrate; an impurity region
formed in a region of the substrate between two adjacent ones of
the device isolation regions; a gate electrode formed on the
substrate; metal wiring layers formed on the substrate; a first
contact plug electrically connecting each of the metal wiring
layers and the impurity region and including first and second sub
contact plugs which are sequentially formed on the impurity region;
and a second contact plug electrically connecting each of the metal
wiring layers and the gate electrode, wherein the first contact
plug and the second contact plug are made of different conductive
materials, and the second contact plug and the second sub contact
plug are made of the same conductive material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The above and other aspects and features of the present
invention will become more apparent by describing in detail
exemplary embodiments thereof with reference to the attached
drawings, in which:
[0011] FIG. 1 is a cross-sectional view of a semiconductor device
according to an exemplary embodiment of the present inventive
concept;
[0012] FIG. 2 is a cross-sectional view of a semiconductor device
according to another exemplary embodiment of the present inventive
concept;
[0013] FIGS. 3 through 9 are cross-sectional views respectively and
sequentially showing processes included in a method of fabricating
the semiconductor device of FIG. 1; and
[0014] FIGS. 10 through 15 are cross-sectional views respectively
and sequentially showing processes included in a method of
fabricating the semiconductor device of FIG. 2.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0015] Advantages and features of the present invention and methods
of accomplishing the same may be understood more readily by
reference to the following detailed description of exemplary
embodiments and the accompanying drawings. The present invention
may, however, be embodied in many different forms and should not be
construed as being limited to the embodiments set forth herein.
Rather, these embodiments are provided so that this disclosure will
be thorough and complete and will fully convey the concept of the
invention to those skilled in the art, and the present invention
will only be defined by the appended claims. Like reference
numerals refer to like elements throughout the specification. In
some embodiments, well-known processes, well-known structures, and
well-known technologies will not be specifically described in order
to avoid ambiguous interpretation of the present invention. Like
reference numerals refer to like elements throughout the
specification.
[0016] It will be understood that when an element is referred to as
being "connected to" or "coupled to" another element, it can be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected to" or "directly coupled to"
another element, there are no intervening elements present. Like
numbers refer to like elements throughout. As used herein, the term
"and/or" includes any and all combinations of one or more of the
associated listed items.
[0017] It will be understood that, although the terms first,
second, third, etc., may be used herein to describe various
elements, components and/or sections, these elements, components
and/or sections should not be limited by these terms. These terms
are only used to distinguish one element, component or section from
another element, component or section. Thus, a first element,
component or section discussed below could be termed a second
element, component or section without departing from the teachings
of the present invention.
[0018] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," when used in this
specification, specify the presence of stated components, steps,
operations, and/or elements, but do not preclude the presence or
addition of one or more other components, steps, operations,
elements, and/or groups thereof. As used herein, the term "and/or"
includes any and all combinations of one or more of the associated
listed items. Like numbers refer to like elements throughout.
[0019] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which this
invention belongs. It will be further understood that terms, such
as those defined in commonly used dictionaries, should be
interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and will not be
interpreted in an idealized or overly formal sense unless expressly
so defined herein.
[0020] Hereinafter, exemplary embodiments of the present invention
will be described with reference to the attached drawings.
[0021] FIG. 1 is a cross-sectional view of a semiconductor device
according to an exemplary embodiment of the present inventive
concept.
[0022] Referring to FIG. 1, a plurality of device isolation regions
101 are formed in a substrate 100. A region between every two
adjacent ones of the device isolation regions 101 is defined as an
active region 102. The substrate 100 may be, but is not limited to,
a silicon-on-insulator (SOI) substrate or a substrate which is made
of one or more semiconductor materials selected from Si, Ge, SiGe,
GaP, GaAs, SiC, SiGeC, InAs, and InP.
[0023] A plurality of gate electrodes are disposed on the substrate
100. Specifically, a first gate electrode 129 may be disposed on
the active region 102 of the substrate 100 with a gate insulating
film 105 interposed therebetween. On the other hand, a second gate
electrode 130 may be disposed directly on each of the device
isolation regions 101 without the gate insulting film 105
interposed therebetween.
[0024] Each of the first and second gate electrodes 129 and 130 may
be a single film such as a polysilicon film, a metal film, or a
silicide film. Alternatively, each of the first and second gate
electrodes 129 and 130 may be a laminated film composed of the
polysilicon film, the metal film, and the silicide film. Examples
of a metal component of the metal film or the silicide film may
include W, Ta, Ti, Mo, Hf, Zr, Co, Ni, Pt, and Ru. In the
embodiment of FIG. 1, each of the first and second gate electrodes
129 and 130 includes a polysilicon film 103 and a silicide film 111
formed on the polysilicon film 103.
[0025] The gate insulating film 105 may be made of SiOx, SiON, or a
high-k dielectric material. The high-k dielectric material may be
HfO.sub.2, ZrO.sub.2, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, HfSiON,
hafnium silicate, zirconium silicate, or a combination of the
same.
[0026] A first spacer 107 and a second spacer 108 are disposed on
sidewalls of each of the first and second gate electrodes 129 and
130. Each of the first and second spacers 107 and 108 may be made
of SiOx, SiON, or a combination of the same. When necessary, any
one of the first and second spacers 107 and 108 may be omitted.
[0027] Impurity regions doped with impurities are formed in a
region of the substrate 100 between two adjacent ones of the device
isolation regions 101. The impurity regions are formed on both
sides of the first gate electrode 129 to face each other with
respect to the, first gate electrode 129. The impurity regions
include lightly doped impurity regions 106 which are overlapped by
the first and second spacers 107 and 108 and heavily doped regions
109 which are not overlapped by the first and second spacers 107
and 108. A silicide film 110, which is identical or similar to the
silicide film 111 formed on the polysilicon film 103 of each of the
first and second gate electrodes 129 and 130, may be formed on each
of the highly doped impurity regions 109.
[0028] A liner insulating film 112 and a first interlayer
insulating film 113 are disposed on the substrate 100 having the
first and second gate electrodes 129 and 130. The liner insulating
film 112 may be made of, e.g., SiNx. The first interlayer
insulating film 113 may be made of SiOx, SiOF, boron phospho
silicate glass (BPSG), tetraethyl orthosilicate (TEOS), undoped
silicate glass (USG), or a high aspect ratio process (HARP) oxide
film.
[0029] Top surfaces of the first interlayer insulating film 113 and
the liner insulating film 112 may be at the same height from the
substrate 100 as top surfaces of the first and second gat
electrodes 129 and 130. The top surfaces of the first insulating
film 113 and the liner insulating film 112 are planarized to be at
the same height as the top surfaces of the first and second gate
electrodes 129 and 130. The height of the top surface of the first
interlayer insulating film 113 from the substrate 100 may be equal
to a thickness of the second gate electrode 130 formed on each of
the device isolation regions 101 and may be approximately
700.quadrature. or less.
[0030] A first contact hole 115 is formed in the liner insulating
film 112 and the first interlayer insulating film 113. The first
contact hole 115 exposes a predetermined region of the silicide
film 110 formed on each of the heavily doped impurity regions 109.
A first contact plug 131 connects each of the heavily doped
impurity regions 109 and a metal wiring layer 128, and a first sub
contact plug 117 of the first contact plug 131 is formed in the
first contact hole 115.
[0031] The first sub contact plug 117 includes a first barrier
metal film 116 which is conformally formed along inner walls of the
first contact hole 115 and a conductive material which fills the
first contact hole 115. The first barrier metal film 116 may be a
single film made of Ti, TiN, Ta or TaN, or may be a double film
made of two of the above materials. The conductive material that
fills the first contact hole 115 may be, e.g., tungsten.
[0032] Since the first contact hole 115 is formed in the liner
insulating film 112 and the first interlayer insulating film 113
which are planarized to the height of the first and second gate
electrodes 129 and 130, a sufficient contact area can be secured
between the first sub contact plug 117 and the silicide film 110,
and open defects which may occur in the process of filling the
first contact hole 115 with the conductive material can be
prevented.
[0033] A second interlayer insulating film 118, an etch-stop film
119, and a metal interlayer insulating film 120 are sequentially
disposed on the first interlayer insulating film 113 having the
first sub contact plug 117. The second interlayer insulating film
118 may be made of a low-k dielectric material. For example, the
second interlayer insulating film 118 may be made of silicon
oxycarbide (SiOC), carbon-doped hydrogenated silicon oxide (SiOCH),
fluoro-silses-quioxane (FSQ), hydro-silses-quioxane (HSQ), or
methyl-silses-quioxane (MSQ). The second interlayer insulating film
118 made of a low-k dielectric material can reduce the capacitance
between the metal wiring layer 128 and each of the first and second
gate electrodes 129 and 130 or between the metal wiring layer 128
and each of the heavily doped impurity regions 109. The etch-stop
film 119 may be made of a material having a high etch selectivity
with respect to the metal interlayer insulating film 120. For
example, the etch-stop film 119 may be made of SiC, SiN, SiCN,
SiCO, or SiCON. If the second interlayer insulating film 118 and
the metal interlayer insulating film 120 are made of materials
having high etch selectivities with respect to each other, the
etch-stop film 119 may not be formed. The metal interlayer
insulating film 120 may be made of SiOx, SiOF, BPSG, TEOS, or the
like.
[0034] A second contact hole 123 and a third contact hole 124 are
formed in the second interlayer insulating film 118 and the
etch-stop film 119. The second contact hole 123 exposes a
predetermined region of the first sub contact plug 117, and the
third contact hole 124 exposes a predetermined region of the top
surface of the second gate electrode 130. Trenches 122 are formed
in the metal interlayer insulating film 120 to form the metal
wiring layer 128. A second sub contact plug 126 of the first
contact plug 131 which connects each of the heavily doped impurity
regions 109 and the metal wiring layer 128 is formed in the second
contact hole 123. A second contact plug 127 which connects the
second gate electrode 130 and the metal wiring layer 128 is formed
in the third contact hole 124. The metal wiring layer 128 is formed
in each of the trenches 122. In FIG. 1, the metal wiring layer 128,
the second sub contact plug 126, and the second contact plug 127
are made of the same material. However, the present inventive
concept is not limited thereto.
[0035] The second sub contact plug 126, the second contact plug
127, and the metal wiring layer 128 include a second barrier metal
film 125 which is conformally formed along inner walls of the
second contact hole 123, the third contact hole 124, and the
trenches 122 and a conductive material which fills the second
contact hole 123, the third contact hole 124, and the trenches 122.
The second barrier metal film 125 may be a single film made of Ti,
TiN, Ta or TaN, or may be a double film made of two of the above
materials. The conductive material that fills the second contact
hole 123, the third contact hole 124, and the trenches 122 may have
a lower resistance than the conductive material that fills the
first contact hole 115. For example, the conductive material that
fills the second contact hole 123, the third contact hole 124, and
the trenches 122 may be made of copper. Unlike the first sub
contact plug 117, if the second contact plug 127 which is connected
to the second gate electrode 130 is made of copper having a low
resistance, the resistance of the second contact plug 127 can be
reduced. In addition, if the second sub contact plug 126 which is
part of the first contact plug 131 is made of copper having a low
resistance, the resistance of the first contact plug 131 can be
reduced.
[0036] FIG. 2 is a cross-sectional view of a semiconductor device
according to another exemplary embodiment of the present inventive
concept. A description of structures substantially identical to
those of the previous embodiment described above with reference to
FIG. 1 will be omitted or simplified, and differences between them
will mainly be described.
[0037] Referring to FIG. 2, in the semiconductor device according
to the current exemplary embodiment, a liner insulating film 112 is
not removed from top surfaces of first and second gate electrodes
129 and 130. In addition, a top surface of the liner insulating
film 112 disposed on the first and second gate electrodes 129 and
130 may be at the same height from a substrate 100 as a top surface
of a first interlayer insulating film 113.
[0038] A second contact plug 127 which connects the second gate
electrode 130 and a metal wiring layer 128 is formed in the liner
insulating film 112 and a second interlayer insulating film
118.
[0039] Hereinafter, a method of fabricating a semiconductor device
according to an exemplary embodiment of the present inventive
concept will be described in detail with reference to FIGS. 1, and
3 through 9. FIGS. 3 through 9 are cross-sectional views
respectively and sequentially showing processes included in a
method of fabricating the semiconductor device of FIG. 1.
[0040] Referring to FIG. 3, the device isolation regions 101 are
formed in the substrate 100. The device isolation regions 101 may
be formed by local oxidation of silicon (LOCOS) or shallow trench
isolation (STI). A region between two adjacent ones of the device
isolation regions 101 is defined as the active region 102.
[0041] A plurality of gate electrodes are formed on the substrate
100. The first gate electrode 129 formed on the active region 102
is disposed on the gate insulating film 105. On the other hand, the
second gate electrode 130 may be formed directly on each of the
device isolation regions 101 without the gate insulating film 105
interposed therebetween.
[0042] The gate insulating film 105 may be formed by depositing and
patterning a high-k dielectric material such as SiOx, SiON,
HfO.sub.2, ZrO.sub.2, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, HfSiON,
hafnium silicate, zirconium silicate, or a combination of the same.
The gate insulating film 105 may be deposited by chemical vapor
deposition (CVD), plasma enhanced chemical vapor deposition
(PECVD), or low pressure chemical vapor deposition (LPCVD).
[0043] The first and second gate electrodes 129 and 130 may be
formed by depositing and patterning a polysilicon film or a metal
film. The polysilicon film or the metal film may be deposited by
LPCVD, atomic layer deposition (ALD), physical vapor deposition
(PVD), or metal organic chemical vapor deposition (MOCVD). Examples
of a metal component of the metal film or the silicide film may
include W, Ta, Ti, Mo, Hf, Zr, Co, Ni, Pt, and Ru. The following
description will be based on the assumption that the polysilicon
film 103 is used to form each of the first and second gate
electrodes 129 and 130.
[0044] Next, the lightly doped impurity regions 106 doped with
impurities are formed in a region of the substrate 100 between two
adjacent ones of the device isolation regions 101. The lightly
doped impurity regions 106 are formed on both sides of the first
gate electrode 129 to face each other with respect to the first
gate electrode 129. The lightly doped impurity regions 106 may be
formed by implanting ions into the active region 102 of the
substrate 100 using the polysilicon film 103 of the first gate
electrode as an ion implantation mask.
[0045] Then, the first spacer 107 and the second spacer 108 are
formed on sidewalls of the polysilicon film 103 of each of the
first and second gate electrodes 129 and 130. Thereafter, ions are
implanted into the active region 102 of the substrate using the
first and second spacers 107 and 108 as an ion implantation mask,
thereby forming the heavily doped impurity regions 109. When
necessary, any one of the first and second spacers 107 and 108 may
not be formed.
[0046] Next, a silicidation process is performed to form the
silicide films 110 and 111 on the heavily doped impurity regions
109 and the polysilicon film 103 of the first and second gate
electrodes 129 and 130. Before the silicidation process, a silicide
metal film made of Ti, Mo, W, Co, Ni, Ta, Pt or Pd is deposited on
the entire surface of the substrate 100 and is then heat-treated.
As a result of the heat treatment process, a silicide film is
formed in a contact area between the silicide metal film and
silicon. In addition, as a result of the silicidation process, the
silicide films 110 and 111 are formed respectively on the heavily
doped impurity regions 109 and the polysilicon film 103 of each of
the first and second gate electrodes 129 and 130. After the heat
treatment process, a non-silicidated portion of the silicide metal
film is removed.
[0047] Next, the liner insulating film 112 is formed on the entire
surface of the substrate 100. The liner insulating film 112 may be
formed of SiN by CVD, PECVD, or the like.
[0048] Next, the first interlayer insulating film 113 is formed on
the liner insulating film 112. The first interlayer insulating film
113 may be formed of SiOx, SiOF, BPSG, TEOS, USG, or a HARP oxide
film by, e.g., CVD.
[0049] Then, referring to FIG, 4, the first interlayer insulating
film 113 is planarized to a top surface of the silicide film 111 of
each of the first and second gate electrodes 129 and 130. The
planarization process may be a chemical mechanical polishing
process or an etch-back process. After the planarization process,
the height of the top surface of the first interlayer insulating
film 113 from the substrate 100 may be equal to the thickness of
the second gate electrode 130 formed on each of the device
isolation regions 101 and may be approximately 700.quadrature. or
less.
[0050] Next, referring to FIG. 5, a first photoresist pattern 114
is formed on the planarized first interlayer insulating film 113 to
expose regions corresponding respectively to the heavily doped
impurity regions 109. Then, the first interlayer insulating film
113 and the liner insulating film 112 are etched using the first
photoresist pattern 114 as an etch mask, thereby forming the first
contact hole 115 which exposes a predetermined region of the
silicide film 110 on each of the heavily doped impurity regions
109. Here, the first interlayer insulating film 113 and the liner
insulating film 112 may be dry-etched or wet-etched.
[0051] Referring to FIG. 6, the first photoresist pattern 114 is
removed, and the first barrier metal film 116 is conformally formed
on the inner walls of the first contact hole 115. The first barrier
metal film 116 may be a single film made of Ti, TiN, Ta or TaN, or
may be a double film made of two of the above materials. The first
barrier metal film 116 may be formed by CVD, ALD, sputtering, or
electron beam deposition.
[0052] Next, the first sub contact plug 117 is formed by filling
the first contact hole 115 with a conductive material. The
conductive material that fills the first contact hole 115 may be
tungsten. The first sub contact plug 117 may formed by filling the
first contact hole 115 with tungsten using MOCVD or electrical
plating and by processing the surface of the first sub contact plug
117 to be at the same height as the surface of the first interlayer
insulating film 113 in a planarization process such as chemical
mechanical polishing.
[0053] Since the first contact hole 115 is formed in the liner
insulating film 112 and the first interlayer insulating film 113
which are planarized to the height of the first and second gate
electrodes 129 and 130, a sufficient contact area can be secured
between the first sub contact plug 117 and the silicide film 110,
and open defects which may occur in the process of filling the
first contact hole 115 with the conductive material can be
prevented.
[0054] Next, referring to FIG. 7, the second interlayer insulating
film 118, the etch-stop film 119, and the metal interlayer
insulating film 120 are sequentially formed on the entire surface
of the substrate 100 having the first sub contact plug 117. The
second interlayer insulating film 118 may be made of a low-k
dielectric material. For example, the second interlayer insulating
film 118 may be made of SiOC, SiOCH, FSQ, HSQ, or MSQ. The second
interlayer insulating film 118 made of a low-k dielectric material
can reduce the capacitance between a metal wiring layer, which will
be described later, and each of the first and second gate
electrodes 129 and 130 or between the metal wiring layer and each
of the heavily doped impurity regions 109.
[0055] The etch-stop film 119 may serve to stop etching of the
metal interlayer insulating film 120 when the metal interlayer
insulating film 120 is etched to form trenches. The etch-stop film
119 may be made of a material having a high etch selectivity with
respect to the metal interlayer insulating film 120. For example,
the etch-stop film 119 may be made of SiC, SiN, SiCN, SiCO, or
SiCON. If the second interlayer insulating film 118 and the metal
interlayer insulating film 120 are made of materials having high
etch selectivities with respect to each other, the etch-stop film
119 may not be formed.
[0056] Next, referring to FIG. 8, a second photoresist pattern 121
which exposes regions corresponding to the first sub contact plug
117 and the second gate electrode 130 is formed on the metal
interlayer insulating film 120. Then, the metal interlayer
insulating film 120 is etched to the etch-stop film 119 using the
second photoresist pattern 121 as an etch mask, thereby forming the
trenches 122 in the metal interlayer insulating film 120. The metal
interlayer insulating film 120 may be etched using reactive ion
etching.
[0057] Next, referring to FIG. 9, the etch-stop film 119 and the
second interlayer insulating film 118 are etched using the second
photoresist pattern 121 as an etch mask, thereby forming the second
contact hole 123 which exposes a predetermined region of the first
sub contact plug 117 and forming the third contact hole 124 which
exposes a predetermined region of the second gate electrode 130.
The etch-stop film 119 and the second interlayer insulating film
118 may be etched using reactive ion etching.
[0058] Then, a portion of the metal interlayer insulating film 120
formed between regions, which correspond respectively to the second
gate electrode 130 and the first sub contact plug 117 neighboring
the second gate electrode 130, may be removed.
[0059] Next, referring to FIG. 1, the second photoresist pattern
121 is removed, and the second barrier metal film 125 is
conformally formed on the inner walls of the trenches 122, the
second contact hole 123, and the third contact hole 124. The second
barrier metal film 125 may be a single film made of Ti, TiN, Ta or
TaN, or may be a double film made of two of the above materials.
The second barrier metal film 125 may be formed by CVD, ALD,
sputtering, or electron beam deposition.
[0060] Then, a conductive material is filled into the trenches 122,
the second contact hole 123, and the third contact hole 124,
thereby forming the second sub contact plug 126 and the second
contact plug 127 in the second interlayer insulating film 118 and
forming the metal wiring layer 128 in the metal interlayer
insulating film 120. The conductive material that fills the second
contact hole 123, the third contact hole 124, and the trenches 122
may have a lower resistance than the conductive material that fills
the first contact hole 115. For example, the conductive material
that fills the second contact hole 123, the third contact hole 124,
and the trenches 122 may be copper. The second sub contact plug
126, the second contact plug 127, and the metal wiring layer 128
may formed by filling the trenches 122 and the second and third
contact holes 123 and 124 with copper using MOCVD or electrical
plating and by processing the surface of the metal wiring layer 128
to be at the same height as the surface of the metal interlayer
insulating film 120 in a planarization process such as chemical
mechanical polishing.
[0061] Unlike the first sub contact plug 117, if the second contact
plug 127 which is connected to the second gate electrode 130 is
made of copper having a low resistance, the resistance of the
second contact plug 127 can be reduced. In addition, if the second
sub contact plug 126 which is part of the first contact plug 131 is
made of copper having a low resistance, the resistance of the first
contact plug 131 can be reduced.
[0062] Hereinafter, a method of fabricating a semiconductor device
according to another exemplary embodiment of the present inventive
concept will be described in detail with reference to FIGS. 2, 3,
and 10 through 15. FIGS. 10 through 15 are cross-sectional views
respectively and sequentially showing processes included in a
method of fabricating the semiconductor device of FIG. 2. Since
most processing conditions of the current embodiment are
substantially the same as those of the previous embodiment, a
description thereof will be omitted or simplified, and differences
between them will mainly be described.
[0063] Referring to FIG. 10, in the method of fabricating the
semiconductor device of FIG. 2, the interlayer insulating film 113
is formed as shown in FIG. 3 and then planarized to a top surface
of the liner insulating film 112 which is disposed on top surfaces
of the first and second gate electrodes 129 and 130. After the
planarization process, a height of a top surface of the first
interlayer insulating film 113 from the substrate 100 may be
approximately 1,200.quadrature. or less.
[0064] Next, referring to FIG. 11, a first photoresist pattern 114
is formed on the planarized first interlayer insulating film 113 to
expose regions corresponding respectively to heavily doped impurity
regions 109. Then, the first interlayer insulating film 113 and the
liner insulating film 112 are etched using the first photoresist
pattern 114 as an etch mask, thereby forming a first contact hole
115 which exposes a predetermined region of a silicide film 110
formed on each of the heavily doped impurity regions 109. Here, the
first interlayer insulating film 113 and the liner insulating film
112 may be dry-etched or wet-etched.
[0065] Next, referring to FIG. 12, the first photoresist pattern
114 is removed, and a first barrier metal film 116 is conformally
formed on inner walls of the first contact hole 115. The first
barrier metal film 116 may be a single film made of Ti, TiN, Ta or
TaN, or may be a double film made of two of the above materials.
The first barrier metal film 116 may be formed by CVD, ALD,
sputtering, or electron beam deposition.
[0066] Next, a first sub contact plug 117 is formed by filling the
first contact hole 115 with a conductive material and planarizing
the conductive material.
[0067] Since the first contact hole 115 is formed in the liner
insulating film 112 and the first interlayer insulating film 113
which are planarized to the height of the first and second gate
electrodes 129 and 130, a sufficient contact area can be secured
between the first sub contact plug 117 and the silicide film 110,
and open defects which may occur in the process of filling the
first contact hole 115 with the conductive material can be
prevented.
[0068] Next, referring to FIG. 13, a second interlayer insulating
film 118, an etch-stop film 119, and a metal interlayer insulating
film 120 are sequentially formed on the entire surface of the
substrate 100 having the first sub contact plug 117.
[0069] Then, referring to FIG. 14, a second photoresist pattern 121
which exposes regions corresponding respectively to the first sub
contact plug 117 and the second gate electrode 130 is formed on the
metal interlayer insulating film 120. Thereafter, the metal
interlayer insulating film 120 is etched to the etch-stop film 119
using the second photoresist pattern 121 as an etch mask, thereby
forming trenches 122 in the metal interlayer insulating film
120.
[0070] Next, referring to FIG. 15, the etch-stop film 119 and the
second interlayer insulating film 118 are etched using the second
photoresist pattern 121 as an etch mask, thereby forming a second
contact hole 123 which exposes a predetermined region of the first
sub contact plug 117 and forming a fourth contact hole 132 which
exposes a predetermined region of the second gate electrode 130.
The fourth contact hole 132 extends up to the liner insulating film
112 formed on the second gate electrode 130.
[0071] Next, a portion of the metal interlayer insulating film 120
formed between regions, which correspond respectively to the second
gate electrode 130 and the first sub contact plug 117 neighboring
the second gate electrode 130, may be removed.
[0072] Then, referring to FIG. 2, the second photoresist pattern
121 is removed, and a second barrier metal film 125 is conformally
formed on inner walls of the trenches 122, the second contact hole
123, and the fourth contact hole 132.
[0073] Next, a conductive material is filled into the trenches 122,
the second contact hole 123, and the fourth contact hole 132,
thereby forming a second sub contact plug 126 and the second
contact plug 127 in the second interlayer insulating film 118 and
forming a metal wiring layer 128 in the metal interlayer insulating
film 120. The conductive material that fills the second contact
hole 123, the fourth contact hole 132, and the trenches 122 may
have a lower resistance than the conductive material that fills the
first contact hole 115. For example, the conductive material that
fills the second contact hole 123, the fourth contact hole 132, and
the trenches 122 may be copper. The second sub contact plug 126,
the second contact plug 127, and the metal wiring layer 128 may
formed by filling the trenches 122 and the second and fourth
contact holes 123 and 132 with copper using MOCVD or electrical
plating and by processing the surface of the metal wiring layer 128
to be at the same height as the surface of the metal interlayer
insulating film 120 in a planarization process such as chemical
mechanical polishing.
[0074] Unlike the first sub contact plug 117, if the second contact
plug 127 which is connected to the second gate electrode 130 is
made of copper having a low resistance, the resistance of the
second contact plug 127 can be reduced. In addition, if the second
sub contact plug 126 which is part of the first contact plug 131 is
made of copper having a low resistance, the resistance of the first
contact plug 131 can be reduced.
[0075] While the present inventive concept has been particularly
shown and described with reference to exemplary embodiments
thereof, it will be understood by those of ordinary skill in the
art that various changes in form and detail may be made therein
without departing from the spirit and scope of the present
inventive concept as defined by the following claims. The exemplary
embodiments should be considered in a descriptive sense only and
not for purposes of limitation.
* * * * *