U.S. patent application number 13/724597 was filed with the patent office on 2014-05-08 for refresh control circuit of semiconductor apparatus.
This patent application is currently assigned to SK HYNIX INC.. The applicant listed for this patent is SK HYNIX INC.. Invention is credited to Jong man IM.
Application Number | 20140126311 13/724597 |
Document ID | / |
Family ID | 50622235 |
Filed Date | 2014-05-08 |
United States Patent
Application |
20140126311 |
Kind Code |
A1 |
IM; Jong man |
May 8, 2014 |
REFRESH CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS
Abstract
A refresh control circuit of a semiconductor apparatus includes
a variable delay unit configured to delay a signal that is
activated quickest among a plurality of row address strobe signals
activated at a predetermined time interval by a predetermined time,
and to generate a preliminary pulse signal, and a piled delay unit
configured to delay the preliminary pulse signal by various times,
and to generate a plurality of refresh period pulse signals that
are sequentially activated.
Inventors: |
IM; Jong man; (Icheon-si,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK HYNIX INC. |
Icheon-si |
|
KR |
|
|
Assignee: |
SK HYNIX INC.
Icheon-si
KR
|
Family ID: |
50622235 |
Appl. No.: |
13/724597 |
Filed: |
December 21, 2012 |
Current U.S.
Class: |
365/193 |
Current CPC
Class: |
G11C 7/222 20130101;
G11C 11/4094 20130101; G11C 11/40618 20130101; G11C 2211/4065
20130101; G11C 11/40611 20130101 |
Class at
Publication: |
365/193 |
International
Class: |
G11C 11/402 20060101
G11C011/402 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 7, 2012 |
KR |
10-2012-0125570 |
Claims
1. A refresh control circuit of a semiconductor apparatus
comprising: a variable delay unit configured to delay a signal that
is activated quickest among a plurality of row address strobe
signals activated at a predetermined time interval by a
predetermined time, and to generate a preliminary pulse signal; and
a piled delay unit configured to delay the preliminary pulse signal
by various times, and to generate a plurality of refresh period
pulse signals that are sequentially activated.
2. The refresh control circuit of the semiconductor apparatus
according to claim 1, wherein the variable delay unit is configured
to change the predetermined time in response to a refresh mode
signal that defines one of a plurality of refresh modes.
3. The refresh control circuit of the semiconductor apparatus
according to claim 1, wherein the variable delay unit is configured
to delay a signal that is obtained by logically operating signals
of a group activated quickest among the plurality of row address
strobe signals by the predetermined time, and to generate the
preliminary pulse signal.
4. A refresh control circuit of a semiconductor apparatus
comprising: a first piled delay unit configured to generate a
plurality of row active signals that are sequentially activated at
a predetermined time interval in response to a refresh signal; a
delay unit configured to delay the plurality of row active signals
and generate a plurality of row address strobe signals; a variable
delay unit configured to delay a signal that is activated quickest
among the plurality of row address strobe signals by a
predetermined time, and to generate a preliminary pulse signal; and
a second piled delay unit configured to delay the preliminary pulse
signal by various times, and to generate a plurality of refresh
period pulse signals that are sequentially activated.
5. The refresh control circuit of the semiconductor apparatus
according to claim 4, wherein the variable delay unit is configured
to change the predetermined time in response to a refresh mode
signal that defines one of a plurality of refresh modes.
6. The refresh control circuit of the semiconductor apparatus
according to claim 4, wherein the variable delay unit is configured
to delay a signal that is obtained by logically operating signals
of a group activated quickest among the plurality of row address
strobe signals by the predetermined time, and to generate the
preliminary pulse signal.
7. The refresh control circuit of the semiconductor apparatus
according to claim 5, wherein within the refresh mode, a piled mode
is individually performed or both the piled mode and a hidden mode
is performed, wherein the piled mode comprises the plurality of row
active signals activating at the predetermined time interval, and
wherein the hidden mode comprises activation periods of the
plurality of row address strobe signals existing in a predetermined
refresh period provided twice.
8. The refresh control circuit of the semiconductor apparatus
according to claim 4, further comprising: a precharge control unit
configured to deactivate the plurality of row active signals in
response to the plurality of refresh period pulse signals, thereby
controlling a precharge operation of the semiconductor
apparatus.
9. The refresh control circuit of the semiconductor apparatus
according to claim 4, wherein the first piled delay unit is
configured to change the predetermined time interval in response to
a refresh mode signal that defines one of a plurality of refresh
modes.
Description
CROSS-REFERENCES TO RELATED APPLICATION
[0001] The present application claims priority under 35 U.S.C.
.sctn.119(a) to Korean application number 10-2012-0125570, filed on
Nov. 7, 2012, in the Korean Intellectual Property Office, which is
incorporated herein by reference in its entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] The present invention relates generally to a semiconductor
apparatus, and more particularly, to a refresh control circuit of a
semiconductor apparatus.
[0004] 2. Related Art
[0005] As illustrated in FIG. 1, a refresh control circuit 1 of a
semiconductor apparatus according to the conventional art includes
a piled delay unit 10, a delay unit 20, first to fourth variable
delay units 30, 40, 50, and 60, and a precharge control unit
70.
[0006] The piled delay unit 10 generates a plurality of row active
signals RACT<0:7> in response to a refresh signal REF and a
refresh mode signal RMODE.
[0007] The plurality of row active signals RACT<0:7> may then
be activated at a predetermined time interval according to the
refresh mode signal RMODE.
[0008] The delay unit 20 delays the plurality of row active signals
RACT<0:7> by a predetermined time and generates a plurality
of row address strobe signals IRAS<0:7>.
[0009] The delay unit 20 includes a plurality of delays 21 to
28.
[0010] The plurality of variable delay units 30, 40, 50, and 60
delay the plurality of row address strobe signals IRAS<0:7>
by a delay time determined by the refresh mode signal RMODE, and
generate a plurality of refresh period pulse signals
RE<0:3>.
[0011] The variable delay unit 30 delays a signal, which is
obtained by logically operating (for example, ORing) the row
address strobe signals IRAS<0, 7> by the delay time
determined by the refresh mode signal RMODE, and generates a
refresh period pulse signal RE<0>.
[0012] The variable delay unit 40 delays a signal, which is
obtained by logically operating (for example, ORing) the row
address strobe signals IRAS<3, 4> by the delay time
determined by the refresh mode signal RMODE, and generates a
refresh period pulse signal RE<1>.
[0013] The variable delay unit 50 delays a signal, which is
obtained by logically operating (for example, ORing) the row
address strobe signals IRAS<2, 5> by the delay time
determined by the refresh mode signal RMODE, and generates a
refresh period pulse signal RE<2>.
[0014] The variable delay unit 60 delays a signal, which is
obtained by logically operating (for example, ORing) the row
address strobe signals IRAS<1, 6> by the delay time
determined by the refresh mode signal RMODE, and generates a
refresh period pulse signal RE<3>.
[0015] The precharge control unit 70 controls the piled delay unit
10 in response to the plurality of refresh period pulse signals
RE<0:3>, and deactivates the plurality of row active signals
RACT<0:7>.
[0016] FIG. 1 illustrates an example in which the semiconductor
apparatus includes first to eight memory banks BK0 to BK7 (not
shown), and supports a 4 piled operation. Memory banks with the
same order are refreshed for a period in which the plurality of row
active signals RACT<0:7> are activated.
[0017] The 4 piled operation then indicates a refresh scheme in
which four row active signal groups RACT<0, 7>, RACT<3,
4>, RACT<2, 5>, and RACT<1, 6> are activated at a
predetermined time interval.
[0018] The conventional art includes a plurality of variable delay
units, such as variable delay units 30, 40, 50, and 60, such that
the 4 piled operation is supported.
[0019] However, the four variable delay units 30, 40, 50, and 60
attribute to an increase in circuit area of the refresh control
circuit, resulting in a reduction of a layout margin of the
semiconductor apparatus. Accordingly, when supporting a piled
operation beyond the 4 piled operation such as an 8 piled
operation, eight variable delay units are required, resulting in a
significant increase in circuit area.
SUMMARY
[0020] A refresh control circuit of a semiconductor apparatus
capable of reducing circuit area is described herein.
[0021] In an embodiment of the present invention, a refresh control
circuit of a semiconductor apparatus includes: a variable delay
unit configured to delay a signal that is activated quickest among
a plurality of row address strobe signals activated at a
predetermined time interval by a predetermined time and to generate
a preliminary pulse signal, and a piled delay unit configured to
delay the preliminary pulse signal by various times and to generate
a plurality of refresh period pulse signals that are sequentially
activated.
[0022] In another embodiment of the present invention, a refresh
control circuit of a semiconductor apparatus includes: a first
piled delay unit configured to generate a plurality of row active
signals that are sequentially activated at a predetermined time
interval in response to a refresh signal, a delay unit configured
to delay the plurality of row active signals and generate a
plurality of row address strobe signals, a variable delay unit
configured to delay a signal that is activated quickest among the
plurality of row address strobe signals by a predetermined time,
and to generate a preliminary pulse signal; and a second piled
delay unit configured to delay the preliminary pulse signal by
various times and to generate a plurality of refresh period pulse
signals that are sequentially activated.
[0023] According to the refresh control circuit of the
semiconductor apparatus in the present invention, an area of a
delay circuit of the refresh control circuit may be minimized in
order to improve a layout margin of the semiconductor
apparatus.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Features, aspects, and embodiments are described in
conjunction with the attached drawings, in which:
[0025] FIG. 1 is a block diagram of a refresh control circuit 1 of
a semiconductor apparatus according to the conventional art;
[0026] FIG. 2 is a block diagram of a refresh control circuit 100
of a semiconductor apparatus according to an embodiment of the
present invention;
[0027] FIG. 3 is a timing diagram illustrating a refresh operation
scheme of a refresh control circuit 100 of a semiconductor
apparatus according to an embodiment of the present invention.
DETAILED DESCRIPTION
[0028] Hereinafter, a refresh control circuit of a semiconductor
apparatus according to the present invention will be described in
detail with reference to the accompanying drawings through various
embodiments.
[0029] A semiconductor apparatus includes a memory area for storing
data.
[0030] A memory bank BK may be used as a unit for dividing the
memory area.
[0031] Embodiments of the present invention corresponds to a
refresh control circuit 100 when a semiconductor apparatus includes
first to eight memory banks BK0 to BK7 (not illustrated) as an
example for convenience of description. However, the present
invention is not limited to eight memory banks.
[0032] FIG. 2 is a block diagram of a refresh control circuit 100
of a semiconductor apparatus according to an embodiment of the
present invention.
[0033] As illustrated in FIG. 2, the refresh control circuit 100
includes a first piled delay unit 101, a delay unit 20, a variable
delay unit 200, a second piled delay unit 300, and a precharge
control unit 70.
[0034] The first piled delay unit 101 is configured to generate a
plurality of row active signals RACT<0:7> in response to a
refresh signal REF and a refresh mode signal RMODE.
[0035] The refresh mode signal RMODE is then used to define one of
a plurality of refresh modes which will be described later,
including a 4 piled+Hidden mode, a 4 piled mode, a 2 piled+Hidden
mode, and a 2 piled mode.
[0036] When the refresh signal REF is inputted, the first piled
delay unit 101 generates the plurality of row active signals
RACT<0:7> that are sequentially activated at a time interval
set in a refresh mode defined by the refresh mode signal RMODE
among the various refresh modes including the 4 piled+Hidden mode,
the 4 piled mode, the 2 piled+Hidden mode, and the 2 piled
mode.
[0037] The delay unit 20 is configured to delay the plurality of
row active signals RACT<0:7> by a predetermined time and
generate a plurality of row address strobe signals
IRAS<0:7>.
[0038] The delay unit 20 may include a plurality of delays 21 to
28.
[0039] The variable delay unit 200 is configured to delay a signal,
which is obtained by logically operating (for example, ORing)
signals activated quickest among the plurality of row address
strobe signals IRAS<0:7>, such as the row address strobe
signal IRAS<0> and the row address strobe signal
IRAS<7>, by a delay time predetermined by the refresh mode
signal RMODE, and to generate a preliminary pulse signal
RE<0>_PRE.
[0040] The row address strobe signal IRAS<0> and the row
address strobe signal IRAS<7> may then be activated at
substantially similar times.
[0041] Consequently, it may be possible to provide a circuit for
generating the preliminary pulse signal RE<0>_PRE by delaying
only one of the row address strobe signal IRAS<0> and the row
address strobe signal IRAS<7> through the variable delay unit
200.
[0042] However, in a specific operation state, only one of the row
address strobe signal IRAS<0> and the row address strobe
signal IRAS<7> may be activated.
[0043] Accordingly, an embodiment of the present invention
corresponds to a circuit using a signal obtained by ORing the row
address strobe signal IRAS<0> and the row address strobe
signal IRAS<7> as an option for the specific operation state
as an example for convenience of description.
[0044] The second piled delay unit 300 is configured to delay the
preliminary pulse signal RE<0>_PRE by various times, and to
generate a plurality of refresh period pulse signals RE<0:3>
that are sequentially activated at a predetermined time
interval.
[0045] The precharge control unit 70 is configured to control the
first piled delay unit 101 in response to the plurality of refresh
period pulse signals RE<0:3>, and to deactivate the plurality
of row active signals RACT<0:7>.
[0046] Unit delay elements, which constitute the first piled delay
unit 101, the delay unit 20, the variable delay unit 200, and the
second piled delay unit 300 may then be configured to delay only a
rising edge of an input signal.
[0047] FIG. 3 is a timing diagram illustrating a refresh operation
scheme of the refresh control circuit 100 of the semiconductor
apparatus according to an embodiment of the present invention.
[0048] The refresh mode may comprise of various modes, including
the 4 piled+Hidden mode, the 4 piled mode, the 2 piled+Hidden mode,
and the 2 piled mode.
[0049] One of the 4 piled+Hidden mode, the 4 piled mode, the 2
piled+Hidden mode, and the 2 piled mode is selected and thus
defined by the refresh mode signal RMODE at a given time.
[0050] Piled modes then indicate a refresh scheme of grouping a
predetermined number of signal bits among the plurality of row
active signals RACT<0:7>, and activating each group at a
predetermined time interval.
[0051] Hidden modes indicate a refresh scheme of performing a
refresh operation twice for a predetermined refresh period. That
is, externally, a refresh period for a one-time refresh operation
is set. However, internally, the refresh signal REF controls
activation periods to be provided twice, and a refresh operation is
performed twice in each activation period.
[0052] A refresh operation of an embodiment when the refresh mode
signal RMODE defines the 4 piled+Hidden mode will be described
below.
[0053] When the refresh signal REF is inputted, the first piled
delay unit 101 activates four row active signal groups RACT<0,
7>, RACT<3, 4>, RACT<2, 5>, and RACT<1, 6> at
a predetermined time interval such as 10 ns.
[0054] The variable delay unit 200 delays a signal that is obtained
by ORing the row address strobe signal IRAS<0> and the row
address strobe signal IRAS<7>, which are activated quickest
among the plurality of row address strobe signals IRAS<0:7>
by a predetermined delay time such as 80 ns, thereby generating the
preliminary pulse signal RE<0>_PRE.
[0055] The second piled delay unit 300 delays the preliminary pulse
signal RE<0>_PRE by various times, thereby generating the
plurality of refresh period pulse signals RE<0:3> that are
sequentially activated at a predetermined time interval.
[0056] The precharge control unit 70 controls the first piled delay
unit 101 in response to the plurality of refresh period pulse
signals RE<0:3>, thereby deactivating the plurality of row
active signals RACT<0:7>.
[0057] A refresh operation is then performed for the first to
eighth memory banks BK0 to BK7 (not illustrated) for activation
periods of the plurality of row active signals RACT<0:7>.
[0058] A refresh operation of an embodiment when the refresh mode
signal RMODE defines the 2 piled+Hidden mode will be described
below.
[0059] When the refresh signal REF is inputted, the first piled
delay unit 101 activates two row active signal groups RACT<0, 7,
2, 5> and RACT<3, 4, 1, 6> at a predetermined time
interval such as 15 ns.
[0060] The variable delay unit 200 delays a signal that is obtained
by ORing the row address strobe signal IRAS<0> and the row
address strobe signal IRAS<7> of the row address strobe
signals IRAS<0, 7, 2, 5>, which are quickly activated
relative to the plurality of row address strobe signals IRAS<3,
4, 1, 6>, by a predetermined delay time such as 95 ns, thereby
generating the preliminary pulse signal RE<0>_PRE.
[0061] The second piled delay unit 300 delays the preliminary pulse
signal RE<0>_PRE by various times, thereby generating the
plurality of refresh period pulse signals RE<0:3> that are
sequentially activated at a predetermined time interval.
[0062] The precharge control unit 70 controls the first piled delay
unit 101 in response to the plurality of refresh period pulse
signals RE<0:3>, thereby deactivating the plurality of row
active signals RACT<0:7>.
[0063] A refresh operation is then performed for the first to
eighth memory banks BK0 to BK7 (not illustrated) for activation
periods of the plurality of row active signals RACT<0:7>.
[0064] The row address strobe signal IRAS<0> and the row
address strobe signal IRAS<7> are then activated at
substantially similar times.
[0065] Consequently, it may be possible to generate the preliminary
pulse signal RE<0>_PRE by delaying only one of the row
address strobe signal IRAS<0> and the row address strobe
signal IRAS<7> through the variable delay unit 200.
[0066] However, in a specific operation state, only one of the row
address strobe signal IRAS<0> and the row address strobe
signal IRAS<7> may be activated.
[0067] Accordingly, an embodiment corresponds to using a signal
obtained by ORing the row address strobe signal IRAS<0> and
the row address strobe signal IRAS<7> as an option for the
specific operation state for example for convenience of
description.
[0068] As a consequence, according to an embodiment, it is possible
to generate the plurality of refresh period pulse signals
RE<0:3> through only one variable delay unit 200, and to
control a refresh operation.
[0069] In the case of a circuit that supports the 4 piled mode, it
is possible to reduce circuit area due to the variable delay unit
by approximately 1/4 in comparison with the conventional art. In
the case of a circuit that supports an 8 piled mode, it is possible
to reduce circuit area due to the variable delay unit by
approximately 1/8 in comparison with the conventional art.
[0070] While certain embodiments have been described above, it will
be understood to those skilled in the art that the embodiments
described are by way of example only. Accordingly, the refresh
control circuit of the semiconductor apparatus described herein
should not be limited based on the described embodiments. Rather,
the refresh control circuit of the semiconductor apparatus
described herein should only be limited in light of the claims that
follow when taken in conjunction with the above description and
accompanying drawings.
* * * * *