U.S. patent application number 14/151617 was filed with the patent office on 2014-05-08 for flash memory device and programming method thereof.
This patent application is currently assigned to MACRONIX International Co., Ltd.. The applicant listed for this patent is MACRONIX International Co., Ltd.. Invention is credited to Hsing-Wen Chang, Yao-Wen Chang, Chu-Yung Liu.
Application Number | 20140126296 14/151617 |
Document ID | / |
Family ID | 46877248 |
Filed Date | 2014-05-08 |
United States Patent
Application |
20140126296 |
Kind Code |
A1 |
Chang; Hsing-Wen ; et
al. |
May 8, 2014 |
FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF
Abstract
A flash memory device including a memory array, a row decoder
and M page buffers is provided, wherein M is an integer greater
than 2. The memory array includes a plurality of memory cells and
is connected to a plurality of word lines and a plurality of bit
lines. The row decoder drives a specific word line among the word
lines during an enabling period. Each of the page buffers is
connected to N bit lines of the bit lines, and N is an integer
equal to or greater than 3. A j.sup.th page buffer drives an
(N*(j-1)+1).sup.th bit line to an (N*j).sup.th bit line during the
enabling period, and one of an (i-1).sup.th bit line and an
(i+1).sup.th bit line is not driven when an i.sup.th bit line is
not driven, wherein j is an integer and 1.ltoreq.j.ltoreq.M, and i
is an integer and 1<i<M*N.
Inventors: |
Chang; Hsing-Wen; (Hsinchu,
TW) ; Chang; Yao-Wen; (Hsinchu, TW) ; Liu;
Chu-Yung; (Hsinchu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MACRONIX International Co., Ltd. |
Hsinchu |
|
TW |
|
|
Assignee: |
MACRONIX International Co.,
Ltd.
Hsinchu
TW
|
Family ID: |
46877248 |
Appl. No.: |
14/151617 |
Filed: |
January 9, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13069778 |
Mar 23, 2011 |
8644081 |
|
|
14151617 |
|
|
|
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Current U.S.
Class: |
365/185.23 |
Current CPC
Class: |
G11C 16/08 20130101;
G11C 16/3418 20130101; G11C 16/0483 20130101 |
Class at
Publication: |
365/185.23 |
International
Class: |
G11C 16/08 20060101
G11C016/08 |
Claims
1. A flash memory device, comprising: a memory cell array,
comprising a plurality of memory cells, and electrically connected
to a plurality of word lines and a plurality of bit lines; a row
decoder, for driving a specific word line among the word lines
during an enabling period; and M page buffers, each of the page
buffers being electrically connected to N bit lines of the bit
lines, wherein a j.sup.th page buffer drives an (N*(j-1)+1).sup.th
bit line to an (N*j).sup.th bit line during the enabling period, so
as to program the memory cells electrically connected to the
specific word line one-by-one, and one of an (i-1).sup.th bit line
and an (i+1).sup.th bit line is not driven when an i.sup.th bit
line is not driven, wherein M is an integer greater than 2, N is an
integer equal to or greater than 3, j is an integer and
1.ltoreq.j.ltoreq.M, and i is an integer and 1<i<M*N.
2. The flash memory device as claimed in claim 1, wherein the
memory cell array is further electrically connected to a string
selection line and a ground selection line, and the row decoder
respectively provides a power voltage and a ground voltage to the
string selection line and the ground selection line during the
enabling period, provides a program voltage to the specific word
line, and provides a pass voltage to the other word lines.
3. The flash memory device as claimed in claim 1, wherein the
j.sup.th page buffer sequentially provides a ground voltage to the
(N*(j-1)+1).sup.th bit line to the (N*j).sup.th bit line during the
enabling period, and the bit lines without receiving the ground
voltage in the (N*(j-1)+1).sup.th bit line to the (N*j).sup.th bit
line are biased at a power voltage.
4. The flash memory device as claimed in claim 1, wherein the
memory cell array is an NAND memory cell array.
5. A programming method of a flash memory device, wherein the flash
memory device comprises a memory cell array electrically connected
to a plurality of word lines and a plurality of bit lines, and the
memory cell array comprises a plurality of memory cells, and the
programming method of the flash memory device comprising: driving a
specific word line among the word lines during an enabling period;
electrically connecting M page buffers through the bit lines, and
each of the page buffers being electrically connected to N bit
lines of the bit lines, wherein M is an integer greater than 2, and
N is an integer equal to or greater than 3; and driving an
(N*(j-1)+1).sup.th bit line to an (N*j).sup.th bit line by a
j.sup.th page buffer during the enabling period, so as to program
the memory cells electrically connected to the specific word line
one-by-one, wherein one of an (i-1).sup.th bit line and an
(i+1).sup.th bit line is not driven when an i.sup.th bit line is
not driven, j is an integer and 1.ltoreq.j.ltoreq.M, and i is an
integer and 1<i<M*N.
6. The programming method of the flash memory device as claimed in
claim 5, wherein the memory cell array is further electrically
connected to a string selection line and a ground selection line,
and the step of driving the specific word line among the word lines
during the enabling period comprises: providing a power voltage to
the string selection line; providing a ground voltage to the ground
selection line; providing a program voltage to the specific word
line; and providing a pass voltage to the other word lines.
7. The programming method of the flash memory device as claimed in
claim 5, wherein the step of driving the (N*(j-1)+1).sup.th bit
line to the (N *j).sup.th bit line by the j.sup.th page buffer
during the enabling period comprises: sequentially providing a
ground voltage to the (N*(j-1)+1).sup.th bit line to the
(N*j).sup.th bit line by the j.sup.th page buffer during the
enabling period; and biasing the bit lines without receiving the
ground voltage in the (N*(j-1)+1).sup.th bit line to the
(N*j).sup.th bit line at a power voltage during the enabling
period.
8. The programming method of the flash memory device as claimed in
claim 5, wherein the memory cell array is an NAND memory cell
array.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional application of and claims
the priority benefit of an application Ser. No. 13/069,778, filed
on Mar. 23, 2011. The entirety of the above-mentioned patent
application is hereby incorporated by reference herein and made a
part of this specification.
BACKGROUND
[0002] 1. Field of the Invention
[0003] The invention relates to a flash memory device and a
programming method thereof. Particularly, the invention relates to
a NAND flash memory device and a programming method thereof.
[0004] 2. Description of Related Art
[0005] FIG. 1 is a block diagram of a typical NAND flash memory
device. Referring to FIG. 1, the NAND flash memory device 100
includes a memory cell array 110, a row decoder 120 and page
buffers 131-133. The memory cell array 110 includes a plurality of
memory cell strings, and each of the memory cell strings includes a
selection transistor, a plurality of memory cells and a ground
transistor connected in series. For example, a memory cell string
140 includes a selection transistor SW11, a plurality of memory
cells 151, 161-163 and a ground transistor SW12 connected in
series.
[0006] Moreover, the row decoder 120 is electrically connected to
the memory cell array 110 through a string selection line SSL1,
word lines WL11-WL14, and a ground selection line GSL1. The page
buffers 131-133 are electrically connected to the memory cell array
110 through bit lines BL11-BL16. During a programming process, the
row decoder 120 selects one of the word lines according to address
data. Moreover, each of the page buffers is electronically
connected to two bit lines, and alternately provides a ground
voltage Vs1 and a power voltage Vc1 to the two bit lines. Moreover,
when the bit line WL12 is selected, the row decoder 120 provides a
programming voltage Vp1 to the selected word line WL12, and
provides a pass voltage Vt1 to the unselected word lines WL11 and
WL13-WL14.
[0007] In this way, as shown in FIG. 1, during a front half period
of the programming operation, the page buffers 131-133 provide the
ground voltage Vs1 to the odd bit lines BL11, BL13 and BL15, and
provide the power voltage Vc1 to the even bit lines BL12, BL14 and
BL16. Then, the odd memory cells 151, 153 and 155 connected to the
word line WL12 are programmed. In order to avoid influencing the
memory cells 152, 154 and 156 located on the same word line WL12, a
channel voltage of each of the memory cell strings can be boosted
to avoid variations of threshold voltages of the memory cells 152,
154 and 156, which is the so-called program disturbance.
[0008] Generally, according to an existing memory operating method,
the channel voltage of each of the memory cell strings is boosted
by increasing the pass voltage Vt1 provided by the row decoder 120,
so as to reduce the program disturbance. However, if the pass
voltage Vt1 provided by the row decoder 120 is excessively high,
the threshold voltages of the memory cells 161-163, 171-173 and
181-183 respectively located on the same bit line with the memory
cells 151, 153 and 155 are influenced, which is the so-called pass
disturbance. In other words, although the existing memory operating
method resolves the problem of program disturbance by increasing
the pass voltage, the pass disturbance is increased. Therefore, how
to reduce the program disturbance in consideration of the pass
disturbance is an important issue to be developed in memory
operation.
SUMMARY OF THE INVENTION
[0009] The invention is directed to a flash memory device, in which
page buffers divide an enabling period into three or more than
three sub-periods, and drive different bit lines during different
sub-periods. In this way, program disturbance of memory cells can
be reduced without increasing a pass voltage.
[0010] The invention is directed to a programming method of a flash
memory device, by which an enabling period is divided into N
sub-periods, and different bit lines are driven during different
sub-periods. In this way, a channel voltage can be increased by
reducing an equivalent total capacitance of memory cells.
[0011] The invention is directed to a flash memory device, in which
each page buffer is electrically connected to three or more than
three bit lines, respectively, and each page buffer drives the
connected bit lines one-by-one during an enabling period. In this
way, program disturbance of memory cells can be reduced without
increasing a pass voltage.
[0012] The invention is directed to a programming method of a flash
memory device, by which each page buffer is electrically connected
to three or more than three bit lines, respectively, and each page
buffer drives the connected bit lines one-by-one. In this way, a
channel voltage can be increased by reducing an equivalent total
capacitance of memory cells.
[0013] The invention provides a flash memory device including a
memory cell array, a row decoder and M page buffers, wherein M is a
positive integer. The memory cell array includes a plurality of
memory cells and is electrically connected to a plurality of word
lines and a plurality of bit lines. The row decoder drives a
specific word line among the word lines during an enabling period.
The M page buffers divide the enabling period into N sub-periods,
wherein N is an integer greater than 2. Furthermore, the M page
buffers drive an i.sup.th, (i+N).sup.th, (i+2N).sup.th, . . . ,
(i+(M-1)*N).sup.th bit lines during an i.sup.th sub-period, so as
to program the memory cells electrically connected to the specific
word line, wherein i is an integer and 1.ltoreq.i.ltoreq.N.
[0014] In an embodiment of the invention, the memory cell array is
further electrically connected to a string selection line and a
ground selection line, and the row decoder respectively provides a
power voltage and a ground voltage to the string selection line and
the ground selection line during the enabling period, provides a
program voltage to the specific word line, and provides a pass
voltage to the other word lines.
[0015] In an embodiment of the invention, the M page buffers
respectively provide a ground voltage to the i.sup.th,
(i+N).sup.th, (i+2N).sup.th, . . . , (i+(M-1)*N).sup.th bit lines
during the i.sup.th sub-period, and respectively provide a power
voltage to the other bit lines.
[0016] The invention provides a programming method of a flash
memory device, wherein the flash memory device includes a memory
cell array electrically connected to a plurality of word lines and
a plurality of bit lines, and the memory cell array includes a
plurality of memory cells. The programming method of the flash
memory device includes following steps. A specific word line among
the word lines is driven during an enabling period. The enabling
period is divided into N sub-periods by M page buffers, wherein M
is a positive integer, and N is an integer greater than 2.
Furthermore, an i.sup.th, (i+N).sup.th, (i+2N).sup.th, . . . ,
(i+(M-1)*N).sup.th bit lines are driven during an i.sup.th
sub-period, so as to program the memory cells electrically
connected to the specific word line, wherein i is an integer and
1.ltoreq.i.ltoreq.N.
[0017] The invention provides a flash memory device including a
memory cell array, a row decoder and M page buffers, wherein M is a
positive integer. The memory cell array includes a plurality of
memory cells and is electrically connected to a plurality of word
lines and a plurality of bit lines. The row decoder drives a
specific word line among the word lines during an enabling period.
Each of the page buffers is electrically connected to N bit lines
of the bit lines, wherein N is an integer greater than 2.
Furthermore, j.sup.th page buffer drives an (N*(j-1)+1).sup.th bit
line to an (N*j).sup.th bit line during the enabling period, so as
to program the memory cells electrically connected to the specific
word line one-by-one, wherein j is an integer and
1.ltoreq.j.ltoreq.M.
[0018] The invention provides a programming method of a flash
memory device, wherein the flash memory device includes a memory
cell array electrically connected to a plurality of word lines and
a plurality of bit lines, and the memory cell array includes a
plurality of memory cells. The programming method of the flash
memory device includes following steps. A specific word line among
the word lines is driven during an enabling period. M page buffers
are electrically connected to the bit lines, and each of the page
buffers is electrically connected to N bit lines of the bit lines,
wherein M is a positive integer, and N is an integer greater than
2. A j.sup.th page buffer drives an (N*(j-1)+1).sup.th bit line to
an (N*j).sup.th bit line during the enabling period, so as to
program the memory cells electrically connected to the specific
word line one-by-one, wherein j is an integer and
1.ltoreq.j.ltoreq.M.
[0019] According to the above descriptions, each of the page
buffers is electrically connected to three or more than three bit
lines, and each of the page buffers drives the electrically
connected bit lines one-by-one during the enabling period.
Moreover, according to another aspect, the enabling period is
divided into N sub-periods, and different bit lines are driven
during different sub-periods. In this way, an equivalent total
capacitance of the memory cell strings can be reduced, so as to
increase a channel voltage of each of the memory cell strings.
Moreover, during the process of increasing the channel voltage, a
level of the pass voltage is not increased, so that the pass
disturbance is not increased. In other words, according to the
invention, the program disturbance of the memory cell is reduced
while considering not to increase the pass disturbance.
[0020] In order to make the aforementioned and other features and
advantages of the invention comprehensible, several exemplary
embodiments accompanied with figures are described in detail
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention.
[0022] FIG. 1 is a block diagram of a typical NAND flash memory
device.
[0023] FIG. 2 is a schematic diagram of a flash memory device
according to an embodiment of the invention.
[0024] FIG. 3 is a flowchart illustrating a programming method of a
flash memory device according to an embodiment of the
invention.
[0025] FIG. 4 is a cross-sectional view of a layout structure of
memory cells according to an embodiment of the invention.
[0026] FIG. 5 is a cross-sectional view of another layout structure
of memory cells according to an embodiment of the invention.
[0027] FIG. 6A and FIG. 6B are layout schematic diagrams of
diffusion bit lines and diffusion word lines according to an
embodiment of the invention.
[0028] FIG. 7 is a programming method of a flash memory device
according to another embodiment of the invention.
DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS
[0029] FIG. 2 is a schematic diagram of a flash memory device
according to an embodiment of the invention. Referring to FIG. 2,
the flash memory device 200 includes a memory cell array 210, a row
decoder 220 and M page buffers. In the embodiment of FIG. 2, three
page buffers 231-233 (M=3) are taken as an example for
descriptions, though the invention is not limited thereto.
[0030] In the present embodiment, the memory cell array 210 is an
NAND memory cell array, so that the memory cell array 210 includes
a plurality of memory cell strings, and each memory cell string
includes a selection transistor, a plurality of memory cells and a
ground transistor connected in series. For example, a memory cell
string 240 includes a selection transistor SW41, a plurality of
memory cells 251, 281-283 and a ground transistor SW42 connected in
series. Moreover, the memory cell array 210 is electrically
connected to a string selection line SSL4, word lines WL41-WL44, a
ground selection line GSL4 and bit lines BL1-BL9.
[0031] The row decoder 220 is electrically connected to each of the
selection transistors, for example, the selection transistor SW41
in the memory cell array 210 through the string selection line
SSL4. Moreover, the row decoder 220 is electrically connected to
each of the ground transistors, for example, the ground transistor
SW42 in the memory cell array 210 through the ground selection line
GSL4. Moreover, the row decoder 220 is electrically connected to
the memory cells in the memory cell array 210 through the word
lines WL41-WL44, for example, the memory cells 251, 281-283. During
a programming operation, the row decoder 220 selects one of the
word lines according to address data, and drives the selected word
line during an enabling period.
[0032] The page buffers 231-233 are electrically connected to N bit
lines, respectively, where N is an integer greater than 2. For
example, if N is equal to 3, the 1.sup.st page buffer 231 is
electrically connected to a 1.sup.st to a 3.sup.rd bit lines
BL1-BL3, the 2.sup.nd page buffer 232 is electrically connected to
a 4.sup.th to a 6.sup.th bit lines BL4-BL6, and the 3.sup.rd page
buffer 233 is electrically connected to a 7.sup.th to a 9.sup.th
bit line BL7-BL9. Namely, a j.sup.th page buffer is electrically
connected to an ((j-1)*N+1).sup.th bit line to an (j*N).sup.th bit
line, where j is an integer and 1.ltoreq.j.ltoreq.M. During the
enabling period, each of the page buffers 231-233 sequentially
drive the N bit lines, so as to program the memory cells
electrically connected to a certain word line one-by-one.
[0033] In order to fully convey the spirit of the invention to
those skilled in the art, a programming method of the flash memory
device is provided below. FIG. 3 is a flowchart illustrating a
programming method of a flash memory device according to an
embodiment of the invention. Referring to FIG. 2 and FIG. 3 for
detailed operations of the flash memory device 200.
[0034] During a process of programming the memory cell array 210,
in step S310, the row decoder 220 drives a specific word line among
the word lines during an enabling period. For example, if the row
decoder 220 regards the word line WL42 as the specific word line,
detailed steps of driving the specific word line WL42 is as
follows. In step S311, the row decoder 220 provides a power voltage
Vc4 to the string selection line SSL4 to turn on each of the
selection transistors in the memory cell array 210. Moreover, in
step S312, the row decoder 220 provides a ground voltage Vs4 to the
ground selection line GSL4 to turn off each of the ground
transistors in the memory cell array 210. In this way, one end of
each memory cell string is electrically connected to the
corresponding page buffer, and another end of each memory cell
string is floating.
[0035] Moreover, in steps S313 and S314, the row decoder 220
provides a program voltage Vp4 to the specific word line WL42, and
provides a pass voltage Vt4 to the other word lines WL41 and
WL43-WL44. In this way, the memory cells 251-253, 261-263 and
271-273 electrically connected to the specific word line WL42 can
be programmed according to signals transmitted by the page buffers
231-233. On the other hand, in step S320, the page buffers 231-233
divide the enabling period into N sub-periods, for example, if the
page buffers 231-233 are respectively connected to three bit lines
(N=3), the page buffers 231-233 may divide the enabling period into
three sub-periods.
[0036] Moreover, in step S330, during an i.sup.th sub-period, the
page buffers 231-233 drive the i.sup.th, (i+N).sup.th,
(i+2N).sup.th, . . . , (i+(M-1).sup.th bit lines, so as to program
the memory cells electrically connected to the specific word line,
wherein i is an integer and 1.ltoreq.i.ltoreq.N. For example, if
the three page buffers 231-233 divide the enabling period into
three sub-periods, i.e. M=3 and N=3, a detailed flow of the step
S330 is as follows.
[0037] As shown in FIG. 2, during the 1.sup.st sub-period, the page
buffers 231-233 respectively provide a ground voltage Vs4 to the
1.sup.st, 4.sup.th and 7.sup.th bit lines BL1, BL4 and BL7, and
respectively provide a power voltage Vc4 to the other bit lines
BL2-BL3, BL5-BL6 and BL8-BL9. Therefore, the memory cells 251-253
can be programmed. Then, during the 2.sup.nd sub-period, the page
buffers 231-233 respectively provide the ground voltage Vs4 to the
2.sup.nd, 5.sup.th and 8.sup.th bit lines BL2, BL5 and BL8, and
respectively provide the power voltage Vc4 to the other bit lines
BL1, BL3-BL4, BL6-BL7 and BL9. Therefore, the memory cells 261-263
can be programmed.
[0038] Finally, during the 3.sup.rd sub-period, the page buffers
231-233 respectively provide the ground voltage Vs4 to the
3.sup.rd, 6.sup.th and 9.sup.th bit lines BL3, BL6 and BL9, and
respectively provide the power voltage Vc4 to the other bit lines
BL1-BL2, BL4-BL5 and BL7-BL. Therefore, the memory cells 271-273
can be programmed. In other words, in steps S331 and S332, during
the i.sup.th sub-period, the page buffers 231-233 respectively
provide the ground voltage Vs4 to the i.sup.th, (i+N).sup.th,
(i+2N).sup.th, . . . , (i+(M-1)*N).sup.th bit lines, and provides
the power voltage Vc4 to the other bit lines.
[0039] In this way, during the process of programming the memory
cells, regarding a bit line biased at the power voltage Vc4, at
most one of the two left and right adjacent bit lines thereof is
biased under the ground voltage Vs4. For example, during the
1.sup.st sub-period, regarding the bit line BL5 biased at the power
voltage Vc4, only the bit line BL4 at the left side thereof is
biased under the ground voltage Vs4. Moreover, during the 1.sup.st
sub-period, regarding the bit line BL6 biased at the power voltage
Vc4, only the bit line BL7 at the right side thereof is biased
under the ground voltage Vs4. In this way, a channel voltage of
each memory cell string can be increased, so as to reduce the pass
disturbance of the memory cell.
[0040] A main reason thereof lies in a layout structure of the
memory cells shown in FIG. 4. FIG. 4 is a cross-sectional view of a
layout structure of the memory cells 281, 251 and 282, in which a
substrate 410, a source/drain doped layer 420, a floating gate
layer 430 and a control gate layer 440 are illustrated. As shown in
FIG. 4, control gates of the memory cells 281, 251 and 282 are
respectively biased at the pass voltage Vt4, the program voltage
Vp4 and the pass voltage Vt4, and the memory cells 281, 251 and 282
respectively form an inversion layer 450. Moreover, parasitic
capacitances formed due to the layout structure include a parasitic
capacitance Cono between the control gate and the floating gate, a
parasitic capacitance Ctun between the floating gate and the
inversion layer, a parasitic capacitance Cdep between the inversion
layer and the substrate, and a junction capacitance Cj. Therefore,
a channel voltage Vch of the memory cell string 240 is shown as a
following equation (1):
Vch = ( n - 1 ) Cs ( Vt 4 - Vth - Vchi ) n Ctotal + Cs ( Vp 4 - Vth
- Vchi ) n Ctotal + Vchi = ( n - 1 ) Cs n Ctotal Vt 4 + Cs n Ctotal
Vp 4 - Cs Ctotal Vt + ( 1 - Cs Ctotal ) Vchi Cs = Cono Ctun Ctun +
Cono , Cch = Cj + Cdep , Ctotal = Cs + Cch equation ( 1 )
##EQU00001##
[0041] Where, n is a number of the memory cells serially connected
in the memory cell string 240, Vchi is an initial level of the
channel voltage Vch when the memory cell string 240 is switched to
a floating state, and Vth is a threshold voltage of the memory
cell. As shown in the equation (1), the channel voltage Vch is
inversely proportional to an equivalent total capacitance Ctotal.
In other words, the channel voltage Vch can be increased by
reducing the equivalent total capacitance Ctotal.
[0042] Moreover, FIG. 5 is a cross-sectional view of another layout
structure of the memory cells according to an embodiment of the
invention, in which the layout structure of the memory cells 251
and 261 are illustrated, and a control gate layer 510, a floating
gate layer 520, an insulating layer 530 and diffusion bit lines 540
and 550 are indicated. As shown in FIG. 5, a parasitic diffusion
capacitance Cdef can be formed between the two diffusion bit lines
540 and 550, and the diffusion capacitance Cdef is a part of the
equivalent total capacitance Ctotal. Moreover, in view of an
integrated circuit layout, the two diffusion bit lines 540 and 550
are electrically connected to the bit lines BL1 and BL2,
respectively. In other words, voltage levels of the bit lines BL1
and BL2 determine whether the diffusion capacitance Cdef is formed,
and accordingly influence a magnitude of the equivalent total
capacitance Ctotal.
[0043] For example, FIG. 6A and FIG. 6B are layout schematic
diagrams of diffusion bit lines and diffusion word lines according
to an embodiment of the invention, in which the diffusion bit lines
540 and 550 and diffusion word lines 610-630 are illustrated. As
shown in FIG. 6A, when the bit lines BL1 and BL2 are respectively
biased at the ground voltage Vs4 and the power voltage Vc4, the two
diffusion bit lines 540 and 550 are also biased at the ground
voltage Vs4 and the power voltage Vc4. Now, a voltage difference
between the bit lines BL1 and BL2 may cause the diffusion
capacitance formed between the diffusion bit lines 540 and 550, so
that the equivalent total capacitance Ctotal is increased.
Comparatively, as shown in FIG. 6B, when the bit lines BL1 and BL2
are all biased at the power voltage Vc4, the two diffusion bit
lines 540 and 550 are also biased at the power voltage Vc4. Now,
since the voltage difference between the bit lines BL1 and BL2 is
0, the diffusion capacitance cannot be formed between the two
diffusion bit lines 540 and 550, so that the equivalent total
capacitance Ctotal is decreased.
[0044] In other words, during the process of programming the memory
cells, regarding a certain bit line biased at the power voltage
Vc4, if the two left and right adjacent bit lines thereof are all
biased at the ground voltage Vs4, voltage differences are
respectively formed between such bit line and the two left and
right adjacent bit lines thereof, so that the equivalent total
capacitance Ctotal is increased. However, in the present
embodiment, regarding a certain bit line biased at the power
voltage Vc4, at most one of the two left and right adjacent bit
lines thereof is biased under the ground voltage Vs4, so that the
equivalent total capacitance Ctotal can be reduced, and the channel
voltage Vch can be accordingly increased. Moreover, in the present
embodiment, during a process of increasing the channel voltage Vch,
a level of the pass voltage Vt4 is not increased, so that
increasing of the pass disturbance is avoided. In other words, the
program disturbance of the memory cell is reduced while considering
not to increase the pass disturbance.
[0045] It should be noticed that in the above embodiment, each of
the page buffers 231-233 drives the N electrically connected bit
lines one-by-one during the enabling period. Therefore, if the
enabling period is divided into N sub-periods, during the i.sup.th
sub-period, the i.sup.th, (i+N).sup.th, (i+2N).sup.th, . . . ,
(i+(M-1)*N).sup.th bit lines are driven by the page buffers
231-233. In other words, according to another aspect, FIG. 7 is a
programming method of a flash memory device according to another
embodiment of the invention.
[0046] Referring to FIG. 2 and FIG. 7, during a process of
programming the memory cell array 210, in step S710, the row
decoder 220 drives a specific word line among the word lines during
the enabling period. Detailed steps of the step S710 are the same
or similar to that of the step S310 of FIG. 3, so that detailed
descriptions thereof are not repeated. Moreover, in step S720, M
page buffers 231-233 are electrically connected to the bit lines
BL1-BL9, where each of the page buffers 231-233 is electrically
connected to N bit lines, where M is a positive integer, and N is
an integer greater than 2. In other words, a j.sup.th page buffer
is electrically connected to an ((j-1)*N+1).sup.th bit line to an
(j*N).sup.th bit line, where j is an integer and
1.ltoreq.j.ltoreq.M.
[0047] Moreover, in step S730, during the enabling period, the
j.sup.th page buffer sequentially drives the (N*(j-1)+1).sup.th bit
line to the (N*j).sup.th bit line, so as to program the memory
cells electrically connected to the specific word line one-by-one,
where j is an integer and 1.ltoreq.j.ltoreq.M. For example, if M=3
and N=3, during the enabling period, the page buffer 231 provides
the ground voltage Vs4 to the bit line BL1-BL3 one-by-one.
Moreover, when the page buffer 231 provides the ground voltage Vs4
to the bit line BL1, the page buffer 231 biases the bit lines BL2
and BL3 at the power voltage Vc4. Similarly, when the page buffer
231 provides the ground voltage Vs4 to the bit line BL2, the page
buffer 231 biases the bit lines BL1 and BL3 at the power voltage
Vc4.
[0048] On the other hand, regarding the page buffer 232, during the
enabling period, the page buffer 232 provides the ground voltage
Vs4 to the bit line BL4-BL6 one-by-one. Moreover, when the page
buffer 232 provides the ground voltage Vs4 to the bit line BL4, the
page buffer 232 biases the bit lines BL5 and BL6 at the power
voltage Vc4. Operations of the page buffer 233 are deduced by
analogy. In other words, in steps S731 and S732, during the
enabling period, the j.sup.th page buffer sequentially provides the
ground voltage Vs4 to the (N*(j-1)+1).sup.th bit line to the
(N*j).sup.th bit line, and the bit lines without receiving the
ground voltage Vs4 in the (N*(j-1)+1).sup.th bit line to the
(N*j).sup.th bit line are biased at the power voltage Vc4. The
above embodiments can be referred for detailed descriptions of the
present embodiment, which are not repeated herein.
[0049] In summary, each of the page buffers is electrically
connected to three or more than three bit lines, and each of the
page buffers drives the electrically connected bit lines during the
enabling period one-by-one. In this way, the equivalent total
capacitance of the memory cell strings can be reduced, so as to
increase a channel voltage of each of the memory cell strings.
Moreover, during the process of increasing the channel voltage, a
level of the pass voltage is not increased, so that the pass
disturbance is not increased. In other words, according to the
invention, the program disturbance of the memory cell is reduced
while considering not to increase the pass disturbance.
[0050] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
invention cover modifications and variations of this invention
provided they fall within the scope of the following claims and
their equivalents.
* * * * *