U.S. patent application number 14/051299 was filed with the patent office on 2014-04-17 for isolation components for transistors formed on fin features of semiconductor substrates.
This patent application is currently assigned to Marvell World Trade Ltd.. The applicant listed for this patent is Marvell World Trade Ltd.. Invention is credited to Runzi Chang, Chuan-Cheng Cheng.
Application Number | 20140103452 14/051299 |
Document ID | / |
Family ID | 50474625 |
Filed Date | 2014-04-17 |
United States Patent
Application |
20140103452 |
Kind Code |
A1 |
Chang; Runzi ; et
al. |
April 17, 2014 |
ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF
SEMICONDUCTOR SUBSTRATES
Abstract
In an embodiment, an apparatus includes a substrate including a
surface having a planar portion and a fin feature extending in a
direction substantially perpendicular to the planar portion and
having a thickness less than a thickness of the substrate. The
apparatus also includes a first transistor that includes a first
gate region formed over the fin feature, a first source region
formed from a body of the fin feature, and a first drain region
formed from the body of the fin feature. Additionally, the
apparatus includes a second transistor that includes a second gate
region formed over the fin feature, a second source region formed
from the body of the fin feature, and a second drain region formed
from the body of the fin feature. Further, the apparatus includes
an isolation component formed between the first transistor and the
second transistor, where the isolation component has a width less
than 30 nm.
Inventors: |
Chang; Runzi; (San Jose,
CA) ; Cheng; Chuan-Cheng; (Fremont, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Marvell World Trade Ltd. |
St. Michael |
|
BB |
|
|
Assignee: |
Marvell World Trade Ltd.
St. Michael
BB
|
Family ID: |
50474625 |
Appl. No.: |
14/051299 |
Filed: |
October 10, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61713990 |
Oct 15, 2012 |
|
|
|
Current U.S.
Class: |
257/401 ;
438/283 |
Current CPC
Class: |
H01L 21/764 20130101;
H01L 27/0886 20130101; H01L 27/1211 20130101; H01L 21/845 20130101;
H01L 21/76224 20130101; H01L 29/66795 20130101; H01L 21/28035
20130101; H01L 21/823431 20130101 |
Class at
Publication: |
257/401 ;
438/283 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 29/66 20060101 H01L029/66 |
Claims
1. An apparatus comprising: a substrate including a surface,
wherein the surface includes a planar portion, and a fin feature
extending in a direction substantially perpendicular to the planar
portion and having a thickness less than a thickness of the
substrate; a first transistor, wherein the first transistor
includes a first gate region formed over the fin feature, a first
source region formed from a body of the fin feature, and a first
drain region formed from the body of the fin feature; a second
transistor, wherein the second transistor includes a second gate
region formed over the fin feature, a second source region formed
from the body of the fin feature, and a second drain region formed
from the body of the fin feature; and an isolation component formed
between the first transistor and the second transistor, wherein the
isolation component has a width less than 30 nm.
2. The apparatus of claim 1, wherein: the fin feature has a
substantially rectangular shape; the fin feature includes four
sides extending in the direction substantially perpendicular to the
planar portion; and the fin feature includes an additional side
substantially parallel to the planar portion.
3. The apparatus of claim 1, wherein: the first drain region of the
first transistor is adjacent to the isolation component; and the
second source region of the second transistor is adjacent to the
isolation component.
4. The apparatus of claim 1, wherein the width of the isolation
component is in a range of 9 nm to 18 nm.
5. The apparatus of claim 1, wherein: a layer is disposed on the
planar portion of the surface of the substrate; the layer includes
a first dielectric material; and the isolation component includes a
second dielectric material.
6. An apparatus comprising: a substrate including a surface,
wherein the surface includes a planar portion, and a fin feature
extending in a direction substantially perpendicular to the planar
portion and having a thickness less than a thickness of the
substrate; a layer formed over the planar portion of the surface of
the substrate, wherein the layer includes a first dielectric
material; a first transistor, wherein the first transistor includes
a first gate region disposed on at least two sides of the fin
feature, a first source region formed from a body of the fin
feature, and a first drain region formed from the body of the fin
feature; a second transistor, wherein the second transistor
includes a second gate region formed on the at least two sides of
the fin feature, a second source region formed from the body of the
fin feature, and a second drain region formed from the body of the
fin feature; and an isolation component formed between the first
transistor and the second transistor, wherein the isolation
component includes a second dielectric material that is different
from the first dielectric material.
7. The apparatus of claim 6, wherein the first dielectric material
has a dielectric constant with a value greater than a value of the
dielectric constant of the second material.
8. The apparatus of claim 6, wherein the first dielectric material
includes one of SiO.sub.2 or SiN.
9. The apparatus of claim 6, wherein the isolation component
includes a third dielectric material that is different from (i) the
first dielectric material and (ii) the second dielectric
material.
10. The apparatus of claim 9, wherein: the isolation component
includes a cavity filled with the third dielectric material; and
the cavity is encased by at least the second dielectric
material.
11. The apparatus of claim 6, wherein the isolation component has a
width in a range of 6 nm to 29 nm.
12. The apparatus of claim 6, wherein the substrate includes an
additional fin feature, and wherein the substrate further includes:
a third transistor, wherein the third transistor includes a third
gate region disposed on at least two sides of the additional fin
feature, a third source region formed from a body of the additional
fin feature, and a third drain region formed from the body of the
fin feature; a fourth transistor, wherein the fourth transistor
includes a fourth gate region disposed on the at least two sides of
the additional fin feature, a fourth source region formed from the
body of the additional fin feature, and a fourth drain region
formed from the body of the additional fin feature; and an
additional isolation component formed between the third transistor
and the fourth transistor.
13. A method comprising: forming a fin feature on a portion of a
surface of a substrate including silicon, wherein the fin feature
extends in a direction perpendicular to a planar portion of the
surface of the substrate; forming a first region of polycrystalline
silicon over a first portion of the fin feature of the substrate;
forming a second region of polycrystalline silicon over a second
portion of the fin feature of the substrate; forming a third region
of polycrystalline silicon over a third portion of the fin feature
of the substrate, wherein the third region of polycrystalline
silicon is disposed between (i) the first region of polycrystalline
silicon and (ii) the second region of polycrystalline silicon;
forming a first spacer region between (i) the first region of
polycrystalline silicon and (ii) the third region of
polycrystalline silicon, wherein the first spacer region includes a
first dielectric material; forming a second spacer region between
(i) the second region of polycrystalline silicon and (ii) the third
region of polycrystalline silicon, wherein the second spacer region
includes the first dielectric material; removing at least (i) the
third region of polycrystalline silicon and (ii) at least a portion
of the fin feature formed under the third region of polycrystalline
silicon to thereby form a gap between (i) the first region of
polycrystalline silicon and (ii) the second region of
polycrystalline silicon; and disposing a second dielectric material
into the gap between (i) the first region of polycrystalline
silicon and (ii) the second region of polycrystalline silicon to
form an isolation component.
14. The method of claim 13, further comprising: placing a mask over
the substrate, wherein the mask includes an opening corresponding
to a location of the third region of polycrystalline silicon; and
etching (i) the third region of polycrystalline silicon and (ii)
the at least a portion of fin feature according to a pattern of the
mask.
15. The method of claim 14, further comprising etching a portion of
the substrate such that the gap extends below a surface of the
planar portion of the surface of the substrate.
16. The method of claim 13, further comprising: forming an
additional fin feature on the substrate, wherein both (i) the fin
feature and (ii) the additional fin feature are formed using a
self-aligning double patterning process.
17. The method of claim 13, wherein a width of the isolation
component is less than 30 nm.
18. The method of claim 13, wherein the first dielectric material
is different from the second dielectric material.
19. The method of claim 13, wherein: the first polycrystalline
silicon region forms a gate of a first transistor; and the third
polycrystalline silicon region forms a gate of a second
transistor.
20. The method of claim 13, further comprising: after forming the
first spacer region and the second spacer region, embedding
stressor materials into the substrate, wherein the stressor
materials include one or both of SiGe and/or SiC.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This claims priority to U.S. Provisional Patent Application
No. 61/713,990, filed on Oct. 15, 2012, which is incorporated
herein by reference.
TECHNICAL FIELD
[0002] This disclosure relates to the formation of transistors from
semiconductor materials. More specifically, this disclosure relates
to the formation of field effect transistors (FETs) having a gate
formed on a fin feature extending from a semiconductor substrate
with an isolation component formed between the field effect
transistors, where the isolation component has minimal
dimensions.
BACKGROUND
[0003] In some cases, transistors can be formed from a
semiconductor substrate that has a fin feature extending from a
surface of the semiconductor substrate. The fin feature can extend
substantially perpendicular to a planar surface of the
semiconductor substrate. The fin feature can also have a thickness
that is less than the thickness of the semiconductor substrate.
Thus, by extending from a surface of the semiconductor substrate
and having a thickness less than a thickness of the semiconductor
substrate, the fin feature may resemble a "fin" extending above the
surface of the semiconductor substrate. Respective gates of the
transistors can be formed by disposing a material, such as a
polycrystalline silicon (also referred to herein as "polysilicon"),
on multiple surfaces of the fin feature. For example, the gates of
the transistors can be formed by encasing a portion of the fin in
polysilicon. Additionally, the source regions and the drain regions
of the transistors can be formed from doped regions of the fin
feature. In particular embodiments, gates of multiple transistors
can be formed around a single fin feature. In these scenarios, the
transistors can be electrically isolated to decrease interference
between the transistors and minimize delays that may occur when the
transistors change states.
[0004] In some cases, transistors formed from semiconductor
substrates having fin features have been isolated using a number of
techniques. In one example, the transistors have been isolated by
placing an isolation gate between the transistors. In this example,
the isolation gates include electrical features that are coupled to
a supply voltage and/or a drain voltage. The connection of the
isolation gates to electrical features of an integrated circuit can
result in a parasitic capacitance that causes a delay in the
response of the transistors to a state change. Further, the area
covered by the isolation gates can be relatively large.
[0005] In another example, transistors formed from substrates
having fin features can be isolated by performing a fin cut to cut
through the fin feature between the transistors. The size of the
fin cut is often limited because of lithographic techniques and has
a width that is 30 nm or greater, which decreases the density of
transistors formed on the substrate. Furthermore, the fin cut can
remove contact between the polysilicon and the fin, which can
inhibit the process for embedding stressors in the semiconductor
substrate, such as SiGe and/or SiC, which are used to increase the
performance of the transistors.
[0006] In still another example, regions of polysilicon can be
placed at the ends of transistors after the fin cut is performed to
create a polysilicon connection with the fins in order to
facilitate the processes used to embed the stressors into the
substrate. However, the regions formed using this technique have
widths limited by 2-D lithography resolution (for example, at least
74 nm in some FinFET technologies), which reduces the density of
transistors formed on the substrate.
SUMMARY
[0007] In accordance with an embodiment, an apparatus includes a
substrate including a surface, and the surface includes a planar
portion and a fin feature extending in a direction substantially
perpendicular to the planar portion. The fin feature has a
thickness less than a thickness of the substrate. The apparatus
also includes a first transistor that includes a first gate region
formed over the fin feature, a first source region formed from a
body of the fin feature, and a first drain region formed from the
body of the fin feature. Additionally, the apparatus includes a
second transistor that includes a second gate region formed over
the fin feature, a second source region formed from the body of the
fin feature, and a second drain region formed from the body of the
fin feature. Further, the apparatus includes an isolation component
formed between the first transistor and the second transistor. The
isolation component has a width less than 30 nm.
[0008] Additionally, in accordance with an embodiment, an apparatus
includes a substrate having a surface that includes a planar
portion and a fin feature extending in a direction substantially
perpendicular to the planar portion. The fin feature has a
thickness less than a thickness of the substrate. The apparatus
also includes a layer formed over the planar portion of the surface
of the substrate, where the layer includes a first dielectric
material. In addition, the apparatus includes a first transistor
having a first gate region disposed on at least two sides of the
fin feature, a first source region formed from a body of the fin
feature, and a first drain region formed from the body of the fin
feature. Further, the apparatus includes a second transistor having
a second gate region formed on the at least two sides of the fin
feature, a second source region formed from the body of the fin
feature, and a second drain region formed from the body of the fin
feature. The apparatus also includes an isolation component formed
between the first transistor and the second transistor. The
isolation component includes a second dielectric material that is
different from the first dielectric material.
[0009] Further, in accordance with an embodiment, a method includes
forming a fin feature on a portion of a surface of a substrate
including silicon, where the fin feature extends in a direction
perpendicular to a planar portion of the surface of the substrate
and has a thickness less than a thickness of the substrate, and the
method includes forming a first region of polycrystalline silicon
over a first portion of the fin feature of the substrate. The
method also includes forming a second region of polycrystalline
silicon over a second portion of the fin feature of the substrate
and forming a third region of polycrystalline silicon over a third
portion of the fin feature of the substrate. The third region of
polycrystalline silicon is disposed between (i) the first region of
polycrystalline silicon and (ii) the second region of
polycrystalline silicon. Additionally, the method includes forming
a first spacer region between (i) the first region of
polycrystalline silicon and (ii) the third region of
polycrystalline and forming a second spacer region between (i) the
second region of polycrystalline silicon and (ii) the third region
of polycrystalline silicon. The second spacer region includes the
first dielectric material. Further, the method includes removing at
least (i) the third region of polycrystalline silicon and (ii) at
least a portion of the fin feature formed under the third region of
polycrystalline silicon to thereby form a gap between (i) the first
region of polycrystalline silicon and (ii) the second region of
polycrystalline silicon and disposing a second dielectric material
into the gap between (i) the first region of polycrystalline
silicon and (ii) the second region of polycrystalline silicon to
form an isolation component.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Embodiments of the present disclosure will be readily
understood by the following detailed description in conjunction
with the accompanying drawings. To facilitate this description,
like reference numerals designate like elements.
[0011] FIG. 1 illustrates a cross-sectional view of a semiconductor
substrate including transistors formed from a fin feature of the
semiconductor substrate and an isolation component formed between
the transistors.
[0012] FIG. 2 illustrates an orthogonal view of a semiconductor
substrate including a fin feature and an oxide layer formed on the
semiconductor substrate.
[0013] FIG. 3 illustrates an orthogonal view of a semiconductor
substrate including a fin feature and a plurality of additional
features formed over the fin feature.
[0014] FIG. 4 illustrates an orthogonal view of a semiconductor
substrate including a fin feature and a plurality of additional
features formed over the fin feature and regions of dielectric
material formed between the additional features.
[0015] FIG. 5 illustrates a top view of a mask to place over a
semiconductor substrate.
[0016] FIG. 6 illustrates an orthogonal view of a semiconductor
substrate formed after placing a mask on the semiconductor
substrate and etching portions of the semiconductor substrate
exposed by the mask.
[0017] FIG. 7 illustrates an orthogonal view of a semiconductor
substrate including isolation components disposed between
transistors formed on the semiconductor substrate.
[0018] FIG. 8 illustrates a top view of an arrangement of features
on a semiconductor substrate formed using a self-aligning double
patterning process.
[0019] FIG. 9 illustrates a flow diagram of a process to form a
semiconductor substrate having isolation components disposed
between transistors formed from the semiconductor substrate having
a fin feature.
DETAILED DESCRIPTION
[0020] Described herein are example systems, components, and
techniques directed to a semiconductor substrate having a fin
feature that includes isolation components disposed between
transistors formed from the semiconductor substrate, where the
isolation components have minimal dimensions. For example, the
isolation components can have a width less than 30 nm. The
following description merely provides examples and is in no way
intended to limit the disclosure, its application, or uses.
[0021] This disclosure is directed to isolation components formed
between transistors on a semiconductor substrate having a fin
feature that minimizes the size of the isolation components.
Additionally, no electrical connections are made between the
isolation components of embodiments described herein and other
features of an integrated circuit. In this way, the density of
transistors formed on the semiconductor substrate is maximized
while minimizing any delay of the operation of the transistors
caused by the isolation components. Further, the techniques
described herein to form the isolation components maintain the
contact between the polysilicon features and the semiconductor
substrate. Thus, the processes used to embed stressors in the
substrate are not inhibited by the lack of contact between
polysilicon regions and the semiconductor substrate.
[0022] FIG. 1 illustrates a cross-sectional view of a portion of a
semiconductor substrate 100 including transistors formed from a fin
feature 102 of the semiconductor substrate 100 and an isolation
region 104 formed between the transistors. In a particular
embodiment, the transistors are included in an integrated circuit
that can be utilized in an electronic device to perform various
operations and functions, such as memory functions, processing
functions, or both.
[0023] In one embodiment, the semiconductor substrate 100 includes
silicon. In some embodiments, the semiconductor substrate 100
includes silicon and germanium. In some cases, a layer 106 is
formed over a planar portion of the semiconductor substrate 100
that extends outward from the base of the fin feature 102. In an
embodiment, the layer 106 includes a dielectric material. In a
particular embodiment, the layer 106 includes an oxide. For
example, the layer 106 can include silicon dioxide. In other cases,
the layer 106 can include silicon nitride. In some cases, the
semiconductor substrate 100 also includes embedded stressors, such
as a silicon germanium stressor and/or a silicon carbide
stressor.
[0024] In an embodiment, the fin feature 102 has a substantially
rectangular shape. In these scenarios, the fin feature 102 has four
sides extending vertically from a planar portion of the
semiconductor substrate 100 and the fin feature 102 has a
horizontal side on top of the four vertical sides that is
substantially parallel with a planar portion of the semiconductor
substrate 100. In other embodiments, the fin feature 102 has a
different shape, such as a circular shape or a triangular
shape.
[0025] A first transistor 108 is formed with the semiconductor
substrate 100, where the first transistor 108 includes a first
region 110, a second region 112, and a gate 114. In some
embodiments, the first region 110 includes a source region and the
second region 112 includes a drain region, while in other
embodiments, the first region 110 includes a drain region and the
second region 112 includes a source region. In an embodiment, the
first region 110 and the second region 112 include doped regions of
the semiconductor substrate 100. In some cases, the first region
110 and/or the second region 112 are doped with phosphorus. In
other cases, the first region 110, the second region 112, or both
are doped with arsenic. In an embodiment, the gate 114 includes
polysilicon.
[0026] A second transistor 116 is also formed with the
semiconductor substrate 100. The second transistor 116 includes a
third region 118, a fourth region 120, and a gate 122. In an
embodiment, the third region 118 includes a source region and the
fourth region 120 includes a drain region. In other embodiments,
the third region 118 includes a drain region and the fourth region
120 includes a source region. In some cases, the third region 118
and the fourth region 120 include a suitable dopant and the gate
122 includes polysilicon.
[0027] Further, the isolation component 104 is formed with the
semiconductor substrate 100. The isolation component 104 has a
width 124. In an embodiment, the width 124 is no greater than 30
nm, no greater than 25 nm, or no greater than 20 nm. In other
embodiments, the width 124 is at least 5 nm, at least 10 nm or at
least 15 nm. In an illustrative embodiment, the width 124 is
included in a range of 6 nm to 29 nm. In another illustrative
embodiment, the width 124 is included in a range of 9 to 18 nm.
[0028] In some cases, the isolation component 104 includes a
dielectric material. In particular, the isolation component 104
includes a dielectric material that is different than a dielectric
material of the layer 106. For example, the isolation component 104
can include a dielectric material that has a dielectric constant
less than the dielectric constant of the layer 106. In an
embodiment, a portion of the isolation region 104 includes air or
another gas. To illustrate, a solid dielectric material can be used
to form a cap on the isolation component 104, thus creating a
cavity within the isolation region 104 that includes air or another
gas. In some embodiments, the isolation component 104 extends below
a plane 126 that defines a base of the fin feature 102. For
example, the isolation region 104 can include an additional region
128.
[0029] Although, the illustrative example of FIG. 1 includes two
transistors 108, 116 and one isolation component 104, any number of
transistors and isolation components can be formed from the
substrate 100.
[0030] FIG. 2 illustrates an orthogonal view of a semiconductor
substrate 100 including a fin feature 102 and a layer 106 formed on
the semiconductor substrate 100. The substrate 100, the fin feature
102, and the layer 106 are formed with a single patterning process
using extreme ultraviolet (UV) radiation techniques. In addition,
the substrate 100, the fin feature 102, and the layer 106 are
formed with a single patterning process using electron beam
techniques.
[0031] In a particular embodiment, the fin feature 102 is formed
according to conventional techniques that can include depositing a
stack of dielectric materials that includes one or more layers
alternating layers of silicon nitride and silicon oxide on the
substrate 100. In an illustrative embodiment, a layer of silicon
nitride is formed at the top of a stack of dielectric materials
followed by a layer of silicon dioxide, another layer of silicon
nitride and an additional layer of silicon dioxide. In some
embodiments, the formation of the fin feature 102 includes etching
the top layer of silicon nitride according to a pattern and the
deposition of polysilicon spacers adjacent to the remaining
portions of the top layer of silicon nitride. Additional etching
steps are then performed to form the fin feature 102. Subsequently,
the layer 106 is formed by depositing a dielectric material, such
as silicon dioxide, on the substrate 100 and the fin feature 102,
followed by chemical mechanical polishing and a wet etch back. In
an embodiment, the fin feature 102 can have a first thickness 202
that is less than a second thickness 204 of the substrate 100.
[0032] In some cases, self-aligned double patterning techniques can
also be used to form a substrate with fin features that can be
utilized with embodiments described herein. In these scenarios, a
plurality of fins can be formed from the substrate 100.
[0033] FIG. 3 illustrates an orthogonal view of a semiconductor
substrate 100 including a fin 102 feature and a plurality of
additional features formed over the fin feature 102. In particular,
a first gate 114 of a first transistor is formed over the fin
feature 102 and a second gate 122 of a second transistor is formed
over the fin feature 102. Additionally, a first isolation region
104, a second isolation region 302 and a third isolation region 304
is formed over the fin feature 102. In an embodiment, one or more
of the first gate 114, the second gate 122, the first isolation
region 104, the second isolation region 302, or the third isolation
region 304 includes polysilicon. In an illustrative embodiment, one
or more of the first gate 114, the second gate 122, the first
isolation region 104, the second isolation region 302, or the third
isolation region 304 are formed by depositing polysilicon over the
fin feature 102 and/or the layer 106 via pyrolysis of silane under
suitable conditions. In some cases, one or more of the first gate
114, the second gate 122, the first isolation region 104, the
second isolation region 302, or the third isolation region 304 are
formed according to a particular pattern.
[0034] In a particular embodiment, doped regions of the fin feature
102 form a source region or a drain region of transistors. For
example, the region 110 and the region 112 can form a respective
source region and a respective drain region for the gate 114 and
the region 118 and the region 120 can form a respective source
region and a respective drain region for the gate 122.
[0035] FIG. 4 illustrates an orthogonal view of a semiconductor
substrate 100 including a fin feature 102 and a plurality of
additional features formed over the fin feature 102 and regions of
dielectric material formed between the additional features. In
particular, a first dielectric material region 402 is formed
between the gate 114 and the second isolation region 302, a second
dielectric material region 404 is formed between the gate 114 and
the first isolation region 104, a third dielectric material region
406 is formed between the gate 122 and the first isolation region
104, and a fourth dielectric material region 408 is formed between
the gate 122 and the third isolation region 304. The dielectric
material regions 402, 404, 406, 408 can also be referred to herein
as "spacer regions." In a particular embodiment, the dielectric
material regions 402, 404, 406, 408 include an oxide. For example,
the dielectric material regions 402, 404, 406, 408 can include
silicon dioxide. In other embodiments, the dielectric material
regions 402, 404, 406, 408 include a nitride. To illustrate, the
dielectric material regions 402, 404, 406, 408 can include silicon
nitride. In further embodiments, stressors are embedded in the
dielectric material regions 402, 404, 406, 408, such as SiGe and/or
SiC, to improve performance of the transistors formed from the
substrate 100.
[0036] FIG. 5 illustrates a top view of a mask 500 to place over a
semiconductor substrate, such as the substrate 100 of FIGS. 1-4. In
the illustrative example of FIG. 5, the mask 500 includes a pattern
having a first open portion 502, a second open portion 504, and a
third open portion 506. The open portions 502, 504, 506 correspond
with isolation regions of the substrate 100, such as the isolation
regions 104, 302, 304 of FIG. 4. In some cases, the mask 500
includes an open portion to correspond with each isolation region
of the substrate 100. In other cases, the number of open portions
of the mask 500 are different from the number of isolation regions
of the substrate 100. In some cases, the open portions 502, 504,
506 are larger than the isolation regions 104, 302, 304.
[0037] In an illustrative embodiment, the mask 500 is placed on top
of the substrate 100 to remove material of the isolation regions of
the substrate. In some cases, the material of the isolation regions
of the substrate 100 is etched away according to the pattern of the
mask 500. For example, using the mask 500 on the substrate 100 of
FIG. 4, material of the isolation regions 104, 302, 304 is removed.
The etchant is selected such that the material of the isolation
regions 104, 302, 304 can be removed, while preserving the material
of the dielectric material regions 402, 404, 406, 408. Furthermore,
due to the pattern of the mask 500, the material of the gates 114
and 122 also remains intact.
[0038] FIG. 6 illustrates an orthogonal view of a semiconductor
substrate formed after placing a mask, such as the mask 500 of FIG.
5, on a semiconductor substrate, such as the semiconductor
substrate 100 of FIG. 4, and etching the portions of the
semiconductor substrate exposed by the mask 500. In the
illustrative example of FIG. 6, the polysilicon material of the
isolation regions is removed leaving gaps 602, 604, and 606. In
addition, material of the fin feature 102 is also removed. In some
cases, additional material of the substrate 100 is also removed to
form a cavity beneath a plane formed by the base of the fin feature
102. In an embodiment, the removal of the additional material from
the substrate 100 is achieved using an isotropic etch process. In
some embodiments, using the mask 500 to remove material from the
semiconductor substrate 100 aligns features of the semiconductor
substrate and results in features of the semiconductor substrate
100 (e.g., gate regions, source regions, drain regions, etc.)
having substantially consistent dimensions, and improves the
performance of the transistors of the semiconductor substrate
100.
[0039] FIG. 7 illustrates an orthogonal view of a semiconductor
substrate 100 including isolation components 702, 704, 706 between
transistors formed on the semiconductor substrate 100. The
isolation components 702, 704, 706 are formed by filling gaps left
by removing the polysilicon of the corresponding isolation regions.
In an illustrative example, the isolation components 702, 704, 706
are formed by filling the gaps 602, 604, 606 with a dielectric
material. In some cases, the dielectric material of the isolation
components 702, 704, 706 is different from the dielectric material
of the layer 106. For example, the dielectric material of the
isolation components 702, 704, 706 can have a lower dielectric
constant than the dielectric constant of the layer 106.
[0040] In an embodiment, the isolation components 702, 704, 706 are
partially filled with a dielectric material. For example, the one
or more of the isolation components 702, 704, 706 can include a
cavity that is surrounded by an amount of the dielectric material
that comprises the dielectric regions. In some cases, the cavity is
filled with a gas, such as air. In other embodiments, the isolation
components 702, 704, 706 can be substantially filled with a
dielectric material.
[0041] After forming the isolation components 702, 704, 706, one or
more additional operations may be performed to form transistors
from the substrate 100. For example a chemical mechanical polishing
step can be performed to smooth surfaces of the transistors and the
substrate 100. Further, forming contacts for trenches can be
formed, silicides can be formed in the trenches, and metallization
can be performed.
[0042] Although the embodiments described with respect to FIGS. 2
to 7 have been performed with respect to a bulk substrate, in some
embodiments, the formation of the transistors and isolation regions
described with respect to embodiments herein can be applied to
silicon on insulator substrates. In silicon on insulator
substrates, an oxide layer can be formed between the silicon on
insulator substrate and the fin feature. The formation of fin
features on silicon on insulator substrates can be formed according
to suitable techniques.
[0043] FIG. 8 illustrates a top view of an arrangement of features
on a semiconductor substrate 800 formed using a self-aligning
double patterning process. In particular, a fin region 802 is
formed using a self-aligning double patterning process.
Additionally, a number of isolation components 804, 806, 808, 810
are formed over the fin region 802. Further, gate regions 812, 814,
816, 818, 820 are also formed over the fin region 802. In an
embodiment, the isolation components 804, 806, 808, 810 include a
dielectric material and the gate regions 812, 814, 816, 818, 820
can include polysilicon.
[0044] In a particular embodiment, the isolation components 804,
806, 808, 810 are formed by depositing polysilicon over the fin
region 802 according to a pattern and then etching away the
polysilicon and at least a portion of a dielectric layer formed
over the fin region 802. Subsequently, the gaps left in the
substrate are filled with additional dielectric material. In some
cases, at least a portion of the techniques described previously
are used to form the isolation components 804, 806, 808, 810. In an
illustrative embodiment, the mask used to etch away the polysilicon
of the isolation regions also includes openings that can be used to
perform a fin cut operation to form the gate regions 818 and 820.
Thus, a single mask can be used to form the gaps that are filled to
produce the isolation regions 804, 806, 808, 810 and to designate
the portions of the substrate 800 that are cut to form the gate
regions 818 and 820. In this way, misalignment between the
isolation regions 804, 806, 808, 810 and the gate regions 812, 814,
816, 818, 820 and the size of source regions and drain regions of
the substrate 800 can be more uniform than with conventional
processes, which improves performance of transistors formed from
the substrate 800.
[0045] FIG. 9 illustrates a flow diagram of a process 900 to form a
semiconductor substrate having isolation components disposed
between transistors formed from the semiconductor substrate having
a fin feature. At 902, the process 900 includes forming a fin
feature on a portion of a surface of a substrate including silicon.
The fin feature extends in a direction that is perpendicular to a
planar portion of the surface of the substrate. In an embodiment,
the fin feature is formed using electron beam or extreme UV
techniques. In other embodiments, a plurality of fin features is
formed using self-aligning double patterning techniques.
[0046] At 904, the process 900 includes forming a first region of
polycrystalline silicon over a first portion of the fin feature of
the substrate. In addition, at 906, the process 900 includes
forming a second region of polycrystalline silicon over a second
portion of the fin feature of the substrate. Further, at 908, the
process 900 includes forming a third region of polycrystalline
silicon over a third portion of the fin feature of the substrate.
The third region of polycrystalline silicon is disposed between the
first region of polycrystalline silicon and the second region of
polycrystalline silicon. In an embodiment, the first
polycrystalline silicon region forms a gate of a first transistor
and the third polycrystalline silicon region forms a gate of a
second transistor.
[0047] At 910, the process 900 includes forming a first spacer
region between the first region of polycrystalline silicon and the
third region of polycrystalline silicon and a second spacer region
between the second region of polycrystalline silicon and the third
region of polycrystalline silicon. The first spacer region and the
second spacer region include a first dielectric material. In some
embodiments, stressor materials are embedded in the semiconductor
substrate to improve the performance of the transistors after
forming the first spacer region and the second spacer region. In
some cases, the stressors include SiGe, SiC, or both into the
substrate.
[0048] At 912, the process 900 includes removing at least the third
region of polycrystalline silicon and at least a portion of the fin
feature formed under the third region of polycrystalline silicon to
form a gap between the first region of polycrystalline silicon and
the second region of polycrystalline silicon. In an embodiment, the
gap is formed by placing a mask over the substrate, where the mask
includes an opening corresponding to a location of the third region
of polycrystalline silicon. In some cases, the third region of
polycrystalline silicon and at least a portion of fin feature are
removed via etching while the mask is placed over the substrate.
Additionally, a portion of the substrate below the fin feature can
also be etched such that the gap extends below a plane formed by a
planar surface of the substrate.
[0049] At 914, the process 900 includes disposing a second
dielectric material into the gap between the first region of
polycrystalline silicon and the second region of polycrystalline
silicon to form an isolation region. In an embodiment, the
isolation region has a width that is less than 30 nm. Additionally,
in some cases, the first dielectric material is different from the
second dielectric material. In particular, the first dielectric
material has a dielectric constant with a value that is greater
than the dielectric constant of the second dielectric material.
[0050] Further aspects of the present invention also relate to one
or more of the following clauses.
[0051] Clause 1. An apparatus comprising: a substrate including a
surface, wherein the surface includes a planar portion, and a fin
feature extending in a direction substantially perpendicular to the
planar portion and having a thickness less than a thickness of the
substrate; a first transistor, wherein the first transistor
includes a first gate region formed over the fin feature, a first
source region formed from a body of the fin feature, and a first
drain region formed from the body of the fin feature; a second
transistor, wherein the second transistor includes a second gate
region formed over the fin feature, a second source region formed
from the body of the fin feature, and a second drain region formed
from the body of the fin feature; and an isolation component formed
between the first transistor and the second transistor, wherein the
isolation component has a width less than 30 nm.
[0052] Clause 2. The apparatus of clause 1, wherein: the fin
feature has a substantially rectangular shape; the fin feature
includes four sides extending in the direction substantially
perpendicular to the planar portion; and the fin feature includes
an additional side substantially parallel to the planar
portion.
[0053] Clause 3. The apparatus of clause 1, wherein: the first
drain region of the first transistor is adjacent to the isolation
component; and the second source region of the second transistor is
adjacent to the isolation component.
[0054] Clause 4. The apparatus of clause 1, wherein the width of
the isolation component is in a range of 9 nm to 18 nm.
[0055] Clause 5. The apparatus of clause 1, wherein: a layer is
disposed on the planar portion of the surface of the substrate; the
layer includes a first dielectric material; and the isolation
component includes a second dielectric material.
[0056] Clause 6. An apparatus comprising: a substrate including a
surface, wherein the surface includes a planar portion, and a fin
feature extending in a direction substantially perpendicular to the
planar portion and having a thickness less than a thickness of the
substrate; a layer formed over the planar portion of the surface of
the substrate, wherein the layer includes a first dielectric
material; a first transistor, wherein the first transistor includes
a first gate region disposed on at least two sides of the fin
feature, a first source region formed from a body of the fin
feature, and a first drain region formed from the body of the fin
feature; a second transistor, wherein the second transistor
includes a second gate region formed on the at least two sides of
the fin feature, a second source region formed from the body of the
fin feature, and a second drain region formed from the body of the
fin feature; and an isolation component formed between the first
transistor and the second transistor, wherein the isolation
component includes a second dielectric material that is different
from the first dielectric material.
[0057] Clause 7. The apparatus of clause 6, wherein the first
dielectric material has a dielectric constant with a value greater
than a value of the dielectric constant of the second material.
[0058] Clause 8. The apparatus of clause 6, wherein the first
dielectric material includes one of SiO.sub.2 or SiN.
[0059] Clause 9. The apparatus of clause 6, wherein the isolation
component includes a third dielectric material that is different
from (i) the first dielectric material and (ii) the second
dielectric material.
[0060] Clause 10. The apparatus of clause 9, wherein: the isolation
component includes a cavity filled with the third dielectric
material; and the cavity is encased by at least the second
dielectric material.
[0061] Clause 11. The apparatus of clause 6, wherein the isolation
component has a width in a range of 6 nm to 29 nm.
[0062] Clause 12. The apparatus of clause 6, wherein the substrate
includes an additional fin feature, and wherein the substrate
further includes: a third transistor, wherein the third transistor
includes a third gate region disposed on at least two sides of the
additional fin feature, a third source region formed from a body of
the additional fin feature, and a third drain region formed from
the body of the fin feature; a fourth transistor, wherein the
fourth transistor includes a fourth gate region disposed on the at
least two sides of the additional fin feature, a fourth source
region formed from the body of the additional fin feature, and a
fourth drain region formed from the body of the additional fin
feature; and an additional isolation component formed between the
third transistor and the fourth transistor.
[0063] Clause 13. A method comprising: forming a fin feature on a
portion of a surface of a substrate including silicon, wherein the
fin feature extends in a direction perpendicular to a planar
portion of the surface of the substrate; forming a first region of
polycrystalline silicon over a first portion of the fin feature of
the substrate; forming a second region of polycrystalline silicon
over a second portion of the fin feature of the substrate; forming
a third region of polycrystalline silicon over a third portion of
the fin feature of the substrate, wherein the third region of
polycrystalline silicon is disposed between (i) the first region of
polycrystalline silicon and (ii) the second region of
polycrystalline silicon; forming a first spacer region between (i)
the first region of polycrystalline silicon and (ii) the third
region of polycrystalline silicon, wherein the first spacer region
includes a first dielectric material; forming a second spacer
region between (i) the second region of polycrystalline silicon and
(ii) the third region of polycrystalline silicon, wherein the
second spacer region includes the first dielectric material;
removing at least (i) the third region of polycrystalline silicon
and (ii) at least a portion of the fin feature formed under the
third region of polycrystalline silicon to thereby form a gap
between (i) the first region of polycrystalline silicon and (ii)
the second region of polycrystalline silicon; and disposing a
second dielectric material into the gap between (i) the first
region of polycrystalline silicon and (ii) the second region of
polycrystalline silicon to form an isolation component.
[0064] Clause 14. The method of clause 13, further comprising:
placing a mask over the substrate, wherein the mask includes an
opening corresponding to a location of the third region of
polycrystalline silicon; and etching (i) the third region of
polycrystalline silicon and (ii) the at least a portion of fin
feature according to a pattern of the mask.
[0065] Clause 15. The method of clause 14, further comprising
etching a portion of the substrate such that the gap extends below
a surface of the planar portion of the surface of the
substrate.
[0066] Clause 16. The method of clause 13, further comprising:
forming an additional fin feature on the substrate, wherein both
(i) the fin feature and (ii) the additional fin feature are formed
using a self-aligning double patterning process.
[0067] Clause 17. The method of clause 13, wherein a width of the
isolation component is less than 30 nm.
[0068] Clause 18. The method of clause 13, wherein the first
dielectric material is different from the second dielectric
material.
[0069] Clause 19. The method of clause 13, wherein: the first
polycrystalline silicon region forms a gate of a first transistor;
and the third polycrystalline silicon region forms a gate of a
second transistor.
[0070] Clause 20. The method of clause 13, further comprising:
after forming the first spacer region and the second spacer region,
embedding stressor materials into the substrate, wherein the
stressor materials include one or both of SiGe and/or SiC.
[0071] Note that the description above incorporates use of the
phrases "in an embodiment," or "in various embodiments," or the
like, which may each refer to one or more of the same or different
embodiments. Furthermore, the terms "comprising," "including,"
"having," and the like, as used with respect to embodiments of the
present disclosure, are synonymous.
[0072] Although certain embodiments have been illustrated and
described herein, a wide variety of alternate and/or equivalent
embodiments or implementations calculated to achieve the same
purposes may be substituted for the embodiments illustrated and
described without departing from the scope of the present
disclosure. This application is intended to cover any adaptations
or variations of the embodiments discussed herein. Therefore, it is
manifestly intended that embodiments in accordance with the present
disclosure be limited only by the claims and the equivalents
thereof.
* * * * *