U.S. patent application number 14/040094 was filed with the patent office on 2014-04-03 for arc suppression control and methods therefor.
This patent application is currently assigned to Arc Suppression Technologies. The applicant listed for this patent is Arc Suppression Technologies. Invention is credited to Reinhold Henke.
Application Number | 20140091060 14/040094 |
Document ID | / |
Family ID | 49304434 |
Filed Date | 2014-04-03 |
United States Patent
Application |
20140091060 |
Kind Code |
A1 |
Henke; Reinhold |
April 3, 2014 |
ARC SUPPRESSION CONTROL AND METHODS THEREFOR
Abstract
A device, circuit, system, and method for arc suppression is
described. A processor, including an input terminal and an output
terminal, is configured to output pulses on the output terminal
based on an indication at the input terminal of a separation of a
pair of electrical contacts. A contact bypass circuit, coupled to
the output terminal and in parallel with the pair of electrical
contacts, is configured to provide an electrical bypass between the
pair of electrical contacts based on the plurality of pulses as
generated by the processor.
Inventors: |
Henke; Reinhold; (Plymouth,
MN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Arc Suppression Technologies |
Bloomington |
MN |
US |
|
|
Assignee: |
Arc Suppression
Technologies
Bloomington
MN
|
Family ID: |
49304434 |
Appl. No.: |
14/040094 |
Filed: |
September 27, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61707373 |
Sep 28, 2012 |
|
|
|
61788786 |
Mar 15, 2013 |
|
|
|
Current U.S.
Class: |
218/8 |
Current CPC
Class: |
H01H 9/54 20130101; H01H
9/542 20130101; G01R 31/50 20200101; H01H 2071/048 20130101; H01H
33/04 20130101; H01H 33/121 20130101 |
Class at
Publication: |
218/8 |
International
Class: |
H01H 33/12 20060101
H01H033/12 |
Claims
1. An electrical circuit, comprising: a processor; and a contact
bypass element, coupled to the processor and in parallel with a
contact, configured to operate in a multi-pulse mode, wherein the
current bypass element triggers with a series of timed pulses
sufficiently long to extinguish an arc over the contact.
Description
PRIORITY
[0001] This application claims priority under 35 U.S.C. 119(e) to
U.S. Provisional Application No. 61/707,373, "ARC SUPPRESSOR,"
filed Sep. 28, 2012, which is incorporated herein in its
entirety.
[0002] This application claims priority under 35 U.S.C. 119(e) to
U.S. Provisional Application No. 61/788,786, "ARC SUPPRESSOR,"
filed Mar. 15, 2013, which is incorporated herein in its
entirety.
TECHNICAL FIELD
[0003] The present application relates generally to electrical
current contact arc suppression.
BACKGROUND
[0004] Electrical current contact arcing may have a deleterious
effects on electrical contact surfaces, such as of relays and
certain switches. Arcing may degrade and ultimately destroy the
contact surface over time and may result in premature component
failure, lower quality performance, and relatively frequent
preventative maintenance needs. Additionally, arcing in relays,
switches, and the like may result in the generation of
electromagnetic interference (EMI) emissions. Electrical current
contact arcing may occur both in alternating current (AC) power and
in direct current (DC) power across the fields of consumer,
commercial, industrial, automotive, and military applications.
Because of its prevalence, there have literally been hundreds of
specific means developed to address the issue of electrical current
contact arcing.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Some embodiments are illustrated by way of example and not
limitation in the figures of the accompanying drawings.
[0006] FIG. 1 is a diagram of a system including an arc suppressor,
in an example embodiment.
[0007] FIG. 2 is a block diagram of an example of an arc
suppressor, in an example embodiment.
[0008] FIGS. 3A-D depicts schematic diagrams illustrating example
embodiments of arc suppression processors.
[0009] FIGS. 4A-4F depicts schematic diagrams illustrating example
embodiments of contact bypass circuit.
[0010] FIGS. 5A-5C depict waveform diagrams illustrating example
embodiments of arc suppressor signal timing.
[0011] FIG. 6 depicts waveform diagrams illustrating an example
embodiment of arc suppressor operating modes.
[0012] FIG. 7 is a flowchart for suppressing an arc, in an example
embodiment.
DETAILED DESCRIPTION
[0013] Certain examples of arc suppressors, to whatever extent they
suppress or purport to suppress arcs, have utilized passive
components to suppress the arc. Thus, for instance, RC snubbers,
which have been utilized substantially ineffectively in the actual
suppression of an arc, may merely include passive components, such
as resistors and capacitors, that are not actively engaged in the
suppression of an arc. Conversely, certain arc suppressors have
utilized active components that are affirmatively turned on or
engaged to suppress the arc. However, such arc suppressors may
merely turn on for some predetermined period of time without
respect to an actual amount of time or activation sequence that may
be utilized to suppress the arc. It may, in certain circumstances,
be preferable to minimize an amount of time actually engaged in the
suppression of an arc.
[0014] A processor and contact bypass circuit have been developed
that may be utilized in the suppression of an arc over a contact.
The processor may receive an indication of a separation of the
contact, upon which the processor may output a plurality of pulses
to the contact bypass circuit. The contact bypass circuit may
provide a bypass over the contact based on the pulses as generated
by the processor. In various examples, the pulses may suppress the
arc without requiring the contact bypass circuit to be open
constantly during an arc duration, over which the arc may tend to
form. Limiting a duration of engaging the contact bypass circuit
may reduce wear on the contact bypass circuit while also, in
various examples, reducing the power that may be utilized to
operate the contact bypass circuit in particular and the arc
suppressor in general.
[0015] FIG. 1 is a diagram of a system 100 including an arc
suppressor 102 as disclosed herein. While the arc suppressor 102
will be discussed herein with respect to electrical contacts, it is
to be recognized and understood that the arc suppressor 102 may be
equally applicable to any of a variety of components and
circumstances in which an arc may tend to form, such as physically
fixed electrodes and the like. The discussion of the arc suppressor
102 with respect to electrical contacts does not limit the
applicable scope of the arc suppressor 102 only to electrical
contacts.
[0016] The system 100 includes a power source 104, a contact 106,
and a load 108. The power source 104 may be an AC power source or a
DC power source. Sources for AC power may include generators,
alternators, transformers, and the like. The source for AC power
may be sinusoidal, non-sinusoidal, or phase controlled. An AC power
source may be utilized on a power grid (e.g., utility power, power
stations, transmission lines, etc.) as well as off the grid, such
as for rail power. Sources for DC power may include various types
of power storage, such as batteries, solar cells, fuel cells,
capacitor banks and thermopiles, dynamos, and power supplies. DC
power types may include direct, pulsating, variable, and
alternating (which may include superimposed AC, full wave
rectification and half wave rectification). DC power may be
associated with self-propelled applications, i.e., articles that
drive, fly, swim, crawl, dive, tunnel, dig, cut, etc.
[0017] The contact 106 may be a switch, relay, contactor, or other
contact. The contact 106 includes a pair of contacts, such as
electrodes, as illustrated herein. As noted above, the contact 106
may alternative be a static electrode or electrodes or other
component over which an arc may tend to form. The load 108 may be a
general purpose loads, such as consumer lighting, computers, data
transfer switches, etc. The load 108 may be a resistive load, such
as a resistor, heater, electroplating device, etc. The load 108 may
be a capacitive load, such as a capacitor, capacitor bank, power
supply, etc. The load 108 may be an inductive load, such as an
inductor, transformer, solenoid, etc. The load 108 may be a motor
load, such as a motor, compressor, fan, etc. The load 108 may be a
tungsten load, such as a tungsten lamp, infrared heater, industrial
light, etc. The load 108 may be a ballast load, such as a
fluorescent light, neon light, light emitting diode (LED), etc. The
load 108 may be a pilot duty load, such as a traffic light, signal
beacon, control circuit, etc.
[0018] In the illustrated example, connection between the power
source 104 and the contact 106 is via a non-switched contact
current node 110. Connection between the contact 106 and the arc
suppressor 102 is optionally via a wire connection 112 affixed to a
wire terminal 114 of the arc suppressor 102. Connection between the
contact 106 and the load 108 is optionally via a switched contact
current node 116. A second connection between the contact 106 and
the arc suppressor 102 is optionally via a wire connection 118
affixed to a wire terminal 120 of the arc suppressor 102.
Connection between the load 108 and the power source 104 is
optionally via a return wire connection 122. Thus, the arc
suppressor 102 is connected directly in parallel with the contact
106 to be protected.
[0019] The arc suppressor 102 may optionally be coupled to an
external power supply via a power supply connection 124. The arc
suppressor 102 may further optionally be coupled to an external
status monitor via a status monitor connection 126. It is
emphasized that, as with various components of the system 100,
while the power supply connection 124 and status monitor connection
126 are illustrated, such components are optional and may not be
included in various examples of the system 100.
Arc Suppressor Block Diagram
[0020] FIG. 2 is a block diagram of an example of the arc
suppressor 102. The arc suppressor 102 optionally includes some or
all of a contact separation detector 200, an indicator 202, a
processor 204, a contact bypass circuit 206, a component protection
circuit 208, a protection circuit 210, a connection termination
212, a power connection 214, and a power supply 216. While the
contact separation detector 200 disclosed herein may be described
with respect to contacts, it is to be understood that the contact
separation detector 200 may be applicable to detecting an arc
generally without respect to contact separation. Thus, in examples
in which the arc suppressor 102 is utilized with respect to
components other than contacts, the contact separation detector 200
may be understood as an arc detector or arc condition detector.
[0021] The block diagram of the arc suppressor 102 includes
elements of the arc suppressor 102 generically and without respect
to specific voltage, current or power ratings. In various specific
implementations, the various blocks may be scaled according to
component ratings such as, but not limited to, resistance,
capacitance, inductance, voltage, current, power, tolerance, and
transformation ratio, to construct specific arc suppressors.
[0022] The contact separation detector 200 may detect a condition
indicative of a separation of the contact 106, such as a change in
voltage and/or current, as disclosed herein. The condition
indicative of the separation of the contacts 106 may more generally
be a condition indicative of an arc or a formation of an arc, and
circumstances in which the contact separation detector 200 is
utilized without respect to contacts may produce a detection and an
indication of an arc or a condition indicative of an arc. The
contact separation detector 200 may, in various examples, output an
analog signal that, at relatively low values, indicates a
condition, such as a contact separation state, that may not
necessarily result in the bypass of the contacts 106. The contact
separation detector 200 may, in various examples, output an analog
signal that, at relatively higher values, indicates the formation
of an arc, as disclosed herein, that may result in bypassing the
contacts 106. The values of those indications may be dependent on
the circumstances in which the contact separation detector 200 is
applied and may be utilized by one or more of the indicator 202,
processor 204, and bypass 206 to variously indicate the separations
state of the contact 106, indicate an arc condition over the
contact 106, and/or bypass the contact 106, as appropriate.
[0023] The contact separation detector 200 may output an indication
of the contact separation. As illustrated, the indicator is
provided to the processor 204. However, in various examples, the
indicator may be provided, alternatively or additionally, to the
indicator 202 and/or to the contact bypass circuit 206 without
respect to the processor 204. On the basis of receiving the
indication, the processor 204 may output a trigger signal to engage
the electrical bypass of the contact bypass circuit 206 over the
contact 106. Alternatively, the contact bypass circuit 206 may
receive the indication directly from the contact separation
detector 200 and engage the bypass over the contact 106. By
bypassing the contact 106 during at least a portion of the time
during which the arc may form or tend to form over the contact 106,
the energy over the contact 106 may be reduced to levels that may
not produce an arc until the conditions within the contact 106 that
may cause an arc have passed or otherwise subsided.
[0024] The component protection circuit 208 and the protection
circuit 210 may provide protection for the various components
within the arc suppressor 102. In various examples, the component
protection circuit 208 includes one or more of a varistor, a
transient voltage suppressor, and back-to-back Zener diodes coupled
in parallel with one or more of the contact separation detector
200, the processor 204, and the contact bypass circuit 206. In
various examples, the protection circuit 210 includes one or more
of a fuse, a resistor, a circuit breaker, and a fusible link
coupled in series with one or more of the contact separation
detector 200, the processor 204, the contact bypass circuit 206,
and the component protection circuit 208.
[0025] The connection termination 212 may be a component of the
contact 106 itself and may, in various examples, not be considered
a component of the arc suppressor 102. In various alternative
examples, the arc suppressor 102 may be considered an integral
component of the contact 106. The contact termination 212 may be
one or more of wire terminals, a pluggable connector, a card-edge
connector, and flying leads. The power connection 214 and power
supply 216 may optionally supply power to the arc suppressor 102 as
a whole, such as to the processor 204. The power connection 214 may
be any one or more of wire terminals, a pluggable connector, a
card-edge connector, flying leads, and a power connector. The power
supply 216 may be any one or more of a battery, a capacitor, one or
more voltage regulators, and one or more power regulators.
[0026] The arc suppressor 102 may be implemented according to any
of a variety of embodiments of some or all of the blocks 200, 202,
204, 206, 208, 210, 212, 214, 216. While specific embodiments are
presented in detail herein, it is to be understood that alternative
embodiments may be implemented. The particular embodiments may be
configured to provide desired performance characteristics, such as
for the circumstances in which the arc suppressor 102 is used. The
particular embodiments disclosed herein are for the purposes of
example and illustration and are not limiting on the
implementations disclosed herein.
Arc Suppression Processor
[0027] FIGS. 3A-3D depicts schematic diagrams illustrating examples
of arc suppression processors. The processors may be utilized as
the processor 204, as disclosed herein. It is to be understood
that, for the purposes of this disclosure, the term "processor" may
include the electronic devices disclosed herein, whether or not
conventionally described as a "processor", and equivalent devices
that may provide the same or similar output as the processors
disclosed herein. The processors described herein may be actively
powered from a power source. Arc suppressors 102 that do not
include a processor as disclosed herein may not necessarily utilize
a power source, as disclosed herein.
[0028] FIG. 3A depicts a schematic diagram illustrating an example
of an arc suppression processor 300 including an analog timer 302.
The analog timer 302 may be configured with an input line 304 to
receive, from the contact separation detector 200, an indication of
contact separation of the contact 106. On the basis of the
indication of contact separation, the analog timer 302 may output a
signal on an output line 306 that may be utilized by the contact
bypass circuit 206 to open a bypass over the contact 106 to
suppress an arc in the contact 106.
[0029] In an example, the analog timer 302 includes a threshold
input terminal 308 and a trigger input terminal 310 that may be
configured to set an overall sensitivity to the indication of
contact separation. As illustrated, a resistor 312 and capacitor
314 may be selected to set the threshold and trigger sensitivity
based on power 316 and ground 318. The threshold and trigger may be
selected based on the particular circumstances in which the arc
suppressor 102 is being utilized, e.g., the threshold and trigger
may be set relatively high for high voltage applications and
relatively low for low voltage applications. In an example, the
resistor 312 is a ten (10) kiloOhm resistor and the capacitor 314
is a 0.01 microFarad capacitor where power 316 is nine (9) Volts.
The output provided by the analog timer 302 will be discussed in
detail herein.
[0030] FIG. 3B depicts a schematic diagram illustrating an example
of an arc suppression processor 320 including a microcontroller
322. The microcontroller 322 may be configured with an input line
324 to receive an indication, from the contact separation detector
200, of contact separation of the contact 106. On the basis of the
indication of contact separation, the processor 320 may output a
signal on an output line 326 that may be utilized by the contact
bypass circuit 206 to open a bypass over the contact 106 to
suppress an arc in the contact 106.
[0031] As illustrated, the microcontroller 322 includes two output
terminals 328, 330. The first output terminal 328 is coupled to a
gate 332 of a transistor 334 which, when enabled by a signal from
the microcontroller 322, opens the transistor 334 to provide the
signal on the output line 326 at a voltage 336 different than the
power voltage 316 for the microcontroller 322. The second output
terminal 330 may provide an output signal from the microcontroller
322 for another purpose, such as for generating a signal from the
indicator 202, as disclosed herein. It is to be recognized and
understood that, in various examples, the processor 320 does not
necessarily include two output terminals 328, 330 where a second
output is not needed. Further, the transistor 334 may not be needed
where the voltage of the output signal from the microcontroller 322
does not need to be changed for use, e.g., by the contact bypass
circuit 206.
[0032] FIG. 3C depicts a schematic diagram illustrating an example
of an arc suppression processor 338 including a programmable system
on a chip 340. As illustrated, the programmable system on a chip
340 has differential input terminals 342, 344, though it is to be
understood that, in various examples, the differential input
terminals 342, 344 may be replaced or supplemented with one or more
non-differential terminals. The input terminals 342, 344 may
receive an input from the contact separation detector 200.
[0033] As illustrated, the system on a chip 340 includes two output
terminals 346, 348. The first output terminal 346 is coupled to a
gate 350 of a transistor 352 which, when enabled by a signal from
the system on a chip 340, opens the transistor 352 to provide the
signal on the output line 354 at a voltage 356 different than the
power voltage 316 for the system on a chip 340. The second output
terminal 348 may provide an output signal from the system on a chip
340 for another purpose, such as for generating a signal from the
indicator 202, as disclosed herein. It is to be recognized and
understood that, in various examples, the processor 320 does not
necessarily include two output terminals 346, 348 where a second
output is not needed. Further, the transistor 352 may not be needed
where the voltage of the output signal from the system on a chip
340 does not need to be changed for use, e.g., by the contact
bypass circuit 206.
[0034] FIG. 3D depicts a schematic diagram illustrating an example
of an arc suppression processor 358 including a digital timer 360.
The digital timer 360 may be configured with an input line 362 to
receive, from the contact separation detector 200, an indication of
contact separation of the contact 106. On the basis of the
indication of contact separation, the digital timer 360 may output
a signal on an output line 364 that may be utilized by the contact
bypass circuit 206 to open a bypass over the contact 106 to
suppress an arc in the contact 106.
Contact Bypass Circuit
[0035] FIGS. 4A-4F depicts schematic diagrams illustrating examples
of contact bypass circuits. Any one or more of the contact bypass
circuits disclosed herein may be utilized as the contact bypass
circuit 206.
[0036] FIG. 4A depicts a schematic diagram illustrating an example
of a contact bypass circuit 400 including a bipolar junction
transistor (BJT) 402 coupled to a bridge rectifier 404. The bridge
rectifier 404 is coupled between terminals 406, 408 which are
coupled over the contact 106. Upon receiving a trigger signal, such
as from the processor 204, the BJT 402 engages the bridge rectifier
404, providing a bypass between the terminals 406, 408 and over the
contact 106. Upon the signal ending, the BJT 402 ceases engaging
the BJT 402 and the bridge rectifier 404 ceases providing the
bypass.
[0037] FIG. 4B depicts a schematic diagram illustrating an example
of a contact bypass circuit 410 including a field effect transistor
(FET) 412 coupled to a bridge rectifier 404. The bridge rectifier
404 is coupled between terminals 406, 408 which are coupled over
the contact 106. Upon receiving a trigger signal, such as from the
processor 204, the FET 412 engages the bridge rectifier 404,
providing a bypass between the terminals 406, 408 and over the
contact 106. Upon the signal ending, the FET 412 ceases engaging
the BJT 402 and the bridge rectifier 404 ceases providing the
bypass.
[0038] FIG. 4C depicts a schematic diagram illustrating an example
of a contact bypass circuit 414 including an insulated gate bipolar
transistor (IGBT) 416 coupled to a bridge rectifier 404. The bridge
rectifier 404 is coupled between terminals 406, 408 which are
coupled over the contact 106. Upon receiving a trigger signal, such
as from the processor 204, the IGBT 416 engages the bridge
rectifier 404, providing a bypass between the terminals 406, 408
and over the contact 106. Upon the signal ending, the IGBT 416
ceases engaging the BJT 402 and the bridge rectifier 404 ceases
providing the bypass. FIG. 4D depicts a schematic diagram
illustrating an example of a contact bypass circuit 418 including
multiple insulated gate bipolar transistors (IGBT's) 420, 422, 424
coupled to a bridge rectifier 404. The bridge rectifier 404 is
coupled between terminals 406, 408 which are coupled over the
contact 106. Upon receiving a trigger signal, such as from the
processor 204, the IGBTs 420, 422, 424 engage the bridge rectifier
404, providing a bypass between the terminals 406, 408 and over the
contact 106. Upon the signal ending, the IGBT 416 ceases engaging
the BJT 402 and the bridge rectifier 404 ceases providing the
bypass. Including multiple IGBTs may provide greater robustness in
high voltage and high power systems.
[0039] FIG. 4E depicts a schematic diagram illustrating an example
of a contact bypass circuit 426 including a silicon controlled
rectifier (SCR) 428 coupled to a bridge rectifier 404. The bridge
rectifier 404 is coupled between terminals 406, 408 which are
coupled over the contact 106. Upon receiving a trigger signal, such
as from the processor 204, the SCR 428 engages the bridge rectifier
404, providing a bypass between the terminals 406, 408 and over the
contact 106. Upon the signal ending, the SCR 428 ceases engaging
the BJT 402 and the bridge rectifier 404 ceases providing the
bypass.
[0040] FIG. 4F depicts a schematic diagram illustrating an example
of a contact bypass circuit 430 including a triac 432. Upon
receiving a trigger signal, such as from the processor 204, the
triac 432 provides a bypass between the terminals 406, 408 and over
the contact 106. Upon the signal ending, the triac 432 ceases
providing the bypass.
Signal Timing
[0041] FIGS. 5A-5C depict waveform diagrams illustrating examples
of arc suppressor signal timing. In various examples, the signals
are as received by a contact bypass circuit, such as the contact
bypass circuit 206, and may regulate the suppression of arcs within
a contact, such as the contact 106.
[0042] FIG. 5A depicts timing diagram 500 illustrating an example
of a contact cycle of timing of a trigger signal to the contact
bypass circuit 206 of the arc suppressor 106. The timing diagram
includes a time axis 502 and a variable amplitude axis 504. The
time axis 502 includes sections corresponding to an open state 506,
a make state 508, a closed state 510, and a break state 512. It is
noted that the time axis 502 has been interrupted during the closed
state 510.
[0043] A contact current waveform 514 shows current through the
contact 106. A contact voltage waveform 516 shows a voltage over
the contact 106. The trigger single waveform 518 shows trigger
signals as received by the contact bypass circuit 206.
[0044] In an example, in the break state 512, the flow of current
may be interrupted and the contact bypass circuit 206 receives
bypass pulses coinciding with the rising edge of the contact
voltage, indicating that the contact 106 is opening during the
break state 512. In turn, the load current may be re-routed through
the arc suppressor 102, thus relieving or substantially relieving
the contact 106 of current carrying duty and in doing so preventing
or substantially preventing the contact 106 from arcing
significantly, in effect suppressing the resulting contact arc.
[0045] FIG. 5B depicts a timing diagram 520 illustrating an example
of a single trigger signal pulse 522 as receivable by the contact
bypass circuit 206. The trigger signal pulse 522 includes a fast
rise time on the leading edge 524 of the trigger signal pulse 522
followed by a pulse duration 526 at maximum voltage, followed by a
slower rise time on the trailing edge 528.
[0046] FIG. 5C depicts a timing diagram 530 illustrating an example
of an arc suppression voltage and current timing of the arc
suppressor 102. The time axis 532 has been magnified in comparison
to the time axis 502. The contact voltage waveform 534 includes a
relatively extremely fast risetime, in this example on the order of
pico- to nanoseconds. In various examples, voltage slew rates may
be of approximately eight (8) kiloVolts or greater. The contact
separation detector 200 may be configured to detect such risetimes.
In an example, within a few pico- to nanoseconds of the contact 106
breaking, the voltage across the contact 106 may reach the arc
voltage which is between, for instance, nine (9) Volts and fifteen
(15) Volts, depending on the specific contact material.
[0047] In this example, when the arc voltage is reached, the
current through the contact 106 multiplied with the arc voltage may
produce sufficient energy for a spark to ignite plasma in the
contact gap 808 and develop into an arc. The arc may burn, for
instance, for about five (5) microseconds before the arc suppressor
102 generates the trigger signal pulse for the contact bypass
circuit 206 and subsequently extinguishes the arc by means of
bypassing the contact current through the arc suppressor.
[0048] An arclet 536 of, for instance, five (5) microseconds in
duration may be the result of the arc suppression. Arc suppression
duration can, in various examples, be around five hundred (500)
microseconds in duration, such as in order to give the contact
enough time to travel out of the ignition space. The trigger signal
pulse 522 may be risetime controlled at the transition to the open
state, such as to reduce a likelihood of the arc suppressor 102
generating the trigger signal pulse based on a spurious signal.
After the trigger signal pulse 522 is over the contact gap 808 may
still widen and the contact 106 may soon thereafter enter the open
state.
[0049] FIG. 6 depicts waveform diagrams illustrating an example of
arc suppressor operating modes. In various examples, there are five
distinctly different two-port arc suppressor-operating modes, such
as may be generated by the processor 204 as a trigger signal.
Alternatively, various ones of the operating modes may be generated
as the indication by the contact separation detector 200. The shape
and type of trigger signal pulses may determine a specific
operational nature of the arc suppressor 102.
[0050] In various examples, as illustrated in a first waveform 600,
in "crowbar" mode the current bypass circuit 206 receives a trigger
pulse that triggers and holds for the remaining duration of a half
cycle of an AC current through the contact 106. When the AC current
waveform is near the current zero crossing, the arc may tend to
extinguish, allowing the contact bypass circuit to be opened and
current to flow through the contact 106.
[0051] In various examples, as illustrated in a second waveform
602, in "linear" mode the current bypass circuit 206 receives a
trigger pulse with a single bypass ramp starting at low resistance
and passing through a linear region of an element, such as a BJT,
FET, IBGT, and the like, of the current bypass circuit 206 long
enough to extinguish a contact arc.
[0052] In various examples, as illustrated in a third waveform 604,
in "oscillating" mode the current bypass circuit 206 receives
trigger pulses with a burst of low resistance sufficiently long
enough to extinguish the contact arc.
[0053] In various examples, as illustrated in a fourth waveform
606, in "multi-pulse" mode the current bypass circuit 206 receives
a series of trigger pulses with low resistance sufficiently long
enough to extinguish the contact arc.
[0054] In various examples, as illustrated in a fifth waveform 608,
in "single-pulse" mode the current bypass circuit 206 receives a
trigger pulse with a low resistance bypass pulse of sufficiently
short duration to extinguish the contact arc.
[0055] In various examples, the waveforms 600, 602, 604 may have a
total duration 610 that is equal or substantially equal to the
duration 526 of the arc condition as disclosed above with respect
to FIG. 5. Thus, in the example of the waveforms 604, each
individual oscillation may occur over the cumulative duration
604.
[0056] In various examples, the multi-pulse waveform 606 and the
single-pulse waveform 608 may have durations 612, 614 less than the
duration 526. In various examples, the durations 612, 614 may be
selected such that the waveforms 606, 608 may extinguish the arc
without necessarily requiring a duration as long as the duration
526 and/or the duration 610. In the illustrated example, three (3)
pulses over a duration 612 approximately one-half the length of the
duration 526 may be sufficient for the multi-pulse waveform 606 to
extinguish the arc without a secondary arc re-igniting. In the
illustrated examples, the single-pulse waveform 608 may utilize a
duration 614 of approximately one-third of the duration 526 to
extinguish the arc. It is noted and emphasized that the example
durations 612, 614 are non-limiting and may be dependent, at least
in part, on the particular circumstances in which they are used. In
various examples, the durations 612, 614 are any duration less than
or approximately equal to the duration 526.
[0057] In an alternative example, the multi-pulse waveform 606 may
be adaptable to the formation of secondary arc re-ignition. The
multi-pulse waveform 606 may perform one or more predetermined
individual pulses 616 followed by additional individual pulses 616
on detecting an additional contact separation and/or a re-ignition
of the arc, as appropriate. In an example, two (2) predetermined
pulses 616 are delivered upon contact separation and/or arc
ignition followed by individual additional pulses 616 upon the
detection of additional contact separation and/or arc ignition.
[0058] In various examples, the individual pulses 616 of the
multi-pulse waveform 606 may be of the same or substantially the
same morphology. Each pulse may be separated by an equal amount of
time. As illustrated, the pulses 616 may be separated by varying
amounts of time, such as an amount of time that approximately
doubles with each successive pulse 616.
Flowchart
[0059] FIG. 7 is a flowchart for suppressing an arc. The flowchart
may be applicable to the arc suppressor 102 or to any other
suitable circuit or system.
[0060] At 700, a plurality of pulses are output on an output
terminal of a processor based on an indication at the input
terminal of a separation of a pair of electrical contacts. In an
example, the plurality of pulses is output for each indication
received by the processor. In an example, the processor is
configured to output the plurality of pulses according to a
predetermined cumulative duration.
[0061] In an example, an arc duration is based on at least one of
an amount of charge carriers between the pair of contacts being
greater than a level at which an arc between the contacts is
maintained and an arc being thermodynamically supported between the
pair of contacts, and the predetermined cumulative duration of the
plurality of pulses is less than the arc duration. In an example,
the predetermined cumulative duration is based on a duration
between a rising edge of a first one of the plurality of pulses and
a falling edge of a last one of the plurality of pulses. In an
example, a duty cycle of the plurality of pulses varies during the
predetermined cumulative duration.
[0062] In an example, the processor is configured to output the
plurality of pulses according to a predetermined number of pulses.
In an example, each one of the plurality of pulses has a
substantially equal pulse duration from a rising edge to a falling
each of each one of the plurality of pulses. In an example, the
processor is at least one of an analog timer, a digital time, a
microcontroller, and a system on a chip.
[0063] At 702, an electrical bypass is provided with a contact
bypass circuit between the pair of electrical contacts based on the
plurality of pulses as generated by the processor. In an example,
the bypass circuit is configured to provide the electrical bypass a
number of times corresponding to a number of pulses of the
plurality of pulses.
Additional Examples
[0064] The description of the various embodiments is merely
exemplary in nature and, thus, variations that do not depart from
the gist of the examples and detailed description herein are
intended to be within the scope of the present disclosure. Such
variations are not to be regarded as a departure from the spirit
and scope of the present disclosure.
[0065] In Example 1, an electrical circuit or system includes a
processor, including an input terminal and an output terminal,
configured to output a plurality of pulses on the output terminal
based on an indication at the input terminal of a separation of a
pair of electrical contacts and a contact bypass circuit, coupled
to the output terminal and in parallel with the pair of electrical
contacts, configured to provide an electrical bypass between the
pair of electrical contacts based on the plurality of pulses as
generated by the processor.
[0066] In Example 2, the electrical circuit of Example 1 optionally
further includes that the plurality of pulses is output for each
indication received by the processor.
[0067] In Example 3, the electrical circuit of any one or more of
Examples 1 and 2 optionally further includes that the bypass
circuit is configured to provide the electrical bypass a number of
times corresponding to a number of pulses of the plurality of
pulses.
[0068] In Example 4, the electrical circuit of any one or more of
Examples 1-3 optionally further includes that the processor is
configured to output the plurality of pulses according to a
predetermined cumulative duration.
[0069] In Example 5, the electrical circuit of any one or more of
Examples 1-4 optionally further includes that an arc duration is
based on at least one of an amount of charge carriers between the
pair of contacts being greater than a level at which an arc between
the contacts is maintained and an arc being thermodynamically
supported between the pair of contacts, and that the predetermined
cumulative duration of the plurality of pulses is less than the arc
duration.
[0070] In Example 6, the electrical circuit of any one or more of
Examples 1-5 optionally further includes that the predetermined
cumulative duration is based on a duration between a rising edge of
a first one of the plurality of pulses and a falling edge of a last
one of the plurality of pulses.
[0071] In Example 7, the electrical circuit of any one or more of
Examples 1-6 optionally further includes that a duty cycle of the
plurality of pulses varies during the predetermined cumulative
duration.
[0072] In Example 8, the electrical circuit of any one or more of
Examples 1-7 optionally further includes that the processor is
configured to output the plurality of pulses according to a
predetermined number of pulses.
[0073] In Example 9, the electrical circuit of any one or more of
Examples 1-8 optionally further includes that each one of the
plurality of pulses has a substantially equal pulse duration from a
rising edge to a falling each of each one of the plurality of
pulses.
[0074] In Example 10, the electrical circuit of any one or more of
Examples 1-9 optionally further includes that the processor is at
least one of an analog timer, a digital time, a microcontroller,
and a system on a chip.
[0075] In Example 11, a method includes outputting, with a
processor including an input terminal and an output terminal, a
plurality of pulses on the output terminal based on an indication
at the input terminal of a separation of a pair of electrical
contacts and providing, with a contact bypass circuit in parallel
with the pair of electrical contacts, an electrical bypass between
the pair of electrical contacts based on the plurality of pulses as
generated by the processor.
[0076] In Example 12, the method of Example 11 optionally further
includes that outputting the plurality of pulses includes
outputting the plurality of pulses for each indication received by
the processor.
[0077] In Example 13, the method of any one or more of Examples 11
and 12 optionally further includes that providing the electrical
bypass includes providing the electrical bypass a number of times
corresponding to a number of pulses of the plurality of pulses.
[0078] In Example 14, the method of any one or more of Examples
11-13 optionally further includes that outputting the plurality of
pulses includes outputting the plurality of pulses according to a
predetermined cumulative duration.
[0079] In Example 15, the method of any one or more of Examples
11-14 optionally further includes that an arc duration is based on
at least one of an amount of charge carriers between the pair of
contacts being greater than a level at which an arc between the
contacts is maintained and an arc being thermodynamically supported
between the pair of contacts, and that the predetermined cumulative
duration of the plurality of pulses is less than the arc
duration.
[0080] In Example 16, the method of any one or more of Examples
11-15 optionally further includes that the predetermined cumulative
duration is based on a duration between a rising edge of a first
one of the plurality of pulses and a falling edge of a last one of
the plurality of pulses.
[0081] In Example 17, the method of any one or more of Examples
11-16 optionally further includes that a duty cycle of the
plurality of pulses varies during the predetermined cumulative
duration.
[0082] In Example 18, the method of any one or more of Examples
11-17 optionally further includes that outputting the plurality of
pulses includes outputting a predetermined number of pulses.
[0083] In Example 19, the method of any one or more of Examples
11-18 optionally further includes that each one of the plurality of
pulses has a substantially equal pulse duration from a rising edge
to a falling each of each one of the plurality of pulses.
[0084] In Example 20, the method of any one or more of Examples
11-19 optionally further includes that the processor is at least
one of an analog timer, a digital time, a microcontroller, and a
system on a chip.
[0085] The above detailed description includes references to the
accompanying drawings, which form a part of the detailed
description. The drawings show, by way of illustration, specific
embodiments. These embodiments are also referred to herein as
"examples." Such examples may include elements in addition to those
shown and described. However, the present inventor also
contemplates examples in which only those elements shown and
described are provided.
[0086] All publications, patents, and patent documents referred to
in this document are incorporated by reference herein in their
entirety, as though individually incorporated by reference. In the
event of inconsistent usages between this document and those
documents so incorporated by reference, the usage in the
incorporated reference(s) should be considered supplementary to
that of this document; for irreconcilable inconsistencies, the
usage in this document controls.
[0087] In this document, the terms "a" or "an" are used, as is
common in patent documents, to include one or more than one,
independent of any other instances or usages of "at least one" or
"one or more." In this document, the term "or" is used to refer to
a nonexclusive or, such that "A or B" includes "A but not B," "B
but not A," and "A and B," unless otherwise indicated. In the
appended claims, the terms "including" and "in which" are used as
the plain-English equivalents of the respective terms "comprising"
and "wherein." Also, in the following claims, the terms "including"
and "comprising" are open-ended, that is, a system, device,
article, or process that includes elements in addition to those
listed after such a term in a claim are still deemed to fall within
the scope of that claim. Moreover, in the following claims, the
terms "first," "second," and "third," etc. are used merely as
labels, and are not intended to impose numerical requirements on
their objects.
[0088] The above description is intended to be, and not
restrictive. For example, the above-described examples (or one or
more aspects thereof) may be used in combination with each other.
Other embodiments may be used, such as by one of ordinary skill in
the art upon reviewing the above description. The Abstract is
provided to comply with 37 C.F.R. .sctn.1.72(b), to allow the
reader to quickly ascertain the nature of the technical disclosure.
It is submitted with the understanding that it will not be used to
interpret or limit the scope or meaning of the claims. In addition,
in the above Detailed Description, various features may be grouped
together to streamline the disclosure. This should not be
interpreted as intending that an unclaimed disclosed feature is
essential to any claim. Rather, inventive subject matter may lie in
less than all features of a particular disclosed embodiment. Thus,
the following claims are hereby incorporated into the Detailed
Description, with each claim standing on its own as a separate
embodiment.
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