U.S. patent application number 13/713747 was filed with the patent office on 2014-03-27 for laminated chip electronic component, board for mounting the same, and packing unit thereof.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. The applicant listed for this patent is SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Dong Gun KIM, Kyeong Jun KIM, Woo Sup KIM, Kyu Ho LEE, Sun Cheol LEE.
Application Number | 20140083755 13/713747 |
Document ID | / |
Family ID | 47665843 |
Filed Date | 2014-03-27 |
United States Patent
Application |
20140083755 |
Kind Code |
A1 |
LEE; Sun Cheol ; et
al. |
March 27, 2014 |
LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME,
AND PACKING UNIT THEREOF
Abstract
A laminated chip electronic component includes: a ceramic body
including internal electrodes and dielectric layers; external
electrodes formed to cover both end portions of the ceramic body in
a length direction; an active layer in which the internal
electrodes are disposed in an opposing manner, while having the
dielectric layers interposed therebetween, to form capacitance; and
upper and lower cover layers formed on upper and lower portions of
the active layer in a thickness direction, the lower cover layer
having a thickness greater than that of the upper cover layer.
Inventors: |
LEE; Sun Cheol; (Suwon-si,
KR) ; KIM; Woo Sup; (Suwon-si, KR) ; KIM; Dong
Gun; (Suwon-si, KR) ; KIM; Kyeong Jun;
(Suwon-si, KR) ; LEE; Kyu Ho; (Suwon-si,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
Suwon |
|
KR |
|
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Suwon
KR
|
Family ID: |
47665843 |
Appl. No.: |
13/713747 |
Filed: |
December 13, 2012 |
Current U.S.
Class: |
174/260 ;
174/258; 310/311; 338/21; 338/22R; 361/301.4 |
Current CPC
Class: |
H05K 1/181 20130101;
H01G 4/06 20130101; H01C 7/10 20130101; H01G 4/30 20130101; H05K
1/0306 20130101; H01G 4/12 20130101; H01L 41/083 20130101; H01G
2/06 20130101; Y02P 70/611 20151101; Y02P 70/50 20151101; H01C
7/008 20130101; H01G 2/24 20130101 |
Class at
Publication: |
174/260 ;
361/301.4; 338/21; 338/22.R; 310/311; 174/258 |
International
Class: |
H05K 1/18 20060101
H05K001/18; H05K 1/03 20060101 H05K001/03; H01C 7/00 20060101
H01C007/00; H01L 41/083 20060101 H01L041/083; H01G 4/12 20060101
H01G004/12; H01C 7/10 20060101 H01C007/10 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 27, 2012 |
KR |
10-2012-0108328 |
Claims
1. A laminated chip electronic component comprising: a ceramic body
including internal electrodes and dielectric layers; external
electrodes formed to cover both end portions of the ceramic body in
a length direction; an active layer in which the internal
electrodes are disposed in an opposing manner, while having the
dielectric layers interposed therebetween, to form capacitance; and
upper and lower cover layers formed on upper and lower portions of
the active layer in a thickness direction, the lower cover layer
having a thickness greater than that of the upper cover layer;
wherein when half of a thickness of the ceramic body is defined as
A, a thickness of the lower cover layer is defined as B, half of a
thickness of the active layer is defined as C, and a thickness of
the upper cover layer is defined as D, the thickness (D) of the
upper cover layer satisfies a range of D.gtoreq.4 .mu.m, a ratio
(B+C)/A in which a central portion of the active layer deviates
from a central portion of the ceramic body satisfies a range of
1.063.ltoreq.(B+C)/A.ltoreq.1.745, the lower cover layer includes
an identification layer having a color distinguished from that of
the upper cover layer, and the identification layer has a thickness
ranging from 30 .mu.m to a thickness equal to that of the lower
cover layer.
2. The laminated chip electronic component of claim 1, wherein a
ratio (D/B) of the thickness (D) of the upper cover layer to the
thickness (B) of the lower cover layer satisfies
0.021.ltoreq.D/B.ltoreq.0.422.
3. The laminated chip electronic component of claim 1, wherein a
ratio (B/A) of the thickness (B) of the lower cover layer to the
half (A) of the thickness of the ceramic body satisfies
0.329.ltoreq.B/A.ltoreq.1.522.
4. The laminated chip electronic component of claim 1, wherein a
ratio (C/B) of the half (C) of the thickness of the active layer to
the thickness (B) of the lower cover layer satisfies
0.146.ltoreq.C/B.ltoreq.2.458.
5. The laminated chip electronic component of claim 1, wherein the
identification layer is white in color.
6. The laminated chip electronic component of claim 1, wherein the
color of the identification layer is brighter than that of the
upper cover layer.
7. The laminated chip electronic component of claim 1, wherein the
identification layer includes a compound represented by ABO.sub.3
as a main ingredient, wherein A includes barium (Ba) or includes
barium (Ba) and at least one of calcium (Ca), zirconium (Zr), and
strontium (Sr), B includes titanium (Ti) or includes titanium (Ti)
and at least one of zirconium (Zr) and hafnium (Hf), and the
identification layer includes 1.0 to 30 mol of silicon (Si) and
aluminum (Al) as accessory ingredients, relative to 100 mol of the
main ingredient.
8. The laminated chip electronic component of claim 7, wherein the
identification layer includes 1.0 to 1.5 mol of silicon (Si) and
0.2 to 0.8 mol of aluminum (Al) as accessory ingredients, relative
to 100 mol of the main ingredient.
9. The laminated chip electronic component of claim 7, wherein the
identification layer includes 0 to 2 mol of magnesium (Mg) and 0 to
0.09 mol of manganese (Mn), relative to 100 mol of the main
ingredient.
10. The laminated chip electronic component of claim 7, wherein the
contents of magnesium (Mg) and manganese (Mn) are less than 0.001
mol, relative to 100 mol of the main ingredient, respectively.
11. The laminated chip electronic component of claim 7, wherein the
identification layer includes one additive selected from among
calcium (Ca) and zirconium (Zr) included in the amount of 1 mol or
less, relative to 100 mol of the main ingredient.
12. A board for mounting a laminated chip electronic component
thereon comprising: the laminated chip electronic component
according to claim 1; an electrode pad connected to the external
electrode through soldering; and a printed circuit board (PCB) in
which the electrode pad is formed and the laminated chip electronic
component is mounted on the electrode pad such that the internal
electrodes are horizontal and the lower cover layer is disposed to
be lower than the upper cover layer in a thickness direction.
13. The board of claim 12, wherein due to a difference between
strain generated in a central portion of the active layer and that
generated in the lower cover layer as a voltage is applied, a point
of inflection (PI) formed at both end portions of the ceramic body
in a length direction is formed in a position equal to or lower
than the height of the soldering.
14. A packing unit comprising: a laminated chip electronic
component according to claim 1; and a packing sheet including a
receiving portion for receiving the laminated chip electronic
component, wherein internal electrodes of all of the laminated chip
electronic components received in the receiving portions are
disposed to be horizontal to lower surfaces of the receiving
portions, and lower cover layers of all of the laminated chip
electronic components received in the receiving portions face the
lower surface of the receiving portions.
15. The packing unit of claim 14, wherein the packing sheet in
which the laminated chip electronic components are received is
wound as a reel.
16. A laminated chip electronic component comprising: external
electrodes formed on both end portions of a ceramic body having a
hexahedral shape in a length direction; an active layer formed
within the ceramic body and including a plurality of internal
electrodes disposed to face each other, while having dielectric
layers interposed therebetween to form capacitance; an upper cover
layer formed on an upper portion of the uppermost internal
electrode of the active layer; and a lower cover layer formed on a
lower portion of the lowermost internal electrode of the active
layer and having a thickness greater than that of the upper cover
layer, wherein the lower cover layer includes an identification
layer having a color distinguished from the upper cover layer, and
the identification layer has a thickness ranging from 30 .mu.m to a
thickness of the lower cover layer.
17. The laminated chip electronic component of claim 16, wherein
due to a difference between strain generated in a central portion
of the active layer and that generated in the lower cover layer as
a voltage is applied, a point of inflection (PI) is formed at both
end portions of the ceramic body in the length direction, which are
lower than the central portion of the ceramic body in the thickness
direction, and when half of a thickness of the ceramic body is
defined as A, a thickness of the lower cover layer is defined as B,
and half of a thickness of the active layer is defined as C, a
ratio (B+C)/A by which a central portion of the active layer
deviates from a central portion of the ceramic body satisfies a
range of 1.063.ltoreq.(B+C)/A.ltoreq.1.745.
18. The laminated chip electronic component of claim 16, wherein
when a thickness of the upper cover layer is defined as D, a ratio
(D/B) of the thickness (D) of the upper cover layer to the
thickness (B) of the lower cover layer satisfies
0.021.ltoreq.D/B.ltoreq.0.422.
19. The laminated chip electronic component of claim 16, wherein a
ratio (B/A) of the thickness (B) of the lower cover layer to the
half (A) of the thickness of the ceramic body satisfies
0.329.ltoreq.B/A.ltoreq.1.522.
20. The laminated chip electronic component of claim 16, wherein a
ratio (C/B) of the half (C) of the thickness of the active layer to
the thickness (B) of the lower cover layer satisfies
0.146.ltoreq.C/B.ltoreq.2.458.
21. The laminated chip electronic component of claim 16, wherein
the identification layer is white in color.
22. The laminated chip electronic component of claim 16, wherein
the color of the identification layer is brighter than that of the
upper cover layer.
23. The laminated chip electronic component of claim 16, wherein
the identification layer includes a compound represented by
ABO.sub.3 as a main ingredient, wherein A includes barium (Ba) or
includes barium (Ba) and at least one of calcium (Ca), zirconium
(Zr), and strontium (Sr), B includes titanium (Ti) or includes
titanium (Ti) and at least one of zirconium (Zr) and hafnium (Hf),
and the identification layer includes 1.0 to 30 mol of silicon (Si)
and aluminum (Al) as accessory ingredients, relative to 100 mol of
the main ingredient.
24. The laminated chip electronic component of claim 23, wherein
the identification layer includes 1.0 to 1.5 mol of silicon (Si)
and 0.2 to 0.8 mol of aluminum (Al) as accessory ingredients,
relative to 100 mol of the main ingredient.
25. The laminated chip electronic component of claim 23, wherein
the identification layer includes 0 to 2 mol of magnesium (Mg) and
0 to 0.09 mol of manganese (Mn), relative to 100 mol of the main
ingredient.
26. The laminated chip electronic component of claim 23, wherein
the contents of magnesium (Mg) and manganese (Mn) are less than
0.001 mol, relative to 100 mol of the main ingredient,
respectively.
27. The laminated chip electronic component of claim 23, wherein
the identification layer includes at least one additive selected
from among calcium (Ca) and zirconium (Zr) of 1 mol or less and at
least one additive selected from among kalium (K), boron (B), and
lithium (Li) of 0.2 mol or less, relative to 100 mol of the main
ingredient.
28. A board for mounting a laminated chip electronic component, the
board comprising: a laminated chip electronic component of claim
16; electrode pads electrically connected to the external
electrodes through soldering; and a printed circuit board (PCB) on
which the electrode pads are formed and the laminated chip
electronic component is mounted on the electrode pads such that the
internal electrodes are horizontal and the lower cover layer is
disposed to be lower than the upper cover layer in a thickness
direction.
29. The board of claim 28, wherein due to a difference between
strain generated in a central portion of the active layer and that
generated in the lower cover layer as a voltage is applied, a point
of inflection (PI) formed at both end portions of the ceramic body
in a length direction is formed to be lower than the height of the
soldering.
30. A packing unit comprising: a laminated chip electronic
component according to claim 16; and a packing sheet including a
receiving portion for receiving the laminated chip electronic
component, wherein internal electrodes of all of the laminated chip
electronic components received in the receiving portions are
disposed to be horizontal to lower surfaces of the receiving
portions, and lower cover layers of all of the laminated chip
electronic components received in the receiving portions face the
lower surfaces of the receiving portions.
31. The packing unit of claim 30, wherein the packing sheet in
which the laminated chip electronic components are received is
wound as a reel.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the priority of Korean Patent
Application No. 10-2012-0108328 filed on Sep. 27, 2012 in the
Korean Intellectual Property Office, the disclosure of which is
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a laminated chip electronic
component for reducing acoustic noise generated by the laminated
chip electronic component, a board for mounting the same, and a
packing unit thereof.
[0004] 2. Description of the Related Art
[0005] A multilayer capacitor, a laminated chip electronic
component, includes internal electrodes formed between a plurality
of dielectric layers.
[0006] When DC or AC voltages are applied to the multilayer
capacitor having internal electrodes overlapping with dielectric
layers interposed therebetween, a piezoelectric effect takes place
between the internal electrodes, generating vibrations.
[0007] As permittivity of a dielectric layer becomes higher and the
size of a chip is larger based on the same capacitance, generated
vibrations become more intense. The generated vibrations are
transferred from external electrodes of the multilayer capacitor to
a printed circuit board (PCB) on which the multilayer capacitor is
mounted. Here, the PCB vibrates to produce a noise.
[0008] When the noise produced due to the vibrations of the PCB is
included in an audio frequency, a corresponding vibrating sound may
make users uncomfortable, and such a sound is known as acoustic
noise.
[0009] In order to reduce acoustic noise, the inventors of the
present invention have conducted research on a mounting direction
of internal electrodes within a multilayer capacitor, in relation
to a PCB. As a result of the research, it has been recognized that
mounting a multilayer capacitor on a PCB to have directionality
such that internal electrodes of the multilayer capacitor are
horizontal with the PCB, may reduce acoustic noise in comparison to
a case in which a multilayer capacitor is mounted on the PCB such
that internal electrodes thereof are perpendicular to the PCB.
[0010] However, even in the case that the multilayer capacitor is
mounted on the PCB such that internal electrodes thereof are
horizontal with the PCB, acoustic noise may be measured and
determined to still be at a certain level or higher, so a further
reduction in acoustic noise remains an issue to be studied.
[0011] In addition, since the exterior of the multilayer capacitor
is dark brown in color, it is difficult to distinguish an upper
side and lower side of the multilayer capacitor. Therefore,
research into mounting the multilayer capacitor on the PCB to have
directionality such that the internal electrodes are horizontal
with the PCB is also required.
[0012] Patent document 1 below discloses internal electrodes
mounted to have horizontal directionality in relation to a PCB, but
it has technical characteristics in which a pitch between signal
lines is narrowed to reduce high frequency noise. Meanwhile, Patent
document 2 and Patent document 3 disclose different thicknesses of
an upper cover layer and a lower cover layer in a multilayer
capacitor. However, these documents do not suggest any motive or
solution for enhancing or reducing the acoustic noise. Moreover,
the documents absolutely do not disclose or anticipate an extent to
which the central portion of the active layer is deviated from the
central portion of the laminated chip capacitor, a ratio of the
upper cover layer to the lower cover layer, a ratio of the lower
cover layer to the thickness of the ceramic body, and a ratio of
the lower cover layer to the thickness of the active layer, etc.,
proposed in the claims and embodiments of the present invention in
order to reduce acoustic noise.
[0013] Also, Patent document 4 and Patent document 5 disclose a
technique of forming a mark on an upper surface of the laminated
chip capacitor in order to differentiate (or distinguish) upper and
lower portions of the laminated chip capacitor, but do not disclose
or anticipate formation of a translucent identification layer on a
cover layer within a ceramic body proposed in claims and
embodiments of the present invention.
PRIOR ART DOCUMENTS
[0014] (Patent document 1) Japanese Patent Laid Open Publication
No. 1994-268464 [0015] (Patent document 2) Japanese Patent Laid
Open Publication No. 1994-215978 [0016] (Patent document 3)
Japanese Patent Laid Open Publication No. 1996-130160 [0017]
(Patent document 4) Japanese Patent Laid Open Publication No.
2006-203165 [0018] (Patent document 5) Japanese Patent Laid Open
Publication No. 1996-330174
SUMMARY OF THE INVENTION
[0019] An aspect of the present invention provides a multilayer
capacitor as a laminated chip capacitor in which a lower cover
layer is thicker than an upper cover layer, and a central portion
of an active layer is set to be within a range deviating from a
central portion of a ceramic body.
[0020] Another aspect of the present invention provides a
multilayer capacitor in which a translucent identification layer is
formed on a lower cover layer thicker than an upper cover layer to
thus allow the upper cover layer and the lower cover layer to be
distinguished from one another.
[0021] Another aspect of the present invention provides a board for
mounting a laminated chip electronic component, on which a
laminated chip electronic component is mounted such that internal
electrodes thereof are horizontal to a printed circuit board (PCB)
and a lower cover layer is adjacent to the PCB, thus reducing
acoustic noise.
[0022] Another aspect of the present invention provides a packing
unit of a laminated chip electronic component, in which internal
electrodes of a laminated chip electronic component are
horizontally disposed and aligned based on a lower surface of a
receiving portion of a packing sheet.
[0023] According to a first embodiment of the present invention,
there is provided a laminated chip electronic component including:
a ceramic body including internal electrodes and dielectric layers;
external electrodes formed to cover both end portions of the
ceramic body in a length direction; an active layer in which the
internal electrodes are disposed in an opposing manner, while
having the dielectric layers interposed therebetween, to form
capacitance; and upper and lower cover layers formed on upper and
lower portions of the active layer in a thickness direction, the
lower cover layer having a thickness greater than that of the upper
cover layer, wherein when half of a thickness of the ceramic body
is defined as A, a thickness of the lower cover layer is defined as
B, half of a thickness of the active layer is defined as C, and a
thickness of the upper cover layer is defined as D, the thickness
(D) of the upper cover layer satisfies a range of D.gtoreq.4 .mu.m,
a ratio (B+C)/A by which a central portion of the active layer
deviates from a central portion of the ceramic body satisfies a
range of 1.063.ltoreq.(B+C)/A.ltoreq.1.745, the lower cover layer
includes an identification layer having a color distinguished from
that of the upper cover layer, and the identification layer has a
thickness ranging from 30 .mu.m to a thickness equal to that of the
lower cover layer.
[0024] A ratio (D/B) of the thickness (D) of the upper cover layer
to the thickness (B) of the lower cover layer may satisfy
0.021.ltoreq.D/.ltoreq.0.422.
[0025] A ratio (B/A) of the thickness (B) of the lower cover layer
to the half (A) of the thickness of the ceramic body may satisfy
0.329.ltoreq.B/A.ltoreq.1.522
[0026] A ratio (C/B) of the half (C) of the thickness of the active
layer to the thickness (B) of the lower cover layer may satisfy
0.146.ltoreq.C/B.ltoreq.2.458.
[0027] The identification layer may be white in color.
[0028] The color of the identification layer may be brighter than
that of the upper cover layer.
[0029] The identification layer may include a compound represented
by ABO.sub.3 as a main ingredient, wherein A includes barium (Ba)
or includes barium (Ba) and at least one of calcium (Ca), zirconium
(Zr), and strontium (Sr), B includes titanium (Ti) or includes
titanium (Ti) and at least one of zirconium (Zr) and hafnium (Hf),
and the identification layer may include 1.0 to 30 mol of silicon
(Si) and aluminum (Al) as accessory ingredients, relative to 100
mol of the main ingredient.
[0030] The identification layer may include 1.0 to 1.5 mol of
silicon (Si) and 0.2 to 0.8 mol of aluminum (Al) as accessory
ingredients, relative to 100 mol of the main ingredient.
[0031] The identification layer may include 0 to 2 mol of magnesium
(Mg) and 0 to 0.09 mol of manganese (Mn), relative to 100 mol of
the main ingredient.
[0032] The contents of magnesium (Mg) and manganese (Mn) may be
less than 0.001 mol, relative to 100 mol of the main ingredient,
respectively.
[0033] The identification layer may include one additive selected
from among calcium (Ca) and zirconium (Zr) included in the amount
of 1 mol or less, relative to 100 mol of the main ingredient.
[0034] According to another aspect of the present invention, there
is provided a board for mounting a laminated chip electronic
component thereon including: the laminated chip electronic
component according to the first embodiment; an electrode pad
connected to the external electrode through soldering; and a
printed circuit board (PCB) in which the electrode pad is formed
and the laminated chip electronic component is mounted on the
electrode pad such that the internal electrodes are horizontal and
the lower cover layer is disposed to be lower than the upper cover
layer in a thickness direction.
[0035] Due to a difference between strain generated in a central
portion of the active layer and that generated in the lower cover
layer as a voltage is applied, a point of inflection (PI) formed at
both end portions of the ceramic body in a length direction may be
formed in a position equal to or lower than the height of the
soldering.
[0036] According to another aspect of the present invention, there
is provided a packing unit including: a laminated chip electronic
component according to the first embodiment; and a packing sheet
including a receiving portion for receiving the laminated chip
electronic component, wherein internal electrodes of all of the
laminated chip electronic components received in the receiving
portions are disposed to be horizontal to lower surfaces of the
receiving portions, and lower cover layers of all of the laminated
chip electronic components received in the receiving portions face
the lower surfaces of the receiving portions.
[0037] The packing sheet in which the laminated chip electronic
components are received may be wound as a reel.
[0038] According to a second embodiment of the present invention,
there is provided a laminated chip electronic component including:
external electrodes formed on both end portions of a ceramic body
having a hexahedral shape in a length direction; an active layer
formed within the ceramic body and including a plurality of
internal electrodes disposed to face each other, while having
dielectric layers interposed therebetween to form capacitance; an
upper cover layer formed on an upper portion of the uppermost
internal electrode of the active layer; and a lower cover layer
formed on a lower portion of the lowermost internal electrode of
the active layer and having a thickness greater than that of the
upper cover layer, wherein the lower cover layer includes an
identification layer having a color distinguished from that of the
upper cover layer, and the identification layer may have a
thickness ranging from 30 .mu.m to a thickness equal to that of the
lower cover layer.
[0039] Due to a difference between strain generated in a central
portion of the active layer and that generated in the lower cover
layer as a voltage is applied, a point of inflection (PI) is formed
at both end portions of the ceramic body in the length direction,
which are lower than the central portion of the ceramic body in the
thickness direction, and when half of a thickness of the ceramic
body is defined as A, a thickness of the lower cover layer is
defined as B, and half of a thickness of the active layer is
defined as C, a ratio (B+C)/A by which a central portion of the
active layer deviates from a central portion of the ceramic body
satisfies a range of 1.063.ltoreq.(B+C)/A.ltoreq.1.745
[0040] When a thickness of the upper cover layer is defined as D,
the ratio a ratio (D/B) of the thickness (D) of the upper cover
layer to the thickness (B) of the lower cover layer may satisfy
0.021.ltoreq.D/B.ltoreq.0.422.
[0041] A ratio (B/A) of the thickness (B) of the lower cover layer
to the half (A) of the thickness of the ceramic body satisfies
0.329.ltoreq.B/A.ltoreq.1.522.
[0042] A ratio (C/B) of the half (C) of the thickness of the active
layer to the thickness (B) of the lower cover layer satisfies
0.146.ltoreq.C/B.ltoreq.2.458.
[0043] The identification layer may be white in color.
[0044] The color of the identification layer may be brighter than
that of the upper cover layer.
[0045] The identification layer may include a compound represented
by ABO.sub.3 as a main ingredient, wherein A includes barium (Ba)
or includes barium (Ba) and at least one of calcium (Ca), zirconium
(Zr), and strontium (Sr), B includes titanium (Ti) or includes
titanium (Ti) and at least one of zirconium (Zr) and hafnium (Hf),
and the identification layer may include 1.0 to 30 mol of silicon
(Si) and aluminum (Al) as accessory ingredients, relative to 100
mol of the main ingredient.
[0046] The identification layer may include 1.0 to 1.5 mol of
silicon (Si) and 0.2 to 0.8 mol of aluminum (Al) as accessory
ingredients, relative to 100 mol, relative to the main
ingredient.
[0047] The identification layer may include 0 to 2 mol of magnesium
(Mg) and 0 to 0.09 mol of manganese (Mn), relative to 100 mol of
the main ingredient.
[0048] The contents of magnesium (Mg) and manganese (Mn) may be
less than 0.001 mol, relative to 100 mol of the main ingredient,
respectively.
[0049] The identification layer may include at least one additive
selected from among calcium (Ca) and zirconium (Zr) of 1 mol or
less and at least one additive selected from among kalium (K),
boron (B), and lithium (Li) of 0.2 mol or less, relative to 100 mol
of the main ingredient.
[0050] According to another aspect of the present invention, there
is provided a board for mounting a laminated chip electronic
component, including: a laminated chip electronic component
according to the second embodiment; electrode pads electrically
connected to the external electrodes through soldering; and a
printed circuit board (PCB) on which the electrode pads are formed
and the laminated chip electronic component is mounted on the
electrode pads such that the internal electrodes are horizontal and
the lower cover layer is disposed to be lower than the upper cover
layer in a thickness direction.
[0051] Due to a difference between strain generated in a central
portion of the active layer and that generated in the lower cover
layer as a voltage is applied, a point of inflection (PI) formed at
both end portions of the ceramic body in a length direction may be
formed to be lower than the height of the soldering.
[0052] According to another aspect of the present invention, there
is provided a packing unit including: a laminated chip electronic
component according to the second embodiment; and a packing sheet
including a receiving portion for receiving the laminated chip
electronic component, wherein internal electrodes of all of the
laminated chip electronic components received in the receiving
portions are disposed to be horizontal to lower surfaces of the
receiving portions, and lower cover layers of all of the laminated
chip electronic components received in the receiving portions face
the lower surfaces of the receiving portions.
[0053] The packing sheet in which the laminated chip electronic
components are received may be wound as a reel.
BRIEF DESCRIPTION OF THE DRAWINGS
[0054] The above and other aspects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0055] FIG. 1 is a schematic cutaway perspective view of a
laminated chip capacitor according to an embodiment of the present
invention;
[0056] FIG. 2 is a cross-sectional view of the laminated chip
capacitor of FIG. 1 taken in length and thickness directions;
[0057] FIG. 3 is a schematic cross-sectional view of the laminated
chip capacitor of FIG. 1 taken in the length and thickness
directions showing dimensions;
[0058] FIG. 4 is a schematic perspective view of the laminated chip
capacitor of FIG. 1 mounted on a printed circuit board (PCB);
[0059] FIG. 5 is a schematic plan view of the laminated chip
capacitor of FIG. 4 mounted on the PCB;
[0060] FIG. 6 is a cross-sectional view of the laminated chip
capacitor of FIG. 4 mounted on the PCB taken in the length and
thickness directions;
[0061] FIG. 7 is a schematic cross-sectional view showing the
laminated chip capacitor of FIG. 4 mounted on the PCB which is
deformed as a voltage is applied thereto;
[0062] FIG. 8A is a graph showing a change in acoustic noise over
electrode pad size when internal electrodes of a related art
laminated chip capacitor are mounted to be vertical in relation to
a PCB and mounted to be horizontal in relation to the PCB;
[0063] FIG. 8B is a graph showing a change in acoustic noise over
electrode pad size when a laminated chip capacitor is mounted on a
PCB such that internal electrodes are horizontal in relation to the
PCB and a lower cover layer is adjacent to the PCB according to an
embodiment of the present invention;
[0064] FIG. 9 is a schematic perspective view illustrating mounting
of laminated chip capacitors in a packing unit according to an
embodiment of the present invention; and
[0065] FIG. 10 is a schematic sectional view illustrating the
packing unit of FIG. 9 wound in a reel shape.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0066] Embodiments of the present invention will now be described
in detail with reference to the accompanying drawings. The
invention may, however, be embodied in many different forms and
should not be construed as being limited to the embodiments set
forth herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope of the invention to those skilled in the art. In the
drawings, the shapes and dimensions of elements may be exaggerated
for clarity, and the same reference numerals will be used
throughout to designate the same or like components.
[0067] A laminated chip electronic component according to an
embodiment of the present invention may be able to be used in a
multilayer ceramic capacitor, a laminated varistor, a thermistor, a
piezoelectric element, a multilayer substrate, and the like, which
uses dielectric layers and has a structure in which internal
electrodes face with the dielectric layer interposed
therebetween.
[0068] Also, elements having the same function within a scope of
the same concept illustrated in drawings of respective embodiments
will be described by using the same reference numerals.
[0069] Laminated Chip Capacitor
[0070] FIG. 1 is a schematic cutaway perspective view of a
laminated chip capacitor according to an embodiment of the present
invention. FIG. 2 is a cross-sectional view of the laminated chip
capacitor of FIG. 1 taken in length and thickness directions. FIG.
3 is a schematic cross-sectional view of the laminated chip
capacitor of FIG. 1 taken in the length and thickness directions
showing dimensions.
[0071] Referring to FIGS. 1 through 3, a laminated chip capacitor
10 may include a ceramic body 12, an external electrode 40, an
active layer 60, and upper and lower cover layers 53 and 55.
[0072] The ceramic body 12 may be fabricated by applying a
conductive paste to a ceramic green sheet to form an internal
electrode 20, laminating the ceramic green sheets each having the
internal electrode 20 formed thereon, and firing the same. The
ceramic body 12 may be formed by repeatedly laminating a plurality
of dielectric layers 52 and 54 and internal electrodes 22 and
24.
[0073] The ceramic body 12 may have a hexahedral shape. When the
chip is fired, ceramic powder is shrunken, so the ceramic body 12
may not have a hexahedral shape with entirely straight lines, yet
it may have substantially hexahedral shape.
[0074] In order to clarify embodiments of the present invention,
directions of the hexahedron may be defined as follows: L, W, and T
indicated in FIG. 1 denote a length direction, a width direction,
and a thickness direction, respectively. Here, the thickness
direction may be used to have the same concept as that of a
lamination direction in which the dielectric layers are
laminated.
[0075] The embodiment of FIG. 1 is a laminated chip capacitor 10
having a rectangular parallelepiped shape in which a length thereof
is greater than width and thickness thereof.
[0076] Ceramic powder having high K-dielectrics (or high dielectric
constant) may be used as a material of the dielectric layer 50 in
order to obtain high capacitance. As the ceramic powder, for
example, barium titanate (BaTiO.sub.3)-based powder, strontium
titanate (SrTiO.sub.3)-based powder, or the like, may be used but
the present invention is not limited thereto.
[0077] The first and second external electrodes 42 and 44 may be
formed with a conductive paste including metal powder. As metal
used for a metal powder included in the conductive paste, copper
(Cu), nickel (Ni), or an alloy thereof may be used, but the present
invention is not particularly limited thereto.
[0078] The internal electrodes 20 may include a first internal
electrode 22 and a second internal electrode 24, and the first and
second internal electrodes 22 and 24 may be electrically connected
to the first and second external electrodes 42 and 44,
respectively.
[0079] Here, the first internal electrode 22 and the second
internal electrode 24 may include first and second electrode
pattern portions 222 and 242 which overlap in an opposing manner
with the dielectric layer 54 (Please See FIG. 1) interposed
therebetween and first and second lead portions 224 and 244 led out
to the first and second external electrodes 42 and 44,
respectively.
[0080] The first and second electrode pattern portions 222 and 242
may be successively laminated in the thickness direction to
constitute the active layer 60 forming capacitance within the
ceramic body 12.
[0081] In view of the section of the laminated chip capacitor in
the length direction and thickness direction, portions other than
the active layer 60 may be defined as margin portions. Among the
margin portions, upper and lower margin portions of the active
layer 60 in the thickness direction may particularly be defined as
the upper cover layer 53 and the lower cover layer 55.
[0082] Like the dielectric layers 52 and 54 formed between the
first internal electrode 22 and the second internal electrode 24,
the upper cover layer 53 and the lower cover layer 55 may be formed
as ceramic green sheets are sintered.
[0083] The plurality of dielectric layers 50 including the upper
cover layer 53 and the lower cover layer 55 are in a sintered state
and adjacent dielectric layers 50 may be integrated such that
boundaries therebetween may not be readily apparent without the use
of a scanning electron microscope (SEM).
[0084] In the present embodiment, the lower cover layer 55 may have
a thickness greater than that of the upper cover layer 53. Namely,
by increasing the lamination number of ceramic green sheets in
comparison to the upper cover layer 53, the lower cover layer 55
may have a thickness greater than that of upper cover layer 53.
[0085] The lower cover layer 55 may include an identification layer
30 having a color distinguished from that of the upper cover layer
53 within the ceramic body 12.
[0086] The identification layer 30 may have a thickness ranging
from 30 .mu.m to a thickness equal to that of the lower cover layer
55 after a firing is performed. For example, the identification
layer 30 may be formed by laminating at least eight or more ceramic
green sheets each having a thickness of 4 .mu.m.
[0087] The identification layer 30 may include a compound
represented by ABO.sub.3 as a main ingredient. Here, A may include
barium (B) or include barium (Ba) and at least one of calcium (Ca),
and zirconium (Zr), and strontium (Sr). In detail, A may be barium
(Ba) or may include at least one of calcium (Ca), zirconium (Zr),
and strontium (Sr) in addition to barium (Ba). Also, B may include
titanium (Ti) or include titanium (Ti) and at least one of
zirconium (Zr) and hafnium (Hf). Namely, B may be titanium (Ti),
titanium (Ti) and zirconium (Zr), titanium (Ti) and hafnium (Hf),
or titanium (Ti), zirconium (Zr), and hafnium (Hf).
[0088] Here, the identification layer 30 may include 1.0 to 30 mol
of silicon (Si) and aluminum (Al) as accessory ingredient, relative
to 100 mol of the main ingredient.
[0089] In detail, in the accessory ingredient including barium
(Ba), silicon (Si), and aluminum (Al), the contents of silicon (Si)
may be 1.0 to 1.5 mol, relative to 100 mol of the main ingredient
and the content of aluminum (Al) may be 0.2 to 0.8 mol, relative to
100 mol of the main ingredient. Also, in case of a low permittivity
(or low-k) product having an acoustic noise attenuation effect, in
the accessory ingredient including barium (Ba), silicon (Si), and
aluminum (Al), the content of silicon (Si) and aluminum (Al) may be
included up to 30 mol, relative to 100 mol of the main
ingredient.
[0090] Also, according to an embodiment of the present invention,
the identification layer 30 may include 0 to 2 mol of magnesium
(Mg) and 0 to 0.09 mol of manganese (Mn), relative to 100 mol of
the main ingredient.
[0091] Here, the additives such as magnesium (Mg) and manganese
(Mn) may have shrinkage rates similar to those of the ingredients
of the other dielectric layers 50 to reduce the generation of
cracks or delamination due to a difference in ingredients with the
dielectric layers 50.
[0092] When a ceramic green sheet prepared by including an
accessory ingredient including silicon (Si) and aluminum (Al) in
base powder of BaTiO.sub.3 and adding a small amount of magnesium
(Mg) or manganese (Mn) as an additive is fired at a temperature of
1,150.degree. C., the fired ceramic green sheet may have a white
color.
[0093] In particular, the amount of magnesium (Mg) and manganese
(Mn) may be reduced to better exhibit the white color, and in this
case, the identification layer 30 may include 0.001 mol of
magnesium (Mg) and manganese (Mn), relative to 100 mol of the main
ingredient, respectively.
[0094] A general ceramic green sheet that does not have a
composition such as that of the accessory ingredient and additive
according to an embodiment of the present invention is dark brown
in color after firing is performed. The white-based identification
layer 30 may be distinguished (or discriminated) from the active
layer 60 or the upper cover layer 53 having a dark brown color by
the difference of color after firing operation is performed.
Namely, the color of the identification layer 30 may be brighter
than that of the active layer 60 or the upper cover layer 53.
[0095] The difference in colors plays an important role in reducing
acoustic noise by mounting the lower cover layer 55 to be adjacent
to an upper surface of the PCB.
[0096] Also, the identification layer 30 may include at least one
additive selected from among calcium (Ca) and zirconium (Zr) of 1
mol or less, relative to 100 mol of the main ingredient and at
least one additive selected from among kalium (K), boron (B), and
lithium (Li) of 0.2 mol or less, relative to 100 mol of the main
ingredient. Here, the additives as colorless additives may
contribute to the formation of glass.
[0097] Table 1 below shows an experiment example of mounting the
lower cover layer 55 such that the lower cover layer 55 is adjacent
to an upper surface of the PCB by adjusting a thickness of the
identification layer after the identification layer 30 is formed on
the lower cover layer 55.
TABLE-US-00001 TABLE 1 Overall thickness of lower Thickness of
Upper/lower cover Thickness of identification/overall
discernibility layer identification thickness of lower defective
rate (.mu.m) layer (.mu.m) cover layer (%) (%) 330 10 3.0 47 20 6.1
23 30 9.1 0 40 12.1 0 50 15.2 0 70 21.2 0 100 30.3 0 150 45.5 0 200
60.6 0 250 75.8 0 270 81.8 0 300 90.9 0 310 93.9 0 330 100 0
[0098] A case in which the lower cover layer 55 is mounted so as
not to be adjacent to the PCB according to a thickness of the
identification layer 30 was determined to be defective, and
referring to Table 1, the thickness of the identification layer 30
is discernible from the outside when it has a thickness of at least
30 .mu.m or greater.
[0099] Referring to FIG. 3, the laminated chip capacitor according
the present embodiment may be more clearly defined.
[0100] First, it may be defined such that half of the overall
thickness of the ceramic body 12 is A, a thickness of the lower
cover layer 55 is B, half of the overall thickness of the active
layer 60 is C, and a thickness of the upper cover layer 53 is
D.
[0101] The overall thickness of the ceramic body 12 does not
include a thickness of the external electrodes 40 coated on an
upper surface S.sub.T and a lower surface S.sub.B of the ceramic
body 12. In the present embodiment, half of a distance (thickness)
from the upper surface S.sub.T to the lower surface S.sub.B of the
ceramic body 12 is defined as A.
[0102] The thickness B of the lower cover layer 55 is defined as a
distance from a lower surface of the lowermost internal electrode
of the active layer 60 in the thickness direction to the lower
surface S.sub.B of the ceramic body 12. The thickness D of the
upper cover layer 53 is defined as a distance from an upper surface
of the uppermost internal electrode of the active layer 60 in the
thickness direction to the upper surface S.sub.T of the ceramic
body 12.
[0103] Here, the overall thickness of the active layer 60 refers to
a distance from an upper surface of the uppermost internal
electrode of the active layer 60 to a lower surface of the
lowermost internal electrode of the active layer 60. C is defined
as half of the active layer 60.
[0104] In the present embodiment, the thickness of the upper cover
layer 53 may satisfy a range of D.gtoreq.4 .mu.m. When D is smaller
than 4 .mu.m, the internal electrode may be exposed from the upper
surface S.sub.T of the ceramic body 12, resulting in a defective
product.
[0105] Also, in the present embodiment, a ratio (B+C)/A by which
the central portion of the active layer 60 deviates from a central
portion of the ceramic body 12 may satisfy a range of
1.063.ltoreq.(B+C)/A.ltoreq.1.745.
[0106] Here, the central portion of the active layer may be defined
as within 1 .mu.m up and down from a center line CL.sub.A, a
central point between the upper surface of the uppermost internal
electrode of the active layer 60 and the lower surface of the
lowermost internal electrode of the active layer 60.
[0107] Also, the central portion of the ceramic body 12 may be
defined as within 1 .mu.m up and down from a center line CLc of the
ceramic body as a central point between the upper surface S.sub.T
and the lower surface S.sub.B of the ceramic body 12.
[0108] When voltages having different polarities are applied to the
first and second external electrodes 42 and 44 formed on both end
portions of the laminated chip capacitor 10, the ceramic body 12
expands and contracts in the thickness direction due to an inverse
piezoelectric effect of the dielectric layers 50, while the both
end portions of the first and second external electrodes 42 and 44
in the thickness direction contract and expand due to a Poisson
effect, contrary to the expansion and contraction of the ceramic
body 12 in the thickness direction.
[0109] Here, the central portion of the active layer 60 is a
portion maximally expanded and contracted in both end portions of
the first and second external electrodes 42 and 44 in the length
direction, causing acoustic noise.
[0110] In the present embodiment, in order to reduce acoustic
noise, the central portion of the active layer 60 is defined as
being outside of the central portion of the ceramic body 12.
[0111] Meanwhile, in the present embodiment, due to a difference
between strain generated in the central portion of the active layer
60 and that generated in the lower cover layer 55 as a voltage is
applied, a point of inflection may be formed at both end portions
of the ceramic body 12 in the length direction, which are lower
than the central portion of the ceramic body 12 in the thickness
direction.
[0112] In order to reduce acoustic noise, in the present
embodiment, the ratio (D/B) of the thickness (D) of the upper cover
layer to the thickness (B) of the lower cover layer may satisfy
0.021.ltoreq.D/B.ltoreq.0.422.
[0113] Also, the ratio (B/A) of the thickness (B) of the lower
cover layer to the half (A) of the thickness of the ceramic body
may satisfy 0.329.ltoreq.B/A.ltoreq.1.522.
[0114] The ratio (C/B) of the half (C) of the thickness of the
active layer to the thickness (B) of the lower cover layer may
satisfy 0.146.ltoreq.C/B.ltoreq.2.458.
[0115] Meanwhile, in order to mount the lower cover layer 55 having
a thickness greater than that of the upper cover layer 53 such that
it is adjacent to an upper surface of a printed circuit board
(PCB), the white identification layer 30 of the lower cover layer
55 may face an upper surface of the PCB.
[0116] Board for Mounting Laminated Chip Capacitor
[0117] FIG. 4 is a schematic perspective view of the laminated chip
capacitor of FIG. 1 mounted on a printed circuit board (PCB). FIG.
5 is a schematic plan view of the laminated chip capacitor of FIG.
4 mounted on the PCB. FIG. 6 is a cross-sectional view of the
laminated chip capacitor of FIG. 4 mounted on the PCB taken in the
length and thickness directions.
[0118] A board 100 for mounting a laminated chip capacitor thereon
according to an embodiment of the present invention may include the
laminated chip electronic component 10, electrode pads 122 and 124,
and a printed circuit board 120.
[0119] The laminated chip electronic component 10 may be the
laminated chip capacitor as described above, and the laminated chip
capacitor 10 may be mounted on the PCB such that the internal
electrodes 22 and 24 are horizontal to the PCB 120.
[0120] Also, the laminated chip capacitor 10 may be mounted on the
PCB 120 such that the lower cover layer 55 thicker than the upper
cover layer 53 within the ceramic body 12 of the laminated chip
capacitor 10 is disposed in a lower side than the upper cover layer
53 in the thickness direction.
[0121] When a voltage is applied to the laminated chip capacitor 10
mounted on the PCB 120, acoustic noise is generated. Here, a size
of the electrode pads 122 and 124 may determine an amount of
solders 142 and 144 connecting the first and second external
electrodes 42 and 44 and the electrode pads 122 and 124,
respectively, and reduce acoustic noise.
[0122] FIG. 7 is a schematic cross-sectional view showing the
laminated chip capacitor of FIG. 4 mounted on the PCB which is
deformed as a voltage is applied thereto.
[0123] Referring to FIG. 7, with the laminated chip capacitor 10
mounted on the PCB 120, when voltages having different polarities
are applied to the first and second external electrodes 42 and 44
formed on both end portions of the laminated chip capacitor 10, the
ceramic body 12 expands and contracts in the thickness direction
due to inverse piezoelectric effect of the dielectric layers 50,
while the both end portions of the first and second external
electrodes 42 and 44 in the length direction contract and expand
due to a Poisson effect, contrary to the expansion and contraction
of the ceramic body 12 in the thickness direction.
[0124] Meanwhile, in the present embodiment, due to a difference
between strain generated in the central portion of the active layer
60 and that generated in the lower cover layer 55, a point of
inflection (PI) may be formed at both end portions of the ceramic
body 12 in the length direction, which are lower than the central
portion of the ceramic body 12 in the thickness direction.
[0125] The PI is a point at which the phase of an outer surface of
the ceramic body 12 is changed. The PI may be formed to be equal to
or lower than a height of the solders 142 and 144 formed on the
external electrodes 42 and 44 of the laminated chip capacitor 10 on
the electrode pads 122 and 124.
[0126] Here, the central portion of the active layer 60 is a
portion which is maximally expanded and contracted in both end
portions of the ceramic body 12 in the length direction according
to a voltage application.
[0127] In FIG. 7, it can be seen that both end portions of the
laminated chip capacitor 10 in the length direction are maximally
expanded, and when both end portions of the laminated chip
capacitor 10 in the length direction are maximally expanded, force
.quadrature. thrusting upper portions of the solders 142 and 144
outwardly due to the expansion is generated, and contracting force
1 thrusting the external electrodes is generated at the lower
portions of the solders 142 and 144 by the force thrust to the
outside.
[0128] Thus, a PI may be formed in a position lower than the height
of the soldering.
[0129] Referring to FIG. 5, a distance between both end portions of
the first electrode pad 122 and the second electrode pad 124 is
defined as Ll and a distance between the outer surfaces of the
first external electrode 42 and the second external electrode 44 of
the laminated chip capacitor 10 is defined as L2. Also, a distance
between both end portions of the first electrode pad 122 and the
second electrode pad 124 is defined as W1, and a distance between
outer surfaces of the first external electrode 42 and the second
external electrode 44 is defined as W2.
[0130] FIG. 8A is a graph showing a change in acoustic noise over
electrode pad size when internal electrodes of a related art
laminated chip capacitor are mounted vertically on a PCB and
mounted horizontally on the PCB.
[0131] Referring to FIG. 8A, it can be seen that, when the size,
i.e., L1/L2, of the electrode pad is reduced to be equal to or
smaller than 1.34 and 1.17, in case of the laminated chip capacitor
in which internal electrodes are mounted horizontally on the PCB,
acoustic noise is reduced. However, it can be seen that, in the
case of the laminated chip capacitor in which internal electrodes
are mounted vertically on the PCB, acoustic noise is not greatly
reduced.
[0132] Namely, the size of the electrode pad has a different
tendency in reducing acoustic noise according to whether the
internal electrodes of the laminated chip capacitor are
horizontally or vertically mounted on the PCB.
[0133] FIG. 8B is a graph showing a change in acoustic noise over
electrode pad size when the laminated chip capacitor is mounted on
a PCB such that internal electrodes are horizontal to the PCB and
the lower cover layer is adjacent to the PCB according to an
embodiment of the present invention.
[0134] Referring to FIG. 8B, it can be seen that the acoustic noise
is different according to whether the thickness of the lower cover
layer is thicker than that of the upper cover layer, even when the
laminated chip capacitor is mounted on a PCB such that internal
electrodes are horizontal to the PCB. Therefore, in order to
further reduce the acoustic noise, it can be seen that another
parameter is required.
[0135] According to example embodiments of the present invention,
acoustic noise may be further reduced by controlling an extent of
how much the central portion of the active layer is deviated from
the central portion of the laminated chip capacitor, a ratio of the
upper cover layer to the lower cover layer, a ratio of the lower
cover layer to the thickness of the ceramic body, and a ratio of
the lower cover layer to the thickness of the active layer,
etc.
[0136] According to example embodiments of the present invention,
it can be seen that the ratio ((B+C)/A) by which the central
portion of the active layer 60 deviates from the central portion of
the ceramic body 12 satisfies 1.063.ltoreq.(B+C)/A.ltoreq.1.745,
the acoustic noise may be sufficiently reduced even when the
electrode pad is small so the amount of solder is small, and the
acoustic noise may be further reduced rather when the electrode pad
is large.
[0137] That is, when the ratio ((B+C)/A) by which the central
portion of the active layer 60 deviates from the central portion of
the ceramic body 12 satisfies the range
1.063.ltoreq.(B+C)/A.ltoreq.1.745, acoustic noise can be
significantly reduced irrespective of the size of the electrode
pad. Herein, A, B and C represents a half of the thickness of the
ceramic body, the thickness of the lower cover layer and a half of
the thickness of the active layer, respectively.
[0138] This is understood to mean that, when the ratio ((B+C)/A) by
which the central portion of the active layer 60 deviates from the
central portion of the ceramic body 12 satisfies the range
1.063.ltoreq.(B+C)/A.ltoreq.1.745, a maximum displacement of the
laminated chip capacitor corresponds to an upper portion of the
central portion of the ceramic body 12 based on the center of the
active layer 60, and thus, displacement transferred to the PCB 120
through the solder is reduced to result in a reduction of the
acoustic noise.
[0139] Packing Unit of Laminated Chip Capacitor
[0140] FIG. 9 is a schematic perspective view illustrating mounting
of laminated chip capacitors in a packing unit according to an
embodiment of the present invention, and FIG. 10 is a schematic
sectional view illustrating the packing unit of FIG. 9 wound in a
reel shape.
[0141] Referring to FIG. 9, a packing unit 200 for packing a
laminated chip capacitor according to the present embodiment may
include a packing sheet 220 having a receiving portion 224 in which
the laminated chip capacitor 10 is received.
[0142] The receiving portion 224 of the packing sheet 220 has a
shape corresponding to an electronic component 10, and internal
electrodes may be disposed horizontally based on a lower surface
225 of the receiving portion 224.
[0143] The laminated chip capacitor 10 is maintained in a state in
which the internal electrodes thereof are aligned horizontally
through an electronic component alignment device 150 and moved to
the packing sheet 220 through a transfer device 170. Thus, the
internal electrodes may be disposed to be horizontal based on the
lower surface 225 of the receiving portion 224. In this manner, all
of the laminated chip capacitors 10 in the packing sheet 220 may be
disposed to have the same directionality in the packing sheet
220.
[0144] Each of the laminated chip capacitors 10 received in the
receiving portions 224 may be disposed such that the lower cover
layer 55 faces the lower surface of the receiving portion 224.
Here, when the lower cover layer 55 includes the identification
layer 30, the upper and lower portions of the ceramic body 12 can
be easily discriminated from one another. In this case, all of the
laminated chip electronic components received in the receiving
portions 224 may face the lower surfaces of the receiving portions.
When the laminated chip electronic components are received in the
receiving portions in this manner, it is advantageous for the lower
cover layer 55 to be mounted to face the PCB later.
[0145] The packing unit 200 for packing the laminated chip
capacitor may further include a packing film 240 covering the
packing sheet 220 in which the electronic component 10 is received
such that the internal electrodes are disposed horizontally based
on the lower surface of the receiving portion 225.
[0146] FIG. 10 illustrates the packing unit 200 for packing the
laminated chip capacitor, which is wound in a reel shape. The
packing unit 200 may be continuously wound to be formed.
Experimental Example
[0147] Multilayer ceramic capacitors (MLCC) according to
embodiments of the present invention and comparative examples were
fabricated as follows.
[0148] First, slurry including powder such as barium titanate
(BaTiO.sub.3), or the like, was applied to a carrier film and then
dried to prepare a plurality of ceramic green sheets having a
thickness of 1.8 .mu.m.
[0149] Next, internal electrodes were formed by applying a
conductive paste for a nickel internal electrode on the ceramic
green sheets by using a screen.
[0150] About three hundreds and seventy (370) ceramic green sheets
were laminated, and here, a larger number of ceramic green sheets
without an internal electrode were laminated below ceramic green
sheets with an internal electrode formed thereon than those above
the ceramic green sheets with an internal electrode formed thereon.
The laminate (or lamination body) was isostatic-pressed under a
pressure condition of 1000 kgf/cm.sup.2 at 85.degree. C. The
pressing-completed ceramic laminate was severed into individual
chips, and a debinding process was performed by maintaining the
severed chips at 230.degree. C. for 60 hours under air
atmosphere.
[0151] Thereafter, the chips were fired at an oxygen partial
pressure of 10.sup.-11 atm.about.10.sup.-10 atm, lower than a
Ni/NiO equilibrium oxygen partial pressure, under a reduced
atmosphere such that the internal electrodes were not oxidized.
After the firing operation, a chip size (lengthxwidth (L.times.W))
of a laminated chip capacitor was 1.64 mm.times.0.88 mm (L.times.W,
1608 size). Here, a fabrication tolerance was determined to be
.+-.0.1 mm in length.times.width, and acoustic noise of a chip
satisfying the fabrication tolerance was measured in the
experimentation.
[0152] Thereafter, the chip was subjected to processes such as an
external electrode formation process, a plating process, and the
like, to fabricate an MLCC.
TABLE-US-00002 TABLE 2 Acoustic obtainment A B C D Noise of #
(.mu.m) (.mu.m) (.mu.m) (.mu.m) (B + C)/A B/A D/B C/B (dB) Cap. 1*
405.5 40.2 365.4 39.9 1.000 0.099 0.993 9.090 29.5 OK 2* 436.0 70.4
365.9 69.7 1.001 0.161 0.990 5.197 25.7 OK 3* 455.5 90.8 364.3 91.5
0.999 0.199 1.008 4.012 23.1 OK 4* 508.1 24.9 361.1 269.1 0.760
0.049 10.807 14.502 31.2 OK 5* 456.6 25.2 360.1 167.8 0.844 0.055
6.659 14.290 32.5 OK 6* 527.3 30.2 191.0 642.4 0.419 0.057 21.272
6.325 30.3 OK 7* 414.5 30.9 188.8 420.4 0.530 0.075 13.605 6.110
30.5 OK 8* 516.2 39.4 360.7 271.5 0.775 0.076 6.891 9.155 28.2 OK
9* 446.0 39.8 365.5 121.2 0.909 0.089 3.045 9.183 29.1 OK 10* 469.1
40.6 364.2 169.1 0.863 0.087 4.165 8.970 27.9 OK 11* 416.2 40.7
360.7 70.3 0.964 0.098 1.727 8.862 28.4 OK 12* 428.3 40.8 360.0
95.7 0.936 0.095 2.346 8.824 28.9 OK 13* 495.9 40.9 364.9 221.0
0.818 0.082 5.403 8.922 28.1 OK 14* 435.9 25.0 421.3 4.2 1.024
0.057 0.168 16.852 31.6 OK 15* 420.7 70.4 365.9 39.1 1.037 0.167
0.555 5.197 25.7 OK 16 431.7 94.8 364.3 40.0 1.063 0.220 0.422
3.843 19.9 OK 17 443.0 103.8 389.1 4.0 1.113 0.234 0.039 3.749 19.3
OK 18 443.7 119.8 363.2 41.1 1.089 0.270 0.343 3.032 18.7 OK 19
447.1 147.3 362.1 22.7 1.139 0.329 0.154 2.458 17.9 OK 20 452.8
164.7 360.2 20.4 1.159 0.364 0.124 2.187 17.3 OK 21 448.7 170.3
361.0 5.1 1.184 0.380 0.030 2.120 17.2 OK 22 470.7 170.4 365.4 40.2
1.138 0.362 0.236 2.144 17.4 OK 23 491.9 220.3 360.8 41.8 1.181
0.448 0.190 1.638 16.9 OK 24 500.6 270.2 360.5 9.9 1.260 0.540
0.037 1.334 16.8 OK 25 516.9 270.4 361.8 39.7 1.223 0.523 0.147
1.338 16.7 OK 26 502.1 364.9 312.3 14.7 1.349 0.727 0.040 0.856
16.6 OK 27 407.5 421.8 189.1 14.9 1.499 1.035 0.035 0.448 16.6 OK
28 445.8 493.3 179.3 39.7 1.509 1.107 0.080 0.363 16.5 OK 29 483.7
632.0 160.1 15.2 1.638 1.307 0.024 0.253 16.4 OK 30 520.0 643.4
190.7 15.2 1.604 1.237 0.024 0.296 16.4 OK 31 486.4 685.3 121.1
45.3 1.658 1.409 0.066 0.177 16.4 OK 32 507.2 742.7 120.8 30.1
1.702 1.464 0.041 0.163 16.4 OK 33 515.2 773.9 118.2 20.1 1.732
1.502 0.026 0.153 16.4 OK 34 524.5 798.2 116.9 16.9 1.745 1.522
0.021 0.146 16.3 OK 35* 533.4 832.4 109.8 14.8 1.766 1.561 0.018
0.132 16.3 NG 36* 533.3 841.1 105.3 14.9 1.775 1.577 0.018 0.125
16.3 NG 37* 534.1 849.7 101.2 16.1 1.780 1.591 0.019 0.119 16.3 NG
*indicates comparative example
[0153] Data in Table 2 was obtained by measuring dimensions of
sections of the central portion of the ceramic body 12 of the
laminated chip capacitor 10 taken in the length direction (L) and
the thickness direction (T) from the central portion of the ceramic
body 12 in the width (W) direction as shown in FIG. 3, based on
images taken by a scanning electron microscope (SEM).
[0154] Here, as described above, A was defined to be half of the
overall thickness of the ceramic body, B was defined to be a
thickness of the lower cover layer, C was defined to be half of the
overall thickness of the active layer, and D was defined to be a
thickness of the upper cover layer.
[0155] In order to measure acoustic noise, a single sample
(laminated chip capacitor) per board for measuring acoustic noise
was discriminated in a vertical direction and mounted on a PCB, and
then, the board was mounted in a measurement jig. Thereafter, a DC
voltage and varied voltages were applied to both terminals of the
sample mounted in the measurement jig by using a power DC power
supply and a signal generator (or a function generator). Acoustic
noise was measured through a microphone installed directly above
the PCB.
[0156] In Table 2, samples 1 to 3 were comparative examples having
symmetrical cover structure which means that the thickness (B) of
the lower cover layer is almost similar to the thickness (D) of the
upper cover layer. Samples 4 to 13 were comparative examples having
a structure that the thickness (D) of the upper cover layer is
thicker than the thickness (B) of the lower cover layer. Samples
14, 15 and 35 to 37 were comparative examples having a structure
that the thickness (B) of the lower cover layer is thicker than the
thickness (D) of the upper cover layer. Samples 16 to 34 were
embodiments of the present invention.
[0157] Embodiments of the present invention may have the upper
cover layer 53 whose thickness (D) is the same to or thicker than 4
.mu.m. If the thickness (D) of the upper cover layer is thinner
than 4 .mu.m, the internal electrode may be exposed from the upper
surface S.sub.T of the ceramic body 12, resulting in a defective
product.
[0158] The case that (B+C)/A is the same as or similar to 1 means
that the central portion of the active layer is hardly deviated
from the central portion of the ceramic body. (B+C)/A of the sample
1 to 3 having the symmetrical cover structure (that is, the
thickness (B) of the lower cover layer is almost similar to the
thickness (D) of the upper cover layer) is nearly 1.
[0159] The case that (B+C)/A is more than 1 may mean that the
central portion of the active layer is deviated upward from the
central portion of the ceramic body, and the case of (B+C)/A
smaller than 1 may mean that the central portion of the active
layer is deviated downward from the central portion of the ceramic
body.
[0160] First, it can be seen that, samples 16 to 34, i.e.,
embodiments of the present invention, in which the ratio ((B+C)/A)
by which the central portion of the active layer deviates from the
central portion of the ceramic body satisfied
1.063.ltoreq.(B+C)/A.ltoreq.1.745, had drastically reduced acoustic
noise less than 20 dB.
[0161] Samples 1 to 15, in which the ratio ((B+C)/A) by which the
central portion of the active layer deviates from the central
portion of the ceramic body was less than 1.063, had a structure
that the central portion of the active layer is hardly deviated
from the central portion of the ceramic body or deviated downward
from the central portion of the ceramic body. It can be seen that
samples 1 to 15 in which the ratio (B+C)/A was less than 1.063 did
not have an acoustic noise reduction effect.
[0162] Samples 35 to 37, in which the ratio (B+C)/A was more than
1.745, had a lack of capacitance. That the capacitance of samples
35 to 37 is significantly lower than a target capacitance. In Table
2, "NG" of the "obtainment of Cap." (i.e., a rate of the
capacitance of sample relative to a target capacitance means that
the capacitance of sample is less than 80% of the target
capacitance, when the target capacitance is 100%.
[0163] Also, it can be seen that embodiments in which a ratio (D/B)
of the thickness (D) of the upper cover layer to the thickness (B)
of the lower cover layer satisfied 0.021.ltoreq.D/B.ltoreq.0.422
had considerably reduced acoustic noise.
[0164] Comparative examples in which the ratio (D/B) of the
thickness (D) of the upper cover layer to the thickness (B) of the
lower cover layer was more than 0.422, did not have an acoustic
noise reduction effect. If the ratio D/B is less than 0.21, the
thickness (B) of the lower cover layer is too thicker than the
thickness (D) of the upper cover layer, such that crack or
unacceptable delamination may occur, or lack of capacitance may
occur.
[0165] It can be seen that samples 19 to 34, which are a portion of
embodiments in which the ratio (B/A) of the thickness (B) of the
lower cover layer to the half (A) of the thickness of the ceramic
body satisfied 0.329.ltoreq.B/A.ltoreq.1.522 or the ratio (C/B) of
the half (C) of the thickness of the active layer to the thickness
(B) of the lower cover layer satisfied
0.146.ltoreq.C/B.ltoreq.2.458, had relatively further reduced
acoustic noise less than 18 dB.
[0166] Samples 35 to 37, in which the ratio (B/A) of the thickness
(B) of the lower cover layer to the half (A) of the thickness of
the ceramic body was more than 1.522 or the ratio (C/B) of the half
(C) of the thickness of the active layer to the thickness (B) of
the lower cover layer was less than 0.146, had a lack of
capacitance.
[0167] As set forth above, in the case of the laminated chip
capacitor and the board for mounting the same according to
embodiments of the invention, acoustic noise can be remarkably
reduced.
[0168] While the present invention has been shown and described in
connection with the embodiments, it will be apparent to those
skilled in the art that modifications and variations can be made
without departing from the spirit and scope of the invention as
defined by the appended claims.
* * * * *