U.S. patent application number 14/086101 was filed with the patent office on 2014-03-20 for passive switched-capacitor filters conforming to power constraint.
This patent application is currently assigned to QUALCOMM Incorporated. The applicant listed for this patent is QUALCOMM Incorporated. Invention is credited to Joseph Patrick Burke, Chengzhi Pan.
Application Number | 20140082040 14/086101 |
Document ID | / |
Family ID | 42097385 |
Filed Date | 2014-03-20 |
United States Patent
Application |
20140082040 |
Kind Code |
A1 |
Pan; Chengzhi ; et
al. |
March 20, 2014 |
Passive switched-capacitor filters conforming to power
constraint
Abstract
Passive switched-capacitor (PSC) filters are described herein.
In one design, a PSC filter implements a second-order infinite
impulse response (IIR) filter with two complex first-order IIR
sections. Each complex first-order IIR section includes three sets
of capacitors. A first set of capacitors receives a real input
signal and an imaginary delayed signal, stores and shares
electrical charges, and provides a real filtered signal. A second
set of capacitors receives an imaginary input signal and a real
delayed signal, stores and shares electrical charges, and provides
an imaginary filtered signal. A third set of capacitors receives
the real and imaginary filtered signals, stores and shares
electrical charges, and provides the real and imaginary delayed
signals. In another design, a PSC filter implements a finite
impulse response (FIR) section and an IIR section for a complex
first-order IIR section. The IIR section includes multiple complex
filter sections operating in an interleaved manner.
Inventors: |
Pan; Chengzhi; (San Diego,
CA) ; Burke; Joseph Patrick; (Glenview, IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
QUALCOMM Incorporated |
San Diego |
CA |
US |
|
|
Assignee: |
QUALCOMM Incorporated
San Diego
CA
|
Family ID: |
42097385 |
Appl. No.: |
14/086101 |
Filed: |
November 21, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12366363 |
Feb 5, 2009 |
|
|
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14086101 |
|
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Current U.S.
Class: |
708/819 |
Current CPC
Class: |
H03H 15/023 20130101;
H03H 19/004 20130101; H03H 2007/0192 20130101; H03H 17/0248
20130101 |
Class at
Publication: |
708/819 |
International
Class: |
H03H 19/00 20060101
H03H019/00 |
Claims
1. A method comprising: obtaining multiple coefficients for a
filter transfer function; scaling at least one of the multiple
coefficients based on a power constraint for a passive
switched-capacitor (PSC) filter; and implementing the PSC filter
based on the at least one scaled coefficient to obtain the filter
transfer function.
2. The method of claim 1, wherein the filter transfer function is
for a finite impulse response (FIR) filter, and wherein the scaling
at least one of the multiple coefficients comprises determining a
scaling factor based on magnitude of each of the multiple
coefficients, and scaling each of the multiple coefficients based
on the scaling factor to obtain a corresponding scaled
coefficient.
3. The method of claim 2, wherein the filter transfer function is
for a second-order FIR filter, and wherein the power constraint
comprises |b.sub.0'|+|b.sub.1'|+|b.sub.2'|=1, where b.sub.0'',
b.sub.1' and b.sub.2' are three scaled coefficients for the
second-order FIR filter.
4. The method of claim 1, wherein the filter transfer function is
for an infinite impulse response (IIR) filter, and wherein the
scaling at least one of the multiple coefficients comprises
replacing one of the multiple coefficients with a new coefficient
determined based on magnitude of each remaining coefficient.
5. The method of claim 4, wherein the filter transfer function is
for a second-order IIR filter, and wherein the power constraint
comprises |c.sub.0'|+|c.sub.1|+|c.sub.2|=1, where c.sub.0' is the
new coefficient and c.sub.1 and c.sub.2 are two coefficients for
the second-order IIR filter.
6. An apparatus comprising: means for obtaining multiple
coefficients for a filter transfer function; means for scaling at
least one of the multiple coefficients based on a power constraint
for a passive switched-capacitor (PSC) filter; and means for
implementing the PSC filter based on the at least one scaled
coefficient to obtain the filter transfer function.
7. The apparatus of claim 6, wherein the filter transfer function
is for a finite impulse response (FIR) filter, and wherein the
means for scaling at least one of the multiple coefficients
comprises means for determining a scaling factor based on magnitude
of each of the multiple coefficients, and means for scaling each of
the multiple coefficients based on the scaling factor to obtain a
corresponding scaled coefficient.
8. The apparatus of claim 6, wherein the filter transfer function
is for an infinite impulse response (IIR) filter, and wherein the
means for scaling at least one of the multiple coefficients
comprises means for replacing one of the multiple coefficients with
a new coefficient determined based on magnitude of each remaining
coefficient.
9. A computer program product, comprising: a computer-readable
medium comprising: code for causing at least one computer to obtain
multiple coefficients for a filter transfer function; code for
causing the at least one computer to scale at least one of the
multiple coefficients based on a power constraint for a passive
switched-capacitor (PSC) filter; and code for causing the at least
one computer to implement the PSC filter based on the at least one
scaled coefficient to obtain the filter transfer function.
10. A method comprising: decomposing a filter transfer function
into multiple complex first-order filter sections; and implementing
the multiple complex first-order filter sections with multiple
passive switched-capacitor (PSC) filter sections to obtain the
filter transfer function.
11. The method of claim 10, wherein the decomposing the filter
transfer function comprises decomposing the filter transfer
function for a second-order infinite impulse response (IIR) filter
into two complex first-order IIR sections.
12. The method of claim 11, wherein the decomposing the filter
transfer function further comprises determining complex
coefficients for the two complex first-order IIR sections based on
coefficients for the filter transfer function.
13. The method of claim 12, wherein the decomposing the filter
transfer function further comprises determining an input
coefficient for the two complex first-order IIR sections based on
magnitude of real and imaginary parts of the complex
coefficients.
14. A method comprising: decomposing a filter transfer function
into a finite impulse response (FIR) part and an infinite impulse
response (IIR) part; and implementing the FIR part and the IIR part
with passive switched-capacitor (PSC) filter sections to obtain the
filter transfer function.
15. The method of claim 14, wherein the decomposing the filter
transfer function comprises decomposing the filter transfer
function for a complex first-order IIR filter into the FIR part and
the IIR part, and determining a complex coefficient for the IIR
part based on a complex coefficient for the complex first-order IIR
filter.
16. The method of claim 15, wherein the complex coefficient for the
IIR part is p.sup.M, where p is the complex coefficient for the
complex first-order IIR filter and M is an integer greater than
one.
17. The method of claim 14, wherein the decomposing the filter
transfer function comprises partitioning the IIR part into multiple
(M) IIR sections, each IIR section operating at 1/M clock rate, the
M IIR sections being sequentially enabled in M clock cycles.
18. The method of claim 14, wherein the decomposing the filter
transfer function comprises partitioning the IIR part into first
and second IIR sections, the first IIR section being enabled in
even-numbered clock cycles, and the second IIR section being
enabled in odd-numbered clock cycles.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application for patent is a divisional of patent
application Ser. No. 12/366,363 entitled "PASSIVE
SWITCHED-CAPACITOR FILTERS CONFORMING TO POWER CONSTRAINT" filed
Feb. 5, 2009, pending, and assigned to the assignee hereof and
hereby expressly incorporated by reference herein.
BACKGROUND
[0002] I. Field
[0003] The present disclosure relates generally to electronics, and
more specifically to filters.
[0004] II. Background
[0005] Filters are commonly used to filter signals to pass desired
signal components and to attenuate undesired signal components.
Filters are widely used for various applications such as
communication, computing, networking, consumer electronics, etc.
For example, in a wireless communication device such as a cellular
phone, filters may be used to filter a received signal to pass a
desired signal on a specific frequency channel and to attenuate
out-of-band undesired signals and noise. For many applications,
filters that occupy small area and consume low power are highly
desirable.
SUMMARY
[0006] Passive switched-capacitor (PSC) filters that may occupy
smaller area and consume less power are described herein. In one
design, a PSC filter may implement a second-order infinite impulse
response (IIR) filter with two complex first-order IIR sections.
The second-order IIR filter may not meet a power constraint whereas
each complex first-order IIR section may meet the power constraint.
The coefficients for the two complex first-order IIR sections may
be determined based on the coefficients for the second-order IIR
filter, as described below. Each complex first-order IIR section
may be implemented with a PSC filter section comprising multiple
capacitors and multiple switches.
[0007] In another design, a PSC filter may implement one or more
complex filter sections (e.g., two complex first-order IIR
sections) coupled in series. Each complex filter section includes
first, second, and third sets of capacitors. The first set of
capacitors (e.g., capacitors 1024a and 1034a in FIG. 10) receives a
real input signal and an imaginary delayed signal, stores and
shares electrical charges, and provides a real filtered signal. The
second set of capacitors (e.g., capacitors 1024b and 1034b in FIG.
10) receives an imaginary input signal and a real delayed signal,
stores and shares electrical charges, and provides an imaginary
filtered signal. The third set of capacitors (e.g., capacitors 1044
and 1054 in FIG. 10) receives the real and imaginary filtered
signals, stores and shares electrical charges, and provides the
real and imaginary delayed signals. Each complex filter section
further includes first, second, third and fourth sets of switches.
The first set of switches couples the first set of capacitors to a
first summing node. The second set of switches couples the second
set of capacitors to a second summing node. The third set of
switches couples the third set of capacitors to the first summing
node. The fourth set of switches couples the third set of
capacitors to the second summing node. Each capacitor stores a
value from an associated summing node when selected for charging
and shares electrical charge with other capacitors via the
associated summing node when selected for charge sharing.
[0008] In yet another design, a PSC filter may implement a finite
impulse response (FIR) section coupled to an IIR section, which may
be for a complex first-order IIR filter. The FIR section receives
and filters a complex input signal and provides a complex filtered
signal. The IIR section receives and filters the complex filtered
signal and provides a complex output signal. The FIR and IIR
sections may be implemented with two PSC filter sections. Each PSC
filter section may include a bank of complex filter sections that
may be enabled in different clock cycles.
[0009] In yet another design, a PSC filter section includes first
and second complex filter sections and may be used for the FIR or
IIR section described above. The first complex filter section
receives and filters a complex input signal and provide a complex
output signal every M clock cycles, where M is greater than one.
The second complex filter section receives and filters the complex
input signal and provides the complex output signal every M clock
cycles. The first and second complex filter sections may be enabled
in different clock cycles. For example, with M=2, the first complex
filter section may be enabled in even-numbered clock cycles, and
the second complex filter section may be enabled in odd-numbered
clock cycles.
[0010] Various aspects and features of the disclosure are described
in further detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 shows a block diagram of a second-order FIR
filter.
[0012] FIG. 2 shows a PSC filter that implements the second-order
FIR filter.
[0013] FIG. 3 shows a timing diagram for the PSC filter in FIG.
2.
[0014] FIG. 4 shows a block diagram of a second-order IIR
filter.
[0015] FIG. 5 shows a PSC filter that implements the second-order
IIR filter.
[0016] FIG. 6 shows a timing diagram for the PSC filter in FIG.
5.
[0017] FIG. 7 shows a process for designing a PSC filter with
coefficient scaling.
[0018] FIG. 8 shows filtering with complex second-order IIR
filters.
[0019] FIG. 9 shows a block diagram of a complex first-order IIR
section.
[0020] FIG. 10 shows a PSC filter that implements the complex
first-order IIR section.
[0021] FIG. 11 shows a timing diagram for the PSC filter in FIG.
10.
[0022] FIG. 12 shows a PSC filter that implements two complex
first-order IIR sections.
[0023] FIG. 13 shows a process for designing a PSC filter with
decomposition.
[0024] FIG. 14 shows a complex first-order IIR section implemented
with a FIR filter bank and an IIR filter bank.
[0025] FIG. 15 shows a PSC filter that implements the IIR filter
bank in FIG. 14.
[0026] FIG. 16 shows a plot of pole movement due to filter bank
transformation.
[0027] FIG. 17 shows a process for designing a PSC filter with
filter bank transformation.
[0028] FIG. 18 shows a plot of a function affecting power
constraint.
[0029] FIG. 19 shows a process for designing an IIR filter to meet
power constraint.
[0030] FIG. 20 shows a block diagram of a wireless communication
device.
DETAILED DESCRIPTION
[0031] The PSC filters described herein may be used for various
types of filters such as FIR filters, IIR filters, auto regressive
moving average (ARMA) filters composed of FIR and IIR sections,
etc. The PSC filters may also implement a filter of any order,
e.g., first, second, third or higher order. Multiple PSC filter
sections may be used to form more complex filters. For clarity, PSC
filters for second-order FIR filter and for first-order and
second-order IIR filters are described in detail below.
[0032] A PSC filter may be implemented with only capacitors and
switches, without using active circuits. This may provide certain
advantages described below. However, due to the passive nature of
the PSC filter, not all filter transfer functions may be directly
implementable with the PSC filter. The PSC filter can implement a
filter transfer function that meets a power constraint. Various
schemes to meet the power constraint are described below and are
based on observation that the total electrical charges before and
after each charge sharing operation in the PSC circuit should be
keep constant. This implies that a FIR filter is implementable if
its coefficients are scaled so that they sum to 1. For an IIR
filter, several schemes for meeting the power constraint are
described below and include coefficient scaling, complex filter
section decomposition, filter bank transformation, and pole
repositioning.
[0033] FIG. 1 shows a block diagram of a second-order FIR filter
100 that may be implemented with a PSC filter. FIR filter 100
includes two delay elements 112 and 114 coupled in series, with
each delay element providing a delay of one clock cycle. Delay
element 112 receives an input sample x(n) and provides a delayed
sample x(n-1). Delay element 114 receives the delayed sample x(n-1)
and provides a delayed sample x(n-2). FIR filter 100 includes two
FIR taps 1 and 2 for second order. A multiplier 120 (which may be
considered as being for FIR tap 0) is coupled to the input of delay
element 112. A multiplier 122 for FIR tap 1 is coupled to the
output of delay element 112. A multiplier 124 for FIR tap 2 is
coupled to the output of delay element 114. Multipliers 120, 122
and 124 multiply their samples with filter coefficients b.sub.0,
b.sub.1 and b.sub.2, respectively. A summer 130 is coupled to the
outputs of all three multipliers 120, 122 and 124. Summer 130 sums
the outputs of multipliers 120, 122 and 124 and provides an output
sample y(n).
[0034] The output sample y(n) from FIR filter 100 may be expressed
as:
y(n)=b.sub.0x(n)+b.sub.1x(n-1)+b.sub.2x(n-2). Eq (1)
[0035] A transfer function H.sub.FIR(z) for FIR filter 100 in the
z-domain may be expressed as:
H.sub.FIR(z)=b.sub.0+b.sub.1z.sup.-1+b.sub.2z.sup.-2, Eq (2)
[0036] where z.sup.-k denotes a delay of k clock cycles.
[0037] The filter coefficients may be defined to meet the following
power constraint for FIR filter:
|b.sub.0|+|b.sub.1|+|b.sub.2|=1. Eq (3)
[0038] If coefficients b.sub.0, b.sub.1 and b.sub.2 do not meet the
power constraint in equation (3), then the coefficients may be
scaled as follows:
b.sub.0'=K.sub.FIRb.sub.0, Eq (4a)
b.sub.1'=K.sub.FIRb.sub.1,and Eq (4b)
b.sub.2'=K.sub.FIRb.sub.2, Eq (4c)
where
K FIR = 1 b 0 + b 1 + b 2 ##EQU00001##
is a scaling factor.
Eq (4d)
[0039] The scaling in equation set (4) results in the scaled
coefficients meeting the power constraint, as follows:
|b.sub.0'|+|b.sub.1'|+|b.sub.2'|=1. Eq (5)
[0040] Any set of FIR filter coefficients may be scaled to meet the
power constraint in equation (5). The power constraint may also be
referred to as an absolute magnitude sum constraint. The FIR filter
may be implemented with the scaled coefficients and may generate
scaled output sample y'(n), which may be expressed as:
y'(n)=b.sub.0'x(n)+b.sub.1'x(n-1)+b.sub.2'x(n-2)=K.sub.FIRy(n). Eq
(6)
[0041] In many cases, y'(n) may be used in place of y(n). However,
in cases where signal level plays a non-trivial role (e.g., to
avoid signal saturation), the K.sub.FIR scaling factor may be
increased or decreased. Active devices such as amplifiers may be
used to increase K.sub.FIR. A switching pattern may be adjusted to
reduce K.sub.FIR.
[0042] FIG. 2 shows a schematic diagram of a design of a PSC filter
200 that implements second-order FIR filter 100 in FIG. 1. PSC
filter 200 includes an input section 220 and two tap sections 230
and 240 for FIR taps 1 and 2, respectively, of FIR filter 100.
Within PSC filter 200, an input switch 212 has one end receiving an
input signal V.sub.in and the other end coupled to a summing node
A. A reset switch 214 is coupled between the summing node and
circuit ground. An output switch 216 has one end coupled to the
summing node and the other end providing an output signal
V.sub.out. Switches 212, 214 and 216 may be implemented with metal
oxide semiconductor (MOS) transistors or other types of transistors
or switches.
[0043] Input section 220 includes an input capacitor 224 coupled
between the summing node and circuit ground. Tap section 230
includes two switches 232a and 232b coupled in series with two
capacitors 234a and 234b, respectively. Both series combinations of
switch 232 and capacitor 234 are coupled between the summing node
and circuit ground. Tap section 240 includes three switches 242a,
242b and 242c coupled in series with three capacitors 244a, 244b
and 244c, respectively. All three series combinations of switch 242
and capacitor 244 are coupled between the summing node and circuit
ground.
[0044] All capacitor(s) in each section have the same
capacitance/size, which is determined by the corresponding filter
coefficient. The capacitances of the capacitors in the three
sections of PSC filter 200 may be given as:
C.sub.00=Kb.sub.0', Eq (7a)
C.sub.10=C.sub.11=Kb.sub.1',and Eq (7b)
C.sub.20=C.sub.21=C.sub.22=Kb.sub.2', Eq (7c)
where C.sub.ij is the capacitance of the j-th capacitor in the
section for FIR tap i, and
[0045] K is a scaling constant.
[0046] As shown in equation set (7), the size of each capacitor
C.sub.ij is proportional to the corresponding scaled coefficient
b.sub.i'. K may be selected based on various factors such as
switching settling time, capacitor size, power dissipation, noise,
etc. A negative capacitor for a negative coefficient may be
obtained by switching the polarity of the capacitor between a read
phase and a charge sharing phase.
[0047] In each clock cycle, switch 212 is closed for a brief period
of time to charge one capacitor in each section with the V.sub.in
signal. The capacitor selected for charging in each tap section is
determined by switches 232 and 242, as described below. The total
input capacitance observed by the V.sub.in signal for the charge
operation may be expressed as:
C.sub.in=C.sub.00+C.sub.1u+C.sub.2v, Eq (8)
where u.epsilon.{0, 1} is an index of the capacitor selected for
charging in tap section 230, and
[0048] v.epsilon.{0, 1, 2} is an index of the capacitor selected
for charging in tap section 240.
[0049] Since the capacitors in each tap section have the same
capacitance, the total input capacitance C.sub.in is constant for
each clock cycle.
[0050] In each clock cycle, an appropriate capacitor in each tap
section is used to generate the V.sub.out signal. For FIR tap L,
the capacitor charged L clock cycles earlier and storing x(n-L) is
selected for use via its associated switch. The two selected
capacitors in tap sections 230 and 240 and input capacitor 224 are
used in a charge sharing operation that implements the
multiplications with filter coefficients b.sub.0' through b.sub.2'
and the summing of the multiplier outputs in equation (6).
[0051] The charge sharing operation uses capacitor size to achieve
multiplication with a filter coefficient and current summing to
achieve summing of the multiplier outputs. For each capacitor
within PSC filter 200, the voltage V.sub.ij across that capacitor
is determined by the V.sub.in signal at the time the capacitor is
charged, or V.sub.ij=V.sub.in. The electrical charge Q.sub.ij
stored by each capacitor is determined by the voltage V.sub.ij
across that capacitor and the capacitance C.sub.ij of the
capacitor, or Q.sub.ij=V.sub.ijC.sub.ij. In each clock cycle, one
capacitor storing the proper sample x(n-1) from each tap section is
selected, and the charges from all selected capacitors as well as
input capacitor 224 are shared. The charge sharing for the FIR
filter may be expressed as:
V out = C 00 V 00 + C 1 p V 1 p + C 2 q V 2 q C 00 + C 1 p + C 2 q
, Eq ( 9 ) ##EQU00002## [0052] where p.epsilon.{0, 1} is an index
of the capacitor storing x(n-1) in tap section 230, and
q.epsilon.{0, 1, 2} is an index of the capacitor storing x(n-2) in
tap section 240.
[0053] Since the capacitors in each tap section have the same
capacitance, the total output capacitance C.sub.out observed by the
V.sub.out signal is constant for each clock cycle and is equal to
the total input capacitance, or C.sub.out=C.sub.in.
[0054] Index p can cycle between 0 and 1, so that in each clock
cycle one capacitor 234 in tap section 230 is charged, and the
other capacitor 234 is used for charge sharing. Index q can cycle
from 0 through 2, so that in each clock cycle one capacitor 244 in
tap section 240 is charged, and another capacitor 244 is used for
charge sharing. PSC filter 200 may be considered as having six
states for the six different (p, q) combinations.
[0055] FIG. 3 shows a timing diagram of various control signals for
PSC filter 200 in FIG. 2. A clock signal CLK is shown at the top of
the timing diagram. Control signals for the switches within PSC
filter 200 are shown below the clock signal.
[0056] In the design shown in FIG. 3, each clock cycle includes a
read/charge phase, a compute/charge sharing phase, a write/output
phase, and a reset/discharge phase. For the read phase from time
T.sub.0 to time T.sub.1, the S.sub.in control signal is asserted,
switch 212 is closed, and input capacitor C.sub.00 and one
capacitor in each tap section are charged with the V.sub.in signal.
The S.sub.ij control signal for each capacitor selected for
charging is asserted during the read phase and de-asserted at time
T.sub.2. For the charge sharing phase starting at time T.sub.3, the
S.sub.ij control signal for each capacitor selected for charge
sharing is asserted, and the selected capacitors in sections 230
and 240 as well as capacitor C.sub.00 perform charge sharing via
the summing node. For the write phase from time T.sub.4 to time
T.sub.5, the S.sub.out control signal is asserted, switch 216 is
closed, and the voltage at the summing node is provided as the
K.sub.out signal. For the reset phase from time T.sub.6 to time
T.sub.7, the S.sub.reset control signal is asserted, switch 214 is
closed, and the capacitors used for charge sharing are
reset/discharged. These capacitors may be charged with the V.sub.in
signal in the next clock cycle.
[0057] FIG. 4 shows a block diagram of a second-order IIR filter
400 that may be implemented with a PSC filter. Within IIR filter
400, a multiplier 420 receives and scales an input sample x(n) with
a filter coefficient c.sub.0. A summer 430 subtracts the output of
a summer 432 from the output of multiplier 420 and provides an
output sample y(n).
[0058] Two delay elements 412 and 414 are coupled in series, with
each delay element providing a delay of one clock cycle. Delay
element 412 receives the output sample y(n) and provides a delayed
sample y(n-1). Delay element 414 receives delayed sample y(n-1) and
provides a delayed sample y(n-2). IIR filter 400 includes two IIR
taps 1 and 2 for second order. A multiplier 422 for IIR tap 1 is
coupled to the output of delay element 412. A multiplier 424 for
IIR tap 2 is coupled to the output of delay element 414.
Multipliers 422 and 424 multiply their samples with filter
coefficients c.sub.1 and c.sub.2, respectively, for the two IIR
taps. Summer 432 sums the outputs of multipliers 422 and 424 and
provides its output to summer 430.
[0059] The output sample y(n) from IIR filter 400 may be expressed
as:
y(n)=c.sub.0x(n)-c.sub.1y(n-1)-c.sub.2y(n-2). Eq (10)
[0060] A transfer function H.sub.IIR(z) for IIR filter 400 may be
expressed as:
H IIR ( z ) = c 0 1 + c 1 z - 1 + c 2 z - 2 . Eq ( 11 )
##EQU00003##
[0061] FIG. 5 shows a schematic diagram of a design of a PSC filter
500 that implements second-order IIR filter 400 in FIG. 4. PSC
filter 500 includes an input section 520 and two tap sections 530
and 540 for IIR taps 1 and 2, respectively, of IIR filter 400.
Within PSC filter 500, an input switch 512 has one end receiving an
input signal V.sub.in and the other end coupled to a summing node
A. A reset switch 514 is coupled between the summing node and
circuit ground. An output switch 516 has one end coupled to the
summing node and the other end providing an output signal
V.sub.out.
[0062] Input section 520 includes a capacitor 524 coupled between
the summing node and circuit ground. Tap section 530 includes a
switch 532 coupled in series with a capacitor 534, the combination
of which is coupled between the summing node and circuit ground.
Tap section 540 includes two switches 542a and 542b coupled in
series with two capacitors 544a and 544b, respectively. Both series
combinations of switch 542 and capacitor 544 are coupled between
the summing node and circuit ground. Capacitors 534 and 544 in tap
sections 530 and 540 may be reset at the start of filtering
operation.
[0063] All capacitor(s) in each section of PSC filter 500 have the
same capacitance, which is determined by the corresponding filter
coefficient. The capacitances of the capacitors in the three
sections of PSC filter 500 may be given as:
C.sub.00=Kc.sub.0, Eq (12a)
C.sub.10=Kc.sub.1,and Eq (12b)
C.sub.20=C.sub.21=Kc.sub.2. Eq (12c)
[0064] As shown in equation set (12), the size of each capacitor
C.sub.ij is proportional to the magnitude of the corresponding
filter coefficient c.sub.1. A negative capacitor for a negative
coefficient may be obtained by switching the polarity of the
capacitor between the read phase and the charge sharing phase.
[0065] In each clock cycle, switch 512 is closed for a brief period
of time to charge capacitor 524 in section 520 with the V.sub.in
signal. The total input capacitance observed by the V.sub.in signal
is thus C.sub.in=C.sub.00, and no extra capacitors are needed for
C.sub.in.
[0066] In each clock cycle, an appropriate capacitor in each tap
section is used to generate the V.sub.out signal. For IIR tap L,
the capacitor charged L clock cycles earlier and storing y(n-L) is
selected for use via its associated switch. Two selected capacitors
in tap sections 530 and 540 as well as input capacitor 524 are used
in a charge sharing operation that implements the multiplications
with filter coefficients c.sub.0 through c.sub.2 and the summing of
the multiplier outputs in equation (10). The charge sharing for the
IIR filter may be expressed as:
V out = C 00 V 00 + C 10 V 10 + C 2 k V 2 k C 00 + C 10 + C 2 k ,
Eq ( 13 ) ##EQU00004##
where k.epsilon.E{0, 1} is an index of the capacitor storing y(n-2)
in tap section 540.
[0067] After completing the charge sharing, the voltage across
capacitors C.sub.00, C.sub.10 and C.sub.2k corresponds to y(n).
Capacitors C.sub.10 and C.sub.2k may store y(n) for use in
subsequent clock cycles. Capacitor C.sub.00 may provide y(n) for
the V.sub.out signal. The total output capacitance observed by the
V.sub.out signal is C.sub.out=C.sub.00, and no extra capacitors are
needed for C.sub.out.
[0068] Index k can cycle between 0 and 1, so that each capacitor
544 in tap section 540 is used for charge sharing in alternating
clock cycle. PSC filter 500 may be considered as having two states
for the two possible values of k.
[0069] FIG. 6 shows a timing diagram of various control signals for
PSC filter 500 in FIG. 5. The clock signal CLK is shown at the top
of the timing diagram. Control signals for the switches within PSC
filter 500 are shown below the clock signal.
[0070] In the design shown in FIG. 6, each clock cycle includes a
read phase, a charge sharing phase, a write phase, and a reset
phase. For the read phase from time T.sub.0 to time T.sub.1, the
S.sub.in control signal is asserted, switch 512 is closed, and
input capacitor C.sub.00 is charged with the V.sub.in signal. For
the charge sharing phase from time T.sub.2 to time T.sub.3, the
S.sub.ij control signal for each capacitor selected for charge
sharing is asserted, and the selected capacitors as well as input
capacitor C.sub.00 perform charge sharing via the summing node. At
the end of the charge sharing phase, the S.sub.ij control signal
for each selected capacitor is de-asserted at time T.sub.3, which
then causes that capacitor to store y(n). For the write phase from
time T.sub.4 to time T.sub.5, the S.sub.out control signal is
asserted, switch 516 is closed, and capacitor C.sub.00 provides
y(n) to the V.sub.out signal. For the reset phase from time T.sub.6
to time T.sub.7, the S.sub.reset control signal is asserted, switch
514 is closed, and capacitor C.sub.00 is reset.
[0071] The coefficients for the second-order IIR filter may be
defined to meet the following power constraint for IIR filter:
|c.sub.0|+|c.sub.1|c.sub.2|=1. Eq (14)
If coefficients c.sub.0', c.sub.1 and c.sub.2 do not meet the power
constraint in equation (14), then several schemes may be used meet
the power constraint.
[0072] In a first scheme for meeting the power constraint for IIR
filter, if |c.sub.1|+|c.sub.2|<1, then a scaled coefficient
c.sub.0' may be computed as follows:
c.sub.0'=1-|c.sub.1|-|c.sub.2|. Eq (15)
[0073] The coefficients c.sub.0', c.sub.1 and c.sub.2 meet the
power constraint for IIR filter, as follows:
|c.sub.0'|+|c.sub.1|+|c.sub.2|=1. Eq (16)
[0074] The IIR filter may be implemented with coefficients
c.sub.0', c.sub.1 and c.sub.2 and may generate output sample y'(n),
which may be expressed as:
y'(n)=c.sub.0'x(n)-c.sub.1y(n-1)-c.sub.2y(n-2). Eq (17)
[0075] The transfer function with coefficients c.sub.0', c.sub.1
and c.sub.2 may be expressed as:
H IIR ' ( z ) = c 0 ' c 0 H IIR ( z ) = 1 - c 1 - c 2 c 0 H IIR ( z
) . Eq ( 18 ) ##EQU00005##
[0076] FIG. 7 shows a process 700 for designing a PSC filter with
coefficient scaling to meet the power constraint. Multiple
coefficients for a filter transfer function may be obtained (block
712). At least one of the multiple coefficients may be scaled based
on a power constraint for the PSC filter (block 714). The PSC
filter may then be implemented based on the at least one scaled
coefficient to obtain the filter transfer function (block 716).
[0077] In one design, the filter transfer function may be for a FIR
filter, e.g., a second-order FIR filter having the power constraint
shown in equation (3). In this design, a scaling factor K.sub.m may
be determined based on the magnitude of each of the multiple
coefficients, e.g., as shown in equation (4d). Each of the multiple
coefficients may then be scaled based on the scaling factor to
obtain a corresponding scaled coefficient, e.g., as shown in
equations (4a) through (4c).
[0078] In another design, the filter transfer function may be for
an IIR filter, e.g., a second-order IIR filter having the power
constraint shown in equation (14). In this design, one of the
multiple coefficients may be replaced with a new coefficient
determined based on magnitude of each remaining coefficient, e.g.,
as shown in equation (15).
[0079] In a second scheme for meeting the power constraint for IIR
filter, if |c.sub.1|+|c.sub.2|.gtoreq.1, then the second-order IIR
filter may be decomposed into two first-order IIR sections.
Lower-order IIR sections often (but not always) result in smaller
coefficients, which may allow the power constraint to be met.
[0080] The decomposition of a second-order FIR section may be
expressed as:
1 + c 1 z - 1 + c 2 z - 2 = ( 1 - p z - 1 ) ( 1 - p * z - 1 ) = ( 1
- ( p re + j p im ) z - 1 ) ( 1 - ( p re - j p im ) z - 1 ) Eq ( 19
) ##EQU00006##
where p=p.sub.re+j p.sub.im is a complex coefficient,
c.sub.1=-2p.sub.re, c.sub.2=p.sub.re.sup.2+p.sub.im.sup.2, and "*"
denotes a complex conjugate.
[0081] As shown in equation (19), the decomposition of a
second-order FIR section typically produces two complex first-order
FIR sections with conjugated coefficients p and p*.
[0082] The complex coefficient may be tested for the following
power constraint condition:
|p.sub.re|+|p.sub.im|<1. Eq (20)
[0083] If the condition in equation (20) is satisfied, then the
second-order IIR filter in equation (10) may be implemented with
two concatenated complex first-order IIR sections, both of which
meet the power constraint. A complex output sample y'(n) from the
first complex first-order IIR section may be expressed as:
y.sub.re'(n)={tilde over
(c)}.sub.0x.sub.re(n)+p.sub.rey.sub.re'(n-1)-p.sub.imy.sub.im'(n-1),and
Eq (21a)
y.sub.im'(n)={tilde over
(c)}.sub.0x.sub.im(n)+p.sub.rey.sub.im'(n-1)+p.sub.imy.sub.re'(n-1),
Eq (21b)
where
[0084] x(n)=x.sub.re(n)+j x.sub.im(n) is a complex input
sample,
[0085] y'(n)=y.sub.re'(n)+j y.sub.im'(n) is a complex output sample
from the first section, and
[0086] {tilde over (c)}.sub.0 is a scaled coefficient that may be
given as:
{tilde over (c)}.sub.0=1-|p.sub.re|-|p.sub.im|. Eq (22)
[0087] A complex output sample y''(n) from the second complex
first-order IIR section may be expressed as:
y.sub.re''(n)={tilde over
(c)}.sub.0y.sub.re'(n)+p.sub.rey.sub.re''(n-1)+p.sub.imy.sub.im''(n-1),an-
d Eq (23a)
y.sub.im''(n)={tilde over
(c)}.sub.0y.sub.im'(n)+p.sub.rey.sub.im''(n-1)-p.sub.imy.sub.re''),
Eq (23b)
where y''(n)=y.sub.re''(n)+j y.sub.im''(n) is a complex output
sample from the second section.
[0088] As shown in equation sets (21) and (23), the first and
second complex first-order IIR sections have the same coefficients.
The only difference in the two complex first-order IIR sections is
the sign of the samples scaled by p.sub.im.
[0089] As an example, a second-order IIR filter may have
coefficients c.sub.0=1, c.sub.1=-0.25 and c.sub.2=0.75. Since
|c.sub.1|+|c.sub.2|=1, the first scheme for scaling coefficients
does not apply. Using the second scheme, second-order IIR filter
may be decomposed into two complex first-order IIR sections with
p.sub.re=0.125, p.sub.im=0.857, and {tilde over (c)}.sub.0=0.018.
Since |p.sub.re|+|p.sub.im|<1, the two complex first-order IIR
sections meet the power constraint.
[0090] FIG. 8 shows filtering of complex input samples with complex
second-order IIR filters 810 and 830. For IIR filter 810, real
input samples x.sub.re(n) may be filtered with a real second-order
IIR filter 820a, e.g., as shown in equation (10), to obtain real
output samples y.sub.re(n). Imaginary input samples x.sub.im(n) may
be filtered with a real second-order IIR filter 820b to obtain
imaginary output samples y.sub.im(n). IIR filters 820a and 820b
independently filter the real and imaginary parts of the complex
input samples. IIR filters 820a and 820b are identical and have the
same coefficients. However, IIR filters 820a and 820b may not meet
the power constraint and thus may not be directly
implementable.
[0091] For IIR filter 830, the complex input samples x.sub.re(n)
and x.sub.im(n) may be filtered with a complex first-order IIR
section 840a, e.g., as shown in equation set (21), to obtain
complex filtered samples y.sub.re'(n) and y.sub.im'(n). The complex
filtered samples may be further filtered with a complex first-order
IIR section 840b, e.g., as shown in equation set (23), to obtain
complex output samples y.sub.re''(n) and y.sub.im''(n).
[0092] IIR filter 810 composed of two real second-order IIR filters
820a and 820b for the real and imaginary parts is equivalent to IIR
filter 830 composed of two complex first-order IIR sections 840a
and 840b. The complex output samples y.sub.re''(n) and y from IIR
filter 830 are equivalent to the complex output samples
y.sub.re''(n) and y.sub.im''(n) from IIR filter 810. However,
complex first-order IIR sections 840a and 840b may be implementable
whereas real second-order IIR filters 820a and 820b may not be
implementable.
[0093] FIG. 9 shows a block diagram of complex first-order IIR
section 840a, which includes an IIR section 910a for the real part
and an IIR section 910b for the imaginary part. Within IIR section
910a, a multiplier 920a receives and scales a real input sample
x.sub.re(n) with filter coefficient {tilde over (c)}.sub.0. A
summer 930a sums the output of multiplier 920a with the output of a
summer 932a and provides a real output sample y.sub.re'. A delay
element 912a receives the real output sample y.sub.re' (n) and
provides a real delayed sample y.sub.re'(n-1). A multiplier 922a
for IIR tap A is coupled to the output of delay element 912a. A
multiplier 924a for IIR tap B is also coupled to the output of
delay element 912a. Multipliers 922a and 924a multiply the real
delayed sample y.sub.re'(n-1) with filter coefficients p.sub.re and
p.sub.im, respectively, for IIR taps A and B. Summer 932a subtracts
the output of a multiplier 924b in IIR section 910b from the output
of multiplier 922a in IIR section 910a and provides its output to
summer 930a.
[0094] IIR section 910b includes all of the elements in IIR section
910a. The elements in IIR section 910b are coupled in the same way
as the elements in IIR section 910a with the following differences.
A multiplier 922b for IIR tap C and a multiplier 924b for IIR tap D
multiply the imaginary delayed sample y.sub.im'(n-1) from a delay
element 912b with filter coefficients p.sub.re and p.sub.im,
respectively. A summer 932b sums the output of multiplier 924a in
IIR section 910a with the output of multiplier 922b in IIR section
910b and provides its output to a summer 930b.
[0095] Complex first-order IIR section 840b in FIG. 8 may be
implemented in similar manner as complex first-order IIR section
840a in FIG. 8, with the difference being a swamp in the signs of
the outputs of multipliers 924a and 924b.
[0096] FIG. 10 shows a schematic diagram of a design of a PSC
filter 1000 that implements complex first-order IIR section 840a in
FIGS. 8 and 9. PSC filter 1000 includes a path 1010a for the real
part and a path 1010b for the imaginary part. Path 1010a includes
an input section 1020a and a tap section 1030a for IIR tap A of IIR
section 840a in FIG. 9. Path 1010b includes an input section 1020b
and a tap section 1030b for IIR tap C in FIG. 9. Both paths 1010a
and 1010b share a tap section 1040 for IIR taps B and D in FIG.
9.
[0097] Within path 1010a, an input switch 1012a has one end
receiving a real input signal V.sub.in,re and the other end coupled
to a summing node A. A reset switch 1014a is coupled between
summing node A and circuit ground. An output switch 1016a has one
end coupled to summing node A and the other end providing a real
output signal V.sub.out,re. Switches 1012b, 1014b and 1016b in path
1010b are coupled in similar manner as switches 1012a, 1014a and
1016a, respectively, in path 1010a.
[0098] Input section 1020a includes a capacitor 1024a coupled
between summing node A and circuit ground. Tap section 1030a
includes a switch 1032a coupled in series with a capacitor 1034a,
the combination of which is coupled between summing node A and
circuit ground. Input section 1020b and tap section 1030b are
coupled in similar manner between summing node B and circuit
ground. Tap section 1040 includes two switches 1042a and 1052a
having one end coupled to summing node A and the other end coupled
to capacitors 1044 and 1054, respectively. Tap section 1040 further
includes two switches 1042b and 1052b having one end coupled to
summing node B and the other end coupled to capacitors 1044 and
1054, respectively. The other ends of capacitors 1044 and 1054 are
coupled to circuit ground.
[0099] The capacitances of the capacitors in PSC filter 1000 may be
given as:
C.sub.00=C.sub.01=K{tilde over (c)}.sub.0, Eq (24a)
C.sub.10=C.sub.11=K{tilde over (p)}.sub.re,and Eq (24b)
C.sub.20=C.sub.21=Kp.sub.im. Eq (24c)
[0100] For the example above with p.sub.re=0.125, p.sub.im=0.857,
and {tilde over (c)}.sub.0=0.018, the capacitance ratios may be
given as follows:
C.sub.00:C.sub.10;C.sub.10:C.sub.11;C.sub.20:C.sub.21={tilde over
(c)}.sub.0:{tilde over
(c)}.sub.0;p.sub.re:p.sub.re;p.sub.im:p.sub.im=0.018:0.018;0.125:0.125;0.-
857:0.857
[0101] In each clock cycle, switches 1012a and 1012b are closed for
a brief period of time to charge capacitor 1024a in section 1020a
with the V.sub.in,re signal and to charge capacitor 1024b in
section 1020b with the V.sub.in,im signal. In each clock cycle,
capacitor 1024a in section 1020a, capacitor 1034a in section 1030b,
and either capacitor 1044 or 1054 in section 1040 are used in a
charge sharing operation that implements the multiplications with
filter coefficients {tilde over (c)}.sub.0, p.sub.re and p.sub.im,
and the summing of the multiplier outputs in equation (21a). In
each clock cycle, capacitor 1024b in section 1020b, capacitor 1034b
in section 1030b, and either capacitor 1054 or 1044 in section 1040
are used in a charge sharing operation that implements equation
(21b). The charge sharing for the real and imaginary parts may be
expressed as:
V out , re = C 00 V 00 + C 10 V 10 + C 2 k V 2 k C 00 + C 10 + C 2
k , and Eq ( 25 a ) V out , im = C 01 V 01 + C 11 V 11 + C 2 k _ V
2 k _ C 01 + C 11 + C 2 k _ , Eq ( 25 b ) ##EQU00007## [0102] where
k.epsilon.{0, 1} is an index of the capacitor storing
y.sub.im'(n-1) in tap section 1040, and k is an index of the
capacitor storing y.sub.re'(n-1) in tap section 1040.
[0103] After completing the charge sharing, the voltage on summing
node A corresponds to y.sub.re'(n), and the voltage on summing node
B corresponds to y.sub.im'(n). Capacitor 1024a may provide
y.sub.re'(n) for the V.sub.out,re signal, and capacitor 1024b may
provide y.sub.im'(n) for the V.sub.out,im signal. Capacitors 1034a
may store y.sub.re'(n) and capacitor 1034b may store y.sub.im'(n)
for use in the next clock cycle. Capacitors 1044 and 1054 are used
in an interleaved manner to store y.sub.re'(n) and y.sub.im'(n) in
each clock cycle. In each even-numbered clock cycle, capacitor 1044
may be coupled to summing node A, perform charge sharing, and store
the y.sub.re'(n), while capacitor 1054 may be coupled to summing
node B, perform charge sharing, and store the y.sub.im'(n). In each
odd-numbered clock cycle, capacitor 1044 may be coupled to summing
node B, perform charge sharing, and store the y.sub.im'(n), while
capacitor 1054 may be coupled to summing node A, perform charge
sharing, and store the y.sub.re'(n). Capacitor 1044 may thus be
coupled to summing nodes A and B in alternating clock cycles, and
capacitor 1054 may be coupled to summing nodes B and A in
alternating clock cycles. Capacitors 1044 and 1054 have the same
size but are interleaved in time.
[0104] FIG. 6 shows a timing diagram that may be used for the
various control signals for PSC filter 1000 in FIG. 10. For the
read phase from time T.sub.0 to time T.sub.1, the S.sub.in control
signal is asserted, switches 1012a and 1012b are closed, capacitor
C.sub.00 is charged with the V.sub.in,re signal, and capacitor
C.sub.01 is charged with the V.sub.in,im signal. For the charge
sharing phase from time T.sub.2 to time T.sub.3, the S.sub.10
control signal and either the S.sub.20 or S.sub.22 control signal
are asserted, and capacitor C.sub.00, capacitor C.sub.10 and either
capacitor C.sub.20 or C.sub.22 perform charge sharing via summing
node A. Simultaneously, the S.sub.11 control signal and either the
S.sub.21 or S.sub.23 control signal are asserted, and capacitor
C.sub.01, capacitor C.sub.11 and either capacitor C.sub.20 or
C.sub.22 perform charge sharing via summing node B. At the end of
the charge sharing phase, the S.sub.ij control signal for each
selected capacitor is de-asserted at time T.sub.3, which then
causes that capacitor to store y.sub.re'(n) or y.sub.im'(n). For
the write phase from time T.sub.4 to time T.sub.5, the S.sub.out
control signal is asserted, switches 1016a and 1016b are closed,
capacitor C.sub.00 provides y.sub.re'(n) to the V.sub.out,re
signal, and capacitor C.sub.01 provides y.sub.im'(n) to the
V.sub.out,im signal. For the reset phase from time T.sub.6 to time
T.sub.7, the S.sub.reset control signal is asserted, switches 1014a
and 1014b are closed, and capacitors C.sub.00 and C.sub.01 are
reset.
[0105] FIG. 11 shows a timing diagram of a switching pattern for
PSC filter 1000 in FIG. 10. The switching pattern includes two
cycles 0 and 1 for the two possible values of k in equation set
(25) and repeats every two clock cycles. Table 1 shows the two
cycles 0 and 1 and, for each cycle, gives the capacitors used to
generate the V.sub.out,re and V.sub.out,im signals.
TABLE-US-00001 TABLE 1 Cycle Capacitors used to Capacitors used to
k generate V.sub.out, re generate V.sub.out, im 0 C.sub.00,
C.sub.10 and C.sub.20 C.sub.01, C.sub.11 and C.sub.21 1 C.sub.00,
C.sub.10 and C.sub.21 C.sub.01, C.sub.11 and C.sub.20
[0106] For cycle 0, input capacitor C.sub.00 is charged with the
V.sub.in,re signal and capacitor C.sub.01 is charged with the
V.sub.in,im signal when the S.sub.in control signal is asserted
during the read phase. The S.sub.10, S.sub.11, S.sub.20 and
S.sub.23 control signals are asserted during the charge sharing
phase, capacitors C.sub.00, C.sub.10 and C.sub.20 are used to
generate the V.sub.out,re signal, and capacitors C.sub.01, C.sub.11
and C.sub.21 are used to generate the V.sub.out,im signal.
Capacitors C.sub.10 and C.sub.20 store the V.sub.out,re signal and
capacitors C.sub.11 and C.sub.21 store the V.sub.out,im signal at
the end of the charge sharing phase.
[0107] For cycle 1, input capacitor C.sub.00 is charged with the
V.sub.in,re signal and capacitor C.sub.01 is charged with the
V.sub.in,im signal during the read phase. The S.sub.10, S.sub.11,
S.sub.21 and S.sub.22 control signals are asserted during the
charge sharing phase, capacitors C.sub.00, C.sub.10 and C.sub.21
are used to generate the V.sub.out,re signal, and capacitors
C.sub.01, C.sub.11 and C.sub.20 are used to generate the
V.sub.out,im signal. Capacitors C.sub.10 and C.sub.21 store the
V.sub.out,re signal and capacitors C.sub.11 and C.sub.20 store the
V.sub.out,im signal at the end of the charge sharing phase.
[0108] For PSC filter 1000, capacitors C.sub.00 and C.sub.01 are
charged with the V.sub.in,re and V.sub.in,im signals in each clock
cycle and are also used for charge sharing in the same clock cycle.
Capacitors C.sub.10 and C.sub.11 are used for charge sharing in
each clock cycle and store y.sub.re'(n) and y.sub.im'(n) for use in
the next clock cycle. For tap section 1040, index k toggles between
0 and 1, capacitors C.sub.20 and C.sub.21 are used for charge
sharing at nodes A and B in one clock cycle, at nodes B and A in
the following clock cycle, etc.
[0109] Table 2 summarizes the action performed by each capacitor in
PSC filter 1000 in each clock cycle.
TABLE-US-00002 TABLE 2 Clock Cycle n n + 1 n + 2 . . . Capacitor
C.sub.00 store x.sub.re(n) store x.sub.re(n + 1) store x.sub.re(n +
2) . . . x.sub.re(n).fwdarw. y.sub.re(n) x.sub.re(n + 1).fwdarw.
y.sub.re(n + 1) x.sub.re(n + 2).fwdarw. y.sub.re(n + 2) Capacitor
C.sub.01 store x.sub.im(n) store x.sub.im(n + 1) store x.sub.im(n +
2) . . . x.sub.im(n).fwdarw. y.sub.im(n) x.sub.im(n + 1).fwdarw.
y.sub.im(n + 1) x.sub.im(n + 2).fwdarw. y.sub.im(n + 2) Capacitor
C.sub.10 y.sub.re(n - 1).fwdarw. y.sub.re(n) y.sub.re(n).fwdarw.
y.sub.re(n + 1) y.sub.re(n + 1).fwdarw. y.sub.re(n + 2) . . . store
y.sub.re(n) store y.sub.re(n + 1) store y.sub.re(n + 2) Capacitor
C.sub.11 y.sub.im(n - 1).fwdarw. y.sub.im(n) y.sub.im(n).fwdarw.
y.sub.im(n + 1) y.sub.im(n + 1).fwdarw. y.sub.im(n + 2) . . . store
y.sub.im(n) store y.sub.im(n + 1) store y.sub.im(n + 2) Capacitor
C.sub.20 y.sub.im(n - 1).fwdarw. y.sub.re(n) y.sub.re(n).fwdarw.
y.sub.im(n + 1) y.sub.im(n + 1).fwdarw. y.sub.re(n + 2) . . . store
y.sub.re(n) store y.sub.im(n + 1) store y.sub.re(n + 2) Capacitor
C.sub.21 y.sub.re(n - 1).fwdarw. y.sub.im(n) y.sub.im(n).fwdarw.
y.sub.re(n + 1) y.sub.re(n + 1).fwdarw. y.sub.im(n + 2) . . . store
y.sub.im(n) store y.sub.re(n + 1) store y.sub.im(n + 2)
[0110] FIG. 12 shows a schematic diagram of a design of a PSC
filter 1200 that implements complex first-order IIR sections 840a
and 840b in FIG. 8. PSC filter 1200 includes a first PSC filter
section 1210a that implements complex first-order IIR section 840a
and a second PSC filter section 1210b that implements complex
first-order IIR section 840b. Each PSC filter section 1210 includes
all elements in PSC filter 1000 in FIG. 10. The capacitors in tap
section 1040 within PSC filter section 1210a are selected in
different order than the capacitors in tap section 1040 within PSC
filter section 1210b due to the difference between equation sets
(21) and (23).
[0111] FIG. 13 shows a process 1300 for designing a PSC filter with
decomposition. A filter transfer function may be decomposed into
multiple complex first-order filter sections, e.g., as shown in
equation (19) (block 1312). In one design of block 1312, the filter
transfer function is for a second-order IIR filter and may be
decomposed into two complex first-order IIR sections. Complex
coefficients (e.g., p and p*) for the two complex first-order IIR
sections may be determined based on coefficients (e.g., {tilde over
(c)}.sub.1 and c.sub.2) for the second-order IIR filter. An input
coefficient (e.g., c.sub.0) for the two complex first-order IIR
sections may be determined based on the magnitude of the real and
imaginary parts (e.g., p.sub.re and p.sub.im) of the complex
coefficients, e.g., as shown in equation (22). The multiple complex
first-order filter sections may be implemented with multiple PSC
filter sections to obtain the filter transfer function (block
1314).
[0112] The two complex first-order IIR sections obtained by
decomposing a second-order IIR filter may not meet the power
constraint. The complex pole obtained from the decomposition may be
expressed as:
p=p.sub.re+jp.sub.in=re.sup.j.theta., Eq (26)
where r is the magnitude of the pole and .theta. is the phase of
the pole.
[0113] The sum of the magnitude of the real and imaginary parts of
the pole may be expressed as:
.ident.p.sub.re|+|p.sub.im|=r(|cos .theta.|+|sin .theta.|) Eq
(27)
[0114] A necessary and sufficient condition for stability of an IIR
filter is r<1. The power constraint may be met with
|p.sub.re|+|p.sub.im|<1. The term (|cos .theta.|+|sin .theta.|)
may be greater than one depending on the value of .theta.. Thus, it
is possible to have |p.sub.re|+|p.sub.im|.gtoreq.1 even with
r<1, in which case the IIR filter is stable but not directly
implementable.
[0115] In a third scheme for meeting the power constraint for IIR
filter, which may be used when the complex first-order IIR sections
do not meet the power constraint, a complex first-order IIR section
may be implemented with an interleaved filter bank. From equation
set (21), the complex filtered samples from complex first-order IIR
section 840a may be expressed as:
y ' ( n ) = c ~ 0 x ( n ) + p y ' ( n - 1 ) = c ~ 0 x ( n ) + p c ~
0 x ( n - 1 ) + p 2 y ' ( n - 2 ) . Eq ( 28 ) ##EQU00008##
[0116] Two consecutive filtered samples from complex first-order
IIR section 840a may be expressed as:
y'(n)={tilde over (c)}.sub.0x(n)+p{tilde over
(c)}.sub.0x(n-1)+p.sup.2y'(n-2),and Eq (29a)
y'(n+1)={tilde over (c)}.sub.0x(n+1)+p{tilde over
(c)}.sub.0x(n)+p.sup.2y'(n-1). Eq (29b)
[0117] Equation set (29) may be partitioned into an IIR part and a
FIR part. The IIR part may also be referred to as a recursive part
or an autoregressive part. The FIR part may also be referred to as
a non-recursive part. The IIR part may be expressed as:
y'(n)={hacek over (c)}.sub.0{hacek over (x)}(n)+p.sup.2y'(n-2),and
Eq (30a)
y'(n+1)={hacek over (c)}.sub.0{hacek over (x)}(n+1)+p.sup.2y'(n-1),
Eq (30b)
where {hacek over (c)}.sub.0=1| real (p.sup.2)|-|imag (p.sup.2)|
and {hacek over (x)}(n) is the output of the FIR part.
[0118] The FIR part may be expressed as:
{hacek over (x)}(n)={hacek over (c)}.sub.0.sup.-1{tilde over
(c)}.sub.0x(n)+{hacek over (c)}.sub.0.sup.-1{tilde over
(c)}.sub.0px(n-1),and Eq (31a)
{hacek over (x)}(n+1)={hacek over (c)}.sub.0.sup.-1{tilde over
(c)}.sub.0x(n+1)+{hacek over (c)}.sub.0.sup.-1{tilde over
(c)}.sub.0px(n). Eq (31b)
[0119] FIG. 14 shows a block diagram of a complex first-order IIR
section 1400 implemented with a FIR filter bank 1410 and an IIR
filter bank 1420. FIR filter bank 1410 may filter the complex input
samples x.sub.re(n) and x.sub.im(n) as shown in equation set (31)
and provide complex filtered samples {hacek over (x)}.sub.re(n) and
{hacek over (x)}.sub.im(n). IIR filter bank 1420 may filter the
complex filtered samples {hacek over (x)}.sub.re(n) and {hacek over
(x)}.sub.im(n) as shown in equation set (30) and provide complex
output samples y.sub.re'(n) and y.sub.im'(n). FIG. 14 shows a
design with IIR filter bank 1420 being placed after FIR filter bank
1410. In another design, FIR filter bank 1410 may be placed after
IIR filter bank 1420. The order of FIR filter bank 1410 and IIR
filter bank 1420 may be selected based on noise and other
considerations.
[0120] FIG. 15 shows a schematic diagram of a design of a PSC
filter 1500 that implements IIR filter bank 1420 in FIG. 14. PSC
filter 1500 includes a first IIR section 1510a and a second IIR
section 1510b. Each IIR section 1510 includes all elements of PSC
filter 1000 in FIG. 10.
[0121] A real input signal V.sub.in,re is provided to both a switch
1512a in IIR section 1510a and a switch 1512c in IIR section 1510b.
An imaginary input signal V.sub.in,im is provided to both a switch
1512b in IIR section 1510a and a switch 1512d in IIR section 1510b.
A switch 1516a in IIR section 1510a and a switch 1516c in IIR
section 1510b are coupled together and provide a real output signal
V.sub.out,re. A switch 1516b in IIR section 1510a and a switch
1516d in IIR section 1510b are coupled together and provide an
imaginary output signal V.sub.out,im. The other elements within IIR
sections 1510a and 1510b are coupled as described above for FIG.
10.
[0122] IIR section 1510a operates in each even-numbered clock
cycle, filters the V.sub.in,re and V.sub.in,im signals, and
provides the V.sub.out,re and V.sub.out,im signals. IIR section
1510a is disabled during each odd-numbered clock cycle. Conversely,
IIR section 1510b operates in each odd-numbered clock cycle,
filters the V.sub.in,re and V.sub.in,im signals, and provides the
V.sub.out,re and V.sub.out,im signals. IIR section 1510b is
disabled during each even-numbered clock cycle. IIR sections 1510a
and 1510b thus operate in an interleaved manner, with IIR section
1510a operating in one clock cycle, then IIR section 1510b
operating in the next clock cycle, then IIR section 1510a operating
in the following clock cycle, etc. IIR section 1510a operates on
{hacek over (x)}(n) and provides y'(n), as shown in equation (30a).
IIR section 1510b operates on {hacek over (x)}(n+1) and provides
y'(n+1), as shown in equation (30b).
[0123] In one design, a PSC filter for FIR filter bank 1410 in FIG.
14 (which may be a FIR filter) may be implemented in similar manner
as PSC filter 1000 in FIG. 10. However, the switches for the PSC
filter for FIR filter bank 1410 are operated to implement a FIR
filter instead of an IIR filter. In another design, two FIR filter
banks may be merged from two first-order complex IIR filters. The
merged second-order FIR filter has real coefficients and may be
implemented as a normal second-order PSC FIR filter.
[0124] Equation sets (30) and (31) show filter bank transformation
for a case in which IIR filter bank 1420 includes two IIR sections.
In general, the filter bank transformation may be performed for any
value of m or M=2.sup.m to obtain a complex pole at
p.sup.2.sup.m=p.sup.M. The IIR part may be expressed as:
y'(n+i)={hacek over (c)}.sub.0{hacek over
(x)}(n+i)+p.sup.My'(n-M+i),for i=0, . . . ,M-1, Eq (32)
where {hacek over (c)}.sub.0=1|real(p.sup.M)|-imag(p.sup.M)|. Eq
(33)
[0125] A filter bank may thus include M IIR sections. Each IIR
section may be implemented as shown in FIG. 15, may operate at 1/M
of the clock rate, and may be enabled every M clock cycles. The M
IIR sections may be sequentially enabled in M clock cycles, one IIR
section in each clock cycle.
[0126] FIG. 16 shows a plot 1610 of pole movement due to filter
bank transformation with different values of M. An IIR filter is
stable if its pole has a magnitude of r<1 and is located within
a unit circle 1612. The pole of the IIR filter meets the power
constraint in equation (20) if it is located within a diamond box
1614. The filter bank transformation changes the pole from p to
p.sup.M. Plot 1610 shows the pole location for an example IIR
filter with c.sub.0=1, c.sub.1=1.5 and c.sub.2=0.6875. In this
example, the pole p obtained from decomposition is located outside
diamond box 1614 and thus does not meet the power constraint. The
filter bank transformation with M=2 results in the pole p.sup.2
being located within diamond box 1614 and thus meets the power
constraint. The filter bank transformation with M=4 and 8 results
in the poles p.sup.4 and p.sup.8 being located closer to the
origin. As shown by this example, the pole generally moves toward
the origin for larger values of M. In general, a larger distance
from the pole to the unit circle may result in smaller insertion
loss, which is desirable.
[0127] The pole due to filter bank transformation with M=2 may be
expressed as:
p.sup.2=r.sup.2e.sup.j2.theta..ident.{hacek over (p)}={hacek over
(p)}.sub.re+j{hacek over (p)}.sub.im. Eq (34)
[0128] The power constraint for the IIR part may then be expressed
as:
|{hacek over (p)}|.sub.re|+|{hacek over (p)}.sub.im|=r.sup.2(|cos 2
.theta.|+|sin 2 .theta.|).ltoreq.1 Eq (35)
[0129] Since r<1 for a stable IR filter, r.sup.2<r and it may
be more possible to meet the power constraint. As an example, a
complex first-order IIR section with pole of p=0.625+j 0.625 does
not meet the power constraint. However, a filter bank with pole of
p.sup.2=j 0.78 meets the power constraint.
[0130] Equation (35) is for a 2-way interleaved filter bank with
M=2. In general, the power constraint for an M-way interleaved
filter bank may be expressed as:
|{hacek over (p)}.sub.re|+|{hacek over (p)}|=r.sup.M(|cos
M.theta.|+|sin M.theta.|).ltoreq.1. Eq (36)
[0131] In theory, the power constraint can always be satisfied if M
is sufficiently large. However, a larger M also corresponds to
greater complexity for the IIR part.
[0132] FIG. 17 shows a process 1700 for designing a PSC filter with
filter bank transformation. A filter transfer function may be
decomposed into a FIR part and an IIR part (block 1712). In one
design, the filter transfer function is for a complex first-order
IIR filter and may be decomposed into the FIR part and the IIR
part. A complex coefficient (e.g., p.sup.M) for the IIR part may be
determined based on a complex coefficient (e.g., p) for the complex
first-order IIR filter. The IIR part may be partitioned into
multiple (M) IIR sections, with each IIR section operating at 1/M
clock rate, and the M IIR sections being sequentially enabled in M
clock cycles (block 1714). In one design, the IIR part may be
partitioned into first and second IIR sections, with the first IIR
section being enabled in even-numbered clock cycles, and the second
IIR section being enabled in odd-numbered clock cycles. The FIR and
IIR parts may be implemented with PSC filter sections to obtain the
filter transfer function (block 1716).
[0133] In a fourth scheme for meeting the power constraint for IIR
filter, pole repositioning may be performed, and a pole may be
moved to a more suitable location in order to meet the power
constraint. The second part of the right hand side of equation (22)
may be expressed as:
f(.theta.)=(|cos .theta.|+|sin .theta.|). Eq (37)
[0134] FIG. 18 shows a plot 1810 of function f(.theta.) in equation
(37). Function f(.theta.) has a minimum value of 1.0 for
.theta.=i.pi./2, where i is an integer. In order to meet the power
constraint |p.sub.re|+|p.sub.im|<1, it is better to minimize
f(.theta.), which means making either .theta. or M B close to
i.pi./2. It may be desirable to have .theta..apprxeq..pi./2, so
that the poles are on the imaginary axis. If the interleaved filter
bank with M=2 is used, then it may be desirable to have
.theta..apprxeq..pi./4 or .theta..apprxeq.3.pi./4. This may be
achieved by a multi-rate filter design.
[0135] For the fourth scheme, the pole location may be varied in a
systematic or pseudo-random manner. The pole at each new location
may be evaluated to determine whether (i) a desired filter response
can be obtained with the new pole location and (ii) the power
constraint is met with the new pole location.
[0136] FIG. 19 shows a process 1900 for designing a second-order
IIR filter to meet power constraint. The second-order IIR filter
may be designed to meet applicable system requirements. The
coefficients c.sub.0, c.sub.1 and c.sub.2 of the second-order IIR
filter may be obtained (block 1912). A determination is made
whether the coefficients can be scaled, e.g., whether
|c.sub.1|+|c.sub.2|<1 (block 1914). If the answer is `Yes` for
block 1914, then coefficient scaling may be performed to obtain
coefficient c.sub.0' as shown in equation (15) (block 1924).
Otherwise, the second-order IIR filter may be decomposed into
complex first-order IIR sections (block 1916). A determination is
made whether the pole of the first-order IIR sections meet the
power constraint, e.g., whether |p.sub.re|+|p.sub.im|<1 (block
1918). If the answer is `Yes` for block 1918, then coefficient
scaling may be performed to obtain coefficient {tilde over
(c)}.sub.0 as shown in equation (22) (block 1924).
[0137] Otherwise, each complex first-order IIR section may be
implemented with a filter bank starting with m=1 (block 1920). A
determination is made whether the pole for the filter bank meets
the power constraint, e.g., whether |{hacek over
(p)}.sub.re|+|{hacek over (p)}.sub.im|<1 (block 1922). If the
answer is `Yes` for block 1922, then coefficient scaling may be
performed to obtain coefficient {hacek over (c)}.sub.0 as shown in
equation (33) (block 1924). Otherwise, a determination is made
whether m is equal to a maximum value (block 1926). If the answer
is `No`, then m may be incremented (block 1928), and the process
may then return to block 1920. Otherwise, pole repositioning may be
performed in order to meet the power constraint (block 1930).
[0138] For clarity, much of the description above is for
second-order FIR filter and first-order and second-order IIR
filters. The PSC filters described herein may be used for FIR
filters and IIR filters of any order.
[0139] The PSC filters described herein may provide certain
advantages. First, the PSC filters do not utilize amplifiers within
the PSC filters, which may reduce size and power consumption.
Amplifiers may be used for input/output buffering. Second, the PSC
filters may be able to provide an accurate frequency response,
which is determined by capacitor ratios that can be more accurately
achieved in an integrated circuit (IC). Third, the PSC filters may
have high adaptability since it uses an array of capacitors that
may be configured during operation, e.g., to obtain different
filter responses.
[0140] The PSC filters described herein may be used for various
applications such as wireless communication, computing, networking,
consumer electronics, etc. The PSC filters may also be used for
various devices such as wireless communication devices, cellular
phones, broadcast receivers, personal digital assistants (PDAs),
handheld devices, wireless modems, laptop computers, cordless
phones, Bluetooth devices, wireless local loop (WLL) stations,
consumer electronics devices, etc. For clarity, the use of the PSC
filters in a wireless communication device, which may be a cellular
phone or some other device, is described below. The PSC filters may
be used to pass a desired signal, to attenuate jammers and
out-of-band noise and interference, and/or to perform other
functions in the wireless device.
[0141] FIG. 20 shows a block diagram of a design of a wireless
communication device 2000 in which the PSC filter described herein
may be implemented. Wireless device 2000 includes a receiver 2020
and a transmitter 2040 that support bi-directional communication.
In general, wireless device 2000 may include any number of
receivers and any number of transmitters for any number of
communication systems and frequency bands.
[0142] In the receive path, an antenna 2012 may receive radio
frequency (RF) modulated signals transmitted by base stations and
provide a received RF signal, which may be routed through an RF
unit 2014 and provided to receiver 2020. RF unit 2014 may include
an RF switch and/or a duplexer that can multiplex RF signals for
the transmit and receive paths. Within receiver 2020, a low noise
transconductance amplifier (LNTA) 2022 may amplify the received RF
signal (which may be a voltage signal) and provide an amplified RF
signal (which may be a current signal). A passive sampler 2024 may
sample the amplified RF signal, perform frequency downconversion
via a sampling operation, and provide analog samples. An analog
sample is an analog value for a discrete time instant. A
filter/decimator 2026 may filter the analog samples, perform
decimation, and provide filtered samples at a lower sample rate.
Filter/decimator 2026 may be implemented with the PSC filters
described herein.
[0143] The filtered samples from filter/decimator 2026 may be
amplified by a variable gain amplifier (VGA) 2028, filtered by a
filter 2030, further amplified by an amplifier (AMP) 2032, further
filtered by a filter 2034, and digitized by an analog-to-digital
converter (ADC) 2036 to obtain digital samples. Filter 2030 and/or
2034 may be implemented with the PSC filters described herein. VGA
2028 and/or amplifier 2032 may be implemented with
switched-capacitor amplifiers that can amplify the analog samples
from filters 2026 and 2030. A digital processor 2050 may process
the digital samples to obtain decoded data and signaling. A control
signal generator 2038 may generate a sampling clock for passive
sampler 2024 and control signals for filters 2026, 2030 and
2034.
[0144] In the transmit path, transmitter 2040 may process output
samples from digital processor 2050 and provide an output RF
signal, which may be routed through RF unit 2014 and transmitted
via antenna 2012. For simplicity, details of transmitter 2040 are
not shown in FIG. 20.
[0145] Digital processor 2050 may include various processing units
for data transmission and reception as well as other functions. For
example, digital processor 2050 may include a digital signal
processor (DSP), a reduced instruction set computer (RISC)
processor, a central processing unit (CPU), etc. A
controller/processor 2060 may control the operation at wireless
device 2000. A memory 2062 may store program codes and data for
wireless device 2000. Data processor 2050, controller/processor
2060, and/or memory 2062 may be implemented on one or more
application specific integrated circuits (ASICs) and/or other
ICs.
[0146] FIG. 20 shows a specific design of receiver 2020. In
general, the conditioning of the signals within receiver 2020 may
be performed by one or more stages of mixer, amplifier, filter,
etc. These circuit blocks may be arranged differently from the
configuration shown in FIG. 20. Furthermore, other circuit blocks
not shown in FIG. 20 may also be used to condition the signals in
the receiver. Some circuit blocks in FIG. 20 may also be omitted.
All or a portion of receiver 2020 may be implemented on one or more
RF ICs (RFICs), mixed-signal ICs, etc.
[0147] The received RF signal from antenna 2012 may contain both a
desired signal and jammers. A jammer is a large amplitude undesired
signal close in frequency to a desired signal. The jammers may be
attenuated prior to ADC 2036 in order to avoid saturation of the
ADC. Filters 2026, 2030 and/or 2034 may attenuate the jammers and
other out-of-band noise and interference and may each be
implemented with any of the PSC filters described herein.
[0148] The PSC filters described herein may be implemented on an
IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed
circuit board (PCB), an electronics device, etc. The PSC filters
may also be fabricated with various IC process technologies such as
complementary metal oxide semiconductor (CMOS), N-channel MOS
(NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT),
bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide
(GaAs), etc.
[0149] An apparatus implementing the PSC filters described herein
may be a stand-alone device or may be part of a larger device. A
device may be (i) a stand-alone IC, (ii) a set of one or more ICs
that may include memory ICs for storing data and/or instructions,
(iii) an RFIC such as an RF receiver (RFR) or an RF
transmitter/receiver (RTR), (iv) an ASIC such as a mobile station
modem (MSM), (v) a module that may be embedded within other
devices, (vi) a receiver, cellular phone, wireless device, handset,
or mobile unit, (vii) etc.
[0150] In one or more exemplary designs, the functions described
may be implemented in hardware, software, firmware, or any
combination thereof. If implemented in software, the functions may
be stored on or transmitted over as one or more instructions or
code on a computer-readable medium. Computer-readable media
includes both computer storage media and communication media
including any medium that facilitates transfer of a computer
program from one place to another. A storage media may be any
available media that can be accessed by a computer. By way of
example, and not limitation, such computer-readable media can
comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage,
magnetic disk storage or other magnetic storage devices, or any
other medium that can be used to carry or store desired program
code in the form of instructions or data structures and that can be
accessed by a computer. Also, any connection is properly termed a
computer-readable medium. For example, if the software is
transmitted from a website, server, or other remote source using a
coaxial cable, fiber optic cable, twisted pair, digital subscriber
line (DSL), or wireless technologies such as infrared, radio, and
microwave, then the coaxial cable, fiber optic cable, twisted pair,
DSL, or wireless technologies such as infrared, radio, and
microwave are included in the definition of medium. Disk and disc,
as used herein, includes compact disc (CD), laser disc, optical
disc, digital versatile disc (DVD), floppy disk and blu-ray disc
where disks usually reproduce data magnetically, while discs
reproduce data optically with lasers. Combinations of the above
should also be included within the scope of computer-readable
media.
[0151] The previous description of the disclosure is provided to
enable any person skilled in the art to make or use the disclosure.
Various modifications to the disclosure will be readily apparent to
those skilled in the art, and the generic principles defined herein
may be applied to other variations without departing from the scope
of the disclosure. Thus, the disclosure is not intended to be
limited to the examples and designs described herein but is to be
accorded the widest scope consistent with the principles and novel
features disclosed herein.
* * * * *