U.S. patent application number 14/084901 was filed with the patent office on 2014-03-20 for fabrication method of packaging substrate having embedded capacitors.
This patent application is currently assigned to UNIMICRON TECHNOLOGY CORPORATION. The applicant listed for this patent is UNIMICRON TECHNOLOGY CORPORATION. Invention is credited to Chun-Chih Huang, Chien-Kuang Lai.
Application Number | 20140076492 14/084901 |
Document ID | / |
Family ID | 48171534 |
Filed Date | 2014-03-20 |
United States Patent
Application |
20140076492 |
Kind Code |
A1 |
Lai; Chien-Kuang ; et
al. |
March 20, 2014 |
FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING EMBEDDED
CAPACITORS
Abstract
A packaging substrate includes: a substrate having a core layer,
a cavity penetrating the core layer and circuit layers formed on
surfaces of the core layer; a first capacitor disposed in the
cavity; a bonding layer formed on the first capacitor in the cavity
of the substrate; a second capacitor disposed on the bonding layer
so as to be received in the cavity; and a dielectric layer formed
on the substrate and in the cavity for covering the first and
second capacitors. By stacking the first and second capacitors in
the cavity through the bonding layer, the single core layer is
embedded with two layers of the capacitors to thereby meet the
multi-function requirement.
Inventors: |
Lai; Chien-Kuang; (Taoyuan,
TW) ; Huang; Chun-Chih; (Taoyuan, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNIMICRON TECHNOLOGY CORPORATION |
Taoyuan |
|
TW |
|
|
Assignee: |
UNIMICRON TECHNOLOGY
CORPORATION
Taoyuan
TW
|
Family ID: |
48171534 |
Appl. No.: |
14/084901 |
Filed: |
November 20, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13458059 |
Apr 27, 2012 |
8610250 |
|
|
14084901 |
|
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Current U.S.
Class: |
156/280 |
Current CPC
Class: |
H05K 1/185 20130101;
H01L 2924/0002 20130101; H01L 23/49827 20130101; H01L 23/49822
20130101; H05K 3/4602 20130101; H01L 2924/00 20130101; H05K
2201/10015 20130101; H01G 4/30 20130101; H01L 23/642 20130101; H01L
28/40 20130101; H05K 2201/10515 20130101; H01L 2924/0002
20130101 |
Class at
Publication: |
156/280 |
International
Class: |
H01G 4/30 20060101
H01G004/30 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 1, 2011 |
TW |
100139804 |
Claims
1-9. (canceled)
10. A fabrication method of a packaging substrate having embedded
capacitors, comprising the steps of: providing a substrate having a
core layer, at least a cavity penetrating the core layer and
circuit layers formed on surfaces of the core layer; disposing a
first capacitor in the at least a cavity of the substrate; forming
a bonding layer on the first capacitor; disposing a second
capacitor on the bonding layer so as for the at least a cavity of
the substrate to receive the first and second capacitors; and
forming a dielectric layer on the substrate and in the at least a
cavity for covering the first and second capacitors.
11. The method of claim 10, wherein the core layer has a plurality
of conductive through holes for electrically connecting the circuit
layers.
12. The method of claim 10, wherein the core layer has opposite
first and second surfaces so as for the cavity to be in
communication therewith.
13. The method of claim 12, wherein the dielectric layer is pressed
to be combined with the first and second surfaces of the core
layer.
14. The method of claim 10, wherein the bonding layer is made of a
dielectric material or an insulating material.
15. The method of claim 10, wherein the dielectric layer is further
formed between the first capacitor and the cavity and also between
the second capacitor and the cavity for securing the first and
second capacitors in position.
16. The method of claim 10, before forming the dielectric layer,
further comprising forming an adhesive layer between the first
capacitor and the cavity and also between the second capacitor and
the cavity for securing the first and second capacitors in
position.
17. The method of claim 10, further comprising forming on the
dielectric layer a built-up structure electrically connecting the
first and second capacitors.
18. The method of claim 17, further comprising forming an
insulating protection layer on the built-up structure and forming a
plurality of openings in the insulating protection layer for
exposing portions of the built-up structure.
19. The method of claim 10, wherein forming the dielectric layer
comprises: attaching a carrier to the first capacitor at one end of
the cavity; forming a first dielectric material on the second
capacitor at the other end of the cavity; removing the carrier; and
forming a second dielectric material on the substrate and the first
capacitor and in the cavity so as to form the dielectric layer
through a combination of the first and second dielectric materials.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to packaging substrates and
fabrication methods thereof, and more particularly, to a packaging
substrate having embedded capacitors and a fabrication method
thereof.
[0003] 2. Description of Related Art
[0004] Along with the rapid development of semiconductor packaging
technologies, different package types have been developed for
semiconductor devices. To reduce the height of packages so as to
meet the miniaturization or thinning requirement of products,
semiconductor components are generally embedded in cavities of
packaging substrates so as to reduce the volume of the overall
semiconductor devices and improve the electrical performance.
[0005] FIGS. 1A to 1D are schematic cross-sectional views showing a
fabrication method of a packaging substrate 1 having an embedded
capacitor according to the prior art. Referring to FIG. 1A, a
substrate la is provided, which has a core layer 10 having opposite
first and second surfaces 10a, 10b, a cavity 100 in communication
with the first and second surfaces 10a, 10b of the core layer 10
and a circuit layer 101 formed on the first and second surfaces
10a, 10b of the core layer 10. The core layer 10 further has a
plurality of conductive through holes 102 formed therein for
electrically connecting the circuit layer 101 on the first and
second surfaces 10a, 10b.
[0006] Then, a capacitor 11 is disposed in the cavity 100. The
capacitor 11 has electrode pads 110a, 110b disposed at left and
right ends thereof, respectively.
[0007] Referring to FIG. 1B, a first dielectric material 14a is
formed on the first surface 10a of the core layer 10, on an upper
side of the capacitor 11 and in a portion of the cavity 100.
[0008] Referring to FIG. 1C, a second dielectric material (not
shown) is pressed to the second surface 10b of the core layer 10,
on a lower side of the capacitor 11 and in the cavity 100 so as to
be combined with the first dielectric material 14a to form a
dielectric layer 14, thereby securing in position the capacitor 11
in the dielectric layer 14.
[0009] Referring to FIG. 1D, a built-up structure 16 is formed on
the dielectric layer 14 and electrically connecting the capacitor
11. The built-up structure 16 has a built-up dielectric layer 160,
a built-up circuit layer 161 formed on the built-up dielectric
layer 160 and a plurality of conductive vias 162 formed in the
built-up dielectric layer 160 for electrically connecting the
built-up circuit layer 161, the circuit layer 101 and the electrode
pads 110a, 110b of the capacitor 11.
[0010] Thereafter, an insulating protection layer 17 is formed on
the built-up structure 16 and has a plurality of openings 170
formed therein for exposing portions of the built-up structure
16.
[0011] However, limited by the area of the core layer 10 and the
design of the circuit layer 101 and the built-up circuit layer 161,
the single core layer 10 can only be embedded with one layer of the
capacitor 11. Therefore, such a packaging substrate has limited
functions and accordingly cannot meet the multi-function
requirement.
[0012] On the other hand, in order to meet the multi-function
requirement, several packaging substrates can be stacked on one
another, which, however, leads to an increase in height of the
overall structure. As such, the structure cannot meet the
miniaturization or thinning requirement.
[0013] Therefore, there is a need to provide a packaging substrate
having embedded capacitors and a fabrication method thereof so as
to overcome the above-described drawbacks.
SUMMARY OF THE INVENTION
[0014] Accordingly, the present invention provides a packaging
substrate having embedded capacitors, which comprises: a substrate
having a core layer, at least a cavity penetrating the core layer
and circuit layers formed on surfaces of the core layer; a first
capacitor disposed in the at least a cavity and having first
electrode pads disposed at two opposite ends thereof; a bonding
layer formed on the first capacitor in the at least a cavity of the
substrate; a second capacitor disposed on the bonding layer so as
to be received in the cavity and having second electrode pads
disposed at two opposite ends thereof; and a dielectric layer
formed on the substrate and in the cavity for covering the first
and second capacitors.
[0015] The present invention further provides a fabrication method
of a packaging substrate having embedded capacitors, which
comprises the steps of: providing a substrate having a core layer,
at least a cavity penetrating the core layer and circuit layers
formed on surfaces of the core layer; disposing a first capacitor
in the at east a cavity of the substrate; forming a bonding layer
on the first capacitor; disposing a second capacitor on the bonding
layer so as for the first and second capacitors to be received in
the at least a cavity of the substrate; and forming a dielectric
layer on the substrate and in the at least a cavity for covering
the first and second capacitors.
[0016] Therefore, by stacking the first and second capacitors in
the cavity through the bonding layer, the single core layer is
embedded with two stacked capacitors so as to increase
combinational and selective functions of the capacitors, thereby
meeting the multi-function requirement.
[0017] Furthermore, by eliminating the need to stack another
packaging substrate having an embedded capacitor as required in the
prior art, the present invention reduces the height of the overall
structure to thereby meet the miniaturization or thinning
requirement.
BRIEF DESCRIPTION OF DRAWINGS
[0018] FIGS. 1A to 1D are schematic cross-sectional views showing a
fabrication method of a packaging substrate having an embedded
capacitor according to the prior art; and
[0019] FIGS. 2A to 2G are schematic cross-sectional views showing a
fabrication method of a packaging substrate having embedded
capacitors according to the present invention, wherein FIG. 2F'
shows another embodiment of FIG. 2F.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0020] The following illustrative embodiments are provided to
illustrate the disclosure of the present invention, these and other
advantages and effects can be apparent to those in the art after
reading this specification.
[0021] It should be noted that all the drawings are not intended to
limit the present invention. Various modification and variations
can be made without departing from the spirit of the present
invention. Further, terms such as "one", "on", "top", "bottom" etc.
are merely for illustrative purpose and should not be construed to
limit the scope of the present invention.
[0022] FIGS. 2A to 2G are schematic cross-sectional views showing a
fabrication method of a packaging substrate 2 having embedded
capacitors according to the present invention.
[0023] Referring to FIG. 2A, a substrate 2a is provided. The
substrate 2a has a core layer 20 having opposite first and second
surfaces 20a, 20b, a cavity 200 in communication with the first and
second surfaces 20a, 20b of the core layer 20, and circuit layers
201a, 201b disposed on the first and second surfaces 20a, 20b,
respectively. The core layer 20 further has a plurality of
conductive through holes 202 formed therein for electrically
connecting the circuit layers 201a, 201b on the first and second
surfaces 20a, 20b.
[0024] Thereafter, a carrier 20 is attached to the second surface
20b of the core layer 20 for covering one end of the cavity 200.
Then, a first capacitor 21 having an upper side 21a and a lower
side 21b is disposed in the cavity 200 with its lower side 21b
attached to the carrier 29. In the present embodiment, the first
capacitor 21 has first electrode pads 210a, 210b disposed at left
and right ends thereof and extending from the upper side 21a to the
lower side 21b. But it should be noted that there is no special
limitation on the structure of the first capacitor.
[0025] Referring to FIG. 2B, a bonding layer 22 is formed on the
upper side 21a of the first capacitor 21. In the present
embodiment, the bonding layer 22 is made of a dielectric material
or an insulating material.
[0026] Referring to FIG. 2C, a second capacitor 23 having an upper
side 23a and a lower side 23b is disposed on the bonding layer 22
via its lower side 23b such that both the first and second
capacitors 21,23 are received in the cavity 200. In the present
embodiment, the second capacitor 23 has second electrode pads 230a,
230b disposed at left and right ends thereof and extending from the
upper side 23a to the lower side 23b. But it should be noted that
there is no special limitation on the structure of the second
capacitor.
[0027] Referring to FIG. 2D, a first dielectric material 24a is
formed on the second capacitor 23 at one end of the cavity 200. In
the present embodiment, the first dielectric material 24a covers
the first surface 20a of the core layer 20, the circuit layer 201a
and the upper side 23a of the second capacitor 23. Further, the
first dielectric material 24a extends between the left and right
sides of the second capacitor 23 and the cavity 200 and between the
left and right side surfaces of the bonding layer 22 and the cavity
200.
[0028] Referring to FIG. 2E, the carrier 29 is removed to expose
the second surface 20b of the core layer 20, the lower side 21b of
the first capacitor 21 and the first electrode pads 210a, 210b.
[0029] Referring to FIG. 2F, a second dielectric material (not
shown) is pressed to the second surface 20b of the core layer 20,
the lower side 21b of the first capacitor 21 and in the cavity 200
such that the second dielectric material is combined with the first
dielectric material 24a to form a dielectric layer 24, thereby
securing in position the first and second capacitors 21, 23 in the
dielectric layer 24.
[0030] The dielectric layer 24 is formed on the first and second
surfaces 20a, 20b of the core layer 20 to cover the first and
second capacitors 21, 23 and extends between the first capacitor 21
and the cavity 200, between the second capacitor 23 and the cavity
200 and between the bonding layer 22 and the cavity 200.
[0031] In another embodiment, as shown in FIG. 2F', an adhesive
material 25 is alternatively formed between the first capacitor 21
and the cavity 200, between the bonding layer 22 and the cavity
200, and between the second capacitor 23 and the cavity 200 for
securing in position the first and second capacitors 21, 23. Then,
a dielectric layer 24' is formed on the first and second surfaces
20a, 20b of the core layer 20, the lower side 21b of the first
capacitor 21 and the upper side 23a of the second capacitor 23.
[0032] Subsequently, referring to FIG. 2G continued from FIG. 2F,
built-up structures 26a, 26b are formed on the dielectric layer 24,
i.e., above the first and second surfaces 20a, 20b of the core
layer 20, and electrically connecting the first and second
capacitors 21, 23. In the present embodiment, the built-up
structures 26a, 26b each have a built-up dielectric layer 260, a
built-up circuit layer 261 formed on the built-up dielectric layer
260, and a plurality of conductive vias 262 formed in the built-up
dielectric layer 260 and electrically connecting the built-up
circuit layer 261. Further, portions of the conductive vias 262
electrically connect the circuit layers 201a, 201b, the first
electrode pads 210a, 210b of the first capacitor 21 and the second
electrode pads 230a, 230b of the second capacitor 23.
[0033] Subsequently, an insulating protection layer 27 is formed on
the built-up structures 26a, 26b and has a plurality of openings
270 for exposing portions of surfaces 261a, 261b of the outermost
circuit layers 261 of the built-up structures 26a, 26b.
[0034] Therefore, by stacking the first and second capacitors 21,
23 in the cavity 200 through the bonding layer 22, the single core
layer 20 is embedded with the two capacitors 21, 23, thereby
increasing the combinational and selective functions of the
capacitors and eliminating the limitation on the number and density
of the embedded capacitors imposed by the area of the core layer
and design of the circuit layer and the built-up circuit layer as
in the prior art.
[0035] Further, the present invention meets the multi-function
requirement without the need to stack another packaging substrate
having an embedded capacitor as in the prior art, thus resulting in
a reduction in height of the overall structure.
[0036] In addition, if the bonding layer 22 is made of a dielectric
material, it can be combined with the dielectric layer 24 to
achieve a preferred bonding force, thereby enhancing the fastening
effect to the first and second capacitors 21, 23 and accordingly
increasing the product reliability.
[0037] The present invention further provides a packaging substrate
2 having embedded capacitors. The package substrate 2 has: a
substrate 2a having a core layer 20, a cavity 200 and circuit
layers 201a, 201b; a first capacitor 21 disposed in the cavity 200;
a bonding layer 22 formed on the first capacitor 21; a second
capacitor 23 disposed on the bonding layer 22; and a dielectric
layer 24 or 24' formed on the substrate 2a and in the cavity
200.
[0038] The core layer 20 of the substrate 2a has a first surface
20a and a second surface 20b opposite to the first surface 20a, and
the cavity 200 is in communication with the first and second
surfaces 20a, 20b. The core layer 20 further has a plurality of
conductive through holes 202 for electrically connecting the
circuit layers 201a, 201b.
[0039] The first capacitor 21 is received in the cavity 200 and has
first electrode pads 210a, 210b disposed at left and right ends
thereof.
[0040] The bonding layer 22 is formed in the cavity 200. The
bonding layer 22 is made of a dielectric material or an insulating
material.
[0041] The second capacitor 23 is received in the cavity 200 and
has two second electrode pads 230a, 230b disposed at left and right
ends thereof.
[0042] The dielectric layer 24 or 24' are formed on the first and
second surfaces 20a, 20b of the core layer 20 and the circuit
layers 201a, 201b for covering the first and second capacitors 21,
23. In an embodiment, the dielectric layer 24 is further formed
between the first capacitor 21 and the cavity 200 and between the
second capacitor 21 and the cavity 200 so as to securing in
position the first and second capacitors 21, 23. In another
embodiment, an adhesive material 25 is formed between the first
capacitor 21 and the cavity 200 and between the second capacitor 23
and the cavity 200 for securing in position the first and second
capacitors 21, 23.
[0043] The packaging substrate 2 further has built-up structures
26a, 26b formed on the dielectric layer 24 and electrically
connecting the first and second capacitors 21, 23, and an
insulating protection layer 27 formed on the built-up structures
26a, 26b and having a plurality of openings 270 formed therein for
exposing portions of surfaces 261a, 261b of the built-up structures
26a, 26b.
[0044] According to the present invention, two capacitors are
received in a cavity of a substrate through a bonding layer such
that a single core layer is embedded with two capacitors, thereby
meeting the multi-function requirement.
[0045] Further, by eliminating the need to stack another packaging
substrate having an embedded capacitor as in the prior art, the
present invention effectively reduces the height of the overall
structure so as to meet the miniaturization requirement.
[0046] The above-described descriptions of the detailed embodiments
are only to illustrate the preferred implementation according to
the present invention, and it is not to limit the scope of the
present invention. Accordingly, all modifications and variations
completed by those with ordinary skill in the art should fall
within the scope of present invention defined by the appended
claims.
* * * * *