U.S. patent application number 14/076806 was filed with the patent office on 2014-03-06 for non-volatile memory devices having charge storage layers at intersecting locations of word lines and active region.
The applicant listed for this patent is Su-Jin Ahn, Won-Cheol Jeong, Yoon-Moon Park. Invention is credited to Su-Jin Ahn, Won-Cheol Jeong, Yoon-Moon Park.
Application Number | 20140061772 14/076806 |
Document ID | / |
Family ID | 38277497 |
Filed Date | 2014-03-06 |
United States Patent
Application |
20140061772 |
Kind Code |
A1 |
Jeong; Won-Cheol ; et
al. |
March 6, 2014 |
NON-VOLATILE MEMORY DEVICES HAVING CHARGE STORAGE LAYERS AT
INTERSECTING LOCATIONS OF WORD LINES AND ACTIVE REGION
Abstract
Nonvolatile memory devices are provided. Devices include active
regions that may be defined by device isolation layers formed on a
semiconductor substrate and extend in a first direction. Devices
may also include word lines that may cross over the active regions
and extend in a second direction intersecting the first direction.
The active regions have a first pitch and the word lines have a
second pitch that is greater than the first pitch.
Inventors: |
Jeong; Won-Cheol; (Seoul,
KR) ; Ahn; Su-Jin; (Seoul, KR) ; Park;
Yoon-Moon; (Seoul, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Jeong; Won-Cheol
Ahn; Su-Jin
Park; Yoon-Moon |
Seoul
Seoul
Seoul |
|
KR
KR
KR |
|
|
Family ID: |
38277497 |
Appl. No.: |
14/076806 |
Filed: |
November 11, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13173759 |
Jun 30, 2011 |
8610192 |
|
|
14076806 |
|
|
|
|
11613345 |
Dec 20, 2006 |
7989869 |
|
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13173759 |
|
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Current U.S.
Class: |
257/324 ;
438/287 |
Current CPC
Class: |
H01L 29/792 20130101;
H01L 27/11568 20130101; H01L 29/66833 20130101; H01L 27/115
20130101; H01L 27/11521 20130101 |
Class at
Publication: |
257/324 ;
438/287 |
International
Class: |
H01L 27/115 20060101
H01L027/115; H01L 29/66 20060101 H01L029/66; H01L 29/792 20060101
H01L029/792 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 30, 2006 |
KR |
10-2006-0029056 |
Claims
1. A nonvolatile memory device comprising: a plurality of parallel
active regions defined by a plurality of device isolation layers
formed on a semiconductor substrate, each of the plurality of
parallel active regions extending in a first direction and having a
top surface and sidewalls; a plurality of parallel word lines each
extending in a second direction and overlapping each of the
plurality of parallel active regions at respective locations; and a
plurality of charge storage layers each disposed at each of the
respective locations between the plurality of parallel active
regions and the plurality of parallel word lines, wherein each of
the plurality of charge storage layers at the respective locations
has a first side and a second side each parallel to the second
direction and each having a first length, and a third side and a
fourth side each parallel to the first direction and each having a
second length, wherein the first length is less than the second
length.
2. The device of claim 1 wherein the respective locations are above
the plurality of active regions and below the plurality of word
lines.
3. The device of claim 1 wherein each of the plurality of charge
storage layers overlap all portions of the plurality of parallel
active regions at the respective locations.
4. The device of claim 3 wherein the plurality of parallel active
regions are exposed through the plurality of charge storage layers
thereon between the respective locations.
5. The device of claim 1 wherein the plurality of charge storage
layers comprise nitride layers.
6. The device of claim 1 further comprising: a plurality of oxide
layers in contact with the plurality of charge storage layers at
the respective locations.
7. A nonvolatile memory device comprising: a plurality of parallel
active regions defined by a plurality of device isolation layers
formed on a semiconductor substrate, each of the plurality of
parallel active regions extending in a first direction and having a
top surface and sidewalls; a plurality of parallel word lines each
extending in a second direction and overlapping each of the
plurality of parallel active regions at respective locations; and a
plurality of charge storage layers each disposed at each the
respective locations between the plurality of parallel active
regions and the plurality of parallel word lines; wherein the
respective locations comprise first and second sides each parallel
to the second direction and each having a first length, and
comprising third and fourth sides each parallel to the first
direction and each having a second length that is greater than the
first length.
8. The device of claim 7 wherein the respective locations are above
the plurality of active regions and below the plurality of word
lines.
9. The device of claim 7 wherein each of the plurality of charge
storage layers overlap all portions of the plurality of parallel
active regions at the respective locations.
10. The device of claim 9 wherein the plurality of parallel active
regions are exposed through the plurality of charge storage layers
thereon between the respective locations.
11. The device of claim 7 wherein the charge storage layers
comprise nitride layers.
12. The device of claim 7 further comprising: a plurality of oxide
layers in contact with the plurality of charge storage layers at
the respective locations.
13. A method of forming a nonvolatile memory device comprising:
Forming a plurality of parallel active regions defined by a
plurality of device isolation layers formed on a semiconductor
substrate, each of the plurality of parallel active regions
extending in a first direction and having a top surface and
sidewalls; Forming a plurality of parallel word lines each
extending in a second direction and overlapping each of the
plurality of parallel active regions at respective locations; and
Forming a plurality of charge storage layers each disposed at each
of the respective locations between the plurality of parallel
active regions and the plurality of parallel word lines, wherein
each of the plurality of charge storage layers at the respective
locations has a first side and a second side each parallel to the
second direction and each having a first length, and a third side
and a fourth side each parallel to the first direction and each
having a second length, wherein the first length is less than the
second length.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 13/173,759, filed Jun. 30, 2011 in the United States Patent and
Trademark Office which is a continuation of U.S. patent application
Ser. No. 11/613,345, filed Dec. 20, 2006 filed in the United States
Patent and Trademark Office, now U.S. Pat. No. 7,989,869, which
claims priority under 35 U.S.C. .sctn.119 to Korean Patent
Application No. 10-2006-0029056, filed on Mar. 30, 2006, the entire
contents of which are hereby incorporated by reference in their
entireties.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to the field of semiconductors
in general, and more particularly, to memory devices.
[0003] In general, a semiconductor memory devices may be classified
as volatile memory devices that can lose stored information when
power is turned OFF, and nonvolatile memory device that can retain
stored information even when not powered.
[0004] A flash memory device is a type of nonvolatile memory
device, and can have advantages of an erasable programmable read
only memory (EPROM), and an electrically erasable programmable read
only memory (EEPROM).
[0005] Flash memory devices may be divided into floating gate types
and charge trap types according to the type of data storage layer
constituting a unit cell. The flash memory devices may also be
divided into stacked gate types and split gate types according to
the structure of the unit cell.
[0006] Furthermore, flash memory devices may be divided into a NOR
type and a NAND type. The NOR type flash memory device may have a
high operation speed since it can independently control individual
memory cells, but undesirably can require one contact per two cells
and can have a large cell area. The NAND type flash memory device
may be able to control a plurality of memory cells as a string,
which can provide advantages in highly integrated applications.
[0007] Referring to FIG. 1, which is an equivalent circuit diagram
illustrating a part of a general NAND type flash memory device, the
NAND type flash memory device may include a cell array including a
plurality of cell strings. Each cell string may include a ground
selection transistor and a string selection transistor connected in
series between a source region and a drain region, and a plurality
of memory cells connected in series between the ground selection
transistor and the string selection transistor. The cell array
includes a plurality of ground selection lines (GSL), a plurality
of string selection lines (SSL), and a plurality of word lines (WL)
disposed between the string selection line (SSL) and the ground
selection line (GSL). Bit lines (BL) are disposed to intersect the
word lines (WL). Each bit line is connected to a drain area through
a bit line contact (DC). A common source line (CSL) is disposed
between the ground selection lines (GSL). Source regions are
electrically connected to each other by the common source line
(CSL).
[0008] Referring to FIG. 2, which is a plan view illustrating a
part of the general NAND type flash memory device, active regions
12 are defined by device isolation layers 15 formed on a
semiconductor substrate. The active region 12 extends in a first
direction (DA). The ground selection line (GSL), the string
selection line (SSL), and the word line (WL) cross over the active
region 12 defined by the device isolation layer 15. The word line
(WL) and the selection line (GSL, SSL) extend in a second direction
(DW) intersecting the first direction (DA) at a right angle. The
common source line (CSL) is disposed between the ground selection
gate lines (GSL) of adjacent cell strings. The common source line
(CSL) crosses over the active region and is electrically connected
to the active region thereunder. The active region between the
adjacent string selection lines (SSL) is electrically connected to
a bit line (not shown) crossing over the word line (WL) by a bit
line contact (DC). Floating gates 24, which may be charge storage
elements, are disposed in regions where the active regions 12 and
the word lines (WL) intersect each other. The floating gate 24 is
placed between the active region 12 and the word line (WL). When
the active region 12, the word line (WL), a region between the
active regions 12, and a region between the word lines (WL) have
the same width `a`, any floating gate placed at the center is
adjacent to two floating gates spaced therefrom at a distance `a`
in the first direction (DA), and also adjacent to two floating
gates spaced therefrom at a distance `a` in the second direction
(DW).
[0009] As the memory device becomes highly integrated, parasitic
capacitance between the floating gates may increase and may cause
malfunctioning of the memory device, such as, for example, a
program disturbance between the memory cells.
[0010] Referring to FIG. 3, which is a schematic perspective view
of a flash memory that illustrates a relation between floating gate
voltage and parasitic capacitance, gate structures 37 are placed on
active regions 19 that are defined by device isolation layers 22
formed in the substrate 10. The gate structure 37 can have a
sequentially-stacked structure of a tunnel oxidation layer 25, a
floating gate 29, an ONO layer 32, and a control gate 35. The
active region 19 extends in the first direction (DA), and the
control gate 35 extends in the second direction (DW) to form a word
line. Interlayer insulation layers (not shown) are placed between
the gate structures 37 adjacent in the first direction (DA).
[0011] Reference signs V and C denote a voltage and capacitance at
a corresponding position, respectively. V.sub.fg denotes a voltage
of a floating gate of the center of nine floating gates. VA denotes
a voltage of each of floating gates adjacent to the center floating
gate in the first direction (DA), and VW denotes a voltage of each
of floating gates adjacent to the center floating gate in the
second direction (DW). Also, C.sub.fga denotes parasitic
capacitance generated between the floating gates adjacent in the
first direction (DA), and C.sub.fgw represents parasitic
capacitance generated between the floating gates adjacent in the
second direction (DW).
[0012] A word line formed of a conductive layer is interposed
between the two floating gates adjacent in the second direction
(DW) to prevent the parasitic capacitance (C.sub.fgw). However,
since just the interlayer insulating layer is placed between the
two floating gates adjacent in the first direction (DA), the
parasitic capacitance (C.sub.fgw) may not be effectively prevented.
That is, electrical interference caused by the floating gates
adjacent in the first direction (DA) can be greater than that of
the floating gates adjacent in the second direction. Thus,
reliability and operation characteristics of the memory device may
be lowered.
SUMMARY OF THE INVENTION
[0013] The present invention provides nonvolatile memory devices
having improved operation characteristics and reliability. In some
embodiments nonvolatile memory devices may include an active region
defined by device isolation layers formed on a semiconductor
substrate and extending in a first direction; and a word line
crossing over the active region and extending in a second direction
intersecting the first direction. The devices may be further
configured such that the active region has a first pitch and the
word line has a second pitch that is greater than the first
pitch.
[0014] In some embodiments, the active region may have a first
width and the word line may have a second width that is greater
than or equal to the first width. Also, a value obtained by
subtracting the first width from the first pitch may be smaller
than or equal to a value obtained by subtracting the second width
from the second pitch.
[0015] In other embodiments of the present invention, nonvolatile
memory devices may include multiple active regions defined by
device isolation layers formed on a semiconductor substrate, and
extending in a first direction and multiple word lines crossing
over the active regions and extending in a second direction
intersecting the first direction. The devices may also include
multiple charge storage regions defined by intersections of the
active regions and the word lines. In some embodiments, each of the
charge storage regions has a first side and a second side being
parallel to the second direction and having a first length, and a
third side and a fourth side being parallel to the first direction,
such that the first length is smaller than the second length.
[0016] In some embodiments, the active regions may have a first
pitch, and the word lines may have a second pitch. The first pitch
may be smaller than the second pitch. A value obtained by
subtracting the first length from the first pitch may be smaller
than or equal to a value obtained by subtracting the second length
from the second pitch.
[0017] In other embodiments, devices may include multiple floating
gate patterns corresponding to the charge storage regions and
placed between the active regions and the word lines. Each of the
floating gate patterns may have two sides being parallel to the
second direction and having a first area, and another two sides
being parallel to the first direction and having a second area that
is greater than the first area. In some embodiments, an area of an
overlapping portion of two facing sides of the floating gate
patterns adjacent in the first direction may be smaller than an
area of an overlapping portion of two facing sides of the floating
gate patterns adjacent in the second direction.
[0018] In some embodiments, nonvolatile memory devices may include
active regions defined by device isolation layers formed on a
semiconductor substrate and extending in a first direction. In some
embodiments, devices may also include word lines crossing over the
active regions and extending in a second direction intersecting the
first direction and charge storage regions defined by intersection
of the active regions and the word lines. A distance between the
charge storage regions adjacent in the first direction is greater
than a distance between the charge storage regions adjacent in the
second direction.
[0019] In some embodiments, the active regions may have a first
pitch and the word lines may have a second pitch such that the
first pitch may be smaller than the second pitch. Each of the
charge storage regions may have a first side and a second side
being parallel to the second direction and having a first length,
and a third side and a fourth side being parallel to the first
direction and having a second length. In some embodiments, the
first length may be smaller than the second length. A value
obtained by subtracting the first length from the first pitch may
be smaller than or equal to a value obtained by subtracting the
second length from the second pitch.
[0020] In some embodiments, floating gate patterns corresponding to
the charge storage regions and placed between the active regions
and the word lines may be further included. Each of the floating
gate patterns may have two sides being parallel to the second
direction and having a first area, another two sides being parallel
to the first direction and having a second area, and the first area
may be smaller than the second area. In some embodiments, an area
of an overlapping portion of two facing sides of the floating gate
patterns adjacent in the first direction may be smaller than an
area of an overlapping portion of two facing sides of the floating
gate patterns adjacent in the second direction.
BRIEF DESCRIPTION OF THE FIGURES
[0021] The components in the drawings are not necessarily to scale,
emphasis instead being placed upon clearly illustrating the
principles of the present invention. Moreover, in the drawings,
like reference numerals designate corresponding parts throughout
the several views.
[0022] FIG. 1 is an equivalent circuit diagram of a part of a
general NAND type flash memory device.
[0023] FIG. 2 is a plan view of a part of the general NAND type
flash memory.
[0024] FIG. 3 is a schematic perspective view of a part of a flash
memory device for describing a relation between a floating gate
voltage and parasitic capacitance.
[0025] FIG. 4A is a schematic plan view of nonvolatile memory
device according to some embodiments of the present invention.
[0026] FIG. 4B is a cross-sectional view taken along line I-I' of
FIG. 4A.
[0027] FIG. 4C is a cross-sectional view taken along line II-II' of
FIG. 4A.
[0028] FIG. 5 is an enlarged view of a part of a memory cell region
of FIG. 4A.
[0029] FIGS. 6A through 11A are plan views illustrating methods for
forming nonvolatile memory devices according to some embodiments of
the present invention.
[0030] FIGS. 6B through 11B are cross-sectional views taken along
line I-I' of FIGS. 6A through 11B.
[0031] FIGS. 6C through 11C are cross-sectional views taken along
line II-II' of FIGS. 6A through 11A.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0032] The present invention now will be described more fully
hereinafter with reference to the accompanying drawings, in which
embodiments of the invention are shown. However, this invention
should not be construed as limited to the embodiments set forth
herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope of the invention to those skilled in the art.
[0033] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements, these
elements should not be limited by these terms. These terms are only
used to distinguish one element from another element. Thus, a first
element discussed below could be termed a second element without
departing from the scope of the present invention. In addition, as
used herein, the singular forms "a", "an" and "the" are intended to
include the plural forms as well, unless the context clearly
indicates otherwise. It also will be understood that, as used
herein, the term "comprising" or "comprises" is open-ended, and
includes one or more stated elements, steps and/or functions
without precluding one or more unstated elements, steps and/or
functions. The term "and/or" includes any and all combinations of
one or more of the associated listed items. Also, the term pitch
refers to a distance from the center of, for example, one pattern
to the center of an adjacent pattern in the case where the patterns
are repetitively formed on a substrate.
[0034] It will also be understood that when an element is referred
to as being "connected" to another element, it can be directly
connected to the other element or intervening elements may be
present. In contrast, when an element is referred to as being
"directly connected" to another element, there are no intervening
elements present. It will also be understood that the sizes and
relative orientations of the illustrated elements are not shown to
scale, and in some instances they have been exaggerated for
purposes of explanation.
[0035] In the figures, the dimensions of structural components,
including layers and regions among others, are not to scale and may
be exaggerated to provide clarity of the concepts herein. It will
also be understood that when a layer (or layer) is referred to as
being `on` another layer or substrate, it can be directly on the
other layer or substrate, or can be separated by intervening
layers. Further, it will be understood that when a layer is
referred to as being `under` another layer, it can be directly
under, and one or more intervening layers may also be present. In
addition, it will also be understood that when a layer is referred
to as being `between` two layers, it can be the only layer between
the two layers, or one or more intervening layers may also be
present.
[0036] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which this
invention belongs. It will be further understood that terms, such
as those defined in commonly used dictionaries, should be
interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and will not be
interpreted in an idealized or overly formal sense unless expressly
so defined herein.
[0037] Although a floating gate flash memory device is described by
way of example, the present invention is not limited thereto, and
may be applied to various memory devices such as, for example, a
charge trapping flash memory device.
[0038] Referring to FIG. 4A, which is a schematic plan view of a
nonvolatile memory device according to some embodiments of the
present invention, active regions (ACT) extending in a first
direction (DA) may be defined by device isolation layer patterns
(ISO) formed on a semiconductor substrate. String selection lines
(SSL) and ground selection lines (GSL) cross over the active
regions (ACT) and extend in a second direction intersecting the
first direction. Multiple word lines (WL) extending in the second
direction (DW) are disposed between the string selection line (SSL)
and the ground selection line (GSL). The active regions (ACT) at
one side of the string selection line (SSL) are electrically
connected to bit lines (not shown) by bit line contacts (DC). The
active regions (ACT) at one side of the ground selection line (GSL)
may be electrically connected to each other by a common source line
(CSL) extending in the second direction. The first direction (DA)
and the second direction (DW) may be perpendicular to one another.
Charge storage regions (SA) are defined in regions where the active
regions (ACT) and the word lines (WL) intersect each other. In some
embodiments, the charge storage regions (SA) may be self-aligned to
the active regions (ACT) and the word lines (WL).
[0039] Referring to FIG. 5, which is an enlarged view of a part of
a memory cell region of FIG. 4A, the active regions (ACT) extend in
the first direction (DA), and the word lines (WL) extend in the
second direction (DW). The first direction (DA) and the second
direction (DW) may be perpendicular to one another. The charge
storage regions (SA) are defined by respective intersections
between the active regions (ACT) and the word lines (WL). In some
embodiments, the charge storage regions (SA) are aligned in a
matrix configuration (in the first and second directions).
[0040] The active regions have a first pitch (P1) and the word
lines (WL) have a second pitch (P2), such that the first pitch (P1)
may be smaller than the second pitch (P2). Also, the active region
(ACT) has a first width (W1) and the word line (WL) has a second
width (W2), such that the first width (W1) may be smaller than the
second width (W2). A distance (D1) between the active regions is
substantially equal to a value obtained by subtracting the first
width (W 1) from the first pitch (P1) and is smaller than a
distance (D2) between the word lines. In this regard, the distance
(D2) is substantially equal to a value obtained by subtracting the
second width (W2) from the second pitch (P2). In this manner, a
distance between the charge storage regions (SA) adjacent in the
first direction is longer than a distance between the charge
storage regions (SA) adjacent in the second direction. Accordingly,
electrical interference generated between the charge storage
regions (SA) adjacent in the first direction may be reduced.
[0041] The charge storage region (SA) may have a rectangular shape.
For example, the charge storage region (SA) may have a first side
129_1 and a second side 129_2 parallel to the second direction
(DW), and a third side 129_3 and a fourth side 129_4 parallel to
the first direction (DA). Accordingly, the first side 129_1 and the
second side 129_2 of the adjacent two charge storage regions (SA)
face each other, and the third 129_3 and the fourth side 129_4
thereof face each other. The first side 129_1 and the second side
129_2 may have the same length, and may have a first length (L1).
The third side 129_3 and the fourth side 129_4 may have the same
length, and may have a second length (L2). A length of each of the
two facing sides of the charge storage regions (SA) adjacent in the
first direction (i.e., a length of an overlapping portion of the
corresponding two sides) is smaller than a length of each of the
two facing sides of the charge storage regions (SA) adjacent in the
second direction (i.e., a length of an overlapping portion of the
corresponding two sides), Accordingly, electrical interference
between the charge storage regions (SA) adjacent in the first
direction may be reduced.
[0042] Referring to FIGS. 4B and 4C, which are cross-sectional
views taken along lines I-I' and II-II', respectively, of FIG. 4A,
the active regions 119 may be defined by the device isolation layer
patterns 123 formed in the semiconductor substrate 110. Gate
structures 137 are placed on the active regions 119. The gate
structure 137 may have a sequentially-stacked structure of a gate
insulating layer 125, a floating gate pattern 129, an intergate
insulating layer 132, and a control gate pattern 135. The floating
gate pattern 129 corresponds to the charge storage region (see FIG.
5), and may function as a charge storage layer. The control gate
pattern 135 extends in the second direction and may form a word
line. Impurity regions 140 for source and drain regions are placed
in the active region 119 at both sides of the floating gate pattern
129, and channel regions 143 are placed between the impurity
regions 140 in the active region.
[0043] Referring again to FIGS. 4B and 4C, two sides of the
floating gate pattern 129 facing the first direction (in a
direction of the active region) each have a first area
(L1.times.H), and another two sides of the floating gate pattern
129 facing the second direction (in a direction of the word line)
each have a second area (L2.times.H). Since the width (L1) of the
floating gate pattern in the second direction is smaller than a
width (L2) of the floating gate pattern in the first direction, the
first area (L1.times.H) is smaller than the second area
(L2.times.H). Accordingly, electrical interference generated
between two floating gate patterns 129 adjacent in the first
direction (DA) may be reduced.
[0044] FIGS. 6A through 11A are plan views illustrating methods for
forming nonvolatile memory devices according to some embodiments of
the present invention. FIGS. 6B through 11B are cross-sectional
views taken along lines I-I' of FIGS. 6A through 11A, respectively,
and FIGS. 6C through 11C are cross-sectional views taken along
lines II-II' of FIGS. 6A through 11A, respectively.
[0045] Referring to FIGS. 6A through 6C, a mask pattern 113 extends
in a first direction (DA) on a semiconductor substrate 110. Various
semiconductor substrates 110 may be used as the semiconductor
substrate 110, such as a single crystal bulk silicon substrate, a
silicon on insulator (SOI) substrate, a silicon on sapphire (SOS)
substrate, or the like. The mask pattern 113 may have a stacked
structure including an oxide layer 113a and a nitride layer 113b at
a position corresponding to the active region 119. The oxidation
layer 113a may serve as a pad oxidation layer that can reduce
stress that may be generated between the semiconductor substrate
110 and the nitride layer 113b.
[0046] A trench 16 for device isolation may be formed in the
semiconductor substrate through an etching process using the mask
pattern 113 as an etching mask. Then, as optional processes, a
thermal oxidation process may be further performed for recovering
from etching damage. A liner layer forming process may be performed
to prevent infiltration of impurities into the active region.
[0047] Using an etching process, an active region 119 extending in
the first direction (DA) is formed at the semiconductor substrate
110 under the mask pattern 113 (i.e., between trenches).
[0048] Referring to FIGS. 7A through 7C, a thin film forming
process may be performed to fill the trench 116 with an insulating
layer. A planarization process is performed to expose an upper
surface of the mask pattern 113 and thus form a device isolation
layer 122.
[0049] A chemical vapor deposition (CVD) process may be performed
as the thin film forming process. Specifically, a high-density
plasma chemical vapor deposition process implementing a high
deposition speed may be performed in some embodiments. Accordingly,
the device isolation layer formed by the thin film forming process
may be a CVD oxidation layer. A chemical mechanical polishing (CMP)
process, or an etch-back process may be used as the planarization
process.
[0050] Referring to FIGS. 8A through 8C, the mask pattern 113 is
removed. Thereafter, a thin film forming process may be performed
to form a gate insulating layer 125 on the active region 119. The
gate insulating layer 125 may be a thermal oxidation layer formed
by, for example, a thermal oxidation process.
[0051] Next, a thin film forming process may be performed to form a
conductive layer on the gate insulating layer 125. Thereafter, a
planarization process is performed to expose an upper surface of
the device isolation layer 122 and thus form a floating gate
conductive layer 128. Thus, the floating gate conductive layer 128
may be self-aligned to the active region 119.
[0052] The floating gate conductive layer 128 may be formed of
polysilicon by a CVD process. In some embodiments, impurity ions
may be injected in-situ during the thin film forming process, or
may be injected through a separate ion implantation process after
the thin film formation.
[0053] A CMP process or an etching process may be performed as the
planarization process. A slurry or an etching gas may have an etch
selectivity with respect to the conductive layer. The term "etch
selectivity" refers to the property of a specific etching gas or an
etching solution that is able to perform selective etching with
respect to one of two layers.
[0054] Referring to FIGS. 9A through 9C, an etching process may be
performed to recess an upper surface of a device isolation layer
and thus form a device isolation pattern 123. In the etching
process, an etching gas or an etching solution having an etch
selectivity with respect to the device isolation layer may be used.
In this manner, an upper surface of the device isolation layer
pattern 123 is lower than an upper surface of the floating gas
conductive layer 128.
[0055] Referring to FIGS. 10A through 10C, a thin film forming
process may be performed to form an insulating layer 131 and a
control gate conductive layer 134. The insulating layer 131 may
have a multi-layered structure of an oxide layer/a nitride layer/an
oxide layer through a CVD process. The control gate conductive
layer 134 may have a multi-layered structure of, for example,
polysilicon or polysilicon and silicide through a CVD process.
[0056] Referring to FIGS. 11A through 11C, an etching process for
patterning the control gate conductive layer 134, the insulating
layer 131 and the floating gate conductive layer 128 may be
performed to form control gate patterns 135, intergate insulating
layers 132, and floating gate patterns 129. In this manner, gate
structures 137 are formed, each of which may include the gate
insulating layer 125, the floating gate pattern 129, the intergate
insulating layer 132, and the control gate pattern 135. The control
gate pattern 135 extends in the second direction (DW) intersecting
the first direction (DA) to form a word line. Such floating gate
patterns 29 may be self-aligned to the active regions and the word
lines, and may be arranged in the first and second directions (DA
and DW).
[0057] In the etching process, a pitch of the word lines may become
greater than a pitch of the active regions. Also, the width of the
word line may be greater than the width of the active region and a
distance between the word lines may be greater than a distance
between the active regions.
[0058] Thereafter, an ion implantation process may be performed to
form impurity regions 140 to be source and drain regions in the
active regions 119 at both sides of the word line. Also, a channel
region 143 may be formed in the active region between the impurity
regions 140 (i.e., the active region under the floating gate
pattern).
[0059] According to some embodiments, since a pitch of word lines
may be greater than that of active regions, electrical interference
that may occur between two charge storage regions adjacent in an
active-region direction may decrease.
[0060] According to some embodiments, since a distance between the
word lines may be greater than that between the active regions, the
electrical interference that may occur between two charge storage
regions adjacent in the active-region direction may decrease.
[0061] According to some embodiments, each of sides of the charge
storage regions (e.g., floating gate patterns) facing each other in
the active region direction may have a smaller area than an area of
each of sides of the charge storage regions facing each other in a
word-line direction. In this manner, the electrical interference
that may occur between the two charge storage regions adjacent in a
direction of the active region may decrease.
[0062] When the disclosure herein is applied to embodiments of a
charge trapping type flash memory device, a nitride layer may be
used as a charge storage layer. Further, in some embodiments, the
insulating layer may not be patterned in a direction in which an
active region extends and/or a word line extends.
[0063] In the drawings and specification, there have been disclosed
embodiments of the invention and, although specific terms are
employed, they are used in a generic and descriptive sense only and
not for purposes of limitation, the scope of the invention being
set forth in the following claims.
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