U.S. patent application number 14/113419 was filed with the patent office on 2014-02-20 for lateral semiconductor device.
This patent application is currently assigned to DENSO CORPORATION. The applicant listed for this patent is Youichi Ashida, Satoshi Shiraki, Takashi Suzuki, Shigeki Takahashi, Norihito Tokura, Akira Yamada. Invention is credited to Youichi Ashida, Satoshi Shiraki, Takashi Suzuki, Shigeki Takahashi, Norihito Tokura, Akira Yamada.
Application Number | 20140048911 14/113419 |
Document ID | / |
Family ID | 47176575 |
Filed Date | 2014-02-20 |
United States Patent
Application |
20140048911 |
Kind Code |
A1 |
Suzuki; Takashi ; et
al. |
February 20, 2014 |
LATERAL SEMICONDUCTOR DEVICE
Abstract
A lateral semiconductor device includes a semiconductor layer,
an insulating layer, and a resistive field plate. The semiconductor
layer includes a first semiconductor region and a second
semiconductor region at a surface portion, and the second
semiconductor region makes a circuit around the first semiconductor
region. The insulating layer is formed on a surface of the
semiconductor layer and is disposed between the first and second
semiconductor regions. The resistive field plate is formed on a
surface of the insulating layer. Between the first and second
semiconductor regions, a first section and a second section are
adjacent to each other along a circumferential direction around the
first semiconductor region. The resistive field plate includes
first and second resistive field plate sections respectively formed
in the first and second sections, and the first and second
resistive field plate sections are separated from each other.
Inventors: |
Suzuki; Takashi;
(Toyota-city, JP) ; Tokura; Norihito;
(Okazaki-city, JP) ; Shiraki; Satoshi;
(Toyohashi-city, JP) ; Takahashi; Shigeki;
(Okazaki-city, JP) ; Ashida; Youichi; (Nukata-gun,
JP) ; Yamada; Akira; (Nukata-gun, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Suzuki; Takashi
Tokura; Norihito
Shiraki; Satoshi
Takahashi; Shigeki
Ashida; Youichi
Yamada; Akira |
Toyota-city
Okazaki-city
Toyohashi-city
Okazaki-city
Nukata-gun
Nukata-gun |
|
JP
JP
JP
JP
JP
JP |
|
|
Assignee: |
DENSO CORPORATION
Kariya-city, Aichi-pref.
JP
|
Family ID: |
47176575 |
Appl. No.: |
14/113419 |
Filed: |
May 10, 2012 |
PCT Filed: |
May 10, 2012 |
PCT NO: |
PCT/JP2012/003065 |
371 Date: |
October 23, 2013 |
Current U.S.
Class: |
257/629 |
Current CPC
Class: |
H01L 29/402 20130101;
H01L 29/405 20130101; H01L 29/404 20130101; H01L 29/861 20130101;
H01L 29/063 20130101; H01L 29/0692 20130101 |
Class at
Publication: |
257/629 |
International
Class: |
H01L 29/06 20060101
H01L029/06 |
Foreign Application Data
Date |
Code |
Application Number |
May 13, 2011 |
JP |
2011-108485 |
Apr 9, 2012 |
JP |
2012-088455 |
Claims
1. A lateral semiconductor device comprising: a semiconductor layer
including a first semiconductor region and a second semiconductor
region at a surface portion, the second semiconductor region making
a circuit around the first semiconductor region; an insulating
layer formed on a surface of the semiconductor layer and disposed
between the first semiconductor region and the second semiconductor
region; and a resistive field plate formed on a surface of the
insulating layer, one end of the resistive field plate electrically
connected with the first semiconductor region, another end of the
resistive field plate electrically connected with the second
semiconductor region, wherein when viewed in a plane, between the
first semiconductor region and the second semiconductor region, a
first section and a second section are adjacent to each other along
a circumferential direction around the first semiconductor region,
the resistive field plate includes a first resistive field plate
section formed in the first section and repeating a round trip
along the circumferential direction and a second resistive field
plate section formed in the second section and repeating a round
trip along the circumferential direction, and the first resistive
field plate section formed in the first section and the second
resistive field plate section formed in the second section are
separated from each other.
2. The lateral semiconductor device according to claim 1, wherein a
number of round trips of the first resistive field plate section
formed in the first section and a number of round trips of the
second resistive field plate section formed in the second section
are different.
3. The lateral semiconductor device according to claim 2, wherein
when viewed in a plane, a region between the first semiconductor
region and the second semiconductor region includes a corner
section and a linear section, the first section is included in the
corner section, the second section is included in the linear
section, and the number of round trips of the first resistive field
plate section formed in the first section is larger than the number
of round trips of the second resistive field plate section formed
in the second section.
4. The lateral semiconductor device according to claim 3, wherein
resistance values of respective portions of the first resistance
field plate section extending along the circumferential direction
are substantially equal to each other.
5. The lateral semiconductor device according to claim 1, wherein
the first resistive field plate section includes a first resistive
field plate protruding portion protruding toward the second
section, the second resistive field plate section includes a second
resistive field plate protruding portion protruding toward the
first section, and when viewed in a plane, the first resistive
field plate protruding portion and the second resistive field plate
protruding portion are repeatedly formed along a direction
connecting the first semiconductor region and the second
semiconductor region.
6. The lateral semiconductor device according to claim 1, wherein a
resistance value of the first resistive field plate section and a
resistance value of the second resistance field plate section are
substantially equal to each other.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is based on Japanese Patent Application No.
2011-108485 filed on May 13, 2011 and Japanese Patent Application
No. 2012-88455 filed on Apr. 9, 2012, the disclosures of which are
incorporated herein by reference.
TECHNICAL FIELD
[0002] The present disclosure relates to a lateral semiconductor
device including a resistive field plate.
BACKGROUND ART
[0003] A lateral semiconductor device is formed, for example, using
a silicon on insulator (SOI) substrate. As an example of a lateral
semiconductor device, a lateral diode is known. At a surface
portion of a semiconductor layer of the lateral diode, a cathode
region and an anode region are formed. The anode region makes a
circuit around the cathode region.
[0004] The lateral diode further includes a local oxidation of
silicon (LOCOS) layer and a resistive field plate. The LOCOS layer
is formed on a surface of the semiconductor layer and is disposed
between the cathode region and the anode region. The resistive
field plate is formed on a surface of the LOCOS layer. An end of
the resistive field plate is electrically connected with the
cathode region, and another end of the resistive field plate is
electrically connected with the anode region. In the resistive
field plate, a micro electric current flows. Accordingly, a
potential distribution on the surface of the semiconductor layer
between the cathode region and the anode region is equalized and a
surface electric field of the semiconductor layer can relax. As
described in the patent document 1, when viewed in a plane, the
resistive field plate includes a resistive field plate section
having a spiral shape or a concentric circle shape between the
cathode region and the anode region.
PRIOR ART DOCUMENTS
Patent Document
[0005] [Patent Document 1] JP-A-2000-22175
SUMMARY OF INVENTION
[0006] It is an object of the present disclosure to provide a
lateral semiconductor device that can increase a freedom of a
layout of a resistive field plate section.
[0007] A lateral semiconductor device according to an aspect of the
present disclosure includes a semiconductor layer, an insulating
layer, and a resistive field plate. The semiconductor layer
includes a first semiconductor region and a second semiconductor
region. The first semiconductor region is formed in a surface
portion of the semiconductor layer. The second semiconductor region
is formed in the surface portion of the semiconductor layer and
makes a circuit around the first semiconductor region. The
insulating layer is formed on a surface of the semiconductor layer
and is disposed between the first and second semiconductor regions.
The resistive field plate is formed on a surface of the insulating
layer. One end of the resistive field plate is electrically
connected with the first semiconductor region, and another end of
the resistive field plate is electrically connected with the second
semiconductor region. When viewed in a plane, between the first and
second semiconductor regions, a first section and a second section
are adjacent to each other along a circumferential direction around
the first semiconductor region. The resistive field plate includes
a first resistive field plate section and a second resistive field
plate section. The first resistive field plate section is formed in
the first section and repeats a round trip along the
circumferential direction. The second restive field plate section
is formed in the second section and repeats a round trip along the
circumferential direction. The first resistive field plate section
formed in the first section and the second resistive field plate
section formed in the second section are separated from each
other.
[0008] According to the above-described lateral semiconductor
device, different layouts can be adopted to the first resistive
field plate section in the first section, and the second resistive
field plate section in the second section.
BRIEF DESCRIPTION OF DRAWINGS
[0009] The above and other objects, features and advantages of the
present disclosure will become more apparent from the following
detailed description made with reference to the accompanying
drawings. In the drawings:
[0010] FIG. 1 is plane view showing a lateral diode according to an
embodiment of the present disclosure;
[0011] FIG. 2 is a cross-sectional view of the lateral diode taken
along line II-II in FIG. 1;
[0012] FIG. 3 is a cross-sectional view of the lateral diode taken
along line III-III in FIG. 1;
[0013] FIG. 4 is a diagram showing a corner section and a linear
section of the lateral diode;
[0014] FIG. 5 is a diagram showing a lateral diode according to a
first modification;
[0015] FIG. 6 is a diagram showing a boundary of linear sections C
and D of a lateral diode according to a second modification;
[0016] FIG. 7 is a diagram showing a boundary of linear sections C
and D of a lateral diode according to a third modification;
[0017] FIG. 8 is a diagram showing a concept of a resistance value
of each portion forming a middle resistive field plate section of a
lateral diode according to a fourth modification; and
[0018] FIG. 9 is a diagram showing a concept of a resistance value
of a middle resistance field plate section provided in each section
of a lateral diode according to a fifth modification.
EMBODIMENTS FOR CARRYING OUT INVENTION
[0019] The inventors of the present application found the following
points in a conventional lateral semiconductor device. When viewed
in a plane, a region between a cathode region and an anode region
has a race track shape. Thus, the region between the cathode region
and the anode region is not uniform along a circumferential
direction and includes a corner section, a linear section, and the
like. It is known that electric field is normally prone to
concentrate at a semiconductor layer corresponding to the corner
section. Thus, in the semiconductor layer corresponding to the
corner section, it is desired that a length in a radial direction
is longer than the linear section.
[0020] However, because a resistive field plate having a spiral
shape or a concentric circle shape makes a circuit between the
cathode region and the anode region, it is difficult to adopt
different layouts to the corner section and the linear section.
Thus, when the corner section and the linear section are compared,
the resistive field plate section formed in the corner section is
relatively few with respect to the length between the cathode
region and the anode region. If different layouts are adopted to
the corner section and the linear section, as long as the resistive
field plate sections in the corner section and the linear section
contact, a micro electric current flows to both via a contact
portion. Thus, influence is not a little. In view of the influence,
a compromising layout which is not optimal to the corner section
and the linear section has to be adopted. The inventors of the
present application made the present invention with focusing on the
above-described points.
[0021] A lateral semiconductor device according to the following
embodiment of the present disclosure is formed in a multilayer
substrate in which a support layer, a buried insulating layer, and
an active layer are stacked. It is preferable that the multilayer
substrate is a SOI substrate. The lateral semiconductor device is
formed in an island region surrounded by an insulated isolation
trench that makes a circuit of the active layer. The lateral
semiconductor device includes a semiconductor structure formed in
the semiconductor layer. The semiconductor structure includes
plural kinds of semiconductor regions and controls electric current
that flows in the semiconductor layer. As the semiconductor
structure, a diode structure, an insulated gate bipolar transistor
(IGBT) structure, a metal-oxide semiconductor field-effect
transistor (MOSFET) structure, or the like is used. In a case of
the diode structure, a first semiconductor region is an n-type
cathode region, and a second semiconductor region is a p-type anode
region. In a case of the IGBT, a first semiconductor region is a
p-type collector region, and a second semiconductor region is an
n-type emitter region. In a case of the MOSFET, a first
semiconductor region is an n-type drain region, and a second
semiconductor region is an n-type source region.
[0022] As shown in FIG. 1 to FIG. 3, a lateral diode 1 according an
embodiment of the present disclosure is formed in a SOI substrate
10 in which a support layer 12 of n-type or p-type, a buried
insulating layer 14, and an active layer 16 of n.sup.--type are
stacked. As shown in FIG. 1, the diode 1 is formed in an island
region of the active layer 16 surrounded by an insulated isolation
trench 18. The insulated isolation trench 18 extends from a surface
of the active layer 16 to the buried insulating layer 14 through
the active layer 16. When viewed in a plane, the insulated
isolation trench 18 makes a circuit of a part of the active layer
16. In an example, the support layer 12 and the active layer 16 are
made of single crystal silicon and the buried insulating layer 14
is made of silicon oxide.
[0023] The diode 1 includes a cathode region 28 of n-type, an anode
region 23 of p-type, and a drift region 26 of n.sup.--type. The
cathode region 28, the anode region 23, and the drift region 26
form a diode structure and controls electric current that flows in
a horizontal direction in the active layer 16. Specifically, when a
forward bias is applied between the cathode region 28 and the anode
region 23 (when the anode region 23 is connected to a high
potential side), electric current flows between the cathode region
28 and the anode region 23. On the other hand, when a reverse bias
is applied between the cathode region 28 and the anode region 23
(when the cathode region 28 is connected to the high potential
side), the cathode region 28 is electrically disconnected with the
anode region 23.
[0024] As shown in FIG. 1, the cathode region 28 is disposed at a
center portion of the island region and extends in one direction.
The cathode region 28 can be formed, for example, by implanting
phosphorus ions to the surface portion of the active layer using an
ion implantation technique. Although the cathode region 28 is
formed by one diffusion region in this example, the cathode region
28 may disperse in the one direction. In addition, a region of
p.sup.+-type may be partially formed so as to be in contact with
the cathode region 28.
[0025] The anode region 23 is disposed in a peripheral portion of
the island region. The anode region 23 makes a circuit around the
cathode region 28 with being in contact with the insulated
isolation trench 18. The anode region 23 includes a high
concentration anode region 22 and a low concentration anode region
24. The low concentration anode region 24 is formed to a depth
deeper than the high concentration anode region 22 and surrounds
the high concentration anode region 22. Shapes of the high
concentration anode region 22 and the low concentration anode
region 24 are not limited to this example. For example, an area of
the high concentration anode region 22 may be smaller, and a part
of the low concentration anode region 24 may be in contact with an
anode electrode 32. A depth of the low concentration anode region
24 may be partially changed. The anode region 23 can be formed, for
example, by implanting boron ions to the surface portion of the
active layer 16 using an ion implantation technique.
[0026] The drift region 26 is formed between the cathode region 28
and the anode region 23. The drift region 26 is a remaining portion
of the active layer 16 in which the cathode region 28 and the anode
region 23 are formed. In the drift region 26, a semiconductor
region for increasing a breakdown voltage (e.g., a RESURF region)
may be formed.
[0027] The diode 1 further includes a cathode electrode 36, the
anode electrode 32, a local oxidation of silicon (LOCOS) layer 37,
and a resistive field plate 30 formed on the surface of the active
layer 16.
[0028] The cathode electrode 36 is disposed in the center portion
of the island region and is in direct contact with the cathode
region 28. The anode electrode 32 is disposed in the peripheral
portion of the island region and is in direct contact with the
anode region 23.
[0029] The LOCOS layer 37 is formed on the surface of the active
layer 16 and is disposed between the cathode region 28 and the
anode region 23. The LOCOS layer 37 is disposed above the drift
region 26. The LOCOS layer 37 is made of, for example, silicon
oxide.
[0030] The resistive field plate 30 is formed on the surface of the
LOCOS layer 37. The resistive field plate 30 includes an inner
peripheral resistive field plate section 35, a middle resistive
field plate section 34, and an outer peripheral resistive field
plate section 33. The inner peripheral resistive field plate
section 35 is disposed so as to make a circuit of the center
portion of the island region. The inner peripheral resistive field
plate section 35 is electrically connected with the cathode region
28 via the cathode electrode 36. The outer peripheral resistive
field plate section 33 is disposed so as to make a circuit of the
peripheral portion of the island region. The outer peripheral
resistive field plate section 33 is connected with the anode region
23 via the anode region 23. The middle resistive field plate
section 34 is connected with both of the inner peripheral resistive
field plate section 35 and the outer peripheral resistive field
plate section 33.
[0031] As shown in FIG. 1 and FIG. 4, when viewed in a plane, the
region between the cathode region 28 and the anode region 23 has a
race track shape. As shown in FIG. 4, the region having the race
track shape includes corner sections A, B, E, F and linear sections
C, D, G, H.
[0032] As shown in FIG. 1 and FIG. 4, in the middle resistive field
plate section 34 formed in each of the sections A-H, one end is in
contact with the inner peripheral resistive field plate section 35
and another end is in contact with the outer resistive field plate
section 33. In addition, the middle resistive field plate section
34 formed in each of the sections A-H is separated from the middle
resistive field plate section 34 formed in the adjacent
section.
[0033] The middle resistive field plate section 34 formed in the
corner sections A, B, E, F repeats a round trip along a
circumferential direction of the cathode region 28 between the
cathode region 28 and the anode region 23. In this example, the
middle resistive field plate section 34 makes five round trips
between the cathode region 28 and the anode region 23. When viewed
in a direction connecting the cathode region 28 and the anode
region 23, a length between the adjacent middle resistive field
plate sections 34 is constant and is fixed to a predetermined
value.
[0034] The middle resistive field plate section 34 formed in the
linear sections C, D, G, H repeats a round trip along a
circumferential direction of the cathode region 28 between the
cathode region 28 and the anode region 23. In this example, the
middle resistive field plate section 34 makes four round trips
between the cathode region 28 and the anode region 23. When viewed
in a direction connecting the cathode region 28 and the anode
region 23, a length between the adjacent middle resistive field
plate sections 34 is constant and is fixed to a predetermined
value. The length between the adjacent middle resistive field plate
sections 34 in the corner sections A, B, E, F when viewed in the
direction connecting the cathode region 28 and the anode region 23
and the length between the adjacent middle resistive field plate
sections 34 in the linear sections C, D, G, H when viewed in the
direction connecting the cathode region 28 and the anode region 23
are the same.
[0035] FIG. 2 shows an example of the middle resistive field plate
section 34 formed in the corner sections A, B, E, F. FIG. 3 shows
an example of the middle resistive field plate section 34 formed in
the linear sections C, D, G, H. Electric field is prone to
concentrate at the drift regions 26 corresponding to the corner
sections A, B, E, F. Thus, a horizontal length of the drift region
26 (i.e., a length between the cathode region 28 and the anode
region 23) is larger in the corner sections A, C, E, F than the
linear sections C, D, G, H. As described above, the number of round
trips of the middle resistive field plate section 34 formed in the
corner sections A, B, E, F is larger than the number of round trips
of the middle resistive field plate section 34 formed in the linear
sections C, D, G, H. Thus, in any of the corner sections A, B, E, F
and the linear sections C, D, G, H, the middle resistive field
plate section 34 is uniformly formed above all sections of the
drift region 26. In other words, arrangement intervals of the
middle resistive field plate sections 34 with respect to the
horizontal length of the drift region 26 are the same in the corner
sections A, B, E, G and the linear sections C, D, G, H. Thus, in
any of the corner sections A, B, E, F and the linear sections C, D,
G, H, the surface electric field of the drift region 26 relaxes and
the diode 1 having a high breakdown voltage is realized.
[0036] A diode 1 according to a first modification of the present
embodiment is shown in FIG. 5. In the diode 1, a semiconductor
region 38 having a high resistance is formed between the adjacent
middle resistive field plate sections 34. The diode 1 is
characterized in that the resistive field plate 30 and the
semiconductor region 38 are formed using an ion implantation
technique. Specifically, after a high resistance semiconductor
layer is formed on the surface of the LOCOS layer 37, a mask having
an opening at a portion corresponding to a forming portion of the
resistive field plate 30 is patterned. Next, an impurity is
introduced to the high resistance semiconductor layer through the
opening to selectively introduce the impurity to the forming
portion of the resistive field plate 30. After that, an annealing
process is performed so as to individually form the resistive field
plate 30 and the semiconductor region 38. Because an etching
process is unnecessary when this manufacturing method is used, a
processing variation can be restricted.
[0037] FIG. 6 is a diagram showing a boundary of linear sections C,
D of a lateral diode 1 according to a second modification of the
present embodiment. As shown in FIG. 6, the middle resistive field
plate section 34 in the linear section C has a protruding portion
34a that protrudes toward the linear section D. Similarly, the
middle resistive field plate section 34 in the linear section D has
a protruding portion 34a that protrudes toward the linear section
C. Accordingly, at a region between the linear sections C and F,
the protruding portion 34a is repeatedly formed in a direction
between the anode and the cathode (an up-and-down direction in FIG.
6). FIG. 7 is a diagram showing a boundary of linear sections C, D
of a lateral diode 1 according to a third modification of the
present embodiment. The protruding portions 34a may have a step
shape as shown in FIG. 7. When the protruding portions 34a are
provided as the second and third modification, a blank portion, at
which the middle resistive field plate section 34 does not exist,
does not exist between a boundary portion of the linear sections C
and D. Thus, the surface electric field of the drift region 26
relaxes also at the boundary portion of the linear sections C and
D, and the diode 1 having a high breakdown voltage can be realized.
Although the boundary portion of the linear sections C and D are
illustrated in FIG. 6 and FIG. 7, it is preferable that a similar
structure is formed also in other portion.
[0038] FIG. 8 is a diagram showing a concept of a resistance value
of each portion forming a middle resistive field plate section 34
of a lateral diode 1 according to a fourth modification of the
present embodiment. The middle resistive field plate section 34
includes a plurality of portions extending along the
circumferential direction (hereafter, referred to as arc portions).
A resistance value of the arc portion closest to the cathode (the
innermost side) is set to R1, and a resistance value of the arc
portion closest to the anode (the outermost side) is set to RN. In
the middle resistive field plate section 34 formed in the corner
sections A, B, E, F, the length of the arc portion in the
circumferential direction increase from the cathode side to the
anode side. Thus, when the width of the middle resistive field
plate section 34 is constant, a relationship of R1<R2<R3<
. . . <RN is satisfied. In the diode 1, the width of the middle
resistive field plate section 34 is increased from the cathode side
(the innermost side) to the anode side (the outermost side) so that
a relationship of R1=R2=R3= . . . =RN is satisfied. Accordingly,
the surface potential distribution of the drift region 26 is
equalized in the direction between the anode and the cathode, and
the surface electric field relaxes.
[0039] FIG. 9 is a diagram showing a concept of a resistance value
of a middle resistance field plate section provided in each section
of a lateral diode 1 according to a fifth modification of the
present embodiment. The middle resistive field plate sections 34
formed in the sections A-H is connected in parallel between the
inner peripheral resistive field plate section 35 and the outer
peripheral resistive field plate section 33. A resistance value of
the middle resistive field plate section 34 formed in the corner
section A is Ra, and a resistance value of the middle resistive
field plate section 34 formed in the linear section H is Rh. In the
diode 1, although a layout of the middle resistive field plate
section 34 is different between the corner sections A, B, E, F and
the linear sections C, D, G, H, a relationship of Ra=Rb= . . . =Rh
is satisfied. Accordingly, electric current that flows in each of
the middle resistive field plate sections 34 becomes the same,
imbalance of electric current is restricted, the surface electric
field of the drift region 26 relaxes, and the diode 1 having a high
breakdown voltage is realized.
[0040] In the above-described embodiment, the active layer 16 is an
example of the semiconductor layer, the cathode region is an
example of a first semiconductor region, the anode region is an
example of a second semiconductor region, and the LOCOS layer 37 is
an example of an insulating layer. In the sections A-H, adjacent
two sections are examples of a first section and a second section,
respectively, the middle resistive field plate section 34 formed in
the first section is an example of a first resistive field plate
section, and the middle resistive field plate section 34 formed in
the second section is an example of the second resistive field
plate section.
[0041] Although the examples of the present invention have been
described in detail above, these are only exemplification and do
not limit a scope of claims. Various changes and modifications of
the examples are included in the technology described in the
claims.
[0042] For example, although an example in which silicon is used as
the semiconductor material is described in the above-described
embodiment, instead of this example, a wide gap semiconductor may
be used.
[0043] The technical elements described in the present
specification and the drawings exert technical utility by itself or
various combinations, and are not limited to the combinations
described in claims at filing. The techniques exemplified in the
present specification and the drawings can achieve plural objects
at the same time, and have technical utility by achieving one of
the objects.
* * * * *