U.S. patent application number 14/047594 was filed with the patent office on 2014-02-13 for segmented pillar layout for a high-voltage vertical transistor.
This patent application is currently assigned to Power Integrations, Inc.. The applicant listed for this patent is Power Integrations, Inc.. Invention is credited to Wayne Bryan Grabowski, Vijay Parthasarathy.
Application Number | 20140042533 14/047594 |
Document ID | / |
Family ID | 39322673 |
Filed Date | 2014-02-13 |
United States Patent
Application |
20140042533 |
Kind Code |
A1 |
Parthasarathy; Vijay ; et
al. |
February 13, 2014 |
Segmented Pillar Layout for a High-Voltage Vertical Transistor
Abstract
In one embodiment, a transistor fabricated on a semiconductor
die includes a first section of transistor segments disposed in a
first area of the semiconductor die, and a second section of
transistor segments disposed in a second area of the semiconductor
die adjacent the first area. Each of the transistor segments in the
first and second sections includes a pillar of a semiconductor
material that extends in a vertical direction. First and second
dielectric regions are disposed on opposite sides of the pillar.
First and second field plates are respectively disposed in the
first and second dielectric regions. Outer field plates of
transistor segments adjoining first and second sections are either
separated or partially merged.
Inventors: |
Parthasarathy; Vijay;
(Mountain View, CA) ; Grabowski; Wayne Bryan; (Los
Altos, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Power Integrations, Inc. |
San Jose |
CA |
US |
|
|
Assignee: |
Power Integrations, Inc.
San Jose
CA
|
Family ID: |
39322673 |
Appl. No.: |
14/047594 |
Filed: |
October 7, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12455462 |
Jun 2, 2009 |
8552493 |
|
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14047594 |
|
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|
11707406 |
Feb 16, 2007 |
7557406 |
|
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12455462 |
|
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Current U.S.
Class: |
257/331 |
Current CPC
Class: |
H01L 29/0696 20130101;
H01L 23/562 20130101; H01L 21/77 20130101; H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H01L 29/7813 20130101; H01L 29/0878
20130101; H01L 29/4236 20130101; H01L 29/4238 20130101; H01L 27/088
20130101; H01L 2924/00 20130101; H01L 29/407 20130101; H01L 29/0607
20130101 |
Class at
Publication: |
257/331 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 29/06 20060101 H01L029/06; H01L 23/00 20060101
H01L023/00; H01L 29/78 20060101 H01L029/78 |
Claims
1-36. (canceled)
37. An apparatus comprising: a plurality of transistor segments
arranged on a die, each transistor segment including: a pillar of a
semiconductor material, the pillar including a drift region that
extends in a vertical direction from a top surface down to a
substrate, the pillar having a loop shape that extends in first and
second lateral directions, the loop shape including a pair of
substantially parallel, elongated straight sections connected at
opposite ends by respective first and second semi-circular
sections; a first and second dielectric regions disposed on
opposite sides of the pillar, respectively, the first dielectric
region being laterally surrounded by the pillar, and the second
dielectric region laterally surrounding the pillar; first and
second field plates respectively disposed in the first and second
dielectric regions; wherein the transistor segments are arranged
into a plurality of sections, the sections being arranged into rows
and columns that extend across first and second lateral directions,
respectively, of the die, the transistor segments of each section
being arranged in an orthogonal relationship relative to the
transistor segments of an adjacent section in both the first and
second directions.
38. The apparatus of claim 37 wherein the pillar further comprises
a source region disposed at or near the top surface, and a body
region that vertically separates the source region from the drift
region.
39. The apparatus of claim 37 wherein the second dielectric region
is terminated at each end in the first lateral direction in a
rounded end.
40. The apparatus of claim 37 wherein the first and second field
plates are fully insulated from the extended drain region, the
first field plate being laterally surrounded by the pillar, and the
second field plate laterally surrounding the pillar.
41. The apparatus of claim 38 wherein the drift region and the
source region are a first conductivity type, and the body region is
a second conductivity type.
42. The apparatus of claim 41 wherein the substrate is the first
conductivity type.
43. The apparatus of claim 38 further comprising a gate disposed
within the first and second dielectric regions adjacent the body
region, the gate being insulated from the body region and the first
and second field plates.
44. The apparatus of claim 37 wherein the plurality of sections
comprise 2N sections, where N is an integer greater than or equal
to one.
45. The apparatus of claim 38 wherein the source comprises first
and second regions separated by a semiconductor region of an
opposite conductivity type.
46. An apparatus comprising: a plurality of transistor segments
arranged on a die. each transistor segment including: a pillar of a
semiconductor material, the pillar including a drift region that
extends in a vertical direction through the die, the pillar having
a loop shape that extends in first and second lateral directions,
the loop shape including a pair of substantially parallel,
elongated straight sections connected at opposite ends by
respective first and second semi-circular sections; a first and
second dielectric regions disposed on opposite sides of the pillar,
respectively, the first dielectric region being laterally
surrounded by the pillar, and the second dielectric region
laterally surrounding the pillar; first and second field plates
respectively disposed in the first and second dielectric regions;
wherein the transistor segments are arranged into a plurality of
sections, each section comprising a set of transistor segments
arranged with the substantially parallel, elongated straight
sections of each transistor segment being in a side-by-side
relationship with the second dielectric region of each transistor
segment being merged, the transistor segments of each section being
arranged in an orthogonal relationship relative to the transistor
segments of an adjacent section in both the first and second
directions.
47. The apparatus of claim 46 wherein the sections extend laterally
substantially across a width and a length of the die.
48. The apparatus of claim 46 wherein the pillar further comprises
a source region disposed near a top surface of the die, and a body
region that vertically separates the source region from the drift
region.
49. The apparatus of claim 48 further comprising a gate disposed
within the first and second dielectric regions adjacent the body
region, the gate being insulated from the body region and the first
and second field plates.
Description
[0001] This application is a continuation of application Ser. No
12/455,462, filed Jun. 2, 2009, now U.S. Pat. No. 8,552,493, which
is a continuation of application Ser. No.: 11/707,406, filed Feb.
16, 2007, now U.S. Pat. No. 7,557,406, entitled, "SEGMENTED PILLAR
LAYOUT FOR A HIGH-VOLTAGE VERTICAL TRANSISTOR", each of which is
assigned to the assignee of the present application.
TECHNICAL FIELD
[0002] The present disclosure relates to semiconductor device
structures and processes for fabricating high-voltage
transistors.
BACKGROUND
[0003] High-voltage, field-effect transistors (HVFETs) are well
known in the e semiconductor arts. Many HVFETs employ a device
structure that includes an extended drain region that supports or
blocks the applied high-voltage (e.g., several hundred volts) when
the device is in the "off" state. In a conventional vertical HVFET
structure, a mesa or pillar of semiconductor material forms the
extended drain or drift region for current flow in the on-state. A
trench gate structure is formed near the top of the substrate,
adjacent the sidewall regions of the mesa where a body region is
disposed above the extended drain region. Application of an
appropriate voltage potential to the gate causes a conductive
channel to be formed along the vertical sidewall portion of the
body region such that current may flow vertically through the
semiconductor material, i.e., from a top surface of the substrate
where the source region is disposed, down to the bottom of the
substrate where the drain region is located.
[0004] In a traditional layout, a vertical HVFET consists of long
continuous silicon pillar structure that extends across the
semiconductor die, with the pillar structure being repeated in a
direction perpendicular to the pillar length. One problem that
arises with this layout, however, is that it tends to produce large
warping of the silicon wafer during high temperature processing
steps. In many processes, the warping is permanent and large enough
to prevent the wafer from tool handling during subsequent
processing steps.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The present disclosure will be understood more fully from
the detailed description that follows and from the accompanying
drawings, which however, should not be taken to limit the invention
to the specific embodiments shown, but are for explanation and
understanding only.
[0006] FIG. 1 illustrates an example cross-sectional side view of
vertical HVFET structure.
[0007] FIG. 2A illustrates an example layout of the vertical HVFET
structure shown in FIG. 1.
[0008] FIG. 2B is an expanded view of one portion of the example
layout shown in FIG. 2A.
[0009] FIG. 3A illustrates another example layout of the vertical
HVFET structure shown in FIG. 1.
[0010] FIG. 3B is an expanded view of one portion of the example
layout shown in FIG. 3A.
[0011] FIG. 4A illustrates yet another example layout of the
vertical HVFET structure shown in FIG. 1.
[0012] FIG. 4B is an expanded view of one portion of the example
layout shown in FIG. 4A.
[0013] FIGS. 5-7 are further example layouts of a vertical HVFET
structure showing transistor segments arranged in sections, with
adjacent sections being oriented orthogonally in first and second
lateral directions.
DETAILED DESCRIPTION
[0014] In the following description specific details are set forth,
such as material types, dimensions, structural features, processing
steps, etc., in order to provide a thorough understanding of the
present invention. However, persons having ordinary skill in the
relevant arts will appreciate that these specific details may not
be needed to practice the present invention. It should also be
understood that the elements in the figures are representational,
and are not drawn to scale in the interest of clarity.
[0015] FIG. 1 illustrates an example cross-sectional side view of a
vertical HVFET 10 having a structure that includes an extended
drain region 12 of N-type silicon formed on an N+ doped silicon
substrate 11. Substrate 11 is heavily doped to minimize its
resistance to current flowing through to the drain electrode, which
is located on the bottom of the substrate in the completed device.
In one embodiment, extended drain region 12 is part of an epitaxial
layer that extends from substrate 11 to a top surface of the
silicon wafer. A P-type body region 13 and N+ doped source regions
14a & 14b laterally separated by a P-type region 16, are formed
near a top surface of the epitaxial layer. As can be seen, P-type
body region 13 is disposed above and vertically separates extended
drain region 12 from N+ source regions 14a & 14b and P-type
region 16.
[0016] In one embodiment, the doping concentration of the portion
of epitaxial layer which comprises extended drain region 12 is
linearly graded to produce an extended drain region that exhibits a
substantially uniform electric-field distribution. Linear grading
may stop at some point below the top surface of the epitaxial layer
12.
[0017] Extended drain region 12, body region 13, source regions 14a
& 14b and P-type region 16 collectively comprise a mesa or
pillar 17 (both terms are used synonymously in the present
application) of silicon material in the example vertical transistor
of FIG. 1. Vertical trenches formed on opposite sides of pillar 17
are filled with a layer of dielectric material (e.g., oxide) that
makes up dielectric region 15. The height and width of pillar 17,
as well as the spacing between adjacent vertical trenches may be
determined by the breakdown voltage requirements of the device. In
various embodiments, mesa 17 has a vertical height (thickness) in a
range of about 30 .mu.m to 120 .mu.m thick. For example, a HVFET
formed on a die approximately 1 mm.times.1 mm in size may have a
pillar 17 with a vertical thickness of about 60 .mu.m. By way of
further example, a transistor structure formed on a die of about 2
mm-4 mm on each side may have a pillar structure of approximately
30 .mu.m thick. In certain embodiments, the lateral width of pillar
17 is as narrow as can be reliably manufactured (e.g., about 0.4
.mu.m to 0.8 .mu.m wide) in order to achieve a very high breakdown
voltage (e.g., 600-800V).
[0018] In another embodiment, instead of arranging P-type region 16
between N+ source regions 14a & 14b across the lateral width of
pillar 17 (as shown in FIG. 1), N+ source regions and P-type
regions may be alternately farmed at the top of pillar 17 across
the lateral length of pillar 17, In other words, a given
cross-sectional view such as that shown in FIG. 1 would have either
an N+ source region 14, or a P-type region 16, that extends across
the full lateral width of pillar 17, depending upon where the
cross-section is taken. In such an embodiment, each N+ source
region 14 is adjoined on both sides (along the lateral length of
the pillar) by P-type regions 16. Similarly, each P-type region 16
is adjoined on both sides (along the lateral length of the pillar)
by N+ source regions 14.
[0019] Dielectric regions 15a & 15b may comprise silicon
dioxide silicon nitride, or other suitable dielectric materials.
Dielectric regions 15 may be formed using a variety of well-known
methods, including thermal growth and chemical vapor deposition.
Disposed within each of the dielectric layers 15, and fully
insulated from substrate 1 and pillar 17, is a field plate 19. The
conductive material used to from field plates 19 may comprise a
heavily doped polysilicon, a metal (or metal alloys), a silicide,
or other suitable materials. In the completed device structure,
field plates 19a & 19b normally function as capacitive plates
that may be used to deplete the extended drain region of charge
when the HVFET is in the off state (i.e., when the drain is raised
to a high voltage potential). In one embodiment, the lateral
thickness of oxide region 15 that separates each field plate 19
from the sidewall of pillar 17 is approximately 4 .mu.m.
[0020] The trench gate structure of vertical HVFET transistor 80
comprises gate members 18a & 18b, each respectively disposed in
oxide regions 15a & 15b on opposite sides of pillar 17 between
field plates 19a & 19b and body region 13. A high-quality, thin
(e.g., .about.500 .ANG.) gate oxide layer separates gate members 18
from the sidewalls of pillar 17 adjacent body region 13. Gate
members 18 may comprise polysilicon, or some other suitable
material. In one embodiment, each gate member 18 has a lateral
width of approximately 1.5 .mu.m and a depth of about 3.5
.mu.m.
[0021] Practitioners in the art will appreciate that N+ source
regions 14 and P-type body region 13 near the top of pillar 17 may
each be formed using ordinary deposition, diffusion, and/or
implantation processing techniques. After formation of the N+
source region 38, HVFET 10 may be completed by forming source,
drain, gate, and field plate electrodes that electrically connect
to the respective regions/materials of the device using
conventional fabrication methods (not shown in the figures for
clarity reasons).
[0022] FIG. 2A illustrates an example layout of the vertical HVFET
structure shown in FIG. 1. The top view of FIG. 2A shows a single,
discrete HVFET comprising an upper transistor section 30a and a
lower transistor section 30b on a semiconductor die 21. The two
sections are separated by a dummy silicon pillar 32. Each section
30 comprises a plurality of "racetrack" shaped transistor
structures or segments, each transistor segment comprises an
elongated ring or oval that includes a silicon pillar 17 surrounded
on opposite sides by dielectric regions 15a & 15b. Pillar 17,
itself, extends laterally in the x and y directions to form a
continuous, elongated, racetrack-shaped ring or oval. Disposed
within dielectric regions 15a & 15b are respective gate members
18a & 18b and field plates 19a & 19b. Field plate 19a
comprises a single elongated member that terminates on either end
in a rounded fingertip area. Field plate 19b, on the other hand,
comprises an enlarged ring or oval that encircles pillar 17. Field
plates 19b of adjacent racetrack structures are shown merged such
that they share a common member on a side. By way of reference, the
cross-sectional view of FIG. 1 may be taken through cut lines A-A'
of the example layout of FIG. 2A.
[0023] It should be understood that in the example of FIG. 2A, each
of the racetrack transistor segments has a width (Le pitch) in the
y-direction of approximately 13 .mu.m, a length in the x-direction
in a range of about 400 .mu.m to 1000 .mu.m, with a pillar height
of about 60 .mu.m. In other words, the length to width ratio of the
individual racetrack transistor segments comprising sections 30a
& 30b is in a range of about 30 up to 80. In one embodiment,
the length of each racetrack shaped segment is at least 20 times
greater than its pitch or width.
[0024] Practitioners in the art will appreciate that in the
completed device structure, patterned metal layers are used to
interconnect each of the silicon pillars 17 of the individual
transistor segments. That is in a practical embodiment, all of the
source regions, gate members, and field plates are respectively
wired together to corresponding electrodes on the die. In the
embodiment shown, the transistor segments in each section 30 are
arranged in a side-by-side relationship in the y-direction
substantially across a width of die 21. Similarly, in the
x-direction the additive length of the transistor segments of
sections 30a & 30b extend substantially over the length of die
21. In the example layout of FIG. 2A the width of dielectric
regions 15 separating the silicon pillars, as well as the width of
the field plates, is substantially uniform across semiconductor die
21. Laying out the transistor segments with uniform widths and
separation distances prevents the formation of voids or holes
following the processing steps used to conformably deposit the
layers that comprise dielectric regions 15 and field plates 19.
[0025] FIG. 2B is an expanded view of one portion of the example
layout shown in FIG. 2A. For purposes of clarity, only pillars 17
and dielectric regions 15a & 15b of each of the transistor
segments is represented. Dummy silicon pillar 32 is shown,
separating the rounded end areas of dielectric regions 15b of
respective transistor segment sections 30a & 30b. In other
words, the deep vertical trenches that are etched in the
semiconductor substrate to define pillars 17 also define dummy
silicon pillar 32. In one embodiment, dummy silicon pillar 32 is
made to have a width in the x-direction (i.e., that separates the
transistor segment sections) that is as small as can be reliably
manufactured.
[0026] The purpose of segmenting the single die HVFET into sections
separated by dummy silicon pillar 32 is to introduce lengthwise
(x-direction) stress-relief in the elongated racetrack shaped
transistor segments. Segmenting or breaking the transistor device
structures into two or more sections relieves mechanical stress
across the length of the die. This stress is induced by the oxide
regions flanking the pillars and normally concentrates at the
rounded ends of each racetrack segment. Relieving mechanical stress
by segmenting the transistor device structures into two or more
sections thus prevents undesirable warping of the silicon pillars
and damage (e.g., dislocations) to the silicon caused by
stress.
[0027] It is appreciated that a tradeoff exists between the stress
relief provided by a highly segmented layout and loss of conduction
area. More segmentation results in greater stress relief, but at
the expense of conduction area. In general, the greater the
vertical height of the pillars and the larger the semiconductor
die, the greater the number of transistor sections or segments that
will be required. In one embodiment, for a 2 mm.times.2mm die with
60 .mu.m high pillars, adequate stress relief is provided in a
HVFET with an on-resistance of about lohm utilizing a layout
comprising four racetrack transistor sections separated by dummy
silicon pillars, each having a pitch (x-direction) of about 13
.mu.m and a length (y-direction) of about 450 .mu.m.
[0028] In another embodiment, instead of a dummy pillar of silicon
to separate pairs of racetrack transistor segments, each pair being
located in a different section, a dummy pillar comprising a
different material may be utilized. The material used for the dummy
pillar should have a thermal coefficient of expansion close to that
of silicon, or sufficiently different from that of the dielectric
region so as to relieve the lengthwise stress induced by the
dielectric regions flanking the silicon pillars.
[0029] FIG. 3A illustrates another example layout of the vertical
HVFET structure shown in FIG. 1. FIG. 3B is an expanded view of one
portion of the example layout shown in FIG. 3A, just showing
pillars 17, oxide region 15b, and an optional dummy silicon pillar
33. Similar to the embodiment of FIGS. 2A & 2B, FIGS. 3A &
3B show a single, discrete HVFET comprising an upper transistor
section 30a and a lower transistor section 30b on a semiconductor
die 21. But in the example of FIGS. 3A & 3B, the deep vertical
trenches filled with oxide regions 15b and field plates 19b of
transistor sections 30a and 30b overlap, or are merged, leaving
small, diamond-shaped dummy silicon pillars 33 between the
segmented transistor sections. In this embodiment, a single dummy
pillar is centrally located between the four rounded ends of
adjacent pairs of transistor segments over the two sections. In the
example shown, for every N (where N is an integer greater than 1)
racetrack segments or structures in a section 30 of the transistor
comprising die 21, there are a total of N-1 dummy pillars 33.
[0030] FIG. 4A illustrates yet another example layout of the
vertical HVFET structure shown in FIG. 1. FIG. 4B is an expanded
view of one portion of the example layout shown in FIG. 4A. Pillars
17 and oxide region 15b are just shown for clarity reasons in the
expanded view of FIG. 4B. In this example, the transistor segments
comprising the HVFET of semiconductor die 21 are alternately
shifted by half of the length of each racetrack segment, resulting
in racetrack transistor segments that are alternately associated
with upper transistor section 40a and lower transistor section 40b.
In other words, each of the transistor segments of a row of section
40a is separated by a pair of the transistor segments of section
40b, the pair being arranged in an end-to-end relationship in the
x-direction.
[0031] It is appreciated that the alternate shifting of the
segments may be any fraction of the segment length. In other words,
shifting of the segments is not limited to 50% or half the length.
Various embodiments may comprise segments alternately shifted by
any percentage or fraction ranging from greater than 0% to less
than 100% of the length of the transistor segments.
[0032] In the example of FIGS. 4A & 4B, the dielectric regions
15b of alternating ones of the transistor segments in respective
sections 40a & 40b are merged. In the specific embodiment
shown, the rounded ends of the transistor segments associated with
different adjacent sections overlap or are merged such that field
plates 19b of the adjacent sections are merged at the ends (in the
x-direction). Also, the extended straight side portions of field
plates 19b of alternating transistor segments of different sections
are merged along a substantial length of each segment. It is
appreciated that regions 15b and 19b may be merged with or without
a dummy pillar (or isolated dummy silicon pillars) between the
respective sections.
[0033] Although the above embodiments have been described in
conjunction with a specific device types, those of ordinary skill
in the arts will appreciate that numerous modifications and
alterations are well within the scope of the present invention. For
instance, although HVFETs have been described, the methods, layouts
and structures shown are equally applicable to other structures and
device types, including Schottky, diode, IGBT and bipolar
structures. Accordingly, the specification and drawings are to be
regarded in an illustrative rather than a restrictive sense.
* * * * *