U.S. patent application number 14/049253 was filed with the patent office on 2014-02-06 for semiconductor structure and method for manufacturing the same.
This patent application is currently assigned to MACRONIX INTERNATIONAL CO., LTD.. The applicant listed for this patent is MACRONIX INTERNATIONAL CO., LTD.. Invention is credited to Yi-Hsuan Hsiao, Hang-Ting Lue.
Application Number | 20140035140 14/049253 |
Document ID | / |
Family ID | 46490166 |
Filed Date | 2014-02-06 |
United States Patent
Application |
20140035140 |
Kind Code |
A1 |
Lue; Hang-Ting ; et
al. |
February 6, 2014 |
Semiconductor Structure and Method for Manufacturing the Same
Abstract
A semiconductor structure and a method for manufacturing the
same are provided. The method comprises following steps. A first
silicon-containing conductive material is formed on a substrate. A
second silicon-containing conductive material is formed on the
first silicon-containing conductive material. The first
silicon-containing conductive material and the second
silicon-containing conductive material have different dopant
conditions. The first silicon-containing conductive material and
the second silicon-containing conductive material are thermally
oxidized for turning the first silicon-containing conductive
material wholly into an insulating oxide structure, and the second
silicon-containing conductive material into a silicon-containing
conductive structure and an insulating oxide layer.
Inventors: |
Lue; Hang-Ting; (Hsinchu,
TW) ; Hsiao; Yi-Hsuan; (Budai Township, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MACRONIX INTERNATIONAL CO., LTD. |
Hsinchu |
|
TW |
|
|
Assignee: |
MACRONIX INTERNATIONAL CO.,
LTD.
Hsinchu
TW
|
Family ID: |
46490166 |
Appl. No.: |
14/049253 |
Filed: |
October 9, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13009502 |
Jan 19, 2011 |
8609554 |
|
|
14049253 |
|
|
|
|
Current U.S.
Class: |
257/750 ;
438/652 |
Current CPC
Class: |
H01L 29/4234 20130101;
H01L 24/64 20130101; H01L 27/11578 20130101; H01L 23/485 20130101;
H01L 29/792 20130101 |
Class at
Publication: |
257/750 ;
438/652 |
International
Class: |
H01L 23/485 20060101
H01L023/485; H01L 23/00 20060101 H01L023/00 |
Claims
1. A semiconductor structure, comprising: a substrate; an
insulating oxide structure formed on the substrate; and a
silicon-containing conductive structure formed on the insulating
oxide structure, wherein at least one of the insulating oxide
structure and the silicon-containing conductive structure has a
bird's beak profile.
2. The semiconductor structure according to claim 1, wherein the
insulating oxide structure and the silicon-containing conductive
structure both have a bird's beak profile.
3. The semiconductor structure according to claim 1, comprising the
silicon-containing conductive structures separated from each other
by the insulating oxide structure.
4. The semiconductor structure according to claim 3, wherein the
insulating oxide structure and the silicon-containing conductive
structures form a stacked structure.
5. The semiconductor structure according to claim 4, wherein the
silicon-containing conductive structures of different layers in the
stacked structure is functioned as bit lines of different
planes.
6. The semiconductor structure according to claim 1, further
comprising a dielectric element formed on the silicon-containing
conductive structure and the insulating oxide structure.
7. The semiconductor structure according to claim 6, wherein the
dielectric element comprises a silicon oxide or a silicon
nitride.
8. The semiconductor structure according to claim 6, wherein the
dielectric element is a single-layer structure or a multi-layer
structure.
9. The semiconductor structure according to claim 6, further
comprising a conductive line formed on the dielectric element.
10. The semiconductor structure according to claim 9, which is a 3D
vertical gate memory device.
11. The semiconductor structure according to claim 9, wherein the
silicon-containing conductive structure is functioned as a bit line
(BL).
12. The semiconductor structure according to claim 9, wherein the
conductive line is functioned as a word line (WL), a ground
selection line (GSL), or a string selection line (SSL).
13. The semiconductor structure according to claim 9, wherein the
conductive line comprises polysilicon.
14. A method of forming a semiconductor structure, comprising:
providing a substrate; forming an insulating oxide structure on the
substrate; and forming a silicon-containing conductive structure on
the insulating oxide structure, wherein at least one of the
insulating oxide structure and the silicon-containing conductive
structure has a bird's beak profile.
Description
[0001] The application is a divisional application of U.S. patent
application Ser. No. 13/009,502, filed on Jan. 19, 2011; the
subject matter of this application is incorporated herein by
reference.
BACKGROUND
[0002] 1. Technical Field
[0003] The disclosure relates to a semiconductor structure and a
method for manufacturing the same.
[0004] 2. Description of the Related Art
[0005] Memory devices are used in storage elements for many
products such as MP3 players, digital cameras, computer files, etc.
As the application increases, the demand for the memory device
focuses on small size and large memory capacity. For satisfying the
requirement, a memory having a high element density is need.
[0006] Designers have developed a method for improving a memory
device density, using 3D stack memory device so as to increase a
memory capacity and a cost per cell. However, the scaling
limitation of a memory cell size of this kind of the memory device
is still bigger than 50 nm. It is not easy to breakthrough the
limitation. The performance of the memory device may also be
limited due to its element material.
SUMMARY
[0007] A method for manufacturing a semiconductor structure is
provided. The method comprises following steps. A first
silicon-containing conductive material is formed on a substrate. A
second silicon-containing conductive material is formed on the
first silicon-containing conductive material. The first
silicon-containing conductive material and the second
silicon-containing conductive material have different dopant
conditions. The first silicon-containing conductive material and
the second silicon-containing conductive material are thermally
oxidized for turning the first silicon-containing conductive
material wholly into an insulating oxide structure, and the second
silicon-containing conductive material into a silicon-containing
conductive structure and an insulating oxide layer on the surface
of the silicon-containing conductive structure and contact with the
silicon-containing conductive structure.
[0008] A semiconductor structure is provided. The semiconductor
structure comprises a substrate, an insulating oxide structure, a
silicon-containing conductive structure, and an insulating oxide
layer. The insulating oxide structure is formed on the substrate.
The silicon-containing conductive structure and the insulating
oxide layer are formed on the insulating oxide structure. At least
one of the insulating oxide structure and the insulating oxide
layer has a bird's beak profile.
[0009] The following description is made with reference to the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 to FIG. 4 illustrate a method for manufacturing a
semiconductor structure in one embodiment.
[0011] FIG. 5 illustrates a semiconductor device in one
embodiment.
DETAILED DESCRIPTION
[0012] Embodiments of the present disclosure relate to a
semiconductor structure and a method for manufacturing the same.
The semiconductor has a small feature size and excellent
characteristic.
[0013] FIG. 1 to FIG. 4 illustrate a method for manufacturing a
semiconductor structure in one embodiment. Referring to FIG. 1,
first silicon-containing conductive materials 4 and second
silicon-containing conductive materials 6 are stacked on a
substrate 2. The second silicon-containing conductive materials 6
are separated from each other by the first silicon-containing
conductive materials 4. For example, the first silicon-containing
conductive material 4 has a thickness T1, about 20 nm. The second
silicon-containing conductive material 6 has a thickness T2, about
40 nm.
[0014] Referring to FIG. 1, in one embodiment, the substrate 2 is
single crystal silicon, and the first silicon-containing conductive
materials 4 and the second silicon-containing conductive materials
6 are single crystal silicon formed from the substrate 2 by an
epitaxial growth. For example, the substrate 2 is single crystal
silicon. The first silicon-containing conductive material 4 is
single crystal silicon formed from the substrate 2 by an epitaxial
growth. The second silicon-containing conductive material 6 is
single crystal silicon formed from the first silicon-containing
conductive material 4 by an epitaxial growth. The first
silicon-containing conductive material 4 is single crystal silicon
formed from the second silicon-containing conductive material 6 by
an epitaxial growth. Therefore, the second silicon-containing
conductive materials 4 and the second silicon-containing conductive
material 6 can be single crystal having an excellent structure and
conductivity characteristic. Thus performance of the semiconductor
structure is improved.
[0015] The first silicon-containing conductive materials 4 and the
second silicon-containing conductive materials 6 are patterned for
forming stacked structures 8 as shown in FIG. 2. Referring to FIG.
2, each of the stacked structure 8 comprises the first
silicon-containing conductive materials 4 and the second
silicon-containing conductive materials 6 stacked alternately. A
method for the pattering comprises removing a part of the first
silicon-containing conductive materials 4 and the second
silicon-containing conductive materials 6 by an etching process. In
one embodiment, the first silicon-containing conductive materials 4
and the second silicon-containing conductive materials 6 have
similar materials such as silicon. Thus, the etching process has
substantially the same etching rate for the first
silicon-containing conductive materials 4 and the second
silicon-containing conductive materials 6. Therefore, the etching
process CaO be exactly controlled to patterning the first
silicon-containing conductive materials 4 and the second
silicon-containing conductive materials 6 into a fine profile or
high aspect ratio. For example, the stacked structure 8 has a width
W, about 20 nm. The two adjacent stacked structures 8 has a
distance D, about 130 nm, therebetween.
[0016] Each of the first silicon-containing conductive materials 4
and the second silicon-containing conductive materials 6 are
thermally oxidized for turning the first silicon-containing
conductive material 4 wholly into an insulating oxide structure 16,
and the second silicon-containing conductive material 6 into a
silicon-containing conductive structure 18 and an insulating oxide
layer 20 on the surface of the silicon-containing conductive
structure 18 and contact witch the silicon-containing conductive
structure 18 as shown in FIG. 3. Referring to FIG. 3 the insulating
oxide structure 16 and the insulating oxide layer 20 have a bird's
beak profile. For example, the thermally oxidizing process
comprises heating the first silicon-containing conductive materials
4 (FIG. 2) and the second silicon-containing conductive materials 6
placed in an oxygen condition, diffusing oxygen into the first
silicon-containing conductive materials 4 and the second
silicon-containing conductive materials 6 from the surfaces of
which to react to produce an insulating oxide such as silicon
oxide.
[0017] In embodiments, the first silicon-containing conductive
material 4 (FIG. 2) and the second silicon-containing conductive
material 6 have different dopant conditions. Thus, under a thermal
oxidizing process of the same condition, or during the thermally
oxidizing the first silicon-containing conductive materials 4 and
the second silicon-containing conductive materials 6
simultaneously, the first silicon-containing conductive material 4
and the second silicon-containing conductive material 6 have
different oxide diffusion rates. In embodiments, the first
silicon-containing conductive material 4 and the second
silicon-containing conductive material 6 have dopants of different
concentrations and the same conductivity type. For example, the
first silicon-containing conductive material 4 and the second
silicon-containing conductive material 6 both have N type dopant,
and the concentration of the N type dopant of the first
silicon-containing conductive material 4 is bigger than the
concentration of the N type dopant of the second silicon-containing
conductive material 6. For example, there may be 2-3 orders
difference between the concentrations of the N type dopants of the
first silicon-containing conductive material 4 and the second
silicon-containing conductive material 6. Therefore, the first
silicon-containing conductive material 4 has an oxide diffusion
rate higher than an oxide diffusion rate the second
silicon-containing conductive material 6 has. The N-type dopant
comprises a VIA-group element such as P, As etc. Otherwise, the
first silicon-containing conductive material 4 and the second
silicon-containing conductive material 6 both have P type dopant.
In addition, the concentration of the P type dopant of the first
silicon-containing conductive material 4 is different from the
concentration of the P type dopant of the second silicon-containing
conductive material 6. The P-type dopant comprises a IIIA-group
element such as B etc. The oxidation situation of the first
silicon-containing conductive material 4 and the second
silicon-containing conductive material 6 can he controlled by
adjusting parameters of the oxidizing process such as a heating
temperature, a heating time, etc.
[0018] The insulating oxide layers 20 are removed for forming
stacked structures 22 as shown in FIG. 4. In embodiments, the
insulating oxide layers 20 are removed by using an etching process
having an etching selectivity to an insulating oxide (such as
silicon oxide) and a silicon-containing conductive material (such
as single crystal silicon). Thus, during the removing the
insulating oxide layer 20, a part of the insulating oxide structure
16 is also removed simultaneously. The insulating oxide structure
16 becomes small. Meanwhile, the silicon-containing conductive
structure 18 is not damaged substantially. For example, the etching
process comprises a dry etching method or a wet etching method.
[0019] FIG. 5 illustrates a semiconductor device in one embodiment.
Referring to FIG. 5, in embodiments, a dielectric element 124 is
formed on the stacked structures 122 similar with the stacked
structure 22 shown in FIG. 4, and conductive lines 126 are formed
on the dielectric element 124 for forming a 3D vertical gate memory
device, for example, comprising a NAND flash memory and an
anti-fuse memory, etc. For example, the silicon-containing
conductive structures 118 of different layers in the stacked
structure 22 act as bit lines (BL) of memory cells of different
planes. The conductive line 126 comprises, for example,
polysilicon. The conductive lines 126 may act as word lines (WL),
ground selection lines (GSL), or string selection lines (SSL). The
dielectric element 124 may have a multi-layers structure, for
example, which may be an ONO composite layers, an ONONO composite
layers, or a BE-SONOS composite layers (referring to U.S. Ser. No.
11/419,977 or U.S. Pat. No. 7,414,889), or comprise dielectric
layers 128, 130, 132, for example. In one embodiment, the
dielectric layer 128 is silicon oxide, the dielectric layer 130 is
silicon nitride, and the dielectric layer 132 is silicon oxide. In
other embodiments, the dielectric element 124 is a single-layer
dielectric material (not shown), comprising a silicon nitride, or a
silicon oxide such as silicon dioxide or silicon oxynitride.
[0020] While the disclosure has been described by way of example
and in terms of the exemplary embodiment(s), it is to be understood
that the disclosure is not limited thereto. On the contrary, it is
intended to cover various modifications and similar arrangements
and procedures, and the scope of the appended claims therefore
should be accorded the broadest interpretation so as to encompass
all such modifications and similar arrangements and procedures.
* * * * *