U.S. patent application number 13/955386 was filed with the patent office on 2014-02-06 for integrated circuit interposer and method of manufacturing the same.
This patent application is currently assigned to Marvell International Ltd.. The applicant listed for this patent is Marvell International Ltd.. Invention is credited to Ido Bourstein, Carol Pincu.
Application Number | 20140035093 13/955386 |
Document ID | / |
Family ID | 50024657 |
Filed Date | 2014-02-06 |
United States Patent
Application |
20140035093 |
Kind Code |
A1 |
Pincu; Carol ; et
al. |
February 6, 2014 |
Integrated Circuit Interposer and Method of Manufacturing the
Same
Abstract
Systems and methods are provided for an interposer for coupling
two or more integrated circuit dies to a circuit package. A first
integrated circuit portion is disposed on a first location of a
single semiconductor substrate. A second integrated circuit portion
is disposed on a second location of the single semiconductor
substrate, where the second integrated circuit portion is
electrically isolated from the first integrated circuit portion
along a first axis. The first and second integrated circuit
portions are configured to provide an electrical coupling to two or
more corresponding top die integrated circuits across a second axis
that is perpendicular to the first axis.
Inventors: |
Pincu; Carol; (Rison
Leziyon, IL) ; Bourstein; Ido; (Pardes Hana,
IL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Marvell International Ltd. |
Hamilton |
|
BM |
|
|
Assignee: |
Marvell International Ltd.
Hamilton
BM
|
Family ID: |
50024657 |
Appl. No.: |
13/955386 |
Filed: |
July 31, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61678506 |
Aug 1, 2012 |
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|
61694151 |
Aug 28, 2012 |
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61731975 |
Nov 30, 2012 |
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Current U.S.
Class: |
257/506 ;
438/107; 438/618 |
Current CPC
Class: |
H01L 23/544 20130101;
H01L 21/8221 20130101; H01L 2924/157 20130101; H01L 23/5385
20130101; H01L 21/4857 20130101; H01L 21/82 20130101; H01L
2224/16225 20130101; H01L 23/49838 20130101; H01L 25/0657 20130101;
H01L 25/50 20130101; H01L 2924/15192 20130101; H01L 25/0655
20130101; H01L 23/147 20130101; H01L 2924/15311 20130101; H01L
23/12 20130101; H01L 23/49827 20130101; H01L 21/78 20130101 |
Class at
Publication: |
257/506 ;
438/618; 438/107 |
International
Class: |
H01L 25/065 20060101
H01L025/065 |
Claims
1. An interposer for coupling two or more integrated circuit dies
to a circuit package, comprising: a first integrated circuit
portion disposed on a first location of a single semiconductor
substrate; and a second integrated circuit portion disposed on a
second location of the single semiconductor substrate, the second
integrated circuit portion being electrically isolated from the
first integrated circuit portion along a first axis, the first and
second integrated circuit portions being configured to provide an
electrical coupling, to two or more corresponding top die
integrated circuits across a second axis that is perpendicular to
the first axis.
2. The interposer of claim 1, wherein a size of each of the first
and second integrated circuit portions corresponds to a reticle
size of one or more reticle masks that are used to fabricate the
first integrated circuit portion and second integrated circuit
portion respectively.
3. The interposer of claim 1, wherein a combined size of the first
integrated circuit portion and the second integrated circuit
portion is larger than a reticle size of a reticle mask that is
used to fabricate the first integrated circuit portion and the
second integrated circuit portion.
4. The interposer of claim 1, wherein the first integrated circuit
portions and the second integrated circuit portion include patterns
of electrical connections for electrically connecting the two or
more corresponding top die portions, the patterns of at least some
electrical connections extending in a direction parallel to the
first axis.
5. The interposer of claim 1, wherein the first integrated circuit
portion and the second integrated circuit portion are formed from
neighboring, but un-scribed, reticle locations on a semiconductor
wafer substrate.
6. The interposer of claim 1, wherein the first integrated circuit
portion is electrically isolated from the second integrated circuit
portion by seal rings that extend along the first axis between the
first integrated circuit portion and the second integrated circuit
portion.
7. The interposer of claim 6, wherein a first seal ring surrounds
the first integrated circuit portion, and a second seal ring
surrounds the second integrated circuit portion, wherein the first
seal ring and the second seal ring are separated by a space.
8. The interposer of claim 1, wherein the first integrated circuit
portion and the second integrated circuit portion each include the
same pattern of electrical connections for electrically connecting
the two or more corresponding top die integrated circuits.
9. The interposer of claim 1, wherein the first integrated circuit
portion and the second integrated circuit portion each include a
different patterns of electrical connections for electrically
connecting the two or more corresponding top die integrated
circuits.
10. A method of fabricating an interposer for coupling two or more
integrated circuit dies to an integrated circuit package,
comprising: printing a first interposer portion at a first reticle
position on an integrated circuit wafer substrate: printing a
second interposer portion at a second reticle position on the
integrated circuit wafer substrate, the second reticle position
being adjacent the first reticle position; providing an isolation
axis between the first and second interposer portions on the
integrated circuit wafer substrate, the isolation axis electrically
isolating the first interposer portion from the second interposer
portion; and cutting the integrated circuit wafer substrate without
cutting along the isolation axis to form an interposer that
includes the first interposer portion and the second interposer
portion.
11. The method of claim 10, wherein the interposer is configured to
provide an electrical coupling to two or more corresponding top die
integrated circuits across a second axis that is perpendicular to
the isolation axis.
12. The method of claim 10, further comprising: lubricating the
first and second interposer portions using a reticle mask such that
a size of each of the first and second integrated circuit portions
corresponds to a reticle size of the reticle mask.
13. The method of claim 10, further comprising: fabricating the
first and second interposer portions using a reticle mask such that
a combined size of the first and second integrated circuit portions
is larger than a reticle size of the reticle mask.
14. The method of claim 10, wherein the isolation axis comprises an
internal double seal ring.
15. The method of claim 11, wherein the first and second interposer
portions each include patterns of electrical connections for
electrically connecting the two or more e corresponding top die
portions, the patterns of electrical connections each extending in
a direction parallel to the isolation axis.
16. The method of claim 11, wherein the first and second interposer
portions are fabricated using the same reticle mask for generating
a pattern of electrical connections for electrically connecting the
two or more corresponding top die integrated circuits.
17. The method of claim 11, wherein the first and second interposer
portions are fabricated using the different reticle masks such that
the first and second interposer portions each include a different
pattern of electrical connections for electrically connecting the
two or more corresponding top die integrated circuits.
18. The method of claim 11, wherein the first and second interposer
portions are printed contemporaneously.
19. An integrated circuit package, comprising: an interposer that
includes a first integrated circuit portion disposed on a first
location of a single semiconductor substrate and a second
integrated circuit portion disposed on a second location of the
single semiconductor substrate, wherein the second integrated
circuit portion is electrically isolated from the first integrated
circuit portion by an isolation axis that extends between the first
and second integrated circuit portions; and two or more integrated
circuit dies electrically coupled to the first and second
integrated circuit portions of the interposer across a second axis
that is perpendicular to the isolation axis, wherein the first and
second integrated circuit portions of the interposer each include
patterns of electrical connections that electrically connect the
two or more integrated circuit dies and that extend between the two
or more integrated circuit dies in a direction parallel to the
isolation axis.
20. The integrated circuit package of claim 19, wherein the
interposer further comprises a third integrated circuit portion
disposed on a third location of the single semiconductor substrate,
the third integrated circuit portion being electrically isolated
from the first integrated circuit portion and the second integrated
circuit portion; wherein the integrated circuit package further
comprises an additional integrated circuit die electrically coupled
to the third integrated circuit portion and at least one of the
first and second integrated circuit portions of the interposer.
21. The integrated circuit package of claim 20, wherein the third
integrated circuit portion is electrically isolated from the first
integrated circuit portion by a second isolation axis that is
parallel to the isolation axis between the first and second
integrated circuit portions.
22. The integrated circuit package of claim 20, wherein the third
integrated circuit portion is electrically isolated from the first
integrated circuit portion by a second isolation axis that is
perpendicular to the isolation axis between the first and second
integrated circuit portions.
23. A method of fabricating an integrated circuit package,
comprising: printing a first interposer portion at a first reticle
position on an integrated circuit wafer substrate; printing a
second interposer portion at a second reticle position on the
integrated circuit wafer substrate; providing an isolation axis
between the first and second interposer portions on the integrated
circuit wafer substrate, the isolation axis electrically isolating
the first interposer portion from the second interposer portion;
electrically coupling two or more integrated circuit dies to the
first and second interposer portions of the interposer across a
second axis that is perpendicular to the isolation axis; cutting,
the integrated circuit wafer substrate without cutting along the
isolation axis to form an integrated circuit assembly comprising
the two or more integrated circuit dies electrically coupled to an
interposer that includes the first interposer portion and the
second interposer portion; and coupling the interposer to a package
substrate to form the integrated circuit package.
24. The method of claim 23, wherein the cutting comprises a dicing
procedure that utilizes a diamond saw or a laser.
25. The method of claim 23, wherein the integrated circuit wafer
substrate is cut prior to electrically coupling the two or more
integrated circuit dies to the first and second interposer
portions.
Description
CROSS-REFERENCE 10 RELATED APPLICATIONS
[0001] The present application claims priority from U.S.
Provisional Application Ser. No. 61/678,506 entitled "Max Size
Interposer, filed 1 Aug. 2012, U.S. Provisional Application Ser.
No. 61/694,151 entitled "Max Size Interposer," filed 28 Aug. 2012,
and U.S. Provisional Application Ser. No. 61/731,975 entitled
"Multi-Interposer Assembly," filed 30 Nov. 2012, the entirety of
which are hereby incorporated by reference.
FIELD
[0002] This disclosure is related generally to integrated circuit
fabrication and more particular to integrated circuit interposer
fabrication.
BACKGROUND
[0003] The maximum size of an integrated circuit die is typically
limited by the reticle size of the photomask used during the
integrated circuit fabrication process. Some devices, however, are
approaching a practical size limitation, not maximal theoretical
size, for manufacture on a single integrated circuit die.
Interposers have been used in semiconductor device fabrication, for
example, to route electrical interconnections between devices, to
make high density chip package interfaces, to create devices from
multiple smaller integrated circuit chips and the like,
[0004] The description above is presented as a general overview of
related art in this field and should not be construed as an
admission that any of the information it contains constitutes prior
art against the present patent application.
SUMMARY
[0005] Systems and methods are provided for an interposer for
coupling two or more integrated circuit dies to a circuit package.
A first integrated circuit portion is disposed on a first location
of a single semiconductor substrate. A second integrated circuit
portion is disposed on a second location of the single
semiconductor substrate, where the second integrated circuit
portion is electrically isolated front the first integrated circuit
portion along a first (isolation) axis. The first and second
integrated circuit portions are configured to provide an electrical
coupling to two or more corresponding top die integrated circuits
across a second axis that is perpendicular to the first axis.
[0006] As another example, an integrated circuit package includes
an interposer that includes a first integrated circuit portion
disposed on a first location of a single semiconductor substrate
and a second integrated circuit portion disposed on a second
location of the single semiconductor substrate. The second
integrated circuit portion is electrically isolated from the first
circuit portion by an isolation axis that extends between the first
and second integrated circuit portions. Two or more integrated
circuit dies are electrically coupled to the first and second
integrated circuit portions of the interposer across a second axis
that is perpendicular to the isolation axis, where the first and
second integrated circuit portions of the interposer each include
patterns of electrical connections that electrically connect the
two or more integrated circuit dies and that extend between the two
or more integrated circuit dies in a direction parallel to the
isolation axis.
[0007] As an additional example, a method of fabricating an
interposer for coupling two or more integrated circuit dies to an
integrated circuit package includes printing a first interposer
portion at a first reticle position on an integrated circuit wafer
substrate. A second interposer portion is printed at a second
reticle position on the integrated circuit wafer substrate, the
second reticle position being adjacent to the first reticle
position. An isolation axis is provided between the first and
second interposer portions on the integrated circuit wafer
substrate, where the isolation axis electrically isolates the first
interposer portion from the second interposer portion, and the
integrated circuit wafer substrate is cut without cutting along the
isolation axis to form an interposer that includes the first
interposer portion and the second interposer portion.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a top view of an example integrated circuit
package that includes two integrated circuit die that are disposed
on a package substrate via a silicon interposer in accordance with
an embodiment of the present disclosure.
[0009] FIG. 2A is a cross-sectional view of the integrated circuit
package seen in FIG. 1.
[0010] FIG. 2B is a second cross-sectional view of the integrated
package seen in FIG. 1.
[0011] FIG. 3 illustrates a silicon wafer including a silicon
interposer configured for interconnecting two or more integrated
circuit die in accordance with the embodiment of FIG. 1.
[0012] FIG. 4 is a diagram depicting example electrical
interconnections of an integrated circuit package comprising an
interposer and two or more integrated circuit dies in accordance
with an embodiment of the disclosure.
[0013] FIG. 5 is a diagram depicting example electrical
interconnections of an integrated circuit package comprising an
interposer and two or more integrated circuit dies in accordance
with another embodiment of the disclosure.
[0014] FIG. 6 is a diagram depicting formulation of different
integrated circuit portions at reticle locations of a semiconductor
wafer in accordance with an embodiment of the disclosure.
[0015] FIG. 7 is a diagram depicting example interposer integrated
circuit portion testing results in accordance with embodiment of
the disclosure.
[0016] FIG. 8 is a diagram depicting positions for installation of
top the integrated circuits.
[0017] FIG. 9 is a diagram depicting dicing of interposers from a
tested wafer in accordance with an embodiment of the
disclosure.
[0018] FIG. 10 is a block diagram depicting the connection of three
circuit components using two interposer portions in accordance with
another embodiment of the disclosure.
[0019] FIG. 11 is a block diagram depicting the connection of n
circuit components using m interposer portions in an integrated
circuit package.
[0020] FIG. 12 is a flow diagram depicting a method of fabricating
an interposer for coupling two or more integrated circuit dies to
an integrated circuit package in accordance with an embodiment of
the disclosure.
[0021] FIG. 13 is a flow diagram depicting a method of fabricating
an integrated circuit package in accordance with an embodiment of
the disclosure.
DETAILED DESCRIPTION
[0022] FIG. 1 is a top view of an example integrated circuit
package 100 that includes two integrated circuit top die 102, 104
that are electrically coupled to a package substrate 106 via a
silicon interposer 108 in one embodiment of the disclosure. As
illustrated, the silicon interposer 108 includes a first integrated
circuit portion 111 and a second integrated circuit portion 113,
where the first and second top die integrated circuits 102, 104 are
connected so as to span an isolation axis 115 that runs between the
first and second interposer integrated circuit portions 111,
113.
[0023] A cross-sectional view of the integrated circuit package 100
of one embodiment of the disclosure is illustrated. FIG. 2A. The
cross-sectional view shown in FIG. 2A includes three magnified
views 110, 112, 114 to illustrate examples of how the silicon
interposer 108 electrically couples the two integrated circuit die
102, 104 to each other and to the package substrate. The silicon
interposer 108 includes through-silicon vias (TSVs) 116 and
interconnection traces 118 for eclectically coupling connectors 120
(e.g., connector bumps, micro-bumps) on the integrated circuit die
102, 104 to connectors 122 (e.g., connector bumps) on a bottom
surface of the silicon interposer 108. The silicon interposer
connectors 122 are electrically coupled to connectors 124 (e.g.,
solder balls) on a bottom surface of the package substrate 106 by
interconnection vias and layers (not shown) within the package
substrate 106 for connection to external circuitry such as a
printed circuit board. The interconnection traces 118, which pass
through interposer 108, are also used to make electrical
connections between two integrated circuit top die 102, 104, as
shown in magnified view 112 at reference numeral 126.
[0024] For instance, the first magnified cross-sectional view 110
illustrates examples of electrical interconnections 116, 118 made
between connectors 120 on a single integrated circuit die 102 and
silicon interposer connectors 122. The second magnified view 112
illustrates examples of electrical interconnections 126 between two
different integrated circuit die 102, 104 disposed on the silicon
interposer 108. The third magnified view 114 illustrates examples
of electrical interconnections between connectors 120 on the second
integrated circuit die 104 and the silicon interposer connectors
122.
[0025] FIG. 2B is a second cross-sectional view of the integrated
package seen in FIG. 1. The cross-sectional view of FIG. 2B
illustrates the first top die integrated circuit 102 being
connected to the first integrated circuit portion 111 and the
second integrated circuit portion 113 of the interposer 108 to
facilitate communications across the isolation axis 115 that runs
between the two interposer integrated circuit portions. As
illustrated in FIG. 2B, those communication, in one embodiment of
the disclosure, are facilitated by intra-die electrical connections
128, such as metal traces fabricated in one or more layers of the
top die integrated circuit 102. In one embodiment of the
disclosure, the second top die integrated circuit 104 (not shown)
is similarly connected across the isolation axis 115. Thus, the
configuration of FIGS. 2A and 2B enables connection between the
first top die integrated circuit 102 and the second top die
integrated circuit 104 by the intra-interposer 108 electrical
connections 126, while connection between the first integrated
circuit portion 111 of the interposer 108 and the second integrated
circuit portion 113 of the interposer 108 are enabled by electrical
connections 128 within the top die integrated circuits 102,
104.
[0026] FIG. 3 illustrates a silicon interposer 200 configured for
interconnecting two or more integrated circuit die fabricated from
a silicon wafer 202 in one embodiment of the disclosure. The area
of active or passive components (such as TSVs and interconnection
traces) that are patterned on a single die on a silicon wafer is
limited by the reticle size of the photomask, indicated by the size
of the reticle location rectangles 204 in FIG. 3, used in the
photolithography process. In order to pattern multiple die on a
wafer, a single die is patterned at a reticle location 204 and then
the wafer 202, or exposure equipment, such as a stepper, is shifted
to pattern another die, and so on. This process is repeated, as
necessary, to add different patterns and/or layers of material,
such as silicon and metal, to the die. The individual die at
reticle locations 204 on the wafer 202 are physically and
electrically isolated from one another, for example by forming a
double ring seal 206 between reticle locations 204. In one
embodiment of the disclosure, each reticle location 204 is
surrounded by a ring seal, such that reticle locations 204 are
separated from one another by two seals, one associated with each
of the respective two reticle locations 204, and a section of
silicon wafer 202 between the seals, sometimes referred to as a
street. The die at the reticle locations 204 are then separated
from the wafer 202 by cutting (i.e., dicing) the wafer between
double ring seals 206, for example using a laser or diamond tipped
saw 208.
[0027] To fabricate silicon interposers 200 that are large enough
to interconnect two or more integrated circuit die, each silicon
interposer 200 is fabricated using two adjacent reticle locations
204 on the silicon wafer 202. The isolation axis 206 (e.g., the
double ring seal) between the two adjacent reticle locations 204 is
left uncut in order to form a silicon interposer 200 that is more
than twice the size of a single reticle location 204. An example is
illustrated in the magnified view 210 shown in FIG. 3.
[0028] As shown in the magnified view 210, an interposer 200 for
coupling two or more integrated circuit dies to an integrated
circuit package is fabricated by printing a first interposer
portion at a first reticle position 212 on an integrated circuit
wafer substrate 202. A second interposer portion is printed at a
second reticle position 214 on the integrated circuit wafer
substrate 202, the second reticle position 214 being adjacent to
the first reticle position 212. In one embodiment of the
disclosure, the first and second interposer portions are formed
contemporaneously, and in another embodiment of the disclosure, the
first and second interposer portions are formed at different times,
for example in interleaved steps. An isolation axis 206 is provided
between the first and second interposer portions on the integrated
circuit wafer substrate 202, the isolation axis 206 electrically
isolating the first interposer portion 212 from the second
interposer portion 214. The integrated circuit substrate 202 is cut
without cutting along the isolation axis 206 to form an interposer
200 that includes the first interposer portion 212 and the second
interposer portion 214. For example, in one embodiment of the
disclosure, the interposer 200 is formed from two interposer
portions formed at the first reticle position 212 and the second
reticle position 214. After the first and second interposer
portions are formed, the integrated circuit wafer substrate 202 is
cut between the double ring seals 206, such as along dotted line
216 to extract the interposer 200 that spans the two interposer
portions formed at the first reticle position 212 and the second
reticle position 214.
[0029] FIG. 4 is a diagram depicting example electrical
interconnections of an integrated circuit package comprising an
interposer and two or more integrated circuit dies in accordance
with an embodiment of the disclosure. The interposer 402 includes a
first integrated circuit portion 404 disposed on a first location
of a single semiconductor substrate. The interposer 402 further
includes a second integrated circuit portion 406 disposed on a
second, adjacent location of the single semiconductor substrate.
The second integrated circuit portion 406 is electrically isolated
from the first integrated circuit portion 404 along a first
(isolation) axis 408. In one embodiment of the disclosure, the size
of the first and second integrated circuit portions 404, 406
correspond to a reticle size of one or more reticle masks that are
used to fabricate the first integrated circuit portion 404 and the
second integrated circuit portion 406, respectively. Thus, the
complete interposer 402 that includes the first integrated circuit
portion 404 and the second integrated circuit portion 406 is larger
in size than the reticle masks that are used to fabricate those
portions 404, 406, respectively.
[0030] In one embodiment of the disclosure, the first integrated
circuit portion 404 and the second integrated circuit portion 406
are electrically isolated by seal rings 410. During, fabrication, a
seal ring 410 is formed around the periphery of each of the
integrated circuit portions 404, 406, with a street gap 408 being
present between the seal rings 410 along the first axis 408. To
separate the interposer 402 from the larger semiconductor
substrate, streets surrounding the outside of the first integrated
circuit portion 404 and the second integrated circuit portion 406
are cut, such as via a laser or saw, while the street along the
first axis 408 remains un-scribed (uncut), resulting in electrical
separation of the first and second integrated circuit portions 404,
406.
[0031] The first and second integrated circuit portions 404, 406
are configured to provide an electrical coupling to two or more
corresponding to die integrated circuits 412, 414, respectively
depicted as an outline, that are positioned so as to each span the
first and second integrated circuit portions 404, 406 along a
second axis 418 that is perpendicular to the first axis 408. The
top die integrated circuits 412, 414 are electrically coupled to
the interposer 402 via contacts 416 formed on the first and second
integrated circuit portions 404, 406 of the interposer 402. For
example, in one embodiment of the disclosure, electrically coupling
connectors (e.g., connector bumps or micro-bumps) of the top die
integrated circuits 412, 414 are matched to the contacts 416 to
facilitate communications between the top die integrated circuits
412, 414 and other components the interposer. In one embodiment of
the disclosure, one or more of the first integrated circuit portion
404 and the second integrated circuit portion 406 of the interposer
402 are fabricated to include electrical connections 420 within the
interposer integrated circuit portions 404, 406 that extend in a
direction parallel to or substantially parallel to the first axis
408. Such connections in the corresponding portion of the
interposer electrically couple the first top die integrated circuit
412 to the second top die integrated circuit 414, despite the
respective top dies being, otherwise electrically isolated from
each other.
[0032] As noted previously, the first integrated circuit portion
and the second integrated circuit portions 404, 406 of the
interposer are electrically isolated from one another. The
configuration of FIG. 4 enables communication, across the isolation
barrier formed by street 408, between the two integrated circuit
portions 404, 406 and any components connected thereto (as shown
and described, for example, in FIG. 10) by way of internal
connections formed in the first top die integrated circuit 412
and/or the second top die integrated circuit 414. Thus, the first
and second top die integrated circuits 412, 414 are connected b the
intra-interposer electrical connections 420, and the first and
second integrated circuit portions 404, 406 are connected through
internal electrical couplings formed in one or more internal layers
of the first and second top die integrated circuits 412, 414.
[0033] In one embodiment of the disclosure, depicted in FIG. 4, the
pattern of top die integrated circuit contacts 416 and other
internal connections(e.g., at 420) are the same for both the first
integrated circuit portion 404 and the second integrated circuit
portion 406 of the interposer 402. In such an embodiment, all of
the reticle locations of a silicon wafer substrate, such as those
shown at 204 in FIG. 3, are formed according to the same
fabrication pattern. In other embodiments, integrated circuit
portion fabrication patterns differ across reticle locations of a
substrate.
[0034] FIG. 5 is a diagram depicting an interposer, similar to the
interposer seen in FIG. 4, for coupling two or more integrated
circuit dies to a circuit package using non-matching interposer
integrated circuit portions in one embodiment of the disclosure.
FIG. 5 discloses an interposer 502 that comprises a first
integrated circuit portion 504 and a second integrated circuit
portion 506 that are electrically separated from one another. In
FIG. 5, the patterns of intra-interposer electrical connections 508
and top die integrated circuit contacts 510 differ between the
first integrated circuit portion 504 and the second integrated
circuit portion 506, such that all of the reticle locations of a
silicon wafer substrate cannot be fabricated identically. In such
an embodiment of the disclosure, certain reticle locations on the
silicon substrate are formed according to a first fabrication
pattern corresponding to the first integrated circuit portion 504
pattern, while neighboring reticle locations are formed according
to a second fabrication pattern corresponding to the second
integrated circuit 506 pattern, as described in further detail with
respect to FIG. 6.
[0035] FIGS. 6-9 describe an example process for manufacturing an
integrated circuit package. FIG. 6 is a diagram depicting
formulation of differing integrated circuit portions at reticle
locations of a substrate in one embodiment of the disclosure. FIG.
6 depicts a silicon substrate 602 and a number of reticle locations
604 defined thereon and represented by the rectangular boxes.
Certain reticle locations 604 of the substrate 602 are designated
for fabrication of an integrated circuit portion of an interposer.
In the embodiment of FIG. 6, first integrated circuit portions 606
of the interposer (represented by northwest-to-southeast diagonal
lines) are to be fabricated according to a different pattern than
second integrated circuit portions 60 (represented by
southwest-to-northeast diagonal lines). In one embodiment of the
disclosure, fabrication of the integrated circuit portions includes
fabricating seal rings around the perimeter of each integrated
circuit portion. Once the integrated circuit portions 606, 608 are
fabricated, they are tested to determine whether that fabrication
was successful.
[0036] FIG. 7 is a diagram depicting example interposer integrated
circuit portion testing results in one embodiment of the
disclosure. After forming the interposer integrated circuit
portions on the substrate 702, those integrated circuit portions
are tested to determine whether or not the respective patterns were
correctly formed. Certain integrated circuit portions, where
testing indicated fabrication failure, are noted at 704. By testing
for interposer integrated circuit portion fabrication failures,
integrated circuit package manufacture costs are reduced, as, in
one embodiment of the disclosure, interposers having integrated
circuit portions identified as failing the fabrication testing will
not have top die integrated circuits installed thereon.
[0037] FIG. 8 is a diagram depicting positions for installation of
top die integrated circuits. Reticle locations of first integrated
circuit portion 802--second integrated circuit portion 804 pairs
are identified on the substrate 806, where neither integrated
circuit portion 802, 804 was identified as a fabrication failure
808. In one embodiment of the disclosure, a first top die
integrated circuit 810 and a second top die integrated circuit 812
are positioned across each of the identified pairs and electrically
coupled (connected) to the pairs prior to dicing the interposers
from the substrate 806. In another embodiments of the disclosure,
the interposers comprising the integrated circuit portion pairs are
cut apart prior to attaching the top die integrated circuits.
[0038] FIG. 9 is a diagram depicting dicing interposers from the
substrate. In a dicing operation in one embodiment of the
disclosure, lasers, diamond tipped saw or other suitable cutting
devices are used to cut the substrate 902 along certain of the
streets between reticle locations (e.g., streets between reticle
location seal rings). Because the interposers comprise integrated
circuit portions at more than one reticle location, cuts (scribes)
are not made along all of the streets. In the embodiment of FIG. 9,
cuts are made along each of the vertical streets 904, and every
other horizontal street, leaving un-sawed lines 908 in between the
cut streets 910 such that individual interposers 912 are formed
that each comprise as first top die integrated circuit 914 and a
second top die integrated circuit 916 connected across a first
integrated circuit portion 918 and a second integrated circuit
portion 920, where the first and second integrated circuit portions
918, 920 are electrically isolated by an isolation axis along the
unsaved line 908, perpendicular to the placement of the first and
second top die integrated circuits 914, 916.
[0039] In addition to connecting two interposer portions using two
top die integrated circuits, as disclosed in the preceding
examples, other embodiments of the disclosure include other
configurations. FIG. 10 is a block diagram depicting the connection
of three circuit components using two interposer portions in an
integrated circuit package, where certain of the circuit components
are connected to wholly separate interposer portions. In the
example of FIG. 10, an interposer 1002 includes an interposer
integrated circuit portion A 1004 and an interposer integrated
circuit portion B 1006 separated along an isolation axis 1007. A
first component 1008 of the integrated circuit package bridges
interposer portion A 1004 and interposer portion B 1006,
facilitating communication among components connected to the
interposer 1002 through internal electrical connections of the
first component 1008 that bridges the isolated interposer portions
1004, 1006. While the first component 1008 includes internal
connections for bridging communications across the isolated
interposer portions 1004, 1006, in one embodiment of the
disclosure, a second component 1010 and a third component 1012 do
not include such interposer-linking internal electrical
connections.
[0040] In one embodiment of the disclosure, the second component
1010 is connected only to interposer portion A 1004, and the third
component 1012 is connected only to interposer portion B 1006.
Communications between the second component 1010 and the first
component 1008 are facilitated via intra-interposer portion
connections of interposer portion A 1004, and communications
between the third component 1012 and the first component 1008 are
facilitated via intra-interposer portion connections of interposer
portion B 1006. Thus, in one embodiment of the disclosure, the
second component 1010 is configured to communicate with the third
component 1012 via a communication path that includes interposer
portion A 1004, the first component 1008, and interposer portion B
1006.
[0041] Components 1008, 1010, 1012 take a variety of forms. For
example, in one embodiment of the disclosure, the second component
1010 is a top die integrated circuit processor component, and the
third component 1012 is a top die integrated circuit memory
component. In another embodiment of the disclosure, the second
component 1010 is a top die I/O integrated circuit component, and
the third component 1012 is a top die integrated circuit memory
component.
[0042] FIG. 11 is a block diagram depicting the connection of n
circuit components using m interposer portions in an integrated
circuit package. In the example of FIG. 11, a number of integrated
circuit components are connected using a number of interposer
portions. In one embodiment of the disclosure, one circuit
component 1102 is connected to each interposer portion 1006 in an
exclusive manner, while circuit components 1104 are positioned to
bridge communications across the interposer portions 1106. Thus, in
one embodiment of the disclosure, n exclusively connected circuit
components and n-1 bridging circuit components communicate across n
interposer portions. In one embodiment of the disclosure, the
interposer portions 1106 are formed from a single semiconductor
substrate and are electrically isolated from one another by
parallel isolation axes 1108 defined by seal rings.
[0043] In other embodiments of the disclosure, different numbers
and configurations of circuit components and interposer portions
are utilized. In the example of FIG. 11, the interposer portions
1106 are positioned in a linear fashion. In other embodiments of
the disclosure, interposer portions 1106 are positioned in a
two-dimensional array with bridging circuit components 1104
connecting those interposer portions 1106 vertically and
horizontally, or in a snaking fashion. In such an embodiment, a
first set of isolation axes are parallel to one another while a
second set of isolation axes are perpendicular to the first set of
isolation axes. In still other embodiments of the disclosure,
multiple circuit components 1102 are connected to one or more of
the interposer portions 1106.
[0044] FIG. 12 is a flow diagram depicting a method of fabricating
an interposer for coupling two or more integrated circuit dies to
an integrated circuit package. At 1202, a first interposer portion
is printed at a first reticle position on an integrated circuit
wafer substrate, and at 1204, a second interposer portion is
printed at a second reticle position on the integrated circuit
wafer substrate, the second reticle position being adjacent the
first reticle position. In the example of FIG. 12, the first and
second interposer portions are printed contemporaneously. In other
embodiments of the disclosure, the first and second interposer
portions are printed at different times. At 1206, an isolation axis
is provided between the first and second interposer portions on the
integrated circuit wafer substrate, where the isolation axis
electrically isolates the first interposer portion from the second
interposer portion, in an embodiment. At 1208, the integrated
circuit wafer substrate is cut without cutting along the isolation
axis to form an interposer that includes the first interposer
portion and the second interposer portion.
[0045] FIG. 13 is a flow diagram depicting, a method of fabricating
an integrated circuit package. At 1302, a first interposer portion
is primed at a first reticle position on an integrated circuit
wafer substrate. At 1304, a second interposer portion is printed at
a second reticle position on the integrated circuit wafer
substrate. An isolation axis is provided at 1306 between the first
and second interposer portions on the integrated circuit wafer
substrate, the isolation axis electrically isolating the first
interposer portion from the second interposer portion. At 1308, two
or more integrated circuit dies are electrically coupled to the
first and second interposer portions of the interposer across a
second axis that is perpendicular to the isolation axis. In one
embodiment of the disclosure, the coupling of the one or more
integrated circuit dies provides electrical connection of the first
and second interposer portions through internal electrical
connections of the one or more integrated circuit dies, while
communications between the one or more integrated circuit dies are
facilitated by intra-interposer portion electrical connections. At
1310, the integrated circuit wafer substrate is cut without cutting
along the isolation axis to form an integrated circuit assembly
comprising the two or more integrated circuit dies electrically
coupled to an interposer that includes the first interposer portion
and the second interposer portion, and at 1312, the interposer is
coupled to a package substrate to form the integrated circuit
package. In the embodiment of FIG. 13, the two or more integrated
circuit dies are electrically coupled to the first and second
interposer portions prior to cutting the integrated circuit wafer
substrate. In other embodiments of the disclosure, the substrate is
cut prior to electrically coupling the integrated circuit dies,
where the top die integrated circuits are mounted onto the
interposers after dicing of the top dies and dicing of the
interposers.
[0046] This application uses examples to illustrate the invention.
The patentable scope of the invention includes other examples.
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