U.S. patent application number 13/939941 was filed with the patent office on 2014-01-16 for contact mems architecture for improved cycle count and hot-switching and esd.
The applicant listed for this patent is RF Micro Devices, Inc.. Invention is credited to Jonathan Hale Hammond, Nadim Khlat.
Application Number | 20140015731 13/939941 |
Document ID | / |
Family ID | 49913542 |
Filed Date | 2014-01-16 |
United States Patent
Application |
20140015731 |
Kind Code |
A1 |
Khlat; Nadim ; et
al. |
January 16, 2014 |
CONTACT MEMS ARCHITECTURE FOR IMPROVED CYCLE COUNT AND
HOT-SWITCHING AND ESD
Abstract
The disclosure is directed to optimized switching circuitry
utilizing MEMS (Microelectromechanical Systems) circuitry in series
with solid state circuitry. Specifically, the MEMS circuitry
includes a first MEMS circuit in parallel with (and separate from)
a second MEMS circuit. A paired signal is defined as a transmit
signal and a receive signal (in a single band) that are transmitted
or received on separate paths or on separate nodes. The transmit
signal is associated with the first MEMS circuit, and the receive
signal is associated with the second MEMS circuit. The solid state
circuitry switches between the first MEMS circuit and second MEMS
circuit without requiring any switching in the first or second MEMS
circuits.
Inventors: |
Khlat; Nadim; (Cugnaux,
FR) ; Hammond; Jonathan Hale; (Oak Ridge,
NC) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
RF Micro Devices, Inc. |
Greensboro |
NC |
US |
|
|
Family ID: |
49913542 |
Appl. No.: |
13/939941 |
Filed: |
July 11, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61670299 |
Jul 11, 2012 |
|
|
|
Current U.S.
Class: |
343/876 ;
307/113 |
Current CPC
Class: |
H01Q 1/50 20130101; H04B
1/44 20130101; H01H 1/0036 20130101; H01Q 21/0006 20130101; H01H
9/548 20130101 |
Class at
Publication: |
343/876 ;
307/113 |
International
Class: |
H01H 1/00 20060101
H01H001/00; H01Q 1/50 20060101 H01Q001/50; H01H 9/54 20060101
H01H009/54 |
Claims
1. Optimized switching circuitry comprising: MEMS
(Microelectromechanical Systems) circuitry including a first MEMS
circuit and a second MEMS circuit, wherein the first MEMS circuit
and the second MEMS circuit are in parallel with each other; and
solid state circuitry in series with the MEMS circuitry.
2. The optimized switching circuitry of claim 1, further
comprising: a first signal pair of nodes in a first band, wherein
the first signal pair of nodes includes a first transmit signal
node and a first receive signal node, wherein the first transmit
signal node is associated with the first MEMS circuit, and wherein
the first receive signal node is associated with the second MEMS
circuit.
3. The optimized switching circuitry of claim 2, wherein the solid
state circuitry includes SOI (Silicon-On-Insulator) circuitry.
4. The optimized switching circuitry of claim 2, wherein the solid
state circuitry is configured to quickly switch back and forth
between the first MEMS circuit and the second MEMS circuit, thereby
quickly switching back and forth between the first transmit signal
node and the first receive signal node without requiring any MEMS
switching.
5. The optimized switching circuitry of claim 4, further comprising
a second signal pair of nodes including a second transmit signal
node and a second receive signal node, wherein the second transmit
signal node is associated with the first MEMS circuit, and wherein
the second receive signal node is associated with the second MEMS
circuit.
6. The optimized switching circuitry of claim 4, further comprising
a second signal pair of nodes including a second transmit signal
node and a second receive signal node, wherein the second transmit
signal node is associated with the second MEMS circuit, and wherein
the second receive signal node is associated with the first MEMS
circuit.
7. The optimized switching circuitry of claim 4, wherein the first
MEMS circuit includes a SPNT (Single Pole, N Throws) MEMS switch,
wherein a first throw of the N throws is associated with the first
transmit signal node; wherein a second throw of the N throws is
associated with the second transmit signal node; wherein the second
MEMS circuit includes a SPMT (Single Pole, M Throws) MEMS switch;
wherein a first throw of the M throws is associated with the first
receive signal node; and wherein a second throw of the M throws is
associated with the second receive signal node;
8. The optimized switching circuitry of claim 7, wherein the solid
state circuitry includes a SPLT (Single Pole, L Throws) solid state
switch; wherein a first throw of the L throws is associated with
the single pole of the first MEMS circuit; wherein a second throw
of the L throws is associated with the single pole of the second
MEMS circuit; wherein the single pole of the solid state circuitry
is associated with an antenna.
9. The optimized switching circuitry of claim 8, wherein the solid
state circuitry includes SOI (Silicon-On-Insulator) circuitry.
10. The optimized switching circuitry of claim 8, further
comprising: a controller, wherein the controller is configured to
switch the solid state circuitry and to switch the MEMS
circuitry.
11. The optimized switching circuitry of claim 10, wherein the
controller is configured to cause the following steps to occur:
during a first period: set the solid state circuitry to communicate
with the first transmit signal node through the first MEMS circuit;
during a second period: switch the solid state circuitry to
communicate with the first receive signal node through the second
MEMS circuit without switching any MEMS switch in the MEMS
circuitry; during a third period: set switch solid state circuitry
to communicate with the first transmit signal node through the
first MEMS circuit, then switch OFF a MEMS switch associated with
the first receive signal node, then switch ON a MEMS switch
associated with the second receive signal node; during a fourth
period: switch the solid state circuitry to communicate with the
second receive signal node, then switch OFF a MEMS switch
associated with the first transmit signal node, then switch ON a
MEMS switch associated with the second transmit signal node; during
a fifth period: switch the solid state circuitry to communicate
with the second transmit signal node; during a sixth period: switch
the solid state circuitry to communicate with the second receive
signal node.
12. The optimized switching circuitry of claim 10, wherein the
controller is configured to cause the following steps to occur: a)
switch the MEMS circuitry so that: the first transmit signal node
is selected by the first MEMS circuit, the first receive signal
node is selected by the second MEMS circuit, and the first MEMS
circuit is selected by the solid state circuitry; b) switch the
second MEMS circuit to deselect the first receive signal node; c)
switch the second MEMS circuit to select the second receive signal
node; d) switch the solid state circuitry to select the second MEMS
circuit; e) switch the first MEMS circuit to deselect the first
transmit signal node; and f) switch the first MEMS circuit to
select the second transmit signal node.
13. The optimized switching circuitry of claim 8, further
comprising a bidirectional coupler located between the solid state
circuitry and a first antenna.
14. The optimized switching circuitry of claim 13, further
comprising a measurement semiconductor circuit configured to
receive bidirectional power information from the bidirectional
coupler.
15. The optimized switching circuitry of claim 14, wherein the MEMS
circuitry further includes a third MEMS circuit, and wherein the
third MEMS circuit is configured to route at least the first
transmit signal node to a second antenna.
16. Optimized switching circuitry comprising: MEMS circuitry
including an SPNT MEMS switch, wherein the SPNT MEMS switch is
configured to select one out of at least two signal nodes, and to
route the selected signal node to an antenna; and solid state
circuitry in parallel with the MEMS circuitry, wherein the solid
state circuitry includes a SPMT solid state switch, and wherein the
SPMT solid state switch is configured to select one out of at least
two additional signal nodes, and to route the selected additional
signal node to the antenna.
17. The optimized switching circuitry of claim 16, wherein the
solid state circuitry includes a controller configured to control
the SPNT MEMS switch and the SPMT solid state switch.
18. The optimized switching circuitry of claim 17, wherein the
controller controls the SPNT MEMS switch via control lines.
19. The optimized switching circuitry of claim 17, further
comprising: a pilot switch configured to ground the antenna upon
receiving a command from the controller.
20. The optimized switching circuitry of claim 19, wherein the
controller is configured to control the SPNT MEMS switch, the SPMT
solid state switch, and the pilot switch by causing the following
steps to be performed: during a first period: switch the solid
state circuitry to select a first solid state signal node, then
switch the solid state circuitry to deselect the first solid state
signal node and to select a second solid state signal node; during
a second period: switch the pilot switch to ground the antenna,
then switch the MEMS circuitry to select a first MEMS signal node,
then switch the pilot switch to isolate the antenna from a ground;
during a third period: switch the pilot switch to ground the
antenna, then switch the MEMS circuitry to deselect a first MEMS
signal node and to select a second MEMS signal node, then switch
the pilot switch to isolate the antenna from a ground; during a
fourth period: switch the pilot switch to ground the antenna, then
switch the MEMS circuitry to deselect the second MEMS signal node,
then switch the pilot switch to isolate the antenna from a ground;
and during a fifth period: switch the solid state circuitry to
select the first solid state signal node, then switch the solid
state circuitry to deselect the first solid state signal node and
to select a second solid state signal node.
Description
RELATED APPLICATIONS
[0001] This application claims the benefit of provisional patent
application Ser. No. 61/670,299, filed Jul. 11, 2012, the
disclosure of which is hereby incorporated herein by reference in
its entirety.
FIELD OF THE DISCLOSURE
[0002] The field of the disclosure is optimized switching circuitry
utilizing MEMS (Microelectromechanical Systems) switches in series
with solid state switches, or in parallel with solid state
switches. Specifically, a MEMS switch is located in series with an
SOI (Silicon-On-Insulator) switch.
BACKGROUND
[0003] Contact MEMS switches offer very low insertion loss,
especially when building switch matrices with high throw counts
(e.g. SP6T up to SP13T) and when operating at high frequencies
(e.g. 2300 to 2700 MHz).
[0004] However, contact MEMS switches suffer from problems that
affect their performance. For example, the following design
constraints are difficult to achieve with MEMS switches: a maximum
number of switching cycles over the lifetime of operation of at
least 1 e10 to 3e10 cycles; a fast switching time of less than 10
.mu.s (this constraint requires very good anti-rebound control in
MEMS); hot-switching capability (MEMS generally requires that the
RF power is less than +0 dBm in order to avoid sparking and local
heating that could degrade reliability); and tolerance for ESD
(electrostatic discharge) events such as antenna discharge.
[0005] Thus, it is difficult to meet many design constraints using
only MEMS switches.
SUMMARY
[0006] Conventionally, switches in a circuit (such as an RF Front
End circuit in a mobile communication device) are either all MEMS
switches, or all solid state switches. Solid state includes SOI
(Silicon-On-Insulator), III-IV semiconductors such as GaAs, and
other devices built from solid materials in which the electrons or
other charge carriers are confined within the solid material. Solid
state excludes vacuum and gas-discharge tubes, and excludes
electro-mechanical devices such as relays and switches with moving
parts. MEMS switches and solid state switches have relative
advantages, and relative disadvantages in comparison to each other.
For example, MEMS switches have the following disadvantages
relative to solid state switches: low cycle lifetimes; slow
switching times (e.g. 40 .mu.s); poor hot switching; and poor
resistance to ESD events. However, MEMS switches have the following
advantages relative to solid state switches: low insertion loss,
high linearity, and high power stand-off capability.
[0007] In one embodiment, a MEMS switch is placed in series with an
SOI switch. The MEMS switch switches when changing frequency bands,
while the SOI switch switches when changing between transmitting
and receiving in a single band.
[0008] In another embodiment, a MEMS switch is placed in parallel
with an SOI switch. Signals requiring fast switching (e.g.
substantially less than 40 .mu.s) or frequent switching are routed
to the SOI switch, and signals that do not require fast or frequent
switching are routed to the MEMS switch. For example, TDD (Time
Division Duplexing) signals are routed to the SOI switch, and FDD
(Frequency Division Duplexing) signals are routed to the MEMS
switch.
[0009] Those skilled in the art will appreciate the scope of the
present disclosure and realize additional aspects thereof after
reading the following detailed description of the preferred
embodiments in association with the accompanying drawing
figures.
BRIEF DESCRIPTION OF THE DRAWING FIGURES
[0010] The accompanying drawing figures incorporated in and forming
a part of this specification illustrate several aspects of the
disclosure, and together with the description serve to explain the
principles of the disclosure.
[0011] FIG. 1 illustrates conventional SP9T MEMS switch
circuitry.
[0012] FIG. 2 illustrates series circuitry including MEMS circuitry
in series with an SOI switch.
[0013] FIG. 3 illustrates summary information regarding FIG. 2.
[0014] FIG. 4 illustrates a first state of FIG. 2, wherein a TRX B7
node (transmit and receive duplex TRX B7) or signal is
selected.
[0015] FIG. 5 illustrates a second state of FIG. 3, wherein a
transmit/receive pair of a first band is selected by the MEMS
switch, and wherein the transmit path of the first band is selected
by the SOI switch.
[0016] FIG. 6 illustrates a third state of FIG. 3, wherein a
transmit/receive pair of a first band is selected by the MEMS
switch, and wherein the receive path of the first band is selected
by the SOI switch.
[0017] FIG. 7 illustrates a first transition of FIG. 3, wherein the
receive path of the first band is turned OFF while isolated by the
SOI switch.
[0018] FIG. 8 illustrates a second transition of FIG. 3, wherein
the transmit path of the first band is turned OFF while isolated by
the SOI switch.
[0019] FIG. 9 illustrates a third transition of FIG. 2, wherein a
TRX (transmit and receive duplex node) is turned ON while isolated
by the SOI circuit.
[0020] FIG. 10 illustrates a parallel circuit C18, including a MEMS
circuit in parallel with an SOI circuit, including multiple
antennas (A1, A2, and A3), and including a bidirectional
coupler.
[0021] FIG. 11 illustrates a MEMS switch in series with a first SOI
switch, and in parallel with a second SOI switch.
[0022] FIG. 12 illustrates a generalized structure very similar to
FIG. 2, except that the dedicated transmitter nodes are not
necessarily grouped together, and the dedicated receiver nodes are
not necessarily grouped together.
[0023] FIG. 13 illustrates a timing chart for a MEMS switch in
series with an SOI switch. The FIG. 13 timing chart corresponds to
the signal pairs of FIG. 2 (excluding TRX B7, RX B7 Div, and
GND).
[0024] FIG. 14 illustrates a MEMS switch in parallel with an SOI
switch.
[0025] FIG. 15 illustrates a timing chart for a MEMS switch in
parallel with an SOI switch.
[0026] FIG. 16 illustrates a MEMS circuit in series with a complex
SOI circuit.
DETAILED DESCRIPTION
[0027] The embodiments set forth below represent the necessary
information to enable those skilled in the art to practice the
embodiments and illustrate the best mode of practicing the
embodiments. Upon reading the following description in light of the
accompanying drawing figures, those skilled in the art will
understand the concepts of the disclosure and will recognize
applications of these concepts not particularly addressed herein.
It should be understood that these concepts and applications fall
within the scope of the disclosure and the accompanying claims.
[0028] FIG. 1 is conventional SP9T MEMS switch circuitry C2
including an SP9T (single pole, nine throw) MEMS switch C6 and a
control circuit C4.
[0029] Conventional contact MEMS switches offer very low insertion
loss, especially when building switches matrix with high throw
counts (SP6T up to SP13T) and when operating at high frequencies
like 2300 to 2700 MHz.
[0030] In FIG. 1, an SP9T contact MEMS switch C6 operates from
2300-2700 MHz for B7 FDD (Band 7 Frequency Division Duplex) and LTE
TDD (Long Term Evolution Time-Division Duplex) bands
B38/40/41/41XGP. Contact MEMS switches configured as in FIG. 1
suffer from constraints which affect their reliability. These
constraints are discussed above in the Background section.
[0031] The nine throws of SP9T contact MEMS switch C6 include nine
individual MEMS switches labeled M1 through M9. These nine
individual switches are associated with the following ports or
signals: TRX B7 (transmit and receiver in Band 7 Frequency Division
Duplex); TX B38/XGP (transmit in Band 38); TX B40 (transmit in Band
40); TX B41 (transmit in Band 41); RX B7 Div (receive in Band 7
through a diversity antenna); RX B38/XGP (Receiver in Band 38); RX
B40 (receive in Band 40); RX B41 (receive in Band 41); and
Ground.
[0032] Switch C6 connects the selected signal to node V2, and V2 is
connected to antenna A1 and to pilot switch PS3.
[0033] Control circuit C4 is a thick film SOI that receives battery
voltage VDD, an interface voltage VIO, a clock signal SCLK, and
serial data SDATA. Control circuit C4 includes the pilot switch PS3
that may ground node V2 to reduce power across the contacts of the
MEMS switches and thereby prolong their useful life. Control
circuit C4 controls the MEMS switch C6 through control lines
CL2.
[0034] In FIG. 1, all of the MEMS circuitry C6 may be located on a
single glass substrate, and control circuit C4 may be located on a
separate substrate.
[0035] FIG. 2 illustrates series circuitry C8 including MEMS
circuits C12 and C14 in series with an SOI circuit C16.
[0036] In FIG. 2, individual MEMS switches labeled M1 through M9
are each associated with the same ports or signals as described in
FIG. 1. However, MEMS circuit C12 is a SP4T (single pole, four
throw) switch connecting MEMS switches M1-M4 to node V4. MEMS
circuit C14 is a SP5T (single pole five throw) switch connecting
switches M5-M9 to node V6. MEMS circuit C12 is isolated from MEMS
Circuit C14 (outputs V4 and V6 are isolated from each other).
[0037] Control circuit C10 is similar to control circuit C4 of FIG.
1, but controls both MEMS circuit C12 and MEMS circuit C14. It also
no longer contains a pilot switch.
[0038] SOI SP2T (single pole, two throw) switch circuit C16 is
controlled by control line CL10, selects either V4 or V6, and
connects the selected node to node V8 and to antenna A1. In this
illustrative example, SOI SP2T switch circuit C16 is made by an SOI
silicon process. Other semiconductor devices such as SOS
(Silicon-On-Sapphire) or PHEMT (Pseudomorphic High Electron
Mobility Transistor) may be substituted for SOI C16. Additionally,
an advanced or "special" MEMS may be substituted for SOI C16. This
advanced or "special" MEMS is a very high quality MEMS that reduces
at least one of the disadvantages of conventional MEMS, and that is
of higher quality than the MEMS in circuits C12 and C14.
[0039] In combination, MEMS circuits C12 and C14 may be described
as a "restricted" DP9T switch, in which the first pole (V4) is
restricted to being connected only the signals associated with
switches M1-M4, and in which the second pole (V6) is restricted to
being connected only with the signals associated with switches
M5-M9). Of course, the first pole and the second pole are isolated
from each other. This "restricted" terminology is not commonly
used, but does indicate that MEMS circuits C12 and C14 are closely
associated with each other, may be located on a single glass
substrate or die (not shown), and may be controlled with one set of
control lines.
[0040] Some of the signals are hereby defined as "opposites" or as
"pairs." Specifically, a paired signal is defined as a transmit
signal and a receive signal (in a single band) that is transmitted
or received on separate paths or nodes (not duplexed).
[0041] For example, band B38/XGP is split into paired signals or
nodes TX B38/XGP and RX B38/XGP. Other paired signals include: TX
B40 and RX B40; and TX B41 and RX B41. Thus, FIG. 2 includes three
pairs of signals (six signals) as discussed above, plus three
unpaired signals (TRX B7, RX B7 Div, and GND).
[0042] It is important that the paired signals are routed such that
the paired signals are not associated with a single MEMS circuit.
In other words, the first signal of a paired signal is associated
with a first MEMS circuit (e.g., TX B40 is associated with MEMS
circuit C12), and the second signal of the paired signal is
associated with a second MEMS circuit (RX B40 is associated with
MEMS circuit C14).
[0043] Splitting a single paired signal into two distinct MEMS
circuits enables the efficient series processing of the split
paired signal, as discussed in detail in later figures. In FIG. 2,
all three paired signals (TX B38/XGP and RX B38/XGP; TX B40 and RX
B40; and TX B41 and RX B41) are split, so that all of these split
pairs may be processed efficiently.
[0044] The allocation or routing of unpaired signals (TRX B7, RX B7
Div, and GND) is less critical. In FIG. 2, duplexed signal TRX B7
is associated with MEMS circuit C12 (along with all of the transmit
signals of the split pairs: TX B38/XGP; TX B40; and TX B41).
[0045] In FIG. 2, unpaired receive signal RX B7 Div and unpaired
Ground are associated with MEMS circuit C14.
[0046] To summarize, MEMS circuit C12 includes the TRX port for an
FDD band (TRX stands for TX and RX, e.g. band 7) and includes the
TX ports of TDD bands (e.g. LTE TDD band 38/40/41). MEMS circuit
C14 includes all the RX ports for TDD (e.g. LTE TDD band 38/40/41)
and also the RX ports for diversity/RX MIMO.
[0047] The first group of switches (e.g. SP4T MEMS circuit C12) and
the second group of switches (e.g. SP5T MEMS circuit C14) are
connected to an SOI SP2T switch circuit C16.
[0048] Thus, SOI circuit C16 can switch very quickly (a
characteristic of semiconductor devices) back and forth between
transmit node B40 (though MEMS circuit C12) and receive node RX B40
(through MEMS circuit 14) while operating in Band 40, and without
switching any individual MEMS switch.
[0049] In this illustrative example, SOI SP2T switch circuit C16 is
made by an SOI silicon process as shown in FIG. 2. Other
semiconductor devices such as SOS (Silicon-On-Sapphire) or PHMET
(Pseudomorphic High Electron Mobility Transistor) may substitute
for SOI C16. Additionally, an advanced or "special" MEMS may be
substituted for SOI C16. This advanced or "special" MEMS is a very
high quality MEMS that reduces at least one of the disadvantages of
conventional MEMS.
[0050] In FIG. 2, the number of cycles of switching for the MEMS is
significantly reduced because the SP2T SOI circuit C16 will be
performing most of the switching (between V4 for TX/TRX and V6 RX
in TDD mode)
[0051] Thus, the MEMS switches in MEMS circuits C12 and C14 do not
switch while a single band operates (transmits; receives; or
transitions between transmitting and receiving), and generally only
switch when the band of operation changes.
[0052] Additionally, SOI circuit C16 provides hot-switching
protection to the MEMS switches when they are opened or closed, and
also providing ESD (Electro Static Discharge) protection. As used
here, `hot-switching protection` refers to the reduction of power
incident on a given MEMS switch during the making or breaking of
contact. Further, the SOI circuit C16 may provide fast switching
(less than 5 .mu.s) and the MEMS switches may provide relatively
slow switching (20-40 .mu.s).
[0053] FIG. 3 illustrates summary information regarding FIG. 2.
Specifically, FIG. 3 emphasizes that SOI circuit C16 provides:
relatively fast switching; hot-switching protection for MEMS
circuits C12 and C14; and ESD protection for MEMS circuits C12 and
C14.
[0054] MEMS circuits C12 and C14 provide band switching only; have
relatively slow switching times; and are grouped such that pairs
are split (e.g. TX B40 in MEMS circuit C12, and RX B40 in MEMS
circuit C14). In this embodiment, TRX B7 is grouped with the
transmit signals or nodes.
[0055] FIG. 4 illustrates a first state of FIG. 2, wherein a TRX
node (transmit and receive duplex TRX B7) or signal is
selected.
[0056] Specifically, FIG. 4 illustrates that the FDD TRX B7 port is
connected to the antenna A1 through switch M1 in MEMS circuit C12
and through SOI SP2T circuit C16. Switch M1 is ON (or CLOSED), and
circuit C16 is UP.
[0057] FIG. 4, the state of MEMS circuit C14 is not critical,
because C14 is isolated by C16, and because TRX B7 is a frequency
duplexed signal that does not require switching among different
nodes in order to change from receiving to transmitting (or vice
versa). However, in this first state it is good practice to turn
OFF (or OPEN) switches M5-M9 in order to further isolate the
associated nodes or ground.
[0058] FIG. 5 illustrates a second state of FIG. 2, wherein a
transmit/receive pair of a first band is selected by the MEMS
circuits C12 and C14, and wherein the transmit path of the first
band is selected by the SOI circuit C16. M3 is ON, M7 is ON, and
SP2T is UP.
[0059] Specifically, FIG. 5 illustrates an example of the operation
of LTE TDD B40 (Band 40) where both TX B40 and RX B40 MEMS contact
switches (M3 and M7 respectively) are ON (or closed)
simultaneously; such switching between TX and RX operation for Band
40 may be performed solely via the SP2T SOI circuit C16.
[0060] SOI circuit C16 is shown in the UP state. In this fashion,
node TX B40 is connected sequentially to switch M3 (ON), to node
V4, to SOI circuit C16, to node V8, and finally to antenna A1. In
other words, series parallel circuit C8 is configured to transmit
Band 40.
[0061] FIG. 6 illustrates a third state of FIG. 2, wherein a
transmit/receive pair of a first band is selected by the MEMS
circuits C12 and C14, and wherein the receive path of the first
band is selected by the SOI circuit C16. M3 is ON, M7 is ON, and
SP2T is DOWN.
[0062] FIG. 6 is the same as FIG. 5, except that SP2T in SOI
circuit C16 is now in the DOWN state (instead of the UP state).
Relative to FIG. 5, FIG. 6 is now configured to receive (instead of
transmit) Band 40. This change (from transmitting in Band 40 to
receiving in Band 40) is caused solely by switching SP2T in SOI
circuit C16 from UP to DOWN.
[0063] In FIG. 6, antenna A1 is connected sequentially to: node V8;
SOI circuit C16; node V6; switch M7; and node RX B40.
[0064] FIG. 5 may be returned to (from FIG. 6) by switching SP2T in
SOI circuit C16 from DOWN to UP.
[0065] Thus, FIG. 5 and FIG. 6 illustrate that transitioning back
and forth over time from transmitting to receiving in a single band
(TDD or time division duplexing) may be accomplished solely by
repeatedly switching SOI circuit C16 UP and DOWN.
[0066] The MEMS switches M1-M9 do not switch at all during
operation from TX to RX and vice-versa (while in a single band).
The switching between TX to RX can be done very quickly using SOI
(e.g., on the order of 5 .mu.s).
[0067] As an additional benefit, the number of cycles is
significantly reduced for the MEMS switches (e.g., by a factor of
100.times.), because the MEMS switches only switch when a band is
changed. Band changes typically occur about once per second (very
infrequently). In contrast, transmit/receive changes (within a
band) typically occurs about once every 10 ms (very frequently, or
about 100 times more frequently than band changes).
[0068] Further, SOI circuit C16 provides an isolation of a TX (or
TRX) signal to the RX port of at least 25 dB, thus reducing the
level of any leakage TX power (to the RX port) to less than +0 dBm
for a +24 dBm TX signal.
[0069] Additionally, as discussed below, certain switching logic
avoids closing or opening a MEMS switch while there is some power
present at one of its ports, also known as hot-switching. For
example, undesired power may come from an ISM (Industrial,
Scientific, and Medical) band blocker signal or from any external
blocker signal (such as a TV station). Specifically, if SOI circuit
C16 is switched into a position that provides isolation for the
MEMS switch to be closed or opened (to be transitioned), then the
leakage port is less than +0 dBm.
[0070] FIG. 7 illustrates a first step in changing bands, wherein
the receive path M7 of the first band is turned OFF while isolated
by the SOI circuit C16.
[0071] Specifically, FIG. 7 illustrates the beginning of a
transition from Band 40 to Band 41 that may occur immediately after
transmitting in Band 40 (as shown in FIG. 5). The RX B40 node is
further isolated by turning OFF (opening) M7 as a first step in
changing from a first band to a second band. Starting with FIG. 5,
SOI circuit C16 remains in the UP position (isolating MEMS circuit
C14) while M7 is turned OFF (opened) as shown in FIG. 7.
[0072] The following set of steps (not shown) will complete the
change in bands from Band 40 to Band 41: turn ON (close) M8; turn
DOWN SOI circuit C16 (isolating MEMS circuit C12); turn OFF (open)
M3; turn ON (close) M4. Now Band 41 is selected for receiving
(through M8), and switching between receiving and transmitting is
performed solely by transitioning SOI circuit C16.
[0073] The following alternative (slightly longer) set of steps
also will complete the change in bands from Band 40 to Band 41
(starting with turning M7 OFF as shown in FIG. 7): turn DOWN SOI
circuit C16 (isolating MEMS circuit C12); turn OFF (open) M3; turn
ON M4; turn UP SOI circuit C16 (isolating MEMS circuit C14); turn
ON (close) M8. Now Band 41 is selected for transmitting, and
switching between transmitting and receiving is performed solely by
transitioning SOI circuit C16.
[0074] Other sets of steps may also switch from one band to another
(see timing chart in FIG. 13).
[0075] FIG. 8 illustrates an alternative first step in changing
bands, wherein the transmit path M3 of the first band is turned OFF
while isolated by the SOI circuit 16.
[0076] Specifically, FIG. 8 illustrates a first step that may occur
immediately after receiving in Band 40 (as shown in FIG. 6); MEMS
switch M3 is turned OFF (opened), isolating node TX B40.
[0077] The following set of steps (not shown) completes the change
in bands from Band 40 to Band 41 (starting with turning M3 OFF as
shown in FIG. 8): while SP2T of SOI circuit C16 remains in the DOWN
position, turn ON (close) M4; turn UP SOI circuit C16; turn OFF
(open) M7; turn ON (close) M8. Now the circuits are configured to
transmit in Band 41.
[0078] The following alternative (slightly longer) set of steps
(not shown) also completes the change in bands from Band 40 to Band
41: turn UP SOI circuit C16; turn OFF (open) M7; turn ON (close)
M8; turn DOWN SOI circuit C16; turn ON (close) M4. Now the circuits
are configured to receive in Band 41.
[0079] Other sets of steps may also switch from one band to
another.
[0080] FIG. 9 illustrates a third transition of FIG. 2, wherein a
TRX (transmit and receive duplex node) is turned ON while isolated
by the SOI circuit C16.
[0081] FIG. 9 illustrates turning ON (closing) MEMS switch M7 while
the SOI circuit C16 is in a DOWN position to provide isolation and
to avoid hot-switching of M7.
[0082] It is possible (and efficient) to sequence opening and
closing of two switches in MEMS circuit C12 while the SOI circuit
C16 is in a single position.
[0083] For example, (not shown, starting with FIG. 6, with SOI
circuit C16 in the DOWN position): M3 is turned OFF (opened); M1 is
turned ON (closed); and SOI circuit C16 is turned UP (now the
circuits are configured for TRX B7). This band transition from B40
to TRX B7 required a first MEMS transition, sequential second MEMS
transition, and then an SOI transition. The total time for this
band switch change (from Band 40 to TRX B7) is less than 80
.mu.s.
[0084] Further, it is good practice (not shown) to finally turn OFF
(open) M7, although transmitting or receiving by TRX B7 does not
necessarily have to wait for this optional last step.
[0085] A slightly different set of steps transitions from Band 40
to TRX if the circuits begin as shown in FIG. 5 (with SOI circuit
C16 in the UP position).
[0086] FIG. 10 illustrates a parallel circuit C18, including a MEMS
circuit C22 in parallel with an SOI circuit C20, including multiple
antennas (A1, A2, and A3), and including a bidirectional coupler
(BC).
[0087] Specifically, FIG. 10 shows a series circuitry C26 (also
referred to as optimized switching circuitry) of a portion of a
radio front end (RFFE) using MEMS switches and covering 24 bands.
Nodes or signals include: TRX B7; TX B38/XGP; TX B40; TX B41; RX B7
Div; RX B38/XGP; RX B40; RX B41; and Ground. A UHB MEMS switch C22A
connects antenna A3 (or antennas A1/A2 via RF1 port) to one of the
nodes listed above.
[0088] SOI circuit C20 includes two SP2T switches, and includes
control circuitry C21 (such as charge pump, pilot switches, and
anti-rebound circuitry).
[0089] Bidirectional coupler BC measures power going to or coming
from antenna A3. The bidirectional coupler measurements transit
through SOI SP2T in SOI C20.
[0090] MEMS circuit C22 includes: MEMS circuit C22A connecting the
inputs to antenna A3, and MEMS circuit C22B connecting a subset of
the inputs to one of antennas A1 and A3.
[0091] The series circuitry C26 may be modified using the concepts
shown below in FIG. 11 (adding an SOI in series).
[0092] The SOI SP2T switches in SOI C20 may be controlled by
control circuitry C21 located in the same SOI C20 die. This avoids
duplicating the serial bus (MIPI RFFE BUS). An SP2T SOI switch
insertion loss (IL) is around 0.3 dB.
[0093] If an SP9T were to be built in SOI, the IL at 2300-2700 MHz
would be around 0.085 dB*7+0.3 dB=.about.0.9 dB w/o including
packaging losses. (0.085 dB for additional throw relative to SOI
SP2T). If an SP5T were to be built in MEMS, the IL at 2300-2700 MHz
would be around 0.005*3+0.22 dB=0.235 dB without including
packaging losses. (0.005 dB for additional throw relative to a MEMS
SP2T).
[0094] If the SP2T SOI is added to the MEMS SP5T IL, we get 0.235
dB+0.3=0.535 dB, which is 0.4 dB lower than the SOI only solution.
Thus, the configuration of FIG. 2 (MEMS in series with SOD provides
a total insertion loss that is 0.4 dB lower than the SOI only
solution. See discussion of FIG. 11 below.
[0095] The above figures may also be generalized such that the
first MEMS switch and the second MEMS switch are associated with
nodes that contain "opposite" or "paired" configurations, as
discussed in FIG. 12 below.
[0096] FIG. 11 illustrates a MEMS circuit 30 in series with a first
SOI switch C33, and in parallel with a second SOI switch C28.
[0097] FIG. 11 is very similar to FIG. 10, except: MEMS circuit
C22A (SP9T) in FIG. 10 becomes MEMS Circuits C30A (SP4T) and C30B
(SP5T); and SOI circuit C33 is added in series with C30A and in
series with C30B.
[0098] This configuration (MEMS circuits in series with SOI
circuit) is as fast as an all SOI circuit in most circumstances
(because most switching is from transmit to receive within a single
band, and is handled solely by SOI circuit C33), and this
configuration has about 0.4 dBG less insertion loss than an all SOI
circuit (as discussed above). Thus, this configuration retains most
of the high speed advantage of an all SOI circuit, and also avoids
much of the insertion loss of an all SOI circuit.
[0099] Also, SOI circuit C32 receives signal RF1 from C30C, and
outputs this signal to antenna A1 or to antenna A2.
[0100] FIG. 12 illustrates a generalized structure very similar to
FIG. 2, except that the dedicated transmitter nodes (TX B38/XGP, TX
B40, and TX B41) are not necessarily grouped together, and the
corresponding (or paired or opposite) dedicated receiver nodes (RX
B38/XGP, RX B40, and RX B41) are not necessarily grouped
together.
[0101] In FIG. 12, each transmitter/receiver signal pair is
separated such that a first member of the signal pair is routed
through a MEMS circuit and a second member of the signal pair is
routed through a different MEMS circuit. In this fashion, an SOI
circuit may quickly switch from the first member of the signal pair
to the second member of the signal pair without requiring any MEMS
switch to be switched.
[0102] Specifically, a first signal pair comprises RX B38/XGP
associated with MEMS circuit C34 and TX B38/XGP associated with
MEMS circuit C36. A second signal pair comprises TX B40 associated
with MEMS circuit C34 and RX B40 associated with MEMS circuit C36.
A third signal pair comprises RX B41 associated with MEMS circuit
C34 and TX.
[0103] In a general sense (not shown), there may be three MEMS
circuits, each MEMS circuit connected to an SOI circuit (or other
semiconductor circuit, or "special" MEMS circuit) having at least
three throws (such as a SP3T SOI circuit). In this general case, a
first signal pair may be distributed among the first and second
MEMS circuits, a second signal pair may be distributed among the
first and third MEMS circuits, and a third signal pair may be
distributed among the second and third MEMS circuits.
[0104] Also in a general sense (not shown), it is not essential
that every signal pair be distributed into separate MEMS
circuits.
[0105] However, the most efficient configuration (quickest
switching times and lowest insertion loss) occurs as shown in FIG.
12, wherein: all signal pairs are distributed among just two
separate MEMS circuits; any non-paired signals are distributed
among these same two separate MEMS circuits C34 and C36; and the
SOI circuit C16 is a SP2T.
[0106] FIG. 13 illustrates a timing chart for a MEMS switch in
series with an SOI switch. The FIG. 13 timing chart corresponds to
the signal pairs of FIG. 2 (excluding TRX B7, RX B7 Div, and
GND).
[0107] MEMS Tx Branches correspond to M2, M3, and M4 of FIG. 2, and
the MEMS Rx branches correspond to M6, M7, and M8 of FIG. 2.
Specifically, MEMS MTx1 and MRx2 correspond to a first signal pair
(e.g. TX B40 and RX B40 respectively) and MTx2 and MRx1 correspond
to a second signal pair (e.g. TX B41 and RX B41 respectively)
[0108] The SOI switches STx ON and SRx OFF correspond to the UP
position of the SP2T in SOI circuit C16, and antenna ANT
corresponds to antenna A1.
[0109] FIG. 13 shows the anticipated timing of the MEMS and SOI
switches arranged in series and how the cycle count is reduced,
switching time demands diminish, and hot switching protection is
provided.
[0110] Specifically, during period 1, MTx1, a first transmit signal
(e.g. TX B40) is transmitted to the antenna ANT.
[0111] During period 2, the paired receive signal (e.g. RX B40) is
received by the antenna and passed through MRx2 to the appropriate
node.
[0112] During period 3, the receiving branches are isolated (STx ON
closed and SRx OFF open), then MRx2 is OFF (opened), then MRx1 is
ON (closed). Thus, RXB40 is turned OFF and RXB41 is turned ON
(while the Rx branches are isolated).
[0113] During period 4, the transmitting branches are isolated (STx
OFF and SRX ON), then TX B40 is turned OFF, then TX B41 is turned
ON (while the Tx branches are isolated). At this time, the circuit
C8 may receive RX B41.
[0114] During period 5 (STx ON and SRx OFF), the circuit C8 may
transmit TX B41 through MTx2 to the antenna ANT.
[0115] During period 6, (Stx OFF and SRx ON), the circuit C8 may
receive TX B41 through MRx1. These 6 periods complete a full
transmit/receive cycle at Band 40, a full transition to Band 41,
and a full transmit/receive cycle at Band 41.
[0116] These periods are illustrative only. For example, the cycles
in a band may begin with receive (instead of with transmit). A full
cycle is not required.
[0117] Additionally, the SOI switching may be much faster than the
MEMS switching, so the periods of the SOI switching may be very
fast (very short) during transmit/receive cycles, but may become
much longer (relatively) to facilitate the relatively slow MEMS
switching required while changing bands.
[0118] FIG. 14 illustrates a MEMS switch in parallel with an SOI
switch.
[0119] As shown in FIG. 14, the SOI switch bC42 is configured in
parallel with MEMS switch C40 to form circuitry C38. Branches
operating in TDD mode or 2G mode which require fast and frequent
switching can be switched by an SOI switch, and slower and less
frequent switching can be switched by a MEMS switch.
[0120] As shown, SOI circuit C42 includes an SP2T SOI switch, as
well as high voltage generation and control and pilot switching
portions.
[0121] This parallel configuration of circuitry C38 is particularly
useful when a majority of the switching occurs from TxHB to TxLB,
and when the other nodes (TRx1 through TRx10) are rarely used.
[0122] Thus, the high speed switching (but high insertion loss) SOI
is strictly limited to those nodes that are frequently
switched.
[0123] This parallel configuration may reduce the cycle count
required as per the previous embodiments (.about.100.times.), and
also potentially the time required for switching. Hot switching and
ESD solutions will still be required and may be achieved by the use
of an SOI pilot switch as described above.
[0124] FIG. 15 illustrates a timing chart for a MEMS switch in
parallel with an SOI switch. Specifically, FIG. 15 shows the timing
of MEMS and SOI switches arranged in parallel, and how the cycle
count is reduced and hot switching protection is provided.
[0125] As shown in FIG. 15, the MEMS switches M1 and M2
respectively correspond to TRx1 and TRx2 branches of MEMS circuit
C40 in FIG. 14. The SOI switches S1 and S2 respectively correspond
to the TxHB and TxLB branches of SOI circuit C42. A pilot switch PS
is also shown in FIG. 15 (not shown in FIG. 14) and is connected to
antenna ANT.
[0126] In period 1, SOI circuit C42 (switches S1 and S2) cycles
rapidly between TxHB and TxLB.
[0127] In period 2, the pilot switch PS switches ON (grounding the
antenna ANT to reduce incident power during MEMS switching), then
M1 switches ON, then PS switches OFF, and then TRx1 transmits
through M1.
[0128] In period 3, the pilot switch PS switches ON (grounding the
antenna ANT to reduce incident power during MEMS switching), then
MEMS M1 turns OFF and M2 turns ON, then PS switches OFF, then TRx2
transmits through M2.
[0129] In period 4, the PS switches ON, then M2 turns OFF, then PS
switches OFF, and circuitry C38 is ready for high speed SOI
switching (all MEMS switches are OFF).
[0130] In period 5, SOI circuit C42 (switches S1 and S2) cycles
rapidly between TxHB and TxLB.
[0131] In its most general form, the concept of FIGS. 14 and 15 is
to have a parallel combination of a SOI circuit and a MEMS circuit,
and to have each signal routed through the circuit that is most
appropriate. For one example, associate (or direct) signals
requiring high switching frequencies to SOI circuit C42, and
associate the remaining signals to MEMS circuit C40.
[0132] The number of throw counts, and inclusion (or not) of
voltage generation, control, and pilot switches capabilities in the
COI circuit are all considered to be within the scope of the
present disclosure.
[0133] FIG. 16 illustrates a MEMS circuit C50 in series with a
complex SOI circuit C54.
[0134] In FIG. 16, MEMS circuit C50 includes a MEMS die C42. The
MEMS die C42 includes a receiving MEMS circuit C52A (configured to
receive a reception signal RxRF1) and a transmission MEMS circuit
C52B (configured to outputting a transmission signal TxRF1). In
this embodiment, C52B is a SP6T, and C52A a SP3T (including one
signal from each of three signal pairs). There are signal pairs in
bands B40a, B41a, and B40/B38x.
[0135] Complex SOI circuit C54 is configured to receive a signal
from antenna ANT1, then route this received signal (RxRF1) through
high band SOI DP5T circuit C58, then through high band SOI SP6T
circuit C56, and then to receiving MEMS circuit C52A for additional
routing to the appropriate node (RxB40a, RxB41a, or RxB40/38x).
[0136] Transmissions from SOI circuit C52B are TxRF1, and are
routed directly to SOI circuit C58 (and then, for example, to
antenna ANT2). The double pole (DP5T) nature of circuit C58 allows
antenna ANT1 (connected to a first pole of the double pole) to
receive while antenna ANT2 (connected to a second pole of the
double pole) transmits.
[0137] In view of the previous timing diagrams, many additional
different timing diagrams (not shown) are inherently disclosed by
FIG. 16.
[0138] Those skilled in the art will recognize improvements and
modifications to the preferred embodiments of the present
disclosure. All such improvements and modifications are considered
within the scope of the concepts disclosed herein and the claims
that follow.
* * * * *