U.S. patent application number 13/682806 was filed with the patent office on 2014-01-02 for transistor with reduced charge carrier mobility and associated methods.
This patent application is currently assigned to Infineon Technologies AG. The applicant listed for this patent is Infineon Technologies AG. Invention is credited to Joerg BERTHOLD, Christian PACHA, Klaus VON ARNIM.
Application Number | 20140003136 13/682806 |
Document ID | / |
Family ID | 40030912 |
Filed Date | 2014-01-02 |
United States Patent
Application |
20140003136 |
Kind Code |
A1 |
BERTHOLD; Joerg ; et
al. |
January 2, 2014 |
TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED
METHODS
Abstract
One or more embodiments relate to a method comprising: raising a
potential of a first bit line and a second bit line; switching on a
first n-channel access transistor coupled between the first bit
line and a first node of a first inverter; switching on a second
n-channel access transistor coupled between the second bit line and
a second node of a second inverter; and reading a static random
access memory (SRAM) cell including the first inverter and the
second inverter by sensing a potential on the first bit line and a
potential on the second bit line.
Inventors: |
BERTHOLD; Joerg; (Muenchen,
DE) ; PACHA; Christian; (Neukeferloh, DE) ;
VON ARNIM; Klaus; (Muenchen, DE) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Infineon Technologies AG |
Neubiberg |
|
DE |
|
|
Assignee: |
Infineon Technologies AG
|
Family ID: |
40030912 |
Appl. No.: |
13/682806 |
Filed: |
November 21, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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13472514 |
May 16, 2012 |
8338251 |
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13682806 |
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13072805 |
Mar 28, 2011 |
8183636 |
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13472514 |
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11764500 |
Jun 18, 2007 |
7915681 |
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13072805 |
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Current U.S.
Class: |
365/156 |
Current CPC
Class: |
H01L 21/84 20130101;
H01L 27/1211 20130101; H01L 27/1203 20130101; G11C 11/412 20130101;
H01L 29/785 20130101; H01L 29/04 20130101; H01L 27/11 20130101;
H01L 27/1108 20130101 |
Class at
Publication: |
365/156 |
International
Class: |
G11C 11/412 20060101
G11C011/412 |
Claims
1. A method comprising: raising a potential of a first bit line and
a second bit line; switching on a first n-channel access transistor
coupled between the first bit line and a first node of a first
inverter, the first inverter including a first p-channel load
transistor coupled between a supply voltage and the first node and
a first n-channel pull-down transistor coupled between the first
node and a ground voltage, the first bit line being coupled to the
supply voltage through the first p-channel load transistor and the
first n-channel access transistor, a fin of the first n-channel
access transistor having a lower charge carrier mobility than a fin
of the first n-channel pull-down transistor; switching on a second
n-channel access transistor coupled between the second bit line and
a second node of a second inverter, the second inverter including a
second p-channel load transistor coupled between the supply voltage
and the second node and a second n-channel pull-down transistor
coupled between the second node and the ground voltage, the second
bit line being coupled to the ground voltage through the second
n-channel pull-down transistor and the second n-channel access
transistor, a fin of the second n-channel access transistor having
a lower charge carrier mobility than a fin of the second n-channel
pull-down transistor; and reading a static random access memory
(SRAM) cell including the first inverter and the second inverter by
sensing a potential on the first bit line and a potential on the
second bit line.
2. The method of claim 1, further comprising: setting the potential
of the first bit line to a high programming voltage; setting the
potential of the second bit line to a low programming voltage;
switching on the first n-channel access transistor, a fin of the
first p-channel load transistor having a lower charge carrier
mobility than the fin of the first re-channel pull-down transistor;
and switching on the second n-channel access transistor to program
the SRAM cell, a fin of the second p-channel load transistor having
a lower charge carrier mobility than the fin of the second
n-channel pull-down transistor.
3. The method of claim 1, wherein switching on a first n-channel
access transistor includes asserting a word line coupled to a gate
of the first n-channel access transistor and to a gate of the
second n-channel access transistor to switch on the first n-channel
access transistor and the second n-channel access transistor.
4. A method comprising: raising a potential of a first bit line and
a second bit line; switching on a first n-channel access transistor
coupled between the first bit line and a first node of a first
inverter; switching on a second n-channel access transistor coupled
between the second bit line and a second node of a second inverter;
and reading a static random access memory (SRAM) cell including the
first inverter and the second inverter by sensing a potential on
the first bit line and a potential on the second bit line.
Description
RELATED APPLICATION INFORMATION
[0001] This application is a divisional application of U.S. patent
application Ser. No. 13/472,514, filed on May 16, 2012, which is a
divisional application of U.S. patent application Ser. No.
13/072,805, filed on Mar. 28, 2011, which is now U.S. Pat. No.
8,183,636, which is a continuation application of U.S. patent
application Ser. No. 11/764,500, filed on Jun. 18, 2007, which is
now U.S. Patent Number 7,915,681. U.S. patent application Ser. No.
13/472,514, U.S. patent application Ser. No. 13/072,805 and U.S.
patent application Ser. No. 11/764,500 are all hereby incorporated
by reference herein.
TECHNICAL FIELD
[0002] The subject matter relates generally to transistors with
reduced charge carrier mobility and associated treatment methods in
connection with such transistors.
BACKGROUND
[0003] Fin field-effect transistor (FinFET) structures are one of
the options for future complementary metal oxide semiconductor
(CMOS) technologies. There is a need for improved FinFET structures
and methods.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 illustrates an electrical schematic diagram of a
static random access memory (SRAM) cell according to various
embodiments.
[0005] FIG. 2 illustrates a block perspective diagram of a fin
field effect transistor according to various embodiments.
[0006] FIG. 3 illustrates a layout of a SRAM cell according to
various embodiments.
[0007] FIG. 4 illustrates a layout of a SRAM cell according to
various embodiments.
[0008] FIG. 5 illustrates a layout of a SRAM cell according to
various embodiments.
[0009] FIG. 6 illustrates characteristic curves of two single-fin
field effect transistors according to various embodiments.
[0010] FIG. 7 illustrates a block diagram of a system according to
various embodiments.
DETAILED DESCRIPTION
[0011] The various embodiments described herein are merely
illustrative. Therefore, the various embodiments shown should not
be considered as limiting of the claims.
[0012] Fin field-effect transistor (FinFET) structures are one of
the options for future complementary metal oxide semiconductor
(CMOS) technologies. P-type FinFETs have a similar performance to
n-type FinFETs for many circuit arrangements. This is mainly due to
a crystal orientation along sidewall channels, which yields a
higher mobility for holes. There are, however, some circuit types
that are difficult to implement with strong p-type transistors. An
example is a static random access memory (SRAM) cell, where certain
current/performance ratios between pull-down, access, and load
transistors are required.
[0013] One of the characteristic features of FinFETs is a
discretization of the effective transistor width imposed by a
constant fin height. If, e.g. in a SRAM, the area has to be kept as
small as possible, this discretization feature could lead to larger
areas: the smaller area is possible when all transistors, the
slowest or weakest transistors and the fastest or strongest
transistors, are implemented using one fin. But, because of the
discretization feature, the required performance ratios of the
access, pull-down, and load transistors of a SRAM cell demand
either a 2-fin implementation of a fast or strong transistor, or a
longer gate electrode of the weak transistor. Both options result
in an increase in area and power dissipation.
[0014] FinFETs of both types can gain performance through use of
fins that are left un-doped. In advanced FinFETs, the threshold
voltage is adjusted by choosing an appropriate gate material. The
charge carriers are subjected to less scattering with undoped fins,
and this results in an improved mobility and in a higher drain
current.
[0015] The mobility mechanism allows an adjustment of FinFET
performance by intentionally reducing the charge carrier mobility
with selective fin doping. FinFETs that are too strong are doped
with one or more additional implantations.
[0016] The increased scattering of holes and electrons leads to a
decreased mobility and a correspondingly lower current. One of the
two main advantages of FinFET technology, the mobility improvement
due to un-doped fins, is sacrificed with the doping.
[0017] Any undesired change of the threshold voltage of a FinFET
due to the introduction of dopants can be reduced by counter-doping
the fin using a dopant species of the opposite polarity according
to various embodiments. In FinFET technology that relies on fin
doping, the mobility can be reduced by using a higher dose, also
called an excess dose, than required for a threshold voltage
adjustment, followed by a counter-doping implantation. The
counter-doping implantation occurs with a dose corresponding to the
dose of the first implantation.
[0018] Doping refers to the incorporation of electrically active
species into a semiconductor lattice, a process including
implantation and anneal operations. The scattering increase of the
charge carrier is then caused, for example, by the local strain due
to a size mismatch in the lattice. The mobility can also be reduced
according to various embodiments by introducing interstitials and
damage to result in, for example, electrically non-active scatter
centers. According to various embodiments, other electrically
non-active materials like germanium (Ge) or carbon (C) can be
incorporated in a channel region of a FinFET.
[0019] Another way to reduce the mobility according to various
embodiments is to introduce additional surface states. This can be
done also by implants damaging the surface of the FinFET or by
introducing additional process steps or by omitting process steps
in a region of a SRAM.
[0020] In a FinFET technology that uses un-doped fins, one or more
fins receive a selective implantation according to various
embodiments. The selective implantation depends on the purpose of
the fins within a circuit to achieve a selective reduction of a
drive current. The implantation dose depends on the required
performance modification. Both types of dopant species can be
introduced in one or more implantations according to various
embodiments to reduce side effects on the threshold voltage of a
FinFET, and this is called counter-doping.
[0021] FIG. 1 illustrates an electrical schematic diagram of a SRAM
cell 100 according to various embodiments. A pair of n-type access
transistors 110 and 112 have gates coupled to a word line (WL), and
drains respectively coupled to a bit line (BL) and complementary
bit line (BLB). A pair of p-type load transistors 120 and 122 and a
pair of n-type pull-down transistors 130 and 132 are coupled to
form a pair of cross coupled inverters indicated by broken line
135. The transistors 120, 130 are coupled to be a first inverter,
and the transistors 122, 132 are coupled to be a second inverter.
The transistors 120, 122 are coupled to a supply voltage VDD, and
the transistors 130, 132 are coupled to a ground voltage VSS.
Drains of the transistors 120, 130 are coupled together at a node Q
to a source of the access transistor 110 and to gates of the
transistors 122, 132. Similarly, drains of the transistors 122, 132
are coupled together at a complementary node QB to a source of the
access transistor 112 and to gates of the transistors 120, 130.
Potentials at the nodes Q and QB indicate data held by the SRAM
cell 100.
[0022] The SRAM cell 100 is read in the following manner Assume
that the data held by the SRAM cell 100 is a 1, stored as VDD at Q
and VSS at QB. The transistors 120, 132 are switched on, and the
transistors 122, 130 are switched off. A read cycle begins when
both BL and BLB are charged to a high potential. WL is then
asserted, enabling both of the access transistors 110, 112. The
respective potentials at the nodes Q and QB are then coupled to BL
and BLB. BLB is discharged through the transistors 112 and 132 to
VSS. On the node Q side, the transistors 120 and 110 pull BL
towards VDD. If the data held by the SRAM cell 100 is a 0, this
data would be stored as VDD at QB and VSS at Q, and a read cycle
would result in the opposite behavior as BLB would be pulled
towards VDD and BL towards VSS.
[0023] The SRAM cell 100 is written to in the following manner A
write cycle is begun by applying the value to be written to BLB and
BL. To write a 0, BLB is charged to a high potential and BL is
discharged. To write a 1, BL is charged to a high potential and BLB
is discharged. WL is then asserted to enable the access transistors
110, 112 and the cross coupled inverters latch the potentials on BL
and BLB.
[0024] If WL is not asserted, the access transistors 110, 112
substantially isolate the SRAM cell 100 from BL and BLB, and the
cross coupled inverters formed by the transistors 120, 122, 130,
and 132 reinforce each other.
[0025] Two requirements regarding the relative characteristics of
the transistors 110, 112, 120, 122, 130, and 132 must be met for a
proper operation of the SRAM cell 100. During a read operation when
the SRAM cell 100 stores the data 1 with Q at VDD and QB at VSS,
the potential of QB should stay close to VSS even when BLB is
pre-charged to VDD and the access transistor 112 between QB and BLB
is switched on. In this case, the access transistor 112 has to be
weaker than the pull-down transistor 132, as both are coupled to
QB. During a write operation to change the data stored by the SRAM
cell 100 from 1 to 0, the two cross-coupled inverters must be
transferred from one stable state where Q is at VDD and QB is at
VSS into a second stable state where Q is at VSS and QB is at VDD.
Since the access transistors 110,112 pass only the potential VSS or
VDD less their respective threshold voltages, the load transistors
120, 122 must be weaker than the respective pull-down transistors
130, 132.
[0026] FIG. 2 illustrates a block perspective diagram of a fin
field effect transistor 200 according to various embodiments. The
transistor 200 has a body, also referred to as a fin 210, and is
referred to as a single fin transistor. The fin 210 is formed of a
semiconductor material and may be formed on an insulating surface
215 over a substrate 220. The insulating surface 215 may be an
oxide such as a buried oxide and the substrate 220 may be silicon
or another semiconductor material. A gate dielectric 230 is formed
over the top and on the sides of the fin 210. A gate electrode 235
is formed over the top and on the sides of the gate dielectric 230
and may include a metal layer. Source 240 and drain 245 regions may
be formed in the fin 210 on either side of the gate electrode 235,
and may be laterally expanded to be significantly larger than the
fin 210 under the gate electrode 235 according to various
embodiments. A channel region 246 may be located in the fin 210
between the source region 240 and the drain region 245 and under
the gate electrode 235. The transistor 200 may be a p-channel
transistor or an n-channel transistor. The fin 210 has a top
surface 250 and laterally opposite sidewalls 255. The fin 210 has a
height or thickness from the insulating surface 215 and a width.
Both the width and height may be uniform or may change between the
source region 240 and the drain region 245. According to various
embodiments, the transistor 200 is a high-k/metal-gate transistor,
where the gate dielectric 230 includes a high-k dielectric and the
gate electrode 235 includes a metal.
[0027] FIG. 3 illustrates a layout of a SRAM cell 300 according to
various embodiments. The SRAM cell 300 has the same arrangement of
transistors as the SRAM cell 100 shown in FIG. 1. The SRAM cell 300
includes single fin field effect transistors formed of
semiconductor material that may be formed on an insulating surface
over a substrate (not shown). The single fin transistors in the
SRAM cell 300 each have a source region, a drain region, and a
channel region in a fin, and a gate dielectric and a gate electrode
similar to the corresponding elements in the transistor 200 shown
in FIG. 2. According to various embodiments, one or more of the
transistors in the SRAM cell 300 may have a plurality of fins.
P-channel transistors are contained in an area 302 defined by a
broken line, and n-channel transistors are contained in two areas
304 and 306 defined by broken lines on either side of the area 302.
The layout of the SRAM cell 300 may be repeated in a pattern to
represent a layout of an array of SRAM cells, and the array may
include shared terminals coupled to VDD for adjacent SRAM cells,
and separate columns of n-type transistors and p-type transistors.
Transistors are identified with reference numbers pointing to their
channels. Contacts are identified by an "x", and may be coupled to
one of WL, BL, BLB, VSS, and VDD.
[0028] A pair of n-type access transistors 310, 312 have respective
gate electrodes 311, 314 coupled to a word line WL, and drains
respectively coupled to a bit line BL and complementary bit line
BLB. A pair of p-type pull-up transistors 320, 322 and a pair of
n-type pull-down transistors 330, 332 are coupled to form a pair of
cross coupled inverters. The transistors 320, 330 are coupled to be
a first inverter, and the transistors 322, 332 are coupled to be a
second inverter. The transistors 320, 330 have a common gate
electrode 340, and the transistors 322, 332 have a common gate
electrode 342. The transistors 320, 322 are coupled to VDD, and the
transistors 330, 332 are coupled to VSS. Drains of the transistors
320, 330 are coupled together at a node Q to a drain of the access
transistor 310 and to the gate electrode 342. The node Q is a body
of semiconductor material connected to the transistors 310, 320,
and 330. Similarly, drains of the transistors 322, 332 are coupled
together at a complementary node QB to a drain of the access
transistor 312 and to the gate electrode 340. The node QB is a body
of semiconductor material connected to the transistors 312, 322,
and 332. A contact on the gate electrode 340 is coupled to a
contact on the node QB through a metal conductor 350, and a contact
on the gate electrode 342 is coupled to a contact on the node Q
through a metal conductor 352.
[0029] FIG. 4 illustrates a layout of a SRAM cell 400 according to
various embodiments. The layout of the SRAM cell 400 has the same
elements as the layout of the SRAM cell 300 shown in FIG. 3, and
similar elements have been given the same reference characters and
will not be further described for purposes of brevity.
[0030] In the SRAM cell 400 illustrated in FIG. 4, the required
performance ratio between the pull-down transistor and the access
transistor is accomplished via longer gate electrodes 311 and 314.
The impact of longer gate electrodes 311 and 314 is on the power
dissipation, since longer gate electrodes imply a higher gate
capacitance and a corresponding switching power. In this case, the
impact on the circuit area is small, but the efficiency of any
layout compaction procedure would be smaller.
[0031] The load transistors 320, 322 in the SRAM cell 400 receive a
treatment that results in the fins of the load transistors 320, 322
having a lower charge carrier mobility than the fins of the
pull-down transistors 330, 332 that do not receive the treatment.
According to various embodiments, the load transistors 320, 322 in
the SRAM cell 400 receive two counter-doping implantations inside
two areas defined by broken lines 420, 422. The two counter-doping
implantations result in the load transistors 320, 322 being weaker
than the respective pull-down transistors 330, 332.
[0032] FIG. 5 illustrates a layout of a SRAM cell 500 according to
various embodiments. The layout of the SRAM cell 500 has the same
elements as the layout of the SRAM cell 300 shown in FIG. 3, and
similar elements have been given the same reference characters and
will not be further described for purposes of brevity.
[0033] Access transistors 510, 512 in the SRAM cell 500 receive a
treatment that results in the fins of the access transistors 510,
512 having a lower charge carrier mobility than the fins of the
pull-down transistors 330, 332 that do not receive the treatment.
According to various embodiments, the access transistors 510, 512
in the SRAM cell 500 receive two counter-doping implantations
inside two areas defined by broken lines 514 and 516. The two
counter-doping implantations result in the access transistors 510,
512 being weaker than the respective pull-down transistors 330,
332. Since the required performance ratio between the access
transistors 510, 512 and the pull-down transistors 330, 332 is
accomplished by a lower charge carrier mobility, the lengths of
gate electrodes 518 519 of the access transistors 510, 512 can be
kept smaller when compared to the corresponding elements in the
SRAM cells 300, 400 illustrated in FIGS. 3 and 4. The lengths of
the gate electrodes 518, 519 are smaller than the lengths of the
gate electrodes 311, 314 illustrated in FIGS. 3 and 4.
[0034] In addition, the load transistors 320, 322 in the SRAM cell
500 receive a treatment that results in the fins of the load
transistors 320, 322 having a lower charge carrier mobility than
the fins of the pull-down transistors 330, 332. According to
various embodiments, the load transistors 320, 322 in the SRAM cell
500 receive two counter-doping implantations inside two areas
defined by broken lines 520, 522. The two counter-doping
implantations result in the load transistors 320, 322 being weaker
than the respective pull-down transistors 330, 332.
[0035] According to various embodiments, channels of the
transistors in the SRAM cells 400, 500 shown in FIGS. 4 and 5 that
do not receive the counter-doping have a doping concentration
substantially less than the doping concentration of the channels of
the transistors that receive the counter-doping. According to
various embodiments, the channel of at least one of the transistors
receiving the counter-doping is doped with a first dopant of a
first polarity and is counter-doped with a second dopant of a
second polarity opposite to the first polarity to a ratio of
approximately 1:1. According to various embodiments, a
concentration of the first dopant is approximately equal to a
concentration of the second dopant. According to various
embodiments, the first dopant is phosphorus (P) or arsenic (As) or
antimony (Sb) and the second dopant is boron (B). According to
various embodiments, channels of the transistors in the SRAM cells
400, 500 shown in FIGS. 4 and 5 that do not receive the
counter-doping do, in fact, receive amounts of the second dopant
that results in a ratio of the first dopant to the second dopant in
these fins being greater than 10:1.
[0036] According to various embodiments, the load transistors 320,
322 and the access transistors 310, 312, 510, 512 in the SRAM cells
400, 500 do not receive the same treatment. The transistors 310,
312, 320, 322, 510, 512 may each receive different dopant
concentrations, or some of the transistors 310, 312, 320, 322, 510,
512 may receive counter-doping, some of the transistors 310, 312,
320, 322, 510, 512 may not receive a treatment, and others of the
transistors 310, 312, 320, 322, 510, 512 may be treated by other
methods to reduce charge carrier mobility as described below.
[0037] Other methods are available to reduce the charge carrier
mobility in the fins of selected transistors in the SRAM cells 400,
500 shown in FIGS. 4 and 5. For example, fins of one or more
selected transistors in the SRAM cells 400, 500 include
interstitials to reduce charge carrier mobility according to
various embodiments. Fins of one or more selected transistors in
the SRAM cells 400, 500 include an electrically non-active material
to reduce charge carrier mobility according to various embodiments.
The electrically non-active material is selected from one or more
of germanium (Ge) and carbon (C). Fins of one or more selected
transistors in the SRAM cells 400, 500 include additional surface
states to reduce charge carrier mobility according to various
embodiments. The additional surface states may be formed by
implants to damage a surface of the fins of the selected
transistors.
[0038] FIG. 6 illustrates characteristic curves 610, 620 of two
single-fin field effect transistors at Ugs=1.2V according to
various embodiments. The transistor with a higher mobility has no
channel doping and has the characteristic curve 610, whereas the
transistor with the lower mobility received 2 implantations with
dopant species of opposite polarity, also called counter-doping,
and has the characteristic curve 620. The reduced mobility leads to
a reduction of saturation and linear currents indicated by arrows
at A and B, respectively. In the linear region, the decreased
mobility reduces current on a relative scale, compared with the
saturation region. The load transistors 120, 122 receive two
counter-doping implantations and have the characteristic curve 620
according to various embodiments.
[0039] FinFET transistors are candidates for high-k/metal-gate
technologies, where a gate dielectric and a gate electrode includes
a high-k dielectric and a metal, respectively. With such a gate
stack, a channel of a FinFET needs no doping to adjust its
threshold voltage. Instead, the threshold voltage is adjusted by an
appropriate choice of the metal with a corresponding work function.
Any of the embodiments described herein introduce dopants of both
polarities into the channels of FinFETs, which have to be weaker
compared to other transistors within a circuit such as a SRAM cell.
According to various embodiments, concentrations of the dopants of
both polarities are nearly identical.
[0040] FIG. 7 illustrates a block diagram of a system 700 according
to various embodiments. The system 700 includes a logic block 710
that is coupled to access a memory array 725 through a periphery
circuit 730. The logic block 710 may be any type of logic device
such as a microprocessor. The logic block 710, the array 725, and
the periphery circuit 730 each may include a respective transistor
750, 752, 754 according to any of the embodiments described herein.
The array 725 may include a SRAM cell 760 according to any of the
embodiments described herein. The array 725 may be a SRAM cell
array including an array of SRAM cells according to any of the
embodiments described herein. The logic block 710, the array 725,
and the periphery circuit 730 each may be fabricated in a separate
integrated circuit, or two or more of the logic block 710, the
array 725, and the periphery circuit 730 may be fabricated in a
single integrated circuit.
[0041] The accompanying drawings that form a part hereof, show by
way of illustration, and not of limitation, specific embodiments in
which the subject matter may be practiced. The embodiments
illustrated are described in sufficient detail to enable those
skilled in the art to practice the teachings disclosed herein.
Other embodiments may be utilized and derived therefrom, such that
structural and logical substitutions and changes may be made
without departing from the scope of this disclosure. This Detailed
Description, therefore, is not to be taken in a limiting sense, and
the scope of various embodiments is defined only by the appended
claims, along with the full range of equivalents to which such
claims are entitled.
[0042] Thus, although specific embodiments have been illustrated
and described herein, it should be appreciated that any arrangement
calculated to achieve the same purpose may be substituted for the
specific embodiments shown. This disclosure is intended to cover
any and all adaptations or variations of various embodiments of the
invention. Combinations of the above embodiments, and other
embodiments not specifically described herein, will be apparent to
those of skill in the art upon reviewing the above description.
[0043] The Abstract of the Disclosure is provided to comply with 37
C.F.R. .sctn.1.72(b), requiring an abstract that will allow the
reader to quickly ascertain the nature of the technical disclosure.
It is submitted with the understanding that it will not be used to
interpret or limit the scope or meaning of the claims.
[0044] In addition, in the foregoing Detailed Description, it can
be seen that various features are grouped together in a single
embodiment for the purpose of streamlining the disclosure. This
method of disclosure is not to be interpreted as reflecting an
intention that the claimed embodiments of the invention require
more features than are expressly recited in each claim. Rather, as
the following claims reflect, inventive subject matter lies in less
than all features of a single disclosed embodiment.
[0045] Thus the following claims are hereby incorporated into the
Detailed Description, with each claim standing on its own as a
separate preferred embodiment. The terms "first," "second," and
"third," etc. are used merely as labels, and are not intended to
impose numerical requirements on their objects.
* * * * *