U.S. patent application number 14/016639 was filed with the patent office on 2014-01-02 for thin film article and method for forming a reduced conductive area in transparent conductive films for photovoltaic modules.
This patent application is currently assigned to First Solar Malaysia Sdn. Bhd.. The applicant listed for this patent is First Solar Malaysia Sdn. Bhd.. Invention is credited to Scott Daniel Feldman-Peabody, Jonathan Mack Frey.
Application Number | 20140000703 14/016639 |
Document ID | / |
Family ID | 44510710 |
Filed Date | 2014-01-02 |
United States Patent
Application |
20140000703 |
Kind Code |
A1 |
Frey; Jonathan Mack ; et
al. |
January 2, 2014 |
Thin Film Article and Method for Forming a Reduced Conductive Area
in Transparent Conductive Films for Photovoltaic Modules
Abstract
A method for forming a reduced conductive area in transparent
conductive. The method includes providing a transparent,
electrically conductive, chemically reducible material. A reducing
atmosphere is provided and concentrated electromagnetic energy from
an energy source is directed toward a portion of the transparent,
electrically conductive, chemically reducible material to form a
reduced conductive area. The reduced conductive area has greater
electrical conductivity than the transparent, electrically
conductive, chemically reducible material. A thin film article and
photovoltaic module are also disclosed.
Inventors: |
Frey; Jonathan Mack;
(Denver, CO) ; Feldman-Peabody; Scott Daniel;
(Golden, CO) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
First Solar Malaysia Sdn. Bhd. |
Kulim |
|
MY |
|
|
Assignee: |
First Solar Malaysia Sdn.
Bhd.
Kulim
MY
|
Family ID: |
44510710 |
Appl. No.: |
14/016639 |
Filed: |
September 3, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12828408 |
Jul 1, 2010 |
8525019 |
|
|
14016639 |
|
|
|
|
Current U.S.
Class: |
136/256 |
Current CPC
Class: |
H01L 31/0465 20141201;
H01L 31/022466 20130101; H01L 31/1884 20130101; Y02E 10/543
20130101; H01L 31/0463 20141201; H01L 31/073 20130101 |
Class at
Publication: |
136/256 |
International
Class: |
H01L 31/0224 20060101
H01L031/0224 |
Claims
1. A thin film article having selectively modified electrical
conductivity: a substrate including a transparent, electrically
conductive, chemically reducible material; and a reduced conductive
area selectively disposed within the electrically conductive,
chemically reducible material; wherein the reduced conductive area
has greater electrical conductivity than the transparent,
electrically conductive, chemically reducible material.
2. The article of claim 1, wherein the reduced conductive area is
metallic.
3. The article of claim 1, wherein the reduced conductive area
further includes a reduced organometallic gas additive.
4. The article of claim 1, wherein the thin film article forms a
portion of a photovoltaic module.
5. The article of claim 1, wherein the reduced conductive area is
disposed within a dead area of the photovoltaic module.
6. The article of claim 1, wherein the thin film article includes a
photovoltaic cell including CdTe.
7. A thin film photovoltaic module having a transparent conductive
oxide layer comprising: a selectively disposed reduced conductive
area within the transparent conductive oxide layer; wherein the
reduced conductive area has greater electrical conductivity than
the transparent conductive oxide layer.
8. The photovoltaic module of claim 7, wherein the reduced
conductive area is metallic.
9. The photovoltaic module of claim 7, wherein the reduced
conductive area further includes a reduced organometallic gas
additive.
10. The photovoltaic module of claim 7, wherein the reduced
conductive area is disposed within a dead area of the photovoltaic
module.
Description
PRIORITY INFORMATION
[0001] The present application claims priority to, and is a
divisional application of, U.S. Pat. No. 8,525,019 of Frey, et al.
titled "Thin Film Article and Method for Forming a Reduced
Conductive Area in Transparent Conductive Films for Photovoltaic
Modules" filed on Jul. 1, 2010, which is incorporated by reference
herein.
FIELD OF THE INVENTION
[0002] The present invention is directed to thin film articles
having transparent conductive films and methods for modifying
transparent conductive films.
BACKGROUND OF THE INVENTION
[0003] Energy demand is constantly increasing. As the energy demand
increases, sources alternative to fossil fuel energy sources
increase in importance. One such alternative energy source is solar
energy. Generally, solar energy is produced by converting radiation
(for example, sunlight) into electricity which may be stored or
transmitted through electrical power grids.
[0004] Transparent conductive oxides (TCOs) are used as
electrically conductive layers for the electrical contact of thin
film photovoltaic (PV) cells in a PV module on a side that receives
sunlight during operation. During processing, interconnections
between cells are provided using thin film application methods and
scribing techniques, using chemicals or lasers to selectively
remove material. As a result of the processing and the structures
forming the interconnections, the area of interconnection between
cells is a "dead area" (i.e., no light collection) and does not
generate electricity.
[0005] In addition, the interconnection between conductive layers
is a large contributor to series resistance in a PV module.
Therefore, it is desirable to decrease the resistivity of the area
of interconnections between PV cells.
[0006] A method for producing an article that has decreased
resistivity/increased conductivity in the interconnection between
cells, without affecting the active area of the PV cells would be
desirable.
BRIEF DESCRIPTION OF THE INVENTION
[0007] One aspect of the present disclosure includes a method for
forming a reduced conductive area in transparent conductive films.
The method includes providing a transparent, electrically
conductive, chemically reducible material. A reducing atmosphere is
providing and concentrated electromagnetic energy from an energy
source is directed toward a portion of the transparent electrically
conductive, chemically reducible material to form a reduced
conductive area. The reduced conductive area has greater electrical
conductivity than the transparent, electrically conductive,
chemically reducible material.
[0008] Another aspect of the present disclosure includes a thin
film article having selectively modified electrical conductivity.
The article includes a substrate having a transparent, electrically
conductive, chemically reducible material and a reduced conductive
area selectively disposed within the electrically conductive,
chemically reducible material. The reduced conductive area has
greater electrical conductivity than the transparent, electrically
conductive, chemically reducible material.
[0009] Still another aspect of the present disclosure includes a
thin film photovoltaic module having a transparent conductive oxide
layer. The module includes a reduced conductive area selectively
disposed within the transparent conductive oxide layer. The reduced
conductive area has greater electrical conductivity than the
transparent conductive oxide layer.
[0010] Other features and advantages of the present invention will
be apparent from the following more detailed description of the
preferred embodiment, taken in conjunction with the accompanying
drawings which illustrate, by way of example, the principles of the
invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 shows a thin film module mounted on a base according
to the disclosure.
[0012] FIG. 2 is a diagram of a layer system making up cells of a
module according to the disclosure.
[0013] FIG. 3 is a process flow diagram for an exemplary process
for forming a module according to the disclosure.
[0014] FIG. 4 shows an enlarged area 400 of the thin film module of
FIG. 1.
[0015] FIG. 5 shows a sectional view taken in direction 5-5 of FIG.
4.
[0016] FIG. 6 is a process flow diagram for an exemplary process
for forming an interconnection according to the disclosure.
[0017] FIG. 7 is a process flow diagram for an exemplary process
for forming a reduced conductive area.
[0018] FIG. 8 is an apparatus for forming a reduced conductive area
according to the disclosure.
[0019] FIG. 9 is an apparatus for forming a reduced conductive area
in a PV cell according to the disclosure.
[0020] Wherever possible, the same reference numbers will be used
throughout the drawings to represent the same parts.
DETAILED DESCRIPTION OF THE INVENTION
[0021] Provided is a method for producing an article that has
decreased resistivity/increased conductivity in the interconnection
between cells, without substantially affecting the active area of
the PV cells. Embodiments of the present disclosure may result in
articles having decreased resistivity in the interconnection area
between cells and increased overall module efficiency. In addition,
other embodiments may permit the laser scribing of the
interconnection in a controlled environment during interconnection
formation in the presence of a readily available oxygen-reducing
gas such as forming gas or carbon monoxide, which decreases the
series resistance of the module. The system and method of the
present disclosure may increase the PV module efficiency, without
complicated or expensive equipment or processes.
[0022] In the disclosure, when a layer is being described as
"adjacent", "on" or "over" another layer or substrate, it is to be
understood that the layer can either be directly in contact or that
another layer or feature can intervene. In addition, "dead area"
includes an area across the PV module that does not produce
electricity when exposed to light. For example a dead area may
include an area having no material that produces electricity or may
include electricity producing layers that are electrically
isolated. Conversely, "active area" includes an area across the PV
module that produces electricity when exposed to light and is
connectable to a load. When a layer or material is described as
"transparent", it is to be understood that a transparent film
includes materials that are fully or partially transparent to light
at some or all wavelengths found in natural sunlight. When a layer
or material is described as "electrically conductive" or
"conductive" or is a "conductor" it is to be understood that the
material permits the flow of electricity with or without electrical
resistance. When a layer or material is described as "electrically
insulative", "insulative" or is an "insulator" it is to be
understood that the material impedes or prevents the flow of
electricity. "Reduced", "reducing", "reduction" and other
grammatical variations thereof refer to chemical reduction of a
material wherein a gain of electrons or a decrease in oxidation
state by a molecule, atom or ion takes place. In particular,
reduction may include the chemical removal of oxygen from an oxide
to form a metallic or partially metallic material. "Modifying",
"modify" and other grammatical variations thereof with respect to
layers, articles and materials refer to a change, such as a
chemical change, in the material resulting in properties that are
different than the original material.
[0023] One embodiment of the disclosure includes a method for
converting a transparent conductive layer, typically a transparent
conductive oxide layer (TCO), in the dead area of a PV module to a
higher conductivity metal. The conversion process may include a
chemical reduction process that removes oxygen from the TCO. The
method through which the TCO is converted is through the
alleviation of oxygen in the films when heated by laser in the
presence of an oxygen-attracting gas such as hydrogen, forming gas
or carbon monoxide.
[0024] FIG. 1 shows a thin film PV module 100 mounted on a base
103. The PV module is arranged to receive light 105. The PV module
is divided into a plurality of cells 107 that are arranged in
series. The cells 107 are divided by spaces, non-conductive
material and/or other structures separating circuits. For example,
cells 107 may be isolated from each other by scribes formed by
laser scribing. When the PV module 100 is exposed to light 105,
electricity is produced. The disclosure is not limited to the
arrangement shown and may include other mounting arrangements
and/or cells 107. For example, the cells 107 may be oriented along
the long dimension of module 100 instead of the short dimension of
module 100. One embodiment of the disclosure includes a thin film
CdTe solar photovoltaic (PV) module. Such modules are used to
produce solar electricity for numerous applications, for example,
large ground-mounted systems and rooftop systems on commercial and
residential buildings. While the PV module may be a thin film
structure, the method and system of the present disclosure may also
be utilized to form gridline front contacts on crystalline solar
cells such as, Si or Group III-V-based concentrators (e.g., GaAs,
and GaInP).
[0025] FIG. 2 is a diagram of the layer system forming cells 107 of
PV module 100. The layers of cell 107 include a superstrate 201, a
first conductive layer 203, a buffer layer 205, a first
semiconductor layer 207, a second semiconductor layer 209, a second
conductive layer 211 and an encapsulating glass 213. The layers of
the cell 107 are arranged to generate and conduct electricity in a
usable form when exposed to light 105.
[0026] The superstrate 201 is a sheet of high transmission glass
onto which thin films are grown. The superstrate receives the light
105 (see FIG. 1) prior to the underlying layers. Superstrate 201
may be standard soda-lime glass, a high-transmission, low-iron
float glass or any other suitable glass material having a high
transmission rate for light 105. In another embodiment, the
superstrate 201 may also be a high transmission borosilicate
glass.
[0027] After the light 105 passes through superstrate 201, at least
a portion of the light 105 passes through first conductive layer
203. First conductive layer 203 may be a transparent conductive
oxide (TCO), which permits transmission of light 105 with little or
no absorption. The first conductive layer 203 is also electrically
conductive, which permits electrical conduction to provide the
series arrangement of cells. The first conductive layer 203 is
formed to a thickness that provides electrical conductivity, but
permits the passage of at least some light 105. While not so
limited, in one embodiment, the first conductive layer 203 may be
formed to a thickness of about 0.1-0.7 .mu.m or 0.1-0.4 .mu.m or
0.2-0.3 .mu.m or 0.2-1.0 .mu.m or 0.3-0.7 .mu.m or 0.35-0.55 .mu.m
of tin oxide. One suitable material for use in formation of the
first conductive layer 203 may be fluorine-doped tin oxide.
[0028] Other suitable conductive layers may include, for example,
stoichiometric cadmium stannate (nominally Cd.sub.2SnO.sub.4),
aluminum-doped zinc oxide, indium tin oxide, doped indium oxide,
zinc or cadmium doped tin oxide, copper aluminum oxides or another
compound of cadmium tin oxide (such as CdSnO.sub.3). First
conductive layer 203 may permit passage of light 105 through to the
semiconductor layers (e.g., first semiconductor layer 207 and
second semiconductor layer 209) while also functioning as an ohmic
electrode to transport photogenerated charge carriers away from the
light absorbing material.
[0029] A buffer layer 205 is adjacent to first conductive layer
203. Buffer layer 205 is more electrically resistive and protects
the layers of cell 107 from chemical interactions from the glass
and/or interactions which might be incurred from subsequent
processing. Inclusion of buffer layer 205 reduces or prevents
electrical or other losses that may take place across cell 107 and
across module 100. Suitable materials for buffer layer 205 may
include tin oxide containing materials, such as, but not limited
to, zinc doped tin oxide, a mixture of zinc and tin oxides (for
example zinc tin oxide having 0.5 to 33 atomic % Zn), zinc
stannate, gallium oxide, aluminum oxide, silicon oxide, indium
oxide, cadmium oxide and any other suitable barrier material having
more electrical resistivity than first conductive layer 203 and the
capability of protecting the layers of the cell from interactions
from the glass or interactions from subsequent processing. In
addition, the inclusion of buffer layer 205 permits the formation
of a first semiconductor layer 207 which permits photon passage
while maintaining a high quality junction capable of generating
electricity. In certain embodiments, buffer layer 205 may be
omitted or substituted by another material or layer. In one
embodiment, buffer layer 205 includes a combination of ZnO and
SnO.sub.2. For example, in one embodiment, the buffer layer 205,
while not so limited, may be formed to a thickness of up to about
1.5 microns or about 0.8-1.5 microns and may include ZnO and
SnO.sub.2 having about 1 to 22 wt % Zn and Zn to Sn ratios from
about 1:60 to 1:2 or from about 1:5 to about 1:18 or about 1:10.
Other suitable Zn to Sn ratios may include 0:1 to 1:2 or about
0:0.5.
[0030] As shown in FIG. 2, first semiconductor layer 207 is
adjacent to buffer layer 205 and receives light 105 subsequent to
superstrate 201, first conductive layer 203 and buffer layer 205.
First semiconductor layer 207 includes a wide bandgap n-type
semiconductor material. Suitable semiconductor material for first
semiconductor layer 207 includes, but is not limited to CdS,
SnO.sub.2, CdO, ZnO, AnSe, GaN, In.sub.2O.sub.2, CdSnO, ZnS, CdZnS
or other suitable n-type semiconductor material. In one embodiment
the first semiconductor layer 207 includes CdS. While not so
limited, first semiconductor layer 207 may have a thickness from
about 0.01 to about 0.12 .mu.m or 0.03 to 0.1 .mu.m or 0.05 to 0.9
.mu.m or about 0.08 .mu.m. First semiconductor layer 207 may be
formed by chemical bath deposition or by sputtering. First
semiconductor layer 207 preferably has a smooth surface and is
substantially uniform and free of impurities and pinholes.
[0031] First semiconductor layer 207 forms the junction with a
second semiconductor layer 209 to create the photovoltaic effect in
cell 107, allowing electricity to be generated from light 105.
Second semiconductor layer 209 may include, for example, Cd, CdTe
or other p-type semiconductor material. When second semiconductor
layer 209 is provided with first semiconductor layer 207 a
photovoltaic effect results when exposed to light 105.
[0032] As shown in FIG. 2, second semiconductor layer 209 is
adjacent to first semiconductor layer 207. A second conductive
layer 211 is adjacent to the second semiconductor layer 209 and
provides an electrically conductive material that is capable of
conducting electricity formed from the combination of the first
semiconductor layer 207 and second semiconductor layer 209 when
exposed to light 105. Although FIG. 2 shows an arrangement of two
layers for first semiconductor layer 207 and second semiconductor
layer 209, any number of layers, including interfacial layers, may
be utilized to provide the photovoltaic effect.
[0033] Second conductive layer 211 may be fabricated from any
suitable conductive material and combinations thereof. For example,
suitable materials may include materials including, but not limited
to, graphite, metallic silver, nickel, copper, aluminum, titanium,
palladium, chrome, molybdenum alloys of metallic silver, nickel,
copper, aluminum, titanium, palladium, chrome, and molybdenum and
any combination thereof. In one embodiment, second conductive layer
209 may be a combination of graphite, nickel and aluminum
alloys.
[0034] An encapsulating glass 213 may be adhered adjacent to second
conductive layer 211. Encapsulating glass 213 may be a rigid
structure suitable for use with the thin films of cell 107.
Encapsulating glass 213 may be the same material as superstrate 201
or may be different. In addition, although not shown in FIG. 2,
encapsulating glass 213 may include openings or structures to
permit wiring and/or connection to cell 107.
[0035] Module 100 and individual cells 107 may include other layers
and structures not shown in FIG. 2. For example, superstrate 201
and/or encapsulating glass 213 may include a barrier coating or
other structure in order to reduce or prevent diffusion of
impurities into the layers. In addition, encapsulating glass 213
may include an adherent layer to adhere encapsulating glass 213 to
the layers. Additional structures that may be present in module 100
and/or cells 107 include, for example, scribes, bussing structures,
external wiring, and various conventional components useful with
thin film and/or PV structures.
[0036] FIG. 3 shows a process flow diagram for an exemplary process
for forming module 100. The process includes the formation of a
thin film stack forming cell 107, wherein the films or layers are
formed on superstrate 201 (shown from the top down in FIG. 2).
[0037] As shown in the flow diagram of FIG. 3, superstrate 201 is
provided (box 301). Superstrate 201 may be fabricated from any
suitable material capable of receiving thin films for use as
photovoltaic cells and sufficiently transparent to allow
transmission of light 105.
[0038] Subsequent to providing superstrate 201, first conductive
layer 203 is deposited onto superstrate 201 (box 303). First
conductive layer 203 is electrically conductive, which permits
electrical conduction to provide the series arrangement of cells
107. While not so limited, in one embodiment, first conductive
layer 203 may be formed to a thickness of about 0.1-0.7 .mu.m or
0.1-0.4 .mu.m or 0.2-0.3 .mu.m or 0.2-1.0 .mu.m or 0.3-0.7 .mu.m or
0.35-0.55 .mu.m of tin oxide. Other suitable conductive layers may
include fluorine-doped stoichiometric cadmium stannate (nominally
Cd.sub.2SnO.sub.4), aluminum-doped zinc oxide, indium tin oxide,
doped indium oxide, zinc or cadmium doped tin oxide, copper
aluminum oxides or another compound of cadmium tin oxide (such as
CdSnO.sub.3). First conductive layer 203 can be formed, for
example, by direct current (DC) or radio frequency (RF) sputtering.
In one embodiment, first conductive layer 203 is a layer of tin
oxide substantially amorphous Cd.sub.2SnO.sub.4 that is deposited
with chemical vapor deposition (CVD) onto superstrate 201. Such CVD
can be performed from tin and fluorine containing precursors in an
oxygen containing environment.
[0039] Once first conductive layer 203 is applied, buffer layer 205
may be applied to first conductive layer 203 (box 305). In one
embodiment, buffer layer 205 may be formed, for example, by
sputtering. In one example, buffer layer 205 may be formed by
sputtering from a hot-pressed target containing, for example,
primarily Sn and 1-22% Zn by weight or stoichiometric amounts of
about 67 mol % SnO.sub.2 and about 33 mol % ZnO onto first
conductive layer 203. When deposited by sputtering, the zinc tin
oxide material for buffer layer 205 may be substantially amorphous.
Buffer layer 205 may have a thickness of between about 200 and
3,000 Angstroms, or between about 800 and 1,500 Angstroms, in order
to have desirable mechanical, optical, and electrical properties.
Buffer layer 205 may have a wide optical bandgap, for example about
3.3 eV or more, in order to permit the transmission of light
105.
[0040] First semiconductor layer 207 is deposited on buffer layer
205 (box 307). In one embodiment, first semiconductor layer 207 may
be formed, for example, by chemical bath deposition or sputtering.
While not so limited, first semiconductor layer 207 may be
deposited to a thickness of from about 0.01 to about 0.3 .mu.m or
about 0.01 to about 0.12 .mu.m or 0.03 to 0.1 .mu.m or 0.05 to 0.9
.mu.m or about 0.08 .mu.m. One suitable material for use as first
semiconductor layer 207 may include CdS. A suitable thickness for a
CdS layer may range from about 500 to 800 Angstroms. First
semiconductor layer 207 forms the junction with second
semiconductor layer 209 to create the photovoltaic effect in cell
107, allowing cell 107 to produce electricity from light 105.
[0041] After the formation of first semiconductor layer 207, second
semiconductor layer 209 is deposited on first semiconductor layer
207 (box 309). Second semiconductor layer 209 may include Cd, CdTe
or other p-type semiconductor material. Second semiconductor layer
209 may be deposited by diffusive transport deposit, sputtering or
other suitable deposition method for depositing p-type
semiconductor thin film material.
[0042] Subsequent to the formation of the second semiconductor
layer 209, second conductive layer 211 is formed (box 311). Second
conductive layer 211 may be fabricated from any suitable conductive
material. Second conductive layer 211 may be formed by sputtering,
electrodeposition, screen printing, physical vapor deposition
(PVD), chemical vapor deposition (CVD) or spraying. In one
embodiment, second conductive layer 211 is a combination of
graphite that is screen printed onto the surface and nickel and
aluminum alloy that is sputtered thereon.
[0043] All the sputtering steps described above may be magnetron
sputtering at ambient temperature under highly pure atmospheres.
For example, a zinc tin oxide buffer layer 205 may be formed by DC
sputtering. However, other deposition processes may be used,
including higher temperature sputtering, electrodeposition, screen
printing, physical vapor deposition (PVD), chemical vapor
deposition (CVD) or spraying. In addition, the processing may be
provided in a continuous line or may be a series of batch
operations. When the process is a continuous process, the
sputtering or deposition chambers are individually isolated and
brought to coating conditions during each coating cycle, then
repeated.
[0044] Once second conductive layer 211 is formed, encapsulating
glass 213 is adhered to second conductive layer 211 (box 313).
Encapsulating glass 213 may be a rigid material suitable for use
with thin film structures and may be the same material or different
material than superstate 201. Encapsulating glass 213 may be
adhered to second conductive layer 211 using any suitable method.
For example, encapsulating glass 213 may be adhered to second
conductive layer 211 using an adhesive or other bonding
composition.
[0045] Although not shown in FIG. 3, other processing steps may be
included in the process for forming module 100 and cells 107. For
example, cleaning, etching, doping, dielectric or other selective
insulative material deposition, formation of interfacial layers,
scribing, heat treatments, and wiring may also be utilized. For
example, wiring and/or bussing devices may be provided to complete
the PV circuit (i.e., cells 107 in series arrangement) and to
provide connectivity of the PV circuit to a load or other external
device.
[0046] Scribing may be utilized to form the interconnections
between the layers and to isolate cells and/or layers of the thin
film stack. Scribing may be accomplished using any known technique
for scribing and/or interconnecting the thin film layers. In one
embodiment, scribing is accomplished using a laser directed at one
or more layers from one or more directions. One or more laser
scribes may be utilized to selectively remove thin film layers and
to provide interconnectivity and/or isolation of cells 107. In one
embodiment, the scribes and layer deposition are accomplished to
interconnect and/or isolate cells 107 to provide a PV circuit
having cells 107 in a series of electrical arrangements.
[0047] FIG. 4 shows an enlarged area 400 from FIG. 1. As shown in
FIG. 4, cells are divided by interconnections 401. The
interconnections 401 may be any suitable structures for forming the
electrical interconnection between cells 107. Suitable structures
may include spacing or scribes, dielectric material, insulating
material, wiring, conductive material or other suitable material
for forming the electrical connection between cells 107.
[0048] FIG. 5 illustrates a side view of an exemplary film stack
for interconnection 401 taken in direction 5-5 of FIG. 4. As shown
in FIG. 5, the interconnection 401 includes structures formed
between cells 107. As shown in FIG. 5, the interconnection 401
includes a first scribe 503, a second scribe 505 and a third scribe
507. First scribe 503, second scribe 505 and third scribe 507 of
interconnection 401 are formed during the formation of the cell 107
(see method of FIG. 3).
[0049] FIG. 6 includes a flowchart illustrating an exemplary method
for forming interconnection 401. The method includes depositing
second semiconductor layer 209 (box 309), as shown and described
with respect to box 309 of FIG. 3. Specifically, first scribe 503
is formed subsequent to the deposition of the second semiconductor
layer (box 603) and may be formed by directing an energy source,
for example in the form of concentrated electromagnetic energy, or
a beam through superstrate 201 to selectively remove the layers
present thereon. Suitable energy sources may include, but are not
limited to, laser, radio frequency (Rf), electron beam, ion beam,
infrared (IR) or source for rapid thermal process (RTA). In another
embodiment, the scribe may be formed by chemical processes, such as
photolithography. To provide electrical isolation, the first scribe
503 is filled with dielectric material 509 (box 605). Suitable
dielectric materials may include, but are not limited to a negative
photo resist or other suitable dielectric material.
[0050] The method for forming interconnection 401 further includes
formation of the second scribe 505 during the deposition of the
second conductive layer 211 (box 609 of FIG. 6, box 311 of FIG. 3).
This step includes depositing a first portion 511 of second
conductive layer 211. This first portion 511 may include any
suitable conductive material. Suitable first portion 511 may
include, for example, graphite. After the first portion 511 is
formed, the second scribe 505 may be formed by directing
concentrated electromagnetic energy or a beam from an energy source
through superstrate 201 to selectively remove the layers present
thereon (box 609). The energy source may be any suitable energy
source and may include the same or different source utilized to
form first scribe 503. Subsequent to formation of second scribe
505, a second portion 513 of the second conductive layer 211 is
provided (box 611). The second portion 513 may be any suitable
conductive material and may include, for example, metal alloys,
such as Ni and Al containing alloys. For example, in one embodiment
a first portion 511 containing a graphite layer is provided prior
to the second scribe 505 and a second portion 513 a metal layer is
provided after the second scribe 505 is formed. In addition to
providing the second portion 513 to the cell 107, the second
portion 513 is also deposited onto surfaces formed by the second
scribe 505. Since the second portion 513 of the second conductive
layer 211 is electrically conductive, the second portion
electrically connects the first conductive layer 203 and buffer
layer 205 to the second conductive layer 211. This connection (upon
isolation with the third scribe 507, see below) places the cells
107 into a series arrangement.
[0051] The third scribe 507 is formed subsequent to the deposition
of the second conductive layer 211 (box 613). The third scribe 507
may be formed by directing concentrated electromagnetic energy from
an energy source onto the layers from the direction opposite the
superstrate 201 to selectively remove the layers present thereon.
The energy source may be any suitable energy source and may include
the same or different source utilized to form first scribe 503.
Third scribe 507 severs the first conductive layer 211, the first
semiconductor layer 207 and the second semiconductor layer 209, but
permits the buffer layer 205 and the first conductive layer 203 to
remain (see e.g., FIG. 5). The arrangement of the module 100
remaining after the third scribe 507 is a series arrangement of
cells 107.
[0052] The second scribe 505 formed after the deposition of the
first portion 511 of the second conductive layer 211 (see e.g., box
609 in FIG. 6) results in a space that extends to the first
conductive layer 203 (see e.g., FIG. 5). In one embodiment of the
present disclosure, reduced conductive area 501 is formed on the
first conductive layer 203. The reduced conductive area 501 is an
area in which the material of the first conductive layer 203 is at
least partially chemically reduced. The reduced conductive area 501
may be located along the first conductive layer 203. The
positioning of the reduced conductive area 501 may be such that the
reduced conductive area 501 occupies the dead areas of module 100
that do not generate electricity, wherein any opacity or lack of
transparency in the reduced conductive area 501 does not affect the
performance of the module 100. In addition, the increased
conductivity or reduced resistivity of the first conductive layer
203 in the area of the reduced conductive area 501 increases the
efficiency and/or performance of the module 100.
[0053] FIG. 7 includes a flowchart illustrating an exemplary method
for forming reduced conductive area 501. The method includes
providing a transparent, electrically conductive, reducible
material (box 701). The reducible material may, for example, be a
first conductive layer 203 including transparent conductive oxide
(TCO) material. Suitable reducible material may include SnO.sub.2,
In.sub.2O.sub.3, Cd.sub.2SnO.sub.4, ZnO, other reducible material
and combinations thereof. The method further includes providing a
reducing atmosphere (box 703). The reducing atmosphere may include
gas such as, for example, hydrogen, carbon monoxide, reforming gas
or other suitable reducing gas. An exemplary reducing atmosphere
may include a combination of carbon monoxide and forming gas (4-5%
H.sub.2, 95-96% N.sub.2) ambient gas composition. In another
embodiment, the reducing atmosphere may include a gas additive to
provide desirable material properties in the formed reduced
conductive area 501. In this embodiment, the reduced conductive
area 501 may include reduced gas additive. In one embodiment, the
gas additive is provided to reduce or eliminate the amount of
volume change that may result from the reduction or exposure to
heat. Suitable gas additives may include organometallic gasses such
as tin tetrachloride, dimethyl cadmium, dimethyl zinc or
combinations thereof. An energy source, such as a laser, is
directed toward the reducible material in the form of concentrated
electromagnetic energy (box 705). The laser or other energy source
is configured to generate concentrated electromagnetic energy with
a power density and/or wavelength that provides heat and energy to
the reducible material. The reduced conductive area 501 where
concentrated electromagnetic energy 803 from the energy source 801
(see e.g., FIG. 8) contacts the reducible material in the reducing
atmosphere includes conditions that facilitate reduction of the
reducible material to form the reduced conductive area 501 (box
707). The reduced conductive area 501 includes an electrical
conductivity that is greater than the conductivity of the reducible
material.
[0054] FIG. 8 illustrates an apparatus for forming the reduced
conductive area 501 as shown and described in FIG. 7. As shown in
FIG. 8, an energy source 801 emits concentrated electromagnetic
energy 803 that is directed at surface 805 of first conductive
layer 203. The energy source 801 may be an energy source capable of
providing sufficient heat to the surface 805 of the first
conductive layer 203 to at least partially reduce the first
conductive layer 203. The process is accomplished in a chamber 807
that is capable of providing a reducing atmosphere 809 at the
surface 805. When concentrated electromagnetic energy 803 contacts
the surface 805 in the presence of the reducing atmosphere, the
first conductive layer 203 is at least partially reduced to form a
reduced conductive area 501. In one embodiment, the reduced
conductive area 501 is metallic. In certain embodiments, the
reduced conductive area 501 is at least partially opaque. In these
embodiments, the positioning of the reduced conductive area 501 is
such that the opacity is in areas that do in impede sunlight and/or
does not substantially affect the operation of the module 100.
[0055] FIG. 9 shows another embodiment, wherein a reduced
conductive area 501 is formed when the second scribe 505 is being
formed (box 609 of FIG. 6). In this embodiment, the energy source
801 includes concentrated electromagnetic energy 803, such as a
laser beam, that is directed through superstrate 201, wherein the
first portion 511 of first conductive layer 203, buffer layer 205,
the first semiconductor layer 207, second semiconductor layer 209
and second conductive layer 211 are selectively removed.
Concentrated electromagnetic energy 803 provides heat to surface
805 of first conductive layer 203. In addition, a reducing
atmosphere 809 is provided to surface 805, resulting in formation
of reduced conductive area 501 on first conductive layer 203.
[0056] While the above has been described with respect to
photovoltaic modules and photovoltaic devices, the method, thin
film structure and apparatus of the present disclosure are usable
with other thin film devices. Other thin film devices usable with
the present disclosure include, but are not limited to photo
detectors, diode application, or thin film displays.
[0057] While the invention has been described with reference to a
preferred embodiment, it will be understood by those skilled in the
art that various changes may be made and equivalents may be
substituted for elements thereof without departing from the scope
of the invention. In addition, many modifications may be made to
adapt a particular situation or material to the teachings of the
invention without departing from the essential scope thereof.
Therefore, it is intended that the invention not be limited to the
particular embodiment disclosed as the best mode contemplated for
carrying out this invention, but that the invention will include
all embodiments falling within the scope of the appended
claims.
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