U.S. patent application number 13/869486 was filed with the patent office on 2013-12-19 for multibit memory with read voltage qualification at startup.
This patent application is currently assigned to Being Advanced Memory Corporation. The applicant listed for this patent is Being Advanced Memory Corporation. Invention is credited to Ryan Jurasek, Aaron D. Willey.
Application Number | 20130336051 13/869486 |
Document ID | / |
Family ID | 49484019 |
Filed Date | 2013-12-19 |
United States Patent
Application |
20130336051 |
Kind Code |
A1 |
Jurasek; Ryan ; et
al. |
December 19, 2013 |
MULTIBIT MEMORY WITH READ VOLTAGE QUALIFICATION AT STARTUP
Abstract
Systems in which multi-bit PCM is used, including memory
systems, as well as methods for operating such systems. A test of
multi-bit PCM memory elements with known states can be used to
determine whether immediately available voltage levels can reliably
read multi-bit PCM. This can be used to accelerate availability of
memory states residing in multi-bit PCM with respect to, for
example, redundancy address storage, other startup state
information, and parameters for which nonvolatile storage is
useful.
Inventors: |
Jurasek; Ryan; (Burlington,
VT) ; Willey; Aaron D.; (Burlington, VT) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Being Advanced Memory Corporation; |
|
|
US |
|
|
Assignee: |
Being Advanced Memory
Corporation
Essex Junction
VT
|
Family ID: |
49484019 |
Appl. No.: |
13/869486 |
Filed: |
April 24, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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61637533 |
Apr 24, 2012 |
|
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|
61784480 |
Mar 14, 2013 |
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Current U.S.
Class: |
365/163 ;
365/148 |
Current CPC
Class: |
G11C 13/003 20130101;
G11C 13/0021 20130101; G11C 2213/79 20130101; G11C 13/0061
20130101; G11C 13/004 20130101; G11C 13/0004 20130101; G11C 29/78
20130101 |
Class at
Publication: |
365/163 ;
365/148 |
International
Class: |
G11C 13/00 20060101
G11C013/00 |
Claims
1. A memory comprising: at least one array of multi-bit phase
change memory cells; redundancy logic which redirects attempted
accesses from defective memory elements in said array to redundant
memory elements, in dependence on a table of defective memory
locations residing in multi-bit phase change memory when power to
the memory is OFF; and a voltage qualification unit configured to
test whether reads of a plurality of multi-bit phase change memory
reference cells produce different outputs corresponding to the at
least three different logic states stored in said reference cells,
and to allow said redundancy logic to begin redirecting accesses
only after said outputs correspond to said logic states, wherein
said test uses a read voltage generated using said power to the
memory.
2. The memory of claim 1, wherein said reference cells instantiate
at least one of each possible state, and wherein said corresponding
is at least partially dependent on comparing said outputs to said
logic states using differential sense amplifiers.
3. The memory of claim 1, further comprising repair logic which
applies one or more activation voltage variances to adjust feature
activation voltages in said memory, said activation voltage
variances being at least partially specified by values residing in
a multi-bit phase change memory when power to the memory is OFF,
wherein said voltage qualification unit is configured to allow said
repair logic to begin adjusting said feature activation voltages
only after said outputs correspond to said logic states.
4. The memory of claim 3, wherein said activation voltage variances
correct for differences between designed feature activation
voltages and as-manufactured feature activation voltages.
5. The memory of claim 1, wherein said reference cells comprise one
or more groups of reference cells, ones of said groups configured
to store at least one of each possible logic state.
6. The memory of claim 1, further comprising configuration logic
which loads configuration information from a multi-bit phase change
memory into a volatile memory, said configuration information
residing in said multi-bit phase change memory when power to the
memory is OFF, said configuration information at least partially
determining one or more operation parameters of said memory,
wherein said voltage qualification unit is configured to allow said
configuration logic to begin loading configuration information only
after said outputs correspond to said logic states.
7. The memory of claim 6, wherein said operation parameters
comprise one or more of internal supply voltages, sense amplifier
timings, setup and/or hold timings in data paths, and an ON/OFF
state of one or more memory functions.
8. The memory of claim 1, wherein different numbers of reference
cells store different ones of said different logic states.
9. The memory of claim 1, wherein said testing comprises performing
multiple comparisons between said outputs and said logic states,
and said corresponding comprises a pre-determined number of
uninterrupted matches between said outputs and said logic
states.
10. A memory connectable to be powered from a supply voltage,
comprising: at least one redundancy data storage comprising a
plurality of multi-bit phase change memory cells; at least one
array of multi-bit phase change memory cells; at least one access
logic controlling access to said array and operating in at least
partial dependence on redundancy data stored in said redundancy
data storage; and a voltage qualification unit configured to detect
whether the supply voltage causes reads of a plurality of multi-bit
reference phase change memory cells to produce correctly distinct
outputs corresponding to at least three different logic states
stored in said reference cells, wherein said redundancy data
storage is operatively connected to enable said access logic only
after said voltage qualification unit has detected said correctly
distinct outputs.
11. The memory of claim 10, wherein said reference cells
instantiate at least one of each possible state, and wherein said
detecting comprises comparing said outputs to said logic states
using differential sense amplifiers.
12. The memory of claim 10, further comprising repair logic which
applies one or more activation voltage variances to adjust feature
activation voltages in said memory, said activation voltage
variances being at least partially specified by values residing in
a multi-bit phase change memory when power to the memory is OFF,
wherein said voltage qualification unit is configured to allow said
repair logic to begin adjusting said feature activation voltages
only after said voltage qualification unit has detected said
correctly distinct outputs.
13. The memory of claim 12, wherein said activation voltage
variances correct for differences between designed feature
activation voltages and as-manufactured feature activation
voltages.
14. The memory of claim 10, wherein said reference cells comprise
one or more pairs of reference cells configured to store
complementary logic states.
15. The memory of claim 10, further comprising configuration logic
which loads configuration information from a phase change memory
into a volatile memory, said configuration information residing in
said phase change memory when power to the memory is OFF, said
configuration information at least partially determining one or
more operation parameters of said memory, wherein said voltage
qualification unit is configured to allow said configuration logic
to begin loading configuration information only after said voltage
qualification unit has detected said correctly distinct
outputs.
16. The memory of claim 15, wherein said operation parameters
comprise one or more of internal supply voltages, sense amplifier
timings, setup and/or hold timings in data paths, and an ON/OFF
state of one or more memory functions.
17. The memory of claim 10, wherein different numbers of reference
cells store different ones of said different logic states.
18. The memory of claim 10, wherein said testing comprises
performing multiple comparisons between said outputs and said
different logic states, and said detecting correctly distinct
outputs comprises a pre-determined number of uninterrupted matches
between said outputs and said different logic states.
19. A memory comprising: at least one multi-bit phase change memory
array; a test logic configured to read/write test memory elements
in said array, and to write redundancy information corresponding to
defective memory elements that fail said read/write testing to a
table of defective memory locations, said table residing in
multi-bit phase change memory when power is OFF; a voltage
qualification unit configured to test whether reads of multiple
multi-bit phase change memory reference cells produce different
outputs corresponding to the at least three different logic states
stored in said reference cells, and to allow a redundancy logic to
begin redirecting accesses from said defective memory elements to
redundant multi-bit phase change memory elements, in dependence on
said table, only after said outputs correspond to said logic
states, wherein said test uses a voltage generated using said power
to the memory.
20. The memory of claim 19, wherein said reference cells
instantiate at least one of each possible state, and wherein said
corresponding is at least partially dependent on comparing said
outputs to said logic states using differential sense
amplifiers.
21.-45. (canceled)
Description
CROSS-REFERENCE
[0001] Priority is claimed from U.S. Provisional Patent Application
Nos. 61/637,533 filed Apr. 24, 2012, and 61/784,480 filed Mar. 14,
2013, both of which are hereby incorporated by reference.
BACKGROUND
[0002] The present application relates to systems, devices and
methods for startup operations involving multi-bit phase change
memory units.
[0003] Note that the points discussed below may reflect the
hindsight gained from the disclosed inventions, and are not
necessarily admitted to be prior art.
[0004] Phase change memory ("PCM") is a relatively new nonvolatile
memory technology, which is very different from any other kind of
nonvolatile memory. First, the fundamental principles of operation,
at the smallest scale, are different: no other kind of solid-state
memory uses a reversible PHYSICAL change to store data. Second, in
order to achieve that permanent physical change, an array of PCM
cells has to allow read, set, and reset operations which are all
very different from each other. The electrical requirements of the
read, set, and reset operations make the peripheral circuit
operations of a PCM very different from those of other nonvolatile
memories. Obviously some functions, such address decoding and bus
interface, can be the same; but the closest-in parts of the
periphery, which perform set, reset, and read operations on an
array or subarray, must satisfy some unique requirements.
[0005] The physical state of a PCM cell's memory material is
detected as resistance. For each selected cell, its bitline is set
to a known voltage, and the cell's access transistor is turned on
(by the appropriate wordline). If the cell is in its low-resistance
state, it will sink a significant current from the bit line; if it
is not, it will not.
[0006] Set and Reset operations are more complicated. Both involve
heat. As discussed below, a "set" operation induces the memory
material to recrystallize into its low-resistance (polycrystalline)
state; a "reset" operation anneals the memory material into its
high-resistance (amorphous) state.
[0007] Write operations (Set and Reset) normally have more time
budget than read operations. In read mode a commercial PCM memory
should be competitive with the access speed (and latency if
possible) of a standard DRAM. If this degree of read speed can be
achieved, PCM becomes very attractive for many applications.
[0008] The phase change material is typically a chalcogenide glass,
using amorphous and crystalline (or polycrystalline) phase states
to represent bit states.
[0009] A complete PCM cell can include, for example: a top
electrode (connected to the bit line), a phase change material
(e.g. a chalcogenide glass), a conductive pillar which reaches down
from the bottom of the phase change material, an access transistor
(gated by a word line), and a bottom connection to ground. The
phase change material can extend over multiple cells (or over the
whole array), but the access transistors are laterally isolated
from each other by a dielectric.
[0010] FIG. 2A shows an example of a PCM element 2010. A top
electrode 2020 overlies a phase change material 2030, e.g. a
chalcogenide glass. Note that material 2030 also includes a
mushroom-shaped annealed zone (portion) 2070 within it. (The
annealed zone 2070 may or may not be present, depending on what
data has been stored in this particular location.) The annealed
zone 2070, if present, has a much higher resistivity than the other
(crystalline or polycrystalline) parts of the material 2030.
[0011] A conductive pillar 2050 connects the material 2030 to a
bottom electrode 2040. In this example, no selection device is
shown; in practice, an access transistor would normally be
connected in series with the phase change material. The pillar 2050
is embedded in an insulator layer 2060.
[0012] When voltage is applied between the top 2020 and bottom 2040
electrodes, the voltage drop will appear across the
high-resistivity zone 2070 (if present). If sufficient voltage is
applied, breakdown will occur across the high-resistivity zone. In
this state the material will become very conductive, with large
populations of mobile carriers. The material will therefore pass
current, and current crowding can occur near the top of the pillar
2050. The voltage which initiates this conduction is referred to as
the "snapback" voltage, and FIG. 2C shows why.
[0013] FIG. 2C shows an example of instantaneous I-V curves for a
device like that of FIG. 2A, in two different states. Three zones
of operation are marked.
[0014] In the zone 2200 marked "READ," the device will act either
as a resistor or as an open (perhaps with some leakage). A small
applied voltage will result in a state-dependent difference in
current, which can be detected.
[0015] However, the curve with open circles, corresponding to the
amorphous state of the device, shows some more complex behaviors.
The two curves show behaviors under conditions of higher voltage
and higher current.
[0016] If the voltage reaches the threshold voltage V.sub.th,
current increases dramatically without any increase in voltage.
(This occurs when breakdown occurs, so the phase-change material
suddenly has a large population of mobile carriers.) Further
increases in applied voltage above V.sub.th result in further
increases in current; note that this upper branch of the curve with
hollow circles shows a lower resistance than the curve with solid
squares.
[0017] If the applied voltage is stepped up to reach the zone 2150,
the behavior of the cell is now independent of its previous
state.
[0018] When relatively large currents are applied, localized
heating will occur at the top of the pillar 2050, due to the
relatively high current density. Current densities with typical
dimensions can be in the range of tens of millions of Amperes per
square cm. This is enough to produce significant localized heating
within the phase-change material.
[0019] This localized heating is used to change the state of the
phase-change material, as shown in FIG. 2B. If maximum current is
applied in a very brief pulse 2100 and then abruptly stopped, the
material will tend to quench into an amorphous high-resistivity
condition; if the phase-change material is cooled more gradually
and/or not heated as high as zone 2150, the material can
recrystallize into a low-resistivity condition. Conversion to the
high-resistance state is normally referred to as "Reset", and
conversion to the low-resistance state is normally referred to as
"Set" (operation 2080). Note that, in this example, the Set pulse
has a tail where current is reduced fairly gradually, but the Reset
pulse does not. The duration of the Set pulse is also much longer
than that of the Reset pulse, e.g. tens of microseconds versus
hundreds of nanoseconds.
[0020] FIG. 2D shows an example of temperature versus resistivity
for various PCM materials. It can be seen that each curve has a
notable resistivity drop 2210 at some particular temperature. These
resistivity drops correspond to phase change to a crystalline (or
polysilicon) state. If the material is cooled gradually, it remains
in the low resistivity state after cooling.
[0021] In a single-bit PCM, as described above, only two phases are
distinguished: either the cell does or does not have a significant
high-resistivity "mushroom cap" 2070. However, it is also possible
to distinguish between different states of the mushroom cap 2070,
and thereby store more than one bit per cell.
[0022] FIG. 2E shows an equivalent circuit for an "upside down" PCM
cell 2010. In this example the pass transistor 2240 is gated by
Wordline 2230, and is connected between the phase-change material
2250 and the bitline 2220. (Instead, it is somewhat preferable to
connect this transistor between ground and the phase-change
material.
[0023] FIG. 2F shows another example of a PCM cell 2010. A bitline
2220 is connected to the top electrode 2020 of the phase-change
material 2250, and transistor 2240 which is connected to the bottom
electrode 2030 of the PCM element. (The wordline 2230 which gates
the vertical transistor 2240 is not shown in this drawing.) Lines
2232, which are shown as separate (and would be in a diode array),
may instead be a continuous sheet, and provide the ground
connection.
[0024] FIG. 2G shows an example of resistance (R) over time (t) for
a single PCM cell following a single PCM write event at time t=0.
The resistance curve 2400 for a cell which has been reset (i.e.
which is in its high-resistance state) may rise at first, but then
drifts significantly lower. The resistance curve 2410 for a cell in
the Set state is much flatter. The sense margin 2420, i.e., the
difference between set and reset resistances, also decreases over
time. Larger sense margins generally result in more reliable reads,
and a sense margin which is too small may not permit reliable
reading at all. 2G represents the approximate behavior of one known
PCM material; other PCM material compositions may behave
differently.
[0025] For example, other PCM material compositions may display
variation of the set resistance over time.
[0026] The downwards drift of reset resistance may be due to, for
example, shrinking size of the amorphous zone of the phase-change
material, due to crystal growth; and, in some cells, spontaneous
nucleation steepening the drift curve (possibly only slightly) due
to introducing further conductive elements into the mushroom-shaped
programmable region.
[0027] FIG. 2H shows an example of a processing system 2300.
Typically, a processing system 2300 will incorporate at least some
of interconnected power supplies 2310, processor units 2320
performing processing functions, memory units 2330 supplying stored
data and instructions, and I/O units 2340 controlling
communications internally and with external devices 2350.
[0028] FIG. 21 shows an example of a PCM single ended sensing
memory. Two different PCM cells 2400 on different ends of a sense
amplifier can be selected separately. Selected elements 2410 are
separately sensed by a single-ended sense amplifier 2420.
[0029] FIG. 2J shows an example of a known PCM single ended sense
amplifier 2500. Generally, in a single ended sense amplifier, a
cell read output conducted by a selected bitline BLB is compared
against a reference current to provide a digital output OUT. When
the PRECHARGE signal turns on transistor 2530, voltage V04 (e.g.,
400 mV) precharges the bitline BLB. After precharge ends, the READ
signal turns on transistor 2550. Transistor 2550 is connected,
through source follower 2560 and load 2580, to provide a voltage
which comparator 2600 compares to Voltage_REF, to thereby generate
the digital output OUT.
[0030] A variety of nonvolatile memory technologies have been
proposed over recent decades, and many of them have required some
engineering to provide reference values for sensing. However, the
requirements and constraints of phase-change memory are
fundamentally different from those of any other kind of nonvolatile
memory. Many memory technologies (such as EEPROM, EPROM, MNOS, and
flash) test the threshold voltage of the transistor in a selected
cell, so referencing must allow for the transistor's behavior. By
contrast, phase-change memory simply senses the resistance of the
selected cell. This avoids the complexities of providing a
reference which will distinguish two (or more) possibilities for an
active device's state, but does require detecting a resistance
value, and tracking external variations (e.g. temperature and
supply voltage) which may affect the instantaneous value of that
resistance.
[0031] The possibility of storing more than one bit of data in a
single phase-change material has also been suggested. Phase-change
memories implementing such architectures are referred to here as
"multibit" PCMs. If the "Set" and/or "Reset" operations can be
controlled to produce multiple electrically distinguishable states,
then more than one bit of information can be stored in each
phase-change material location. It is known that the current over
time profile of the Set operation can be controlled to produce
electrically distinguishable results, though this can be due to
more than one effect. In the simplest implementation, shorter
anneals--too short to produce full annealing of the amorphous
layer--can be used to produce one or more intermediate states. In
some materials, different crystalline phases can also be produced
by appropriate selection of the current over time profile. However,
what is important for the present application is merely that
electrically distinguishable states can be produced.
[0032] For example, if the complete layer of phase-change material
can have four possible I/V characteristics, two bits of information
can be stored in each cell--IF the read cycle can accurately
distinguish among the four different states.
[0033] (The I/V characteristics of the cells which are not in the
fully Set state are typically nonlinear, so it is more accurate to
distinguish the states in terms of current flow at a given voltage;
resistance is often used as a shorthand term, but implies a
linearity which may not be present.)
[0034] In order to make use of the possible multibit cell
structures, it is necessary to reliably distinguish among the
possible states. To make this distinction reliably, there must be
some margin of safety, despite the change in characteristics which
may occur due to history, manufacturing tolerances, and
environmental factors. Thus the read architecture of multibit PCMs
is a far more difficult challenge it is for PCMs with single-bit
cells.
SUMMARY
[0035] The present application discloses surprising new approaches
to systems in which multi-bit PCM is used, as well as methods for
operating such systems. One example of systems using multi-bit PCM
is memory incorporating multi-bit PCM. At power-up, test reads of
multi-bit PCM memory elements with known states are used to
determine whether instantaneous supply voltage levels permit
multi-bit PCM to be reliably read.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The disclosed inventions will be described with reference to
the accompanying drawings, which show important sample embodiments
and which are incorporated in the specification hereof by
reference, wherein:
[0037] FIG. 1 schematically shows a multi-bit PCM memory
system.
[0038] FIG. 2A shows an example of a PCM element.
[0039] FIG. 2B shows an example of PCM bit line signals.
[0040] FIG. 2C shows an example of voltage versus current in a PCM
material.
[0041] FIG. 2D shows an example of temperature versus resistance in
a PCM material.
[0042] FIG. 2E shows an example of a PCM cell.
[0043] FIG. 2F shows an example of a PCM cell.
[0044] FIG. 2G shows an example of resistance over time for a PCM
cell.
[0045] FIG. 2H shows an example of a processing system.
[0046] FIG. 2I shows an example of a PCM single ended sensing
memory.
[0047] FIG. 2J shows an example of a known PCM single ended sense
amplifier.
[0048] FIG. 3 shows an example of loading information from PCRAM
into volatile memory.
[0049] FIG. 4A shows an example of a voltage-time curve during
power-up.
[0050] FIG. 4B shows an example of a voltage-time curve during
power-up.
[0051] FIG. 5 shows an example of a multi-bit PCM voltage
qualification unit.
[0052] FIG. 6A schematically shows a multi-bit PCM differential
sensing memory system.
[0053] FIG. 6B schematically shows an example of multi-bit PCM
differential sensing.
[0054] FIG. 6C shows an example of a multi-bit sense amplifier.
[0055] FIG. 7 shows an example of a tristate differential sense
amplifier.
[0056] FIG. 8 shows an example of a multi-bit PCM voltage
qualification unit.
[0057] FIG. 9A shows an example of a multi-bit PCM memory
system.
[0058] FIG. 9B shows an example of a processing system.
[0059] FIG. 10 shows an example of multi-bit PCM memory
power-up.
[0060] FIG. 11 shows an example of processing system power-up.
[0061] FIG. 12 shows an example of a processing system.
[0062] FIG. 13 shows an example of a processing system.
[0063] FIG. 14 shows an example of a sense amplifier.
DETAILED DESCRIPTION OF SAMPLE EMBODIMENTS
[0064] The numerous innovative teachings of the present application
will be described with particular reference to presently preferred
embodiments (by way of example, and not of limitation). The present
application describes several inventions, and none of the
statements below should be taken as limiting the claims
generally.
[0065] Multi-bit PCM can be used to make high-density non-volatile
RAM memory (multi-bit PCRAM) in a variety of interfaces. It is
advantageous to use multi-bit PCM as non-volatile redundancy memory
for multi-bit PCRAM to store redundancy information to route around
multi-bit PCRAM manufacturing defects; or as non-volatile repair
memory to store repair, test, trim or configuration information to
tune multi-bit PCRAM and other component (e.g., processor,
input/output controller or power controller) behavior in a design,
test, or as-manufactured context.
[0066] To increase performance when accessing multi-bit PCRAM, it
is further advantageous to transfer the (for example) redundancy
information to a volatile memory for comparisons to determine
whether a redundant element is required for a given memory
address.
[0067] Since multi-bit PCM is a very promising nonvolatile memory
technology, one might consider storing startup information (e.g.,
redundancy or configuration information) in multi-bit PCM memory
which will be used when a memory array comprising multi-bit PCM or
other memory comes into operation after a complete or partial
power-down. However, the present inventor has realized it is
surprisingly difficult to determine at what point during a power-on
process sufficient voltage is available to perform reliable reads
on multi-bit PCM memory cells; and there are other surprising
difficulties to implementation of multi-bit PCM. Typical power-on
detect circuitry generally measures whether basic logic is
functional by measuring the thresholds of devices used in the
logic. Power-on detect for multi-bit PCM is significantly more
complex, because multi-bit PCM sense/compare circuitry determines
the particular voltage (or current) output as the result of an
activated multi-bit PCM cell and compares that output to signal
levels corresponding to multi-bit PCM bit states. Put another way,
typical power-on detect only has to make an on/off determination
corresponding to device thresholds; multi-bit PCM power-on detect
has to make an analog determination of signal levels.
[0068] The present application discloses implementations for
multi-bit PCM memories which accelerate the start of multi-bit PCM
operation, e.g., from the start of a power-on sequence, to be
exactly as fast as possible. To capture the first moment when the
behavior of multi-bit PCM cells permit accurate read operations,
the present inventor has developed a configuration which not only
discriminates valid read operations, but also tracks temperature
dependence and processing variations in the multi-bit PCM cells
themselves.
[0069] To determine whether the supplied voltage can generate
proper operating voltages to drive read operations, one or more
memory elements with known resistances are activated and test
voltages are applied to, e.g., voltage qualification test cells and
corresponding sense amplifiers. The resulting cell outputs are used
to determine corresponding logical states, substantially similarly
to a typical multi-bit PCM element read, and the results are
compared to expected logical states. If the comparisons indicate
matches, multi-bit PCM reads can proceed. If the comparisons
indicate match failure, then after a delay the test read procedure
repeats.
[0070] By causing multi-bit PCM memory to begin reads earlier in a
power-up process, inventive voltage qualification units can save
total energy expenditure by, for example, (1) shortening the amount
of total time when power to a corresponding memory needs to be on,
because if reads begin sooner, then under certain conditions (e.g.,
when the memory has a finite set of operations, including reads, to
complete before power-down that will keep the memory busy) the
memory can power-down sooner; and (2) shortening the amount of time
that a corresponding memory takes to reply to read requests, thus
potentially reducing the number of wasted cycles (and thus wasted
energy) in units requesting memory reads.
[0071] In some inventive embodiments, a Power On Reset test can be
expected to produce an affirmative result before an inventive
multi-bit PCM voltage qualification unit produces a voltage-valid
result.
[0072] Multi-bit PCM can be used to increase storage density and
data throughput of multi-bit PCM memories. However, the resistance
levels corresponding to bit states in multi-bit PCM are closer
together, and thus more difficult to discriminate, than in
single-bit PCM.
[0073] Generally, PCM materials are subject to resistance "drift";
resistance levels of one or more states change over time. This
means that, long term, outputs corresponding to states may become
confused. For example, lower intermediate states may become
confused with higher intermediate states as a resistance level of
one drifts past an original (pre-drift) resistance level of
another.
[0074] PCM materials also typically experience resistance changes
as a result of temperature changes insufficient to cause state
change. This, too, can cause difficulty in state
discrimination.
[0075] In preferred embodiments, groups of multi-bit PCM cells are
read all at once, by comparison with each other rather than against
a reference voltage, i.e., using differential sensing rather than
single ended sensing; and further, members of the group of cells
are written contemporaneously. As a result, the temperature and
drift histories of the group of cells are linked, so that
comparison of read outputs of the grouped cells can be relied on to
show the proper ordering. For example, if cells A, B and C are
grouped, and A, B and C are written so that resistances are ordered
A>B>C, later reads of this group state can be relied on to
produce outputs corresponding to the resistance ordering
A>B>C.
[0076] Preferably, but not necessarily, the number of cells in a
group is equal to the number of PCM states that such cells can
contain.
[0077] In preferred embodiments using differential sensing, where
multi-bit PCM cells can have n nonvolatile states, groups of cells
contain at least at least n members, with at least one instance of
each state in a group.
[0078] Most preferably, groups contain exactly n members and are
written so that groups do not contain repeat instances of states.
For example, for groups of four cells that can each have any of
four states "1", "2", "3" and "4", group state "2314" is allowed,
but group state "2334" is not; and for groups of three cells that
can each have any of three states "1", "2", and "3", the allowed
group states are "012", "021", "102", "120", "201" and "210".
[0079] Multi-bit voltage qualification is used with, generally,
three or more states per cell. When differential sensing is used,
then generally, groups of cells have three or more members.
[0080] FIG. 1 shows an example of a multi-bit PCM voltage
qualification unit 10. In a preferred embodiment, the voltage
qualification unit 10 is configured to cause repair information 20
stored in non-volatile multi-bit PCM to begin loading into a
volatile memory 30--here, SRAM (though other volatile memory
technologies can also be used)--once the voltage qualification unit
10 detects a valid multi-bit PCM read voltage. By using multi-bit
PCM cells to qualify potential read voltages, inventive embodiments
determine whether read outputs of multi-bit PCM test cells 40 in
the voltage qualification test unit 10--for example, three-state
PCM test cells 40 with high, middle and low resistance states
corresponding to "0", "1" and "2" logical states--produce valid
logical states at sense amplifiers 60, and that those valid logical
states match expected logical states when compared at a compare
block 70. Matches are reported 80 (READ_VALID) to a controller 90.
Once sufficient match results have been reported 80 to the
controller 90 (e.g., a long enough streak or other statistical
indicator of high probability of reliably valid reads), the
controller 90 sends a signal 100 (EN_SAMPLE) to cause repair
information 20 to begin loading into volatile memory 30.
[0081] Sense amplifiers 60 are advantageously on the same datapaths
as those used by multi-bit PCM cells storing repair information 20,
so that test cell 40 read behavior is matched to expected read
behavior of the multi-bit PCM cells storing repair information 20
(or other data-storage cells within corresponding multi-bit PCM
memories). Matched behaviors can include multi-bit PCM cell
responses to temperature changes and responses to variable (e.g.,
erroneous) voltage inputs.
[0082] Repair information, often called test modes (though
generally not limited to test configurations), is configuration
information and can be, for example, redundancy, trim, test or
other configuration information. Redundancy information is
generally used to redirect accesses (read and write requests) from
defective or otherwise inoperative memory cells to redundant
(backup) memory cells. Trim information is generally used to alter
the state of an existing topology when device features
as-manufactured show variation--which can be expected within some
degree of statistical distribution--that can be corrected using
measures built into the device. Typically, trim information is
determined on a per device (e.g., per chip) basis, and is not
accessible to users. Trim can be used to correct, for example,
variations in voltage supply outputs or sense amplifier thresholds.
Test information can be used to implement test functions, e.g., for
device design, design testing or as-manufactured quality assurance
purposes. Configuration information can be used, for example, to
change timing (e.g., sense amp timing, or setup and hold timing in
a data path), internal supply voltages, whether ECC (error
correction) or other memory or other component functionality is
activated, or other device operation parameters.
[0083] In some embodiments, as shown in FIG. 1, one or more groups
of multi-bit PCM test cells 40 storing at least one of each
possible logical state are accessed by one or more wordlines 110
and bitlines 120, and resulting outputs are analyzed at
corresponding sense amplifiers 60 (SENSE AMP/DATAPATH). Sense
amplifier outputs are then compared 70 to known resistance values
(COMPARE), generally hard-coded resistances, generally using logic
gates (e.g., ANDs and NORs for 1s and 0s, respectively) to make
sure the test cells were properly read. If successful reads of the
test cells occurred, then volatile memory 30 (SRAM) is caused to
begin loading repair information 20, e.g., using an enable sample
signal 100 (EN_SAMPLE) sent by a controller 90 (Controller) after
it receives a valid read signal 80 (READ_VALID) indicating said
successful reads. It is generally advantageous to use multiple
pairs of test cells demonstrating successful reads across multiple
test read cycles to avoid false positives.
[0084] To save chip area, it is advantageous for test cells 40 to
share sense amplifiers 60 with multi-bit PCM cells used for other
purposes, e.g., data-storing PCM cells and PCM cells containing
non-volatile repair information 20. Test cells 40 can be located in
an extended address space, hidden from users.
[0085] FIG. 3 shows an example of loading information from
multi-bit PCRAM into volatile memory. A multi-bit PCM cell 300 is
activated by a corresponding wordline 110 (WL) and bitline 120
(sense line), and the resulting voltage is detected by a sense
amplifier 310 (Sense Amp/Datapath). The bit output by the sense
amplifier 310 is then loaded into volatile memory 30, e.g.,
SRAM.
[0086] Performing this transfer (which requires multi-bit PCM
reads) during power-up, as early in the power-up process as
possible--preferably before the minimum complete power-up time has
elapsed--can save both time and power. FIG. 4A shows an example of
a voltage-time curve showing voltage in a memory during power-up.
Voltage 400 (Vcc) starts low at the beginning of power-up 410,
rises over time 420, and then levels off when a target stable
voltage level is substantially fully achieved 430.
[0087] However, as explained, finding the earliest possible time
during power-up when multi-bit PCM reads can reliably be performed
is complex and difficult, and can be made more difficult when
system specifications do not provide a reset command or allow
extremely slow skew rates of the external power supply. FIG. 4b
shows an example of a voltage-time curve during power-up of a power
supply with a slow skew rate, along with an example of a power-on
detect interval 440 (tinit) when an voltage qualification unit can
usefully attempt to detect an adequate voltage for memory
operations that is lower than and achieved prior to a target stable
voltage 430.
[0088] Inventive embodiments incorporate voltage qualification
units that detect whether a sense path corresponding to a multi-bit
PCM cell is operational, that is, whether reads on memory cells
containing multi-bit PCM elements along the sense path reliably
produce voltage ranges corresponding to multi-bit PCM bit
states.
[0089] FIGS. 5 and 8 show examples of a PCM voltage qualification
unit 10. Following Power-Up 600, multi-bit PCM test cells with
preset test resistances 40 are activated 610 by a wordline 110 (WL)
(or respective wordlines) and respective bitlines 120. The
resulting read outputs are detected 620 by respective sense
amplifiers 60 (Sense Amp/Datapath). The sense amplifier 60 outputs
are compared to logical states (essentially, to resistances or read
outputs corresponding to resistances) corresponding to the
resistances of the multi-bit PCM test cells by respective compare
stages 70, and the results are reviewed 630 by a Read Valid stage
500 (which can be considered to have been incorporated into some
embodiments as shown in FIG. 1), e.g., using one or more logic
gates. If the multi-bit PCM cells were correctly read by the input
voltage 640, as determined by the sense amplifiers and compare
stages, then the voltage qualification is successful and multi-bit
PCM reads can begin 650. Otherwise 660, after a delay 670, the
voltage qualification test is repeated 680.
[0090] FIG. 6A schematically shows an example of multi-bit PCM
differential sensing, particularly the three cells per group, three
states per cell case. For cells Cell0, Cell1 and Cell2 with
respective output currents I_Cell0 1300, I_Cell1 1310 and I_Cell2
1320, differential comparison blocks 1330 perform pair-wise
comparisons of the output currents 1300, 1310, 1320 and output
results Bit0 1340, Bit1 1350 and Bit2 1360 depending on which
compared pair is currents is greater--one member being greater
results in a pull-up to a voltage source value, and the other
member being greater results in a pull-down to ground.
[0091] FIG. 6B schematically shows multi-bit PCM voltage
qualification using differential sensing. Differential sense
amplifiers for multi-bit PCM architecture can be analog in nature.
The figure shows an example of the three cells per group, three
states per cell case. As shown, cell resistances for selected
cell.sub.--0 1370, cell.sub.--1 1380 and cell.sub.--2 1390 in a
co-addressed group 1410 can be converted into respective currents
Icell0 1300, Icell1 1310 and Icell2 1320, and then the currents can
be mirrored by current mirrors (to allow multiple comparisons using
undivided currents) and compared to each other. Output bits Bit0
1340, Bit1 1350 and Bit2 1360 resulting from these comparisons can
then be reviewed by a Read Valid 1400 block to determine whether
the differential sense amplifier outputs reflect the appropriate
inequality relationships between respective logical states of group
member cells; if so, Read Valid indicates a successful read
attempt; if not, Read Valid indicates a failed read attempt.
[0092] FIG. 6C shows an example of a multi-bit sense amplifier.
This multi-bit PCM differential sense amplifier handles three cell
groups with three states per cell.
[0093] Input X from bitline decoder BLD.sub.X enters nFET 1. nFET 1
is configured as a source follower; given the Bias applied to the
gate of nFET 1, nFET 1 source is fixed at a particular voltage so
that the drain has a current output I.sub.X. Put differently, nFET
1 forces a voltage on the bitline selected in bitline decoder
BLD.sub.X and transforms the bitline output into a current output.
pFET 2 is diode connected, i.e., the drain and gate are connected
together and to the output of nFET 1, i.e., I.sub.X. pFET 2 and
pFET 3 (the sources of which are connected to a voltage source,
e.g., V.sub.dd) are matched to form a current mirror with ratio
1:1, and together they mirror the source follower output current
I.sub.X from the drain of pFET 3 to the drain and gate of diode
connected nFET 4 and the gates of nFETs 5 and 6. nFETs 4, 5 and 6
are matched, and current mirror I.sub.X to nFET 5 and 6 outputs
OutA and OutC.
[0094] Input Y from bitline decoder BLD.sub.Y enters nFET 7. nFET 7
is configured as a source follower with gate input Bias. nFET 7
current output T.sub.Y is input to the gate and drain of diode
connected pFET 8 and to the gates of pFETs 9 and 10 (sources of
pFETS 8, 9 and 10 are connected to a voltage source, e.g.,
V.sub.dd). pFETs 8, 9 and 10 are matched, and current mirror
I.sub.Y to pFET 9 and 10 outputs OutB and OutC.
[0095] Input Z from bitline decoder BLD.sub.Z enters nFET 11. nFET
11 is configured as a source follower with gate input Bias. nFET 7
current output I.sub.Z is input to the gate and drain of diode
connected pFET 12 and to the gates of pFETs 13 and 14 (sources of
pFETS 12, 13 and 14 are connected to a voltage source, e.g.,
V.sub.dd). pFETs 12, 13 and 14 are matched, and current mirror
I.sub.Z to pFET 13 output OutA and to nFET 15 gate and drain (nFET
15 is diode connected) and nFET 16 gate. nFET 15 and 16 sources are
connected to ground. I.sub.Z is current mirrored to nFET 16 output
OutB.
[0096] OutA equals I.sub.X+I.sub.Z; OutB equals I.sub.Y+I.sub.Z;
and OutC equals I.sub.X+I.sub.Y. Depending on which of each pair of
currents comprising, respectively, OutA, OutB, and OutC is greater,
the voltages of OutA, OutB and OutC will be driven to the supply
voltage (e.g, V.sub.dd) or to ground, depending on which of supply
or ground the source of the respective outputting transistor was
connected to (nFETs 5 and 6, I.sub.X, to ground, pFETs 9 and 10,
I.sub.Y, to source, pFET 13, I.sub.Z, to source, and nFET 16,
I.sub.Z, to ground).
[0097] FIG. 7 shows an example of a tristate differential sense
amplifier. Tristate differential sense amplification can be used to
recover additional information states in multi-bit PCM memories
using differential sense amplification. It is useful to match
voltage qualification testing to memory configuration in order to
improve voltage qualification accuracy.
[0098] Continuing with two cell groups, two states per cell, a
typical differential comparison is performed to obtain BIT0 1500. A
1510 and B 1520 are obtained by multiplying one of each pair of
compared cell output currents I_Cell0 1530 and I_Cell1 1540 by a
specified proportion (e.g., 20% to 50%, creating I_Cell0*(20% to
50%) 1550 and I_Cell1*(20% to 50%) 1560). The specified proportion
is preferably chosen to avoid overlap between possible states. A
1510 and B 1520 are compared by comparison logic 1570; if A 1510 is
low and B 1520 is high, the two cells are the same value, and BIT1
1580 is a "Don't Care" (the value of BIT0 1500 is discarded as
undetermined). In the two cell group, two states per cell case, use
of tristate differential amplifiers can recover at least one
additional information state (i.e., the state where the two
compared cells have the same phase state). Generally, a tristate
differential sense amplifier will not be able to tell by itself
which possible state two cells with identical states have been
written to.
[0099] FIG. 9A shows an example of a multi-bit PCM randomly
accessible memory chip 700, which incorporates an array of
multi-bit PCM cells 702 to store instructions and/or data for the
system(s) into which the memory system is incorporated; memory
addressing logic 704 with which to access specified cells in the
memory array using wordlines 706 and bitlines 708 (row and column
lines); multi-bit PCM redundancy memory 710 to store redundancy
information regarding which memory array cells are defective and
where calls made to defective cells should be redirected to;
redundancy logic 712 to control loading of redundancy information
into addressing registers; and a voltage qualification unit 714 to
determine, on power-up, when sufficient voltage is available to
perform multi-bit PCM functions. The memory chip can also contain
volatile memory, such as SRAM, into which redundancy information is
loaded for the purpose of performing fast compares between
defective memory addresses and requested memory locations.
[0100] FIG. 9B shows an example of a processing system 750
incorporating a multi-bit PCM randomly accessible memory 700. The
processing system 750 comprises at least one processor 752, power
controller 754 connected to manage power from a power source 756,
input/output controllers and devices 758 (I/O), and memory 700. The
I/O 758 is connected to manage interaction with external devices
760. In the memory 700, data operations requested by the processor
752, power controller 754 or I/O 758 are executed using address
logic 704 to select corresponding memory cells within multi-bit PCM
memory 702. On power-up, a voltage qualification test unit 714
determines when sufficient voltage is available to perform
multi-bit PCM functions; when sufficient voltage is available,
multi-bit PCM redundancy/repair load logic 712 is caused to begin
loading repair information from multi-bit PCM redundancy/repair
storage 710 (which is configured to store repair information, such
as redundancy information) into address logic 704 so that the
access logic 704 can properly access the multi-bit PCM memory 700,
e.g., by redirecting accesses from defective multi-bit PCM cells to
redundant multi-bit PCM cells.
[0101] FIG. 10 shows an example of multi-bit PCM memory power-up.
After power-up 800, a voltage qualification unit begins repeated
testing 810 to determine whether sufficient voltage is available
for reliable multi-bit PCM reads 820. If sufficient voltage is not
available 830, then after a delay 840 the test 810 is repeated.
Once the voltage qualification unit determines that reliable
multi-bit PCM reads are available 850, it causes a multi-bit PCM
redundancy memory to begin loading repair (e.g., redundancy)
information into volatile memory 860. Once repair information is
loaded and other startup conditions are satisfied, the PCM array
can begin performing memory functions 870.
[0102] FIG. 11 shows an example of processing system power-up.
After power-up 900, a processor requests instructions and/or data
stored in a multi-bit PCM array 910. The processor request stalls
920 until a voltage qualification unit has determined 930 that
sufficient voltage is available for reliable multi-bit PCM reads
940; repair (e.g., redundancy) information is determined 950 to
have been loaded into volatile memory 960; and the multi-bit PCM
array is determined to have begun performing memory functions 970.
Once these conditions have been met, addressing logic causes the
multi-bit PCM array to respond to the processor request 990.
[0103] FIG. 12 shows an example of a processing system 1000. After
power-on, multi-bit PCM voltage qualification 1010 determines
whether sufficient voltage is available for reliable reads. Once
such voltage is available, a multi-bit PCM unit 1020 loads repair
information (e.g., configuration information or a machine execution
state from a previous power-down event) into volatile memory in
cache addressing logic 1030 or into volatile memory cache 1040
(e.g., as an initial cache state on startup). The cache addressing
logic 1030 controls volatile cache 1040 to respond to cache memory
requests from processing logic 1050. Processor configuration
information can include, for example, any processor operation
parameters amenable to adjustment at runtime.
[0104] An I/O controller can also be configured as shown in FIG.
10. An I/O controller is generally equivalent to a specialized
processor, with I/O control logic corresponding to processing
logic.
[0105] FIG. 13 shows an example of a processing system 1100. After
power-up, multi-bit PCM voltage qualification 1110 determines
whether sufficient voltage is available for reliable reads. Once
such voltage is available, a multi-bit PCM unit 1120 loads initial
state information into volatile memory registers 1130 connected to
processing logic 1140. The contents of the multi-bit PCM unit 1120
can be changed by the processing logic 1140 to reflect a new
initial state for a later power-up event. Initial state information
can be, for example, static, user-configurable (e.g., from a BIOS),
or comprise a prior machine execution state such as the contents of
registers and other memory at power-down.
[0106] FIG. 14 shows an example of a sense amplifier 1200 in a
memory. Sense amplifiers 1200 generally use a reference value 1210
(typically a current) to distinguish between logic states
potentially stored in a corresponding memory element and
represented by a read output of that element. Here, an Offset
Reference 1220--a fine trim used to fine-tune a reference, and
unsuitable for use by itself as a reference--appears as an
additional input to the Sense Amplifier 1200, where it will be used
to modify a reference 1210 prior to comparison between the memory
cell read output 1230 and the reference 1210.
[0107] The disclosed innovations, in various embodiments, provide
one or more of at least the following advantages. However, not all
of these advantages result from every one of the innovations
disclosed, and this list of advantages does not limit the various
claimed inventions. [0108] More agile transitions between
power-down and power-up modes; [0109] systems can make more
frequent transitions between power-down and power-up modes; [0110]
shorter total power-up duration for multi-bit PCM memory reads;
[0111] less total energy usage for multi-bit PCM memory reads;
[0112] less total energy usage by systems incorporating multi-bit
PCM memory; [0113] improved multi-bit PCM memory read reliability;
[0114] faster multi-bit PCM memory, including lower average memory
latency; [0115] less multi-bit PCM memory power usage; [0116]
devices incorporating multi-bit PCM memory are faster; and [0117]
devices incorporating multi-bit PCM memory use less power, and
therefore can operate longer and/or with a smaller power supply;
[0118] devices incorporating multi-bit PCM memory perform
operations that require periodic interruption of power conservation
modes more quickly and with less power usage; and [0119] fast
startup state loading of various parameters. [0120] increased
multi-bit PCM element resistance drift tolerance; [0121] increased
multi-bit PCM element temperature change tolerance on reads; [0122]
increased multi-bit PCM read signal margin, i.e. a greater ability
to discriminate between different multi-bit PCM resistance states;
[0123] increased memory/area quotient; [0124] substantially perfect
temperature and resistance drift tracking across co-addressed
groups of multi-bit PCM cells; and [0125] more reliable multi-bit
PCM memory reads.
[0126] According to some but not necessarily all embodiments, there
is provided: A memory comprising: at least one array of multi-bit
phase change memory cells; redundancy logic which redirects
attempted accesses from defective memory elements in said array to
redundant memory elements, in dependence on a table of defective
memory locations residing in multi-bit phase change memory when
power to the memory is OFF; and a voltage qualification unit
configured to test whether reads of a plurality of multi-bit phase
change memory reference cells produce different outputs
corresponding to the at least three different logic states stored
in said reference cells, and to allow said redundancy logic to
begin redirecting accesses only after said outputs correspond to
said logic states, wherein said test uses a read voltage generated
using said power to the memory.
[0127] According to some but not necessarily all embodiments, there
is provided: A memory connectable to be powered from a supply
voltage, comprising: at least one redundancy data storage
comprising a plurality of multi-bit phase change memory cells; at
least one array of multi-bit phase change memory cells; at least
one access logic controlling access to said array and operating in
at least partial dependence on redundancy data stored in said
redundancy data storage; and a voltage qualification unit
configured to detect whether the supply voltage causes reads of a
plurality of multi-bit reference phase change memory cells to
produce correctly distinct outputs corresponding to at least three
different logic states stored in said reference cells, wherein said
redundancy data storage is operatively connected to enable said
access logic only after said voltage qualification unit has
detected said correctly distinct outputs.
[0128] According to some but not necessarily all embodiments, there
is provided: A memory comprising: at least one multi-bit phase
change memory array; a test logic configured to read/write test
memory elements in said array, and to write redundancy information
corresponding to defective memory elements that fail said
read/write testing to a table of defective memory locations, said
table residing in multi-bit phase change memory when power is OFF;
a voltage qualification unit configured to test whether reads of
multiple multi-bit phase change memory reference cells produce
different outputs corresponding to the at least three different
logic states stored in said reference cells, and to allow a
redundancy logic to begin redirecting accesses from said defective
memory elements to redundant multi-bit phase change memory
elements, in dependence on said table, only after said outputs
correspond to said logic states, wherein said test uses a voltage
generated using said power to the memory.
[0129] According to some but not necessarily all embodiments, there
is provided: A processing system comprising: one or more memory
units, one or more processors which execute programmable
instruction sequences, and one or more input/output units; repair
logic which applies one or more activation voltage variances to
adjust feature activation voltages in at least one of said memory
units, said processors and said input/output units, said activation
voltage variances being at least partially specified by values
residing in a multi-bit phase change memory when power to the
memory is OFF; and a voltage qualification unit configured to test
whether reads of a plurality of reference phase change memory cells
produce different outputs corresponding to the at least three
different logic states stored in said reference cells, and to allow
said repair logic to begin adjusting feature activation voltages
only after said outputs correspond to said logic states, wherein
said test uses a voltage generated using said power to the
memory.
[0130] According to some but not necessarily all embodiments, there
is provided: A processing system comprising: a phase change memory
unit, a processor which executes programmable instruction
sequences, an input/output unit, and configuration logic which
loads configuration information from said multi-bit phase change
memory when power is turned on; a voltage qualification unit
configured to test whether reads of a plurality of multi-bit phase
change memory reference cells of said multi-bit phase change memory
unit, after power is turned on, produce correctly distinct outputs
corresponding to the at least three different logic states stored
in said reference cells; wherein said configuration logic begins
loading the configuration information only if said voltage
qualification unit confirms said reads produce said correctly
distinct outputs, and wherein said processor and/or said
input/output unit operate external elements in accordance with said
configuration data.
[0131] According to some but not necessarily all embodiments, there
is provided: A method of accessing a memory comprising: redirecting
attempted accesses from defective memory elements in an array of
phase change memory cells to redundant memory elements using a
redundancy logic, said redirecting in dependence on a table of
defective memory locations residing in multi-bit phase change
memory when power to the memory is OFF; and testing, using a
voltage qualification unit, whether reads of a plurality of
multi-bit phase change memory reference cells produce different
outputs corresponding to the different logic states stored in said
reference cells; and allowing said redundancy logic to begin
redirecting accesses only after said outputs correspond to said
logic states, wherein said testing uses a read voltage generated
using said power to the memory.
[0132] According to some but not necessarily all embodiments, there
is provided: A method of accessing a memory comprising: read/write
testing memory elements in at least one phase change memory array;
writing redundancy information corresponding to defective memory
elements that fail said read/write testing to a table of defective
memory locations, said table residing in multi-bit phase change
memory when power to the memory is OFF; testing whether an input
voltage generated using power to the memory causes different read
outputs of multiple multi-bit phase change memory reference cells
to correspond to at least three different logic states stored in
said reference cells; and allowing a redundancy logic to begin
redirecting accesses from said defective memory elements to
redundant phase change memory elements in dependence on said table,
only after said read outputs correspond to said logic states.
[0133] According to some but not necessarily all embodiments, there
is provided: A method of operating a processing system comprising:
applying one or more activation voltage variances, using a repair
logic, to adjust feature activation voltages in at least one of one
or more memory units, one or more processors which execute
programmable sequence instructions and one or more input/output
units, said activation voltage variances being at least partially
specified by values residing in a multi-bit phase change memory
when power to the memory is OFF; and testing whether an input
voltage generated using said power to the memory causes one or more
multi-bit phase change memory outputs to correspond to at least
three logic states stored in corresponding phase change memory
cells; and allowing said repair logic to begin adjusting said
feature activation voltages only after said outputs correspond to
said logic states.
[0134] According to some but not necessarily all embodiments, there
is provided: Systems in which multi-bit PCM is used, including
memory systems, as well as methods for operating such systems. A
test of multi-bit PCM memory elements with known states can be used
to determine whether immediately available voltage levels can
reliably read multi-bit PCM. This can be used to accelerate
availability of memory states residing in multi-bit PCM with
respect to, for example, redundancy address storage, other startup
state information, and parameters for which nonvolatile storage is
useful.
Modifications and Variations
[0135] As will be recognized by those skilled in the art, the
innovative concepts described in the present application can be
modified and varied over a tremendous range of applications, and
accordingly the scope of patented subject matter is not limited by
any of the specific exemplary teachings given. It is intended to
embrace all such alternatives, modifications and variations that
fall within the spirit and broad scope of the appended claims.
[0136] Embodiments described herein have been disclosed with
respect to three- and four-state PCM materials. However, in some
embodiments, PCM materials with larger numbers of states (e.g.,
five) may also be used.
[0137] In some embodiments, outputs from physical cells within
groups of cells are not compared pairwise. For example, pairs of
outputs may be added together and the sums compared.
[0138] In some embodiments, more than one physical cell within a
group of cells is allowed to have a given state. In such
embodiments, differential sense amplifiers may use, for example,
tri-state logic so that the output equality case can be
represented.
[0139] In some embodiments, a group of cells may contain a
different number of multi-bit PCM cells than the corresponding
multi-bit PCM material has nonvolatile states.
[0140] In some embodiments, output values other than current may be
compared, e.g., voltage.
[0141] In some embodiments, cells within a group may be accessed
substantially simultaneously when said group is accessed.
[0142] In some embodiments, cells within a group may be accessed at
different times when said group is accessed.
[0143] In some embodiments, cells can be switched from differential
sense amplification to single ended sense amplification and
back.
[0144] In some embodiments, divided (unmirrored) currents are
compared.
[0145] In some embodiments, fewer than all possible states of
corresponding multi-bit PCM cells can be used.
[0146] In some embodiments, contents of groups can be rearranged so
that groups are comprised of different sets of cells from prior to
being rearranged.
[0147] In some embodiments, duplicate instances of a state can be
stored within a group of cells.
[0148] In some embodiments, a voltage qualification test could use
differential sensing for some bitlines, and single ended sensing
for other bitlines.
[0149] In some embodiments, a memory could use a lower signal
margin to obtain higher storage density at the expense of longer
sense and/or write times. In other embodiments, a memory could use
a higher single margin to obtain higher sense and/or write times at
the expense of lower storage density.
[0150] In some embodiments, multi-bit PCM is used in contexts in
which embedded DRAM is typically used.
[0151] In some embodiments, multi-bit PCM is used for CPU on-chip
memory.
[0152] In some embodiments, multi-bit PCM is used in on-chip memory
contexts where field-programmable gate array (FPGA) memory is
typically used.
[0153] In some embodiments, multi-bit PCM may be used to load a
startup state into device registers, e.g., CPU registers.
[0154] In some embodiments, multi-bit PCM may be used with multiple
other memory types on a single chip.
[0155] In some embodiments, more than one cell storing a particular
logical state can be used in the multi-bit PCM cells in the voltage
qualification unit.
[0156] In some embodiments, information is stored in multi-bit PCM
cells for startup procedures other than defective memory
repair.
[0157] In some embodiments, multiple valid reads are required by
some or all of the cells within the voltage qualification unit,
across multiple test cycles, before a usable read voltage is
determined to be available.
[0158] In some embodiments using multiple multi-bit PCM cells
storing ones of possible logical states in a voltage qualification
unit, at least one of said cells within the voltage qualification
unit is not rewritten, either (1) for an extended period of time or
(2) ever.
[0159] In some embodiments using multiple multi-bit PCM cells
storing ones of possible logical states in a voltage qualification
unit, at least one of said cells within the voltage qualification
unit is rewritten at random intervals when a corresponding memory's
power is on.
[0160] In some embodiments, multi-bit phase change memory cells can
contain multiple multi-bit phase change memory elements, ones of
said memory elements having separate readable states.
[0161] In some embodiments, multi-bit SET and RESET pulses reset
multi-bit PCM cell drift characteristics of both "0" and "1"
logical states, i.e., without requiring a logical state
transposition to reset cell drift characteristics.
[0162] In some embodiments, outputs of groups of multi-bit PCM
cells storing all possible logical states of a multi-bit PCM are
compared to each other, e.g., using a logic gate, after having been
read by a sense amplifier.
[0163] In some embodiments, multi-bit PCM test cells storing all
possible logical states of a multi-bit PCM are not grouped
physically or by address.
[0164] In some embodiments, different numbers of multi-bit PCM test
cells store different logical states.
[0165] In some embodiments using multiple multi-bit PCM cells
storing ones of possible logical states in a voltage qualification
unit, multi-bit PCM cells within the voltage qualification unit are
rewritten to store different logical states when certain conditions
are met, e.g., after a certain number of reads or writes, after a
certain amount of time, after a certain amount of time when a
corresponding memory's power is on, after a certain number of
voltage qualification tests, after a certain number of
voltage-valid voltage qualification test results, or after every
power-on. In some of these embodiments, different cells or groups
of cells may have different criteria to trigger a rewrite.
[0166] None of the description in the present application should be
read as implying that any particular element, step, or function is
an essential element which must be included in the claim scope: THE
SCOPE OF PATENTED SUBJECT MATTER IS DEFINED ONLY BY THE ALLOWED
CLAIMS. Moreover, none of these claims are intended to invoke
paragraph six of 35 USC section 112 unless the exact words "means
for" are followed by a participle.
[0167] Additional general background, which helps to show
variations and implementations, may be found in the following
publications, all of which are hereby incorporated by reference:
Lam, Chung. "Phase Change Memory: A Replacement or Transformational
Memory Technology," IEEE Workshop on Microelectronics and Electron
Devices (WMED), c. 2011. Choi, Youngdon, et al. "A 20 nm 1.8V 8 Gb
PRAM with 40 MB/s Program Bandwidth." ISSCC 2012/Session 2/High
Bandwidth DRAM & PRAM/2.5. c. 2012. U.S. Pat. No. 8,259,490 for
"Multi-level Phase-Change Memory Device and Method of Operating
Same". U.S. Pat. No. 8,238,147 for "Multi-Level Phase Change Memory
Device, Program Method Thereof, and Method and System Including the
Same". Papandreou, N., et al., "Multi-Level Phase Change Memory",
17.sup.th IEEE International Conference on Electronics, Circuits
and Systems (ICECS), 2010, Zurich, Switzerland (Dec. 2010),
1017-1020. Papandreou, N., et al., "Drift-Tolerant Multilevel
Phase-Change Memory", 3.sup.rd IEEE International Memory Workshop
(IMW), 2011, Zurich, Switzerland (May 2011), 1-4.
[0168] Additional general background, which helps to show
variations and implementations, as well as some features which can
be synergistically with the inventions claimed below, may be found
in the following US patent applications. All of these applications
have at least some common ownership, copendency, and inventorship
with the present application, and all of them are hereby
incorporated by reference: U.S. Provisional Pat. Nos. 61/637,331;
61/637,496; 61/637,513; 61/637,518; 61/637,526; 61/637,533;
61/638,217; 61/694,217; 61/694,220; 61/694,221; 61/694,223;
61/694,224; 61/694,225; 61/694,228; 61/694,234; 61/694,240;
61/694,242; 61/694,243; and 61/694,245.
[0169] The claims as filed are intended to be as comprehensive as
possible, and NO subject matter is intentionally relinquished,
dedicated, or abandoned.
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