U.S. patent application number 13/771514 was filed with the patent office on 2013-12-19 for single-crystal reo buffer on amorphous siox.
The applicant listed for this patent is Andrew Clark, Rytis Dargis, Michael Lebby, Robin Smith. Invention is credited to Andrew Clark, Rytis Dargis, Michael Lebby, Robin Smith.
Application Number | 20130334536 13/771514 |
Document ID | / |
Family ID | 47780415 |
Filed Date | 2013-12-19 |
United States Patent
Application |
20130334536 |
Kind Code |
A1 |
Dargis; Rytis ; et
al. |
December 19, 2013 |
SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx
Abstract
A method of forming a layer of amorphous silicon oxide
positioned between a layer of rare earth oxide and a silicon
substrate. The method includes providing a crystalline silicon
substrate and depositing a layer of rare earth metal on the silicon
substrate in an oxygen deficient ambient at a temperature above
approximately 500.degree. C. The rare earth metal forms a layer of
rare earth silicide on the substrate. A first layer of rare earth
oxide is deposited on the layer of rare earth silicide with a
structure and lattice constant substantially similar to the
substrate. The structure is annealed in an oxygen ambience to
transform the layer of rare earth silicide to a layer of amorphous
silicon and an intermediate layer of rare earth oxide between the
substrate and the first layer of rare earth oxide.
Inventors: |
Dargis; Rytis; (Fremont,
CA) ; Clark; Andrew; (Los Altos, CA) ; Smith;
Robin; (Palo Alto, CA) ; Lebby; Michael;
(Apache Junction, AZ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Dargis; Rytis
Clark; Andrew
Smith; Robin
Lebby; Michael |
Fremont
Los Altos
Palo Alto
Apache Junction |
CA
CA
CA
AZ |
US
US
US
US |
|
|
Family ID: |
47780415 |
Appl. No.: |
13/771514 |
Filed: |
February 20, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13495215 |
Jun 13, 2012 |
8394194 |
|
|
13771514 |
|
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Current U.S.
Class: |
257/76 |
Current CPC
Class: |
C30B 25/183 20130101;
C30B 1/02 20130101; H01L 21/0254 20130101; H01L 21/02433 20130101;
C30B 29/22 20130101; H01L 21/02505 20130101; H01L 29/2003 20130101;
H01L 21/02381 20130101; H01L 21/02516 20130101; H01L 21/02488
20130101; C30B 29/403 20130101 |
Class at
Publication: |
257/76 |
International
Class: |
H01L 29/20 20060101
H01L029/20 |
Claims
1-9. (canceled)
10. A III-N on silicon wafer comprising: a crystalline silicon
substrate; a layer of rare earth metal deposited on the silicon
substrate in an oxygen deficient ambient at a temperature above
approximately 500.degree. C., the rare earth metal forming a layer
of rare earth silicide on the substrate, the layer of rare earth
silicide being transformed by annealing into a layer of amorphous
silicon and an intermediate layer of rare earth oxide positioned
between the substrate and the first layer of rare earth oxide; and
a first layer of rare earth oxide deposited on the layer of rare
earth silicide with a structure and lattice constant substantially
similar to the substrate.
11. A III-N on silicon wafer as claimed in claim 10 further
including a second layer of rare earth oxide with a structure and
lattice constant substantially similar to the substrate, the second
layer of rare earth oxide positioned on the first layer of rare
earth oxide to form a template for the subsequent deposition of a
III-N semiconductor material.
12. A III-N on silicon wafer as claimed in claim 11 further
including a layer of III-N semiconductor material positioned on the
second layer of rare earth oxide, the III-N semiconductor material
having a structure and lattice constant substantially similar to
the substrate.
13. A III-N on silicon wafer as claimed in claim 12 wherein the
second layer of rare earth oxide includes gadolinium.
14. A III-N on silicon wafer as claimed in claim 13 wherein the
layer of III-N semiconductor material includes gallium.
Description
FIELD OF THE INVENTION
[0001] This invention relates in general to the formation of
amorphous silicon oxide on silicon wafers between the substrate and
a single-crystal rare earth oxide buffer for the growth of III-N
semiconductor material.
BACKGROUND OF THE INVENTION
[0002] It has been found that III-N materials are a desirable
semiconductor material in many electronic and photonic
applications. As understood in the art, the III-N semiconductor
material must be provided as a crystalline or single-crystal
formation for the most efficient and useful bases for the
fabrication of various electronic and photonic devices therein.
Further, the single-crystal III-N semiconductor material is most
conveniently formed on single-crystal silicon wafers because of the
extensive background and technology developed in the silicon
semiconductor industry. However, the crystal lattice constant
mismatch between silicon and a III-N material, such as GaN, is 17%
if grown c-axis on (111) oriented silicon. Also, the thermal
expansion difference between the III-N material, such as GaN, is
56%. Both of these factors lead to residual stress and consequently
to structural defects and mechanical damage (e.g. cracks) in the
structure.
[0003] A buffer layer between the silicon substrate and the III-N
layer that could absorb stress would help solve the problem.
Several copending patent applications have been filed in the U.S.
in which rare earth oxides were grown on a silicon substrate to
serve as a stress engineered buffer layer for the subsequent growth
of III-N semiconductor material. Two of these copending U.S. patent
applications are: Strain Compensated REO Buffer for III-N on
Silicon, filed 21 Oct. 2011, bearing Ser. No. 13/278,952; and
Nucleation of III-N on REO Templates, filed 20 Mar. 2012, bearing
Ser. No. 61/613,289, both of which are included herein by
reference.
[0004] While the rare earth oxide (REO) stress engineered buffer
layers can reduce stress to a manageable level the stress can be
conveniently reduced or substantially eliminated by including a
layer of amorphous silicon oxide between the silicon substrate and
the rare earth oxide buffer. Silicon oxide is amorphous material
and has low viscosity at temperatures above 500.degree. C. that
results in stress relaxation, critical from the point of view of
thermal stress during cooling down of GaN (III-N material) on
silicon heterostructure. A major problem is that the formation of
the amorphous silicon oxide layer must take place during the growth
of the single-crystal REO buffer because growth of the REO on an
amorphous silicon layer would lead to a polycrystalline REO buffer
which is not suitable for single-crystal III-N growth.
[0005] There are potentially several ways to form the silicon oxide
interface layer all of which have severe drawbacks. In a first
method, an atmosphere of excess oxygen can be provided during the
REO growth. Some problems with this method are that high oxygen
pressure is needed during the process which causes the lifetime of
the MBE components in the chamber to deteriorate and the SiO.sub.x
layer is not thick enough to adequately perform the stress relief.
In a second method, the REO is grown and the structure is
subsequently annealed in oxygen atmosphere. A method of this type
is described in U.S. Pat. No. 7,785,706, entitled "Semiconductor
Wafer and Process for its Production", issued Aug. 31, 2010 and
U.S. Pub. 2010/0221869 of the same title. One problem with this
type of method is that the formation of the interface can be hard
to control, the oxidation needs long time, temperature and/or high
oxygen pressure because oxidation of silicon is diffusion limited
process, which means that oxidation becomes slower with increasing
of thickness of the silicon dioxide layer.
[0006] It would be highly advantageous, therefore, to remedy the
foregoing and other deficiencies inherent in the prior art.
[0007] Accordingly, it is an object of the present invention to
provide new and improved methods of forming a layer of amorphous
silicon between a REO buffer and a silicon substrate.
[0008] It is another object of the present invention to provide new
and improved methods of forming a layer of amorphous silicon
dioxide between a REO buffer and a silicon substrate that is
sufficiently thick to adequately perform stress relief that is easy
and reliable to control.
[0009] It is another object of the present invention to provide a
new and improved III-N semiconductor layer on a silicon substrate
including a layer of amorphous silicon between a REO buffer and the
substrate.
SUMMARY OF THE INVENTION
[0010] Briefly, the desired objects and aspects of the instant
invention are achieved in accordance with a preferred method of
forming a layer of amorphous silicon oxide positioned between a
layer of rare earth oxide and a silicon substrate. The method
includes providing a crystalline silicon substrate and depositing a
layer of rare earth metal on the silicon substrate in an oxygen
deficient ambient at a temperature above approximately 500.degree.
C. The rare earth metal forms a layer of rare earth silicide on the
substrate. A first layer of rare earth oxide is deposited on the
layer of rare earth silicide with a structure and lattice constant
substantially similar to the substrate. The structure is annealed
in an oxygen ambience to transform the layer of rare earth silicide
to a layer of amorphous silicon and an intermediate layer of rare
earth oxide between the substrate and the first layer of rare earth
oxide.
[0011] The desired objects and aspects of the instant invention are
further realized in accordance with a preferred embodiment of a
crystalline silicon substrate including a layer of rare earth metal
deposited on the silicon substrate in an oxygen deficient ambient
at a temperature above approximately 500.degree. C. The rare earth
metal forms a layer of rare earth silicide on the substrate. The
layer of rare earth silicide is transformed by annealing into a
layer of amorphous silicon and an intermediate layer of rare earth
oxide positioned between the substrate and the first layer of rare
earth oxide. A first layer of rare earth oxide is deposited on the
layer of rare earth silicide with a structure and lattice constant
substantially similar to the substrate.
[0012] The preferred embodiment can further include a second layer
of rare earth oxide with a structure and lattice constant
substantially similar to the substrate. The second layer of rare
earth oxide is positioned on the first layer of rare earth oxide to
form a template for the subsequent deposition of a III-N
semiconductor material. The preferred embodiment can further
include a layer of III-N semiconductor material positioned on the
second layer of rare earth oxide. The III-N semiconductor material
has a structure and lattice constant substantially similar to the
substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The foregoing and further and more specific objects and
advantages of the instant invention will become readily apparent to
those skilled in the art from the following detailed description of
a preferred embodiment thereof taken in conjunction with the
drawings, in which:
[0014] FIGS. 1-5 are simplified layer diagrams illustrating several
sequential steps in a process of the formation of amorphous silicon
oxide on silicon wafers between a substrate and a single-crystal
rare earth oxide buffer for the growth of III-N semiconductor
material in accordance with the present invention;
[0015] FIG. 6 illustrates a final step in which a III-N layer of
semiconductor material is grown on a single-crystal rare earth
oxide buffer; and
[0016] FIG. 7 is a pictorial view of a REO layer grown on an
amorphous silicon oxide on a silicon wafer, in accordance with the
present invention.
DETAILED DESCRIPTION OF THE DRAWINGS
[0017] In view of the need for stress relaxation in a process of
forming III-N semiconductor layers on silicon substrates some
effort and study has gone into the formation of an amorphous layer
of silicon oxide (SiO.sub.x) between the silicon substrate and the
III-N layer or layers. However, to date various proposed methods
for the formation of the amorphous layer all have several drawbacks
or problems that substantially reduce the efficiency or
effectiveness of the process and results. Accordingly, a new method
for the formation of an amorphous layer of silicon oxide
(SiO.sub.x) between the silicon substrate and the III-N layer or
layers is herein disclosed. The new method is greatly improved and
results in the formation of an amorphous layer that can be
accurately controlled and which substantially absorbs or reduces
stress between the silicon substrate and the III-N semiconductor
layer.
[0018] Turning now to FIG. 1, a silicon substrate 10 is illustrated
which is, as understood in the art, a single-crystal material
including silicon and may in some applications include other
materials all of which are included in the general term "silicon"
substrate. Also, the substrate may be for example a silicon wafer
or some part thereof and is referred to herein by the general term
"substrate". While silicon substrate 10 is illustrated as having a
<111> crystal orientation, it will be understood, is not
limited to any specific crystal orientation but could include
<111> silicon, <110> silicon, <100> silicon or
any other orientation or variation known and used in the art.
[0019] A very thin layer 12a of rare earth metal is deposited on
the surface of silicon substrate 10. Rare earth metal layer 12a is
grown directly on the surface of substrate 10 using any of the
well-known growth methods, such as MBE, MOCVD, PLD (pulsed laser
deposition), sputtering, ALD (atomic layer deposition), or any
other known growth method for thin films. Throughout this
disclosure whenever rare earth materials are mentioned it will be
understood that "rare earth" materials are generally defined as any
of the lanthanides as well as scandium and yttrium. Metal layer 12a
is grown 1-2 monolayers thick which is about 0.5 nm to about 1.0 nm
thick. The typical growth temperature for the rare earth metal is
above approximately 550.degree. C.
[0020] As illustrated in FIG. 2, rare earth metal layer 12a at the
typical growth temperatures in an oxygen deficient ambience
transforms to silicide (layer 12b) during reaction with silicon
atoms in substrate 10. For convenience of understanding layer 12 is
designated with different letter designations (i.e. a, b, c) to
show the changes that occur. It is important to keep layer 12b very
thin so that the following single-crystal growth steps can be
performed. Thin silicide layer 12b is epitaxially stabilized to
silicon substrate 10 so that the crystalline structure is similar
to silicon and has a similar lattice constant. As an example, some
gadolinium silicides have a very close structure with silicon. By
starting growth of metal layer 12a with a lower oxygen pressure
(oxide deficient condition) initial oxidation of the silicide is
prevented which leads to the formation of a thicker silicide layer
12b.
[0021] Referring to FIG. 3, it will be understood that for
convenience and efficiency of procedure the growth process from
FIG. 2 is continued (i.e. in situ). In the step illustrated in FIG.
3, oxygen is introduced into the process and growth of a
single-crystal rare earth oxide (REO) layer 14 is accomplished.
Because silicide layer 12b is very thin REO layer 14 has the atom
stacking sequence from the silicon substrate, that is REO layer 14
and substrate 10 have a similar crystalline structure and a similar
lattice constant. REO layer 14 is grown with a thickness from
several nanometers (3 nm or less) to 10 nm or more, depending on
the subsequent annealing time. Primarily, REO layer 14 is grown
thin enough to promote oxygen diffusion through layer 14.
[0022] Referring to FIG. 4, after the growth of REO layer 14 the
structure is annealed preferably at approximately 900.degree. C. in
an oxygen ambience for oxide diffusion to the interface between
silicide layer 12b and REO layer 14. Silicide layer 12b is
transformed to a rare earth silicate and ultimately to rare earth
oxide because rare earth metals are strong reducers. During this
process excessive oxygen in cooperation with the silicon in
silicide layer 12b forms a layer 12c of amorphous silicon oxide at
the interface with substrate 10. Thus, silicide layer 12b is
essentially reduced to a thin layer 12c of amorphous silicon oxide
and a thin layer of rare earth oxide (illustrated in FIG. 4 as part
of layer 14.
[0023] Referring additionally to FIG. 7, in the pictorial view the
REO silicide layer 12b includes gadolinium silicide as an example.
As can be seen from the pictorial, after the annealing layer
described above, the gadolinium silicide is reduced to a thin
amorphous layer of SiO.sub.x and a thin Gd.sub.zSi.sub.yO.sub.x
layer. The silicide layer 12b is not stable because both Si and Gd
have a very high affinity to oxygen. Thus, it is substantially
easier to transform the silicide of layer 12b to amorphous silicate
and silicon dioxide than to transform the silicon of substrate 10
to silicon dioxide. The silicide transforms easier than the
substrate silicon because oxidation of silicon is a diffusion
limited process (i.e. the oxidation rate slows with the oxide
thickness) and requires higher temperatures and oxygen pressures
when compared to the present silicide reduction process.
[0024] In a subsequent step illustrated in FIG. 5, a thicker layer
16 of rare earth oxide (REO) is grown on REO layer 14. REO layer 16
is preferably grown to a thickness in a range from less than
approximately 50 nm to greater than approximately 500 nm so as to
serve as a template for the subsequent growth of a III-N
semiconductor layer. REO templates are disclosed in more detail in
the copending patent applications described above and included
herein by reference.
[0025] Turning to FIG. 6 a final step in the process of the growth
of III-N semiconductor material on a silicon substrate is
illustrated. It will of course be understood that this is simply
described as a final step because a layer 20 of III-N semiconductor
material (in this example GaN) is grown on the REO template 14/16.
Once layer 20 is grown additional steps in a process of fabricating
a semiconductor product (e.g. photonic device, sensor, etc.) can be
performed. As explained above, layer 12c of amorphous silicon oxide
has low viscosity at temperatures above 500.degree. C. that results
in stress relaxation, which is critical in point of view of thermal
stress during cooling down of III-N on Si heterostructure.
[0026] Thus, the silicide of layer 12b is transformed to amorphous
silicate and silicon dioxide rather than attempting to transform
the silicon of substrate 10 to silicon dioxide as in prior art
methods. The present novel method is relatively easy to perform and
results in a substantially uniform layer of amorphous silicon oxide
that is sufficiently thick to provide the desired stress relief
during the cool down of a III-N semiconductor layer of material
deposited on the REO template.
[0027] Various changes and modifications to the embodiments herein
chosen for purposes of illustration will readily occur to those
skilled in the art. To the extent that such modifications and
variations do not depart from the spirit of the invention, they are
intended to be included within the scope thereof which is assessed
only by a fair interpretation of the following claims.
* * * * *