U.S. patent application number 13/965055 was filed with the patent office on 2013-12-12 for apparatus and methods for control of sleep modes in a transceiver.
This patent application is currently assigned to QUALCOMM Incorporated. The applicant listed for this patent is QUALCOMM Incorporated. Invention is credited to Chinnappa Kelapanda Ganapathy, Tadeusz Jarosinski, Michael Mao Wang.
Application Number | 20130329617 13/965055 |
Document ID | / |
Family ID | 36589043 |
Filed Date | 2013-12-12 |
United States Patent
Application |
20130329617 |
Kind Code |
A1 |
Jarosinski; Tadeusz ; et
al. |
December 12, 2013 |
APPARATUS AND METHODS FOR CONTROL OF SLEEP MODES IN A
TRANSCEIVER
Abstract
Disclosed are apparatus and methods for control of sleep modes
in a transceiver or receiver. In particular, a transceiver is
disclosed including a processor configured to determine timing
information concerning sleep periods for at least a portion of
components within the transceiver. The transceiver also includes a
sleep control logic coupled to the processor to receive information
concerning sleep periods from the processor and configured to
effect shutting down of the at least a portion of the components of
the transceiver during power reduction periods independent of the
processor.
Inventors: |
Jarosinski; Tadeusz; (San
Diego, CA) ; Ganapathy; Chinnappa Kelapanda; (San
Diego, CA) ; Wang; Michael Mao; (San Diego,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
QUALCOMM Incorporated |
San Diego |
CA |
US |
|
|
Assignee: |
QUALCOMM Incorporated
San Diego
CA
|
Family ID: |
36589043 |
Appl. No.: |
13/965055 |
Filed: |
August 12, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11372876 |
Mar 10, 2006 |
8509859 |
|
|
13965055 |
|
|
|
|
60660916 |
Mar 11, 2005 |
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Current U.S.
Class: |
370/311 |
Current CPC
Class: |
H04B 1/1615 20130101;
H04W 52/0293 20130101; H04W 52/0225 20130101; Y02D 30/70
20200801 |
Class at
Publication: |
370/311 |
International
Class: |
H04W 52/02 20060101
H04W052/02 |
Claims
1. A wireless transceiver comprising: a processor configured to
determine timing information concerning sleep periods for at least
a portion of components within the transceiver; and a sleep control
logic coupled to the processor to receive information concerning
sleep periods from the processor and configured to effect shutting
down of the at least a portion of the components of the transceiver
during power reduction periods independent of the processor.
2. The transceiver as defined in claim 1, wherein the sleep control
logic is further configured to effect powering up of the at least a
portion of the components independently and synchronously with a
transceiver system timing.
3. The transceiver as defined in claim 1, wherein the sleep control
logic is further configured to shut down a partial number of
components of the at least a portion of the components when a
portion of signal processing of a received communication signal by
the transceiver has been completed prior to a predetermined timing
point and shut down another portion of components of the at least a
portion of the components if signal processing by the processor is
completed by predetermined time.
4. The transceiver as defined in claim 1, wherein the sleep control
logic is further configured to issue an interrupt signal to the
processor configured to wake up the processor after determination
of an end of a sleep mode by the sleep control logic.
5. The transceiver as defined in claim 1, wherein the processor is
configured to program the sleep control logic with the information
sent to the sleep control logic.
6. The transceiver as defined in claim 1, wherein the sleep control
logic is part of baseband receiver configured to receive burst
communication signals.
7. The transceiver as defined in claim 1, wherein the sleep control
logic is configured to determine an end timing of a sleep mode and
initiate wakeup of at least a portion of components in the
transceiver.
8. The transceiver as defined in claim 7, wherein the sleep control
logic is configured to issue a wakeup interrupt signal to the
processor after determining an end timing of a sleep mode.
9. The transceiver as defined in claim 1, wherein the wakeup
interrupt signal is a dynamic parameter determined by the processor
after each received burst of data.
10. Computer-readable medium encoded with a set of instructions,
the instructions comprising: an instruction for determining timing
information concerning sleep periods for at least a portion of
components within the transceiver with a processor; an instruction
for receiving information concerning sleep periods from the
processor with a sleep control logic coupled to the processor; and
an instruction for shutting down of the at least a portion of the
components of the transceiver during power reduction periods
independent of and synchronous with a transceiver system
timing.
11. The computer program product of claim 10, wherein the
computer-readable medium further comprises: code for causing a
processor to use the sleep control logic to shut down a partial
number of components of the at least a portion of the components of
the receiver when a portion of signal processing of a received
communication signal by the transceiver has been completed prior to
a predetermined timing point and shut down another portion of
components of the at least a portion of the components of the
receiver if signal processing by the processor is completed by a
predetermined time.
12. The computer program product of claim 10, wherein the
computer-readable medium further comprises: code for causing a
processor to determine an end of a sleep mode with the sleep
control logic; and code for causing a processor to issue an
interrupt signal to the processor with the sleep control logic
operable to wake up the processor based on the determination of the
end of the sleep mode.
13. The computer program product of claim 10, wherein the
computer-readable medium further comprises: code for causing a
processor to program the sleep control logic with the timeline.
14. The computer program product of claim 10, wherein the
computer-readable medium further comprises: code for causing a
processor to receive burst communication signals.
15. The computer program product of claim 10, wherein the
computer-readable medium further comprises: code for causing a
processor to determine an end timing of a sleep mode; and code for
causing a processor to initiate a wakeup of the at least a portion
of the components of the receiver.
16. The computer program product of claim 15, wherein the
computer-readable medium further comprises: code for causing a
processor to issue a wakeup interrupt signal to the processor after
determining an end timing of a sleep mode.
17. The computer program product of claim 16, wherein the wakeup
interrupt signal is a dynamic parameter determined by the processor
after a received burst of data.
Description
CLAIM OF PRIORITY UNDER 35 U.S.C. .sctn.119
[0001] The present application for patent is a Divisional of U.S.
application Ser. No. 11/372,876 entitled "APPARATUS AND METHODS FOR
CONTROL OF SLEEP MODES IN A TRANSCEIVER," filed on Mar. 10, 2006,
now U.S. Pat. No. 8,509,859, issued on Aug. 13, 2013, which claims
priority to Provisional Application No. 60/660,916 entitled
"RECEIVER SLEEP MODE CONTROLLER" filed Mar. 11, 2005, and assigned
to the assignee hereof and hereby expressly incorporated by
reference herein.
BACKGROUND
[0002] 1. Field
[0003] The present disclosure relates to apparatus and methods for
control of sleep modes in a transceiver and, more particularly, for
automated control of different sleep modes using a hardware
implemented sleep mode controller.
[0004] 2. Background
[0005] Conservation of energy in battery-powered devices, such as
mobile phones, is an important concern in order to maximize the
limited energy available to such devices. During operation of
mobile devices such as mobile phones, however, it is known that
some of the power consuming units within such devices can be
temporarily powered down without adversely affecting the
performance of the mobile device. This powering down, known as
"sleep," affords power savings since current consuming units only
consume power periodically, rather than continuously.
[0006] In order to improve the battery life of a device, it is
known to place numerous current consuming units within the device
into a power saving mode and maintain the system time using
low-power sleep circuits. Because of the high current draw (and,
thus, power usage) of voltage-controlled temperature-compensated
oscillators (VCTCXOs) that are used for accurate system timing in a
mobile device, in particular, it is not energy efficient to use
such devices to maintain system time for sleep circuits.
Accordingly, it is known to maintain system timing during sleep or
power saving modes by using a sleep controller consuming much less
power and clocked by a crystal oscillator at lower frequency (e.g.,
30-60 kHz) rather than the VCTCXO. frequency, which is usually much
higher (e.g., 19.2 MHz). Usage of the cost effective crystal
oscillator as the sleep controller clocking device is at the
expense of some accuracy in time keeping because the clock
frequency tends to drift with temperature. This clock is otherwise
known as the "sleep clock" or "slow clock." Thus, when the mobile
device is asleep, the system clock or "fast clock" (and VCTCXO) is
off. The sleep clock is used as a timer to wake up the system. Upon
wake up, once the fast clock becomes stable after waking up, system
timing is once again handed over to the fast clock.
[0007] Furthermore, in certain types of transceivers that receive
burst type communications, such as in orthogonal frequency division
multiplexed (OFDM) systems, the nature of such systems lend
themselves to sleep mode usage due to the periodic nature of when
system resources are actually used. In such devices, however, the
use of software execution of timing events for shutting down
components or waking up components can engender latencies that
cause errors or do not result in effective reduction of power
consumption during sleep mode due to under utilization of the
potentially available time for shutdown of components.
SUMMARY
[0008] According to an aspect of the present disclosure, a wireless
transceiver is disclosed including a processor configured to
determine timing information concerning sleep periods for at least
a portion of components within the transceiver; and a sleep control
logic coupled to the processor to receive information concerning
sleep periods from the processor and configured to effect shutting
down and waking up of the at least a portion of the components of
the transceiver during power reduction periods independent of the
processor.
[0009] According to another aspect of the present disclosure, a
sleep controller for use in a wireless transceiver is disclosed and
includes a sleep control logic communicatively coupled to a
processor to receive information concerning sleep periods from the
processor and configured to effect shutting down and powering up of
the at least a portion of the components of the transceiver during
power reduction periods independent of the processor.
[0010] According to yet another aspect of the present disclosure, a
method for controlling sleep modes in a wireless transceiver is
disclosed and includes determining timing information concerning
sleep periods for at least a portion of components within the
transceiver with a processor; and receiving information concerning
sleep periods from the processor with a sleep control logic coupled
to the processor; and shutting down of the at least a portion of
the components of the transceiver during power reduction periods
independent of and synchronously with the system time.
[0011] According to a further aspect of the present disclosure,
another transceiver apparatus is disclosed. The transceiver
apparatus includes means for determining timing information
concerning sleep periods for at least a portion of components
within the transceiver; means for outputting information concerning
sleep periods from the means for determining; and means for
executing sleep periods configured to shut down the at least a
portion of the components of the transceiver during power reduction
periods independent of and synchronous with the means for
determining timing information.
[0012] According to still another aspect, a computer-readable
medium encoded with a set of instructions is disclosed. The
instructions include an instruction for determining timing
information concerning sleep periods for at least a portion of
components within the transceiver with a processor; an instruction
for receiving information concerning sleep periods from the
processor with a sleep control logic coupled to the processor; and
an instruction for shutting down of the at least a portion of the
components of the transceiver during power reduction periods
independent of and synchronous with a transceiver system
timing.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is an exemplary block diagram of wireless device
including an implemented sleep controller.
[0014] FIG. 2 is an exemplary block diagram illustrating a more
detailed architecture of the transceiver of FIG. 1 including a
hardware implemented sleep controller.
[0015] FIG. 3 is a block diagram of an exemplary baseband receiver
chipset including sleep control logic.
[0016] FIG. 4 is an exemplary timing diagram showing the timing
operation of the sleep control logic.
[0017] FIG. 5 is an exemplary timing diagram showing a "snooze"
operation.
[0018] FIG. 6 is a flow diagram of an exemplary method for sleep
mode control.
[0019] FIG. 7 is a block diagram of a further exemplary
transceiver.
[0020] It is noted that like numerals refer to like parts
throughout the several views of the drawings.
DETAILED DESCRIPTION
[0021] FIG. 1 illustrates a wireless device 100, such as a mobile
transceiver for receiving and transmitting wireless communication
signals, such as CDMA and OFDM signals. As illustrated, the
transceiver 100 includes a transceiver chipset 102 used for
processing communications signals received or to be transmitted.
The chipset 102 includes a microprocessor 104, which may be a
single processor or multiple processors such as a general purpose
processor (GPP) and a digital signal processor (DSP). It also
includes the baseband transceiver 106 and the RF integrated
circuits 108, which are used to actually receive and transmit the
wireless communication signals via antenna(s) 110. As will be
described further below, the microprocessor 104 is configured to
execute software that determines timing of sleep modes for the
transceiver device 100. That is, the software run by the
microprocessor 104 determines when particular components of the
transceiver device 100 may be powered down to conserve life of the
device battery (not shown).
[0022] The transceiver 100 also includes another chipset used to
receive communication signals, such as burst communications in an
orthogonal frequency division multiplexed (OFDM) system, for
example. This chipset is shown as a receiver chipset 112 in the
example of FIG. 1. Within the chipset 112 is another baseband
circuit including a baseband receiver 114, which processes received
communication signals. In particular, the baseband receiver 114
receives communication signals from a RF chip 116 and an
analog-to-digital converter (ADC) 118 (e.g., a sigma-delta
modulator ADC). Additionally, the chipset 112 includes sleep
control logic 120 that is used to execute sleep modes within the
receiver chipset 112. Logic 120 may be implemented with digital
logic or any other suitable hardware that characteristically
execute instructions quickly with low latency. The chipset is
coupled to the microprocessor 104 via bus 122, such as external
parallel or serial bus and GPIO (general purpose input/output), in
order to communicate sleep mode timing information to the hardware
sleep control logic 120. Logic 120, in turn, then actually executes
the sleep mode timing, as will be discussed in more detail
below.
[0023] Additionally, the transceiver 100 includes a fast and
accurate system clock 124, originating from a stable source, such
as a voltage controlled temperature compensated crystal oscillator
(VCTCXO) used for providing system timing when the transceiver 100
is in awake modes. A sleep clock source 126, which consumes less
power and is slower than the fast clock 124, is used for system
timing during sleep modes to conserve battery energy. Each of the
chipsets 102 and 112 receive clock signals from clocks 124 and 126
as illustrated by connections 128 and 130, respectively.
[0024] FIG. 2 illustrates an exemplary detailed block diagram of
portions of the transceiver 100 utilizing chipset-based phone
architecture. The transceiver 100 includes the transceiver chipset
102, such as a CDMA transceiver chipset, which includes
microprocessor 104. The transceiver 100 also includes receiver
chipset 112 that is used to receive broadcast wireless signals,
including those utilizing burst communication (i.e., bursts of
packets of information). Examples of such standards include
orthogonal frequency division multiplexing (OFDM) standards. Within
the receiver chipset 112, the baseband receiver 114 utilizes sleep
control logic 120, which executes sleep modes determined by the
microprocessor 104.
[0025] In the particular architecture exemplified in FIG. 2, the
microprocessor 104 determines the sleep functionality for sleep
modes to be effected. This determination is made with software run
by the processor 104. This sleep software ("Sleep SW") is indicated
diagrammatically by cloud 200. The software, in turn, interacts
with the sleep control logic 120 via the bus 122 to program logic
120 with information concerning what timing is too be executed by
logic 120 when going to sleep or waking up from sleep.
[0026] As further illustrated in the particular example of FIG. 2,
the transceiver chipset 102 includes the baseband transceiver 106,
which includes respective sleep controllers for supporting other
modes such as CDMA 1x, High Data Rate (HDR), UMTS, Global System
for Mobile Communications (GSM), Global Positioning System (GPS),
and other modes. The sleep software also controls or sets the
operation of the sleep controllers in the baseband transceiver 106,
where communication is effected by a bus 208 between the baseband
transceiver 106 and the processor 104. The processor 104 also runs
software (VCTCXO Controller SW 202) to control a Pulse Density
Modulator (PDM) of the VCTCXO clock 124 in concurrent support of
different modes as illustrated by communication bus 214.
Connections between the VCTCXO Controller SW 202 and the Sleep SW
200 illustrate that an exchange information occurs therebetween
concerning when the VCTCXO can be turned off and on, as illustrated
in FIG. 2.
[0027] Since a goal of a sleep controller is to conserve power by
reducing the power consumption of as many devices within a mobile
transceiver, the sleep functionality of the present disclosed
system interacts or affects various devices in the transceiver 100.
For example, as explained above, various components within the
transceiver chipset 102 are controlled to enter sleep modes. For
instance, the baseband transceiver 106 may include sleep control.
Additionally, the processor 104 may actually be put to sleep as
well.
[0028] The sleep clock or crystal oscillator 126 is run
continuously to provide a low power, uninterrupted clock source for
the transceiver 100 during sleep modes. The system clock 124 also
is affected by the sleep functionality. In particular, the sleep
software 200 running on microprocessor 104 will issue controls via
a bus 216 to a power management chip 204, which, in turn, controls
the delivery of power to the VCTCXO 124 (thereby turning the system
clock 128 on and off). As explained previously, the high power
consumption clock 124 is turned off during sleep modes to converse
energy.
[0029] The RF ICs 108, which support the baseband transceiver 106
and accompanying modes, are also affected by sleep functionality.
In particular, the microprocessor 104 may issue instructions to RF
IC 108 via a bus 218, such as a serial bus interface. Also the
baseband receiver 114 may issue control signals to the RF IC 108
via a serial bus 220.
[0030] FIG. 2 also illustrates that the transceiver 100 may include
a user interface (UI) 210, such as a keypad, microphone, or other
interfacing apparatus which input to the microprocessor. Similarly,
the transceiver 100 may also connect to various peripherals 212,
such as via a Universal Serial Bus (USB) or other serial or
parallel connection. The sleep functionality is responsive to these
input or communication connections since they present "rude"
interrupts that may require sleep modes to be aborted or
rescheduled.
[0031] It is noted here that the digital logic and other various
devices in the transceiver 100 are operable with multiple clock
regimes, which may be turned on/off to conserve power. Switching
may be effected by a clock gating logic (not shown) or any other
suitable switching device. As further illustrated in FIG. 2, each
of the sleep controllers (i.e., the baseband transceiver sleep
controllers and sleep control logic 120) receive input from the
sleep clock 126 (receiver chipset 112 shown receiving both the
system clock and sleep clock signals directly). As noted before,
the sleep controllers are configured to switch their timing to the
low-power sleep clock 126 during sleep modes to conserve power.
[0032] In the transceiver 100 of FIG. 2, the microprocessor
104(with system clock turned on) can continue to display data on a
display (not shown) of the transceiver 100 during streaming of
packets received via the baseband receiver 112, such as streaming
video via an OFDM system. Nonetheless, the receiver chipset 112 can
still conserve power during "off" time by switching its system
clocks and PLL off (e.g., disabling clocks in order to inactivate
sub-blocks in the chipset 112) and switching the sleep control
logic's (120) clock source to the sleep clock 126. In instances
that do not involve direct display to the display, the
microprocessor 104 may have time to go to sleep too.
[0033] In the disclosed transceiver 100 and, in particular, the
receiver chipset 112, sleep modes can be activated during various
states of the receiver chipset 112. The first of these states is an
active state where data received via the RF chip 116 and ADC 118 is
being demodulated burst by burst (e.g., a group of adjacent active
symbols is forming a burst, in the case of an OFDM system). When
receiving bursts of information in the active state, for example,
sleep modes may be effected such as when received overhead
information is being demodulated (e.g. OFDM overhead information
symbols) or when receiving traffic or control channel data. Another
state when sleep modes may be effected include deep sleep states,
which are dormant states where no pending requests are being
received and only periodic wakeups are necessary, such as for
example updating information concerning what information will be
broadcast (e.g., a program guide).
[0034] A function of the sleep control logic 120 is to minimize
power consumption during sleep when the receiver chipset 112 is not
receiving active bursts of information. Due to the nature of burst
communication that the receiver chipset 112 is designed to receive,
the operation of the chipset 112 tends to be systolic (i.e.,
occurring in bursts of processing corresponding to received bursts
of information with idle processing times in between bursts). In
certain systems, such as OFDM systems, bursts can last about 10 ms
(4% duty cycle) or longer, depending on the payload configuration.
Since there is no correlation between on/off cycles of the sleep
controller 120 and other modes in the wireless device 100, the
presently disclosed example includes independent sleep timelines
for processor 104, which may include separate sleep timelines for
multiple processors in the transceiver 102, and the baseband
receiver chipset 112, although they share the same system clock
derived from the VCTCXO clock 124. Furthermore, in order to prevent
problems due to latencies inherent to software run by the
microprocessor 104 and that the receiver chipset 112 could not
tolerate such latency, it was recognized that sleep control for the
receiver 112 would be more efficient using separate hardware logic
(e.g., 120) to execute sleep modes in the receiver 112.
[0035] Although in the particular disclosed examples, the sleep
control logic 120 executes a separate sleep timing operation for
chipset 112, logic 120 nonetheless is configured to interface with
various other portions of the transceiver 100. This is because the
timing operation of the receiver affects and is affected by other
operations of other parts of the transceiver 100. A more detailed
block diagram of an exemplary implementation of the sleep control
logic 120 and its interactions is illustrated in FIG. 3.
[0036] As shown in FIG. 3, the sleep control logic 120 includes
sleep core logic 300 having sleep timers 302 and system time buffer
304. The sleep timers 302 are programmed by the processor 104 via a
bus interface 306 which interfaces with bus 308 between the
processor 104 and the receiver chipset 112. The bus 308 is coupled
to another interface 310 in the sleep control logic 120. A sleep
register 312 is used to then direct programming information to
sleep timers 302, such as timing information and predefined that
the logic 120 will automatically execute when effecting the sleep
timeline.
[0037] The baseband receiver 112 also includes a phase lock loop
(PLL) 314, which generates the system clock and other clock domains
or regimes. These clock signals are fed to a clock gating logic
316, which is used to selectively turn on and off the different
clock domains based on clock disable signals received from core
logic 300. From the Sleep Control Logic standpoint in the disclosed
example of FIG. 3, multiple clock regimes are controlled through
the clock gating logic 316 . . . . The first of these is a primary
system clock regime. The next is a secondary clock regime, which is
used during the draining process of the decoder output buffer (not
shown on the diagram), when the burst demodulation has ended.
Additional domains include a Sleep Core Logic fast clock regime
(sleep_fast_clk), a sleep controller core sleep clock regime (not
shown), and a RF serial interface block clock regime (used with
serial bus interface 318, not shown).
[0038] It is noted that the microprocessor 104 can disable or
enable each clock via a halt input, overriding the sleep controller
hardware.
[0039] As illustrated, the core logic 300 is configured to issue a
wakeup interrupt signal (wakeup_int) to the interrupt controller in
the transceiver chipset 102. It is noted that this interrupt is
dynamically determined based on programming information from the
microprocessor 104 since the wakeup point is not the same for every
sleep mode operation and changes from burst to burst.
[0040] In operation, sleep control logic 120 disables the primary
and secondary system clocks via clock disable signals to conserve
energy during a sleep mode. The sleep core logic 300 also disables
one or more Phase Lock Loops (PLLs) 314, which are used to generate
system clock regimes. The control logic, in turn, receives a system
time synchronization pulse, sys_time_en, and exact timing
information (sys_time_in) from Receiver Core Logic 114 before sleep
begins, and updates (or triggers the update) the system time before
sleep finishes. The microprocessor 104 and sleep control logic 120
operation are synchronized via interrupts multiplexed to a single
transceiver GPIO signal 322 by interrupt controller 320, and
wakeup_int. The microprocessor 104 (not shown in FIG. 3)
communicates with the control logic 120 over the interface 306,
308, and 310. The control logic further interfaces to the RF and
ADC chips 116, 118, through a serial bus interface 318 and a couple
of discrete lines for issuing direct signals such as turning on the
TXCO buffer in the RF chip 116.
[0041] According to the disclosed examples, software or
instructions run by the microprocessor 104 are used to configure
the sleep timeline. It is noted that the software can also "tag"
bursts after which a snooze cycle or partial sleep cycle can
automatically start. It is further noted that the sleep control
logic hardware 120 executes the sleep and/or snooze timeline with
the resolution of the system clock (sys_clk), which is greater than
sleep clock frequency to preserve maximum accuracy.
[0042] FIG. 4 is an exemplary timing diagram showing the timing
operation of the sleep control logic 120. Because the receiver
chipset 112 does not actively track system time during sleep modes,
the system time counter is not updated. Accordingly, the baseband
receiver 114 is configured to tightly control the sleep time (i.e.,
the period between the assertion of the next sample-aligned trigger
signal (sys_time_en), and pulsing of the on_line_int signal when
system time counter is restored after wakeup. System time is known
when sys_time_en is pulsed and an estimate is made for the system
time when on_line_int is pulsed.
[0043] As may be seen in the timeline of FIG. 4, the VCTCXO 124 is
shut down during sleep mode and, thus, the sleep_fast_clock which
uses clock 124 as the source for timing, is also shut down. During
the sleep period, from the first sleep clock rising edge after a
next sample trigger, the sleep clock 126 is used for timing during
the sleep mode (e.g., for determining how long to stay in sleep
mode and when to issue the wakeup interrupt signal). The sleep
clock is used for timing until the PLLs settle after wakeup as
shown in FIG. 4. After the PLL settled (i.e., sleep_fast_clk is
restored), timing for receiver 112 reverts to the system clock
domain.
[0044] It was recognized, however, that a substantial source of
power inefficiency in the receiver chipset 112 is long response
times (latency) of the microprocessor (i.e., software) to real-time
events, such as interrupts. This resulted in delay of shutdown of
the RF chip 116. Accordingly, the presently disclosed sleep control
logic 120 includes a "snooze" feature to provide for immediate RF
chips 116 shutdown after the end of a received burst. The "snooze"
allows shutdown of a portion of components, while leaving a minimum
clock domain (secondary system clock) active, in order to allow the
microprocessor 104 to finish processing the current task and drain
the decoder output buffer. After processing is finished, the
secondary system clock regime and the PLL can also be shut down.
The majority of power consumption, however, is due to resources
that are shut down at snooze time, particularly the RF chip 116.
Thus, a significant degree of efficiency can be garnered through
partial shutdown of components in the "snooze".
[0045] In an specific implementation, the "snooze" feature allows
software to tag received bursts after which snooze/sleep cycle can
occur, and let the sleep control logic 120 initiate RF and part of
the digital circuitry shutdown automatically at the end of those
bursts, when the snooze trigger (snooze_trig) is generated by
hardware (see FIG. 3 and reference 402 as the start of a "snooze"
cycle after a snooze tagged burst). In the OFDM systems, in
particular, the burst snooze tags in the FFT descriptors are used
to detect the last tagged burst sample. When this sample is
processed by a Fast Fourier Transform (FFT) and passed to a
descrambler, for instance, the snooze trigger is generated by
Receiver Core Logic 114 and sent to the sleep control logic 120, as
shown in FIG. 3. At this point, the RF chip 116, ADC 118, the front
end blocks and the FFT are ready to be shut down. It is noted also
that most of the time, interrupts to the microprocessor that
indicate commencement of the snooze cycle will have already
occurred by the time the software is ready to issue a go_to_sleep
request. Thus, typically the sleep control logic 120 can effect a
full sleep mode immediately after microprocessor 104 issues the
go_to_sleep request.
[0046] It is also noted that sleep control logic 120 executes the
sleep timeline based on the secondary system clock during snooze.
The reason for this is twofold. First, the secondary system clock
domain is still needed by the decoder output buffer, interrupt
controller, and other blocks. Second, the process of computing
sleep parameters and sleep clock frequency estimation is too
complex to be done by hardware. For those reasons, the complete
shutdown of the system clock and the PLL and switch to the sleep
clock is not possible.
[0047] FIG. 5 illustrates a timeline for an exemplary snooze
operation, which was discussed above. As shown, after an over the
air signal comprising a snooze tagged burst 502 (tagged by software
run on processor 104) is received by the transceiver 100. After the
last sample of the burst 502, front end processing 504 is
performed, such as FFT processing in the case of an OFDM system, as
an example. Once this processing 504 is complete, the receiver core
logic 114, which may me hardware, issues a snooze trigger signal
(snooze_trig) 506 to the sleep control logic 120 (see FIG. 3 also).
Logic 120 then initiates a snooze cycle 508 where part of the
components is chipset 112 may be shut down, such as the RF chip
116, and ADC 118, as examples. Since other processing 510, such as
decoding, is still being performed, not all components may be put
to sleep.
[0048] If before the other processing 510 is completed, and the
software and hardware processing latency 512 does not exceed this
time, a go_to_sleep signal 514 may be processed. After signal 514
has issued, synchronization occurs between hardware and software
and software proceeds to issue a sleep execution 518. IF request
518 occurs before wakeup signal 520, then sleep is accepted by
hardware and starts immediately. Otherwise it is rejected and
snooze 508 continues to start of next pulse. and the remaining
components put to sleep for a full sleep cycle 516. If the latency
512 is longer than processing 510 (this is not shown on timeline),
then the sleep control logic will not initiate a full slee
[0049] FIG. 6 illustrates an exemplary flow diagram of a process
600 for effecting sleep mode control. As shown, the process 600
begins at start block 602. Flow proceeds to block 604 where the
microprocessor 104 determines timing information concerning sleep
periods for at least a portion of components within the transceiver
100. That is, microprocessor determines through the sleep software
200 configures the timeline for sleep modes and also may determine
which components are allowed to be powered down, such as during
"snooze" modes which effect only partial shutdowns.
[0050] After the determination in block 604, flow proceeds to block
606 where the logic control 120 receives the determined information
or programming. This is performed, for example, by the
microprocessor 104 writing the information to the sleep control
logic 120 via bus interface 306, bus 308, bus interface 310 and
sleep registers 312 as illustrated in FIG. 3. After the sleep
timeline information is written in the sleep control logic 120,
flow proceeds to block 608.
[0051] At block 608, the sleep control logic 120 automatically
shuts down at least a potion of the components of the transceiver
100 during sleep modes, either full sleep mode or snooze modes. The
operation in block 608 also includes bringing back or using sleep
control logic 120 independent of, but synchronous with receiver or
transceiver 106 or 114. That is, the sleep control logic 120 is
configured to effect or execute the sleep timeline from entering
sleep modes to bringing powered down components back out of sleep
mode to powered up operation. This operation is automatically
executed by the logic 120 independent of the microprocessor 104 in
the sense that the microprocessor does not trigger the sleep modes
for the receiver chipset 112. Notwithstanding, the sleep mode
operation is performed synchronous with the system timing (e.g.,
TCXO system clock) used by the receiver or transceiver 106 or
114.
[0052] It is noted that the process of block 608 is repeated for
each awake/sleep mode cycle, which continue while the transceiver
is operational. The process in blocks 604 and 606 may be performed
during initialization of the transceiver 100, but can also be
performed anytime after initialization as well if desired.
[0053] FIG. 7 is block diagram of a further exemplary transceiver
700 according to the present disclosure. As shown, the transceiver
700 includes means for determining timing information concerning
sleep periods for at least a portion of components within the
transceiver 702. This means may be, for example, processor 104
discussed previously. Coupled to means 702 is means for outputting
information concerning sleep periods from the means for determining
704. Means 704 may be implemented by bus interface 306, bus 308,
bus interface 310, and sleep register 312, for example. Coupled to
means 704 is a means for executing sleep periods 706, which is
configured to shut down the at least a portion of the components of
the transceiver during power reduction periods independent of and
synchronous with the means for determining timing information.
Means 706 may be implemented, for example, by sleep control logic
120.
[0054] As described in the foregoing, the inefficiencies that arise
from latencies due to software processing may be overcome by
effecting sleep mode execution through hardware logic. Furthermore,
utilization of a partial shutdown of components yields a further
rise in the efficiency of sleep mode in cases where sleep modes
would be thwarted due to software latency.
[0055] It is noted that the baseband receiver 114 and the sleep
control logic 120 may reside in a separate ASIC or similar
processing circuit as illustrated, but may also be part of an ASIC
or chipset incorporated with the transceiver chipset 102. It is
further noted that the above-described apparatus and methods may
also be utilized for sleep control performed by the baseband
transceiver 106.
[0056] The examples described above are merely exemplary and those
skilled in the art may now make numerous uses of, and departures
from, the above-described examples without departing from the
inventive concepts disclosed herein. Various modifications to these
examples may be readily apparent to those skilled in the art, and
the generic principles defined herein may be applied to other
examples, e.g., in an instant messaging service or any general
wireless data communication applications, without departing from
the spirit or scope of the novel aspects described herein. Thus,
the scope of the disclosure is not intended to be limited to the
examples shown herein but is to be accorded the widest scope
consistent with the principles and novel features disclosed herein.
The word "exemplary" is used exclusively herein to mean "serving as
an example, instance, or illustration." Any example described
herein as "exemplary" is not necessarily to be construed as
preferred or advantageous over other examples. Accordingly, the
novel aspects described herein are to be defined solely by the
scope of the following claims.
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