U.S. patent application number 13/904383 was filed with the patent office on 2013-12-05 for semiconductor device and processing unit.
This patent application is currently assigned to Semiconductor Energy Laboratory Co., Ltd.. The applicant listed for this patent is Semiconductor Energy Laboratory Co., Ltd.. Invention is credited to Hidetomo Kobayashi, Yoshiyuki Kurokawa, Yutaka Shionoiri.
Application Number | 20130322187 13/904383 |
Document ID | / |
Family ID | 49670093 |
Filed Date | 2013-12-05 |
United States Patent
Application |
20130322187 |
Kind Code |
A1 |
Shionoiri; Yutaka ; et
al. |
December 5, 2013 |
SEMICONDUCTOR DEVICE AND PROCESSING UNIT
Abstract
A semiconductor device in which the power consumption of a
register is low is provided. Further, a processing unit whose
operation speed is high and whose power consumption is low is
provided. In the semiconductor device, a register operating at high
speed and a nonvolatile FILO (first-in-last-out) register capable
of reading and writing data from/to the register are provided.
Inventors: |
Shionoiri; Yutaka; (Isehara,
JP) ; Kobayashi; Hidetomo; (Isehara, JP) ;
Kurokawa; Yoshiyuki; (Sagamihara, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Semiconductor Energy Laboratory Co., Ltd. |
Atsugui-shi |
|
JP |
|
|
Assignee: |
Semiconductor Energy Laboratory
Co., Ltd.
Atsugui-shi
JP
|
Family ID: |
49670093 |
Appl. No.: |
13/904383 |
Filed: |
May 29, 2013 |
Current U.S.
Class: |
365/189.011 |
Current CPC
Class: |
G11C 19/0875 20130101;
G11C 7/00 20130101 |
Class at
Publication: |
365/189.011 |
International
Class: |
G11C 7/00 20060101
G11C007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 1, 2012 |
JP |
2012-125993 |
Jan 24, 2013 |
JP |
2013-010751 |
Claims
1. A semiconductor device comprising: a register; and a
first-in-last-out register comprising a first flip-flop circuit and
a second flip-flop circuit, wherein the register is electrically
connected to the first flip-flop circuit, wherein the first
flip-flop circuit is electrically connected to the second flip-flop
circuit, wherein each of the first flip-flop circuit and the second
flip-flop circuit comprises a first transistor and a capacitor,
wherein the first transistor comprises a channel formation region
comprising an oxide semiconductor, and wherein a first terminal of
the first transistor is electrically connected to a first terminal
of the capacitor.
2. The semiconductor device according to claim 1, wherein each of
the first flip-flop circuit and the second flip-flop circuit is a
nonvolatile flip-flop circuit.
3. The semiconductor device according to claim 2, wherein each of
the first flip-flop circuit and the second flip-flop circuit
comprises a first three-state buffer, and wherein an output of the
first three-state buffer is electrically connected to a second
terminal of the first transistor.
4. The semiconductor device according to claim 3, wherein each of
the first flip-flop circuit and the second flip-flop circuit
comprises a second transistor and a second three-state buffer,
wherein the second transistor comprises a channel formation region
comprising an oxide semiconductor, wherein a first terminal of the
second transistor is electrically connected to an input of the
first three-state buffer, wherein a second terminal of the second
transistor is electrically connected to an output of the second
three-state buffer, and wherein an input of the second three-state
buffer is electrically connected to the first terminal of the
capacitor.
5. The semiconductor device according to claim 4, wherein the
register is electrically connected to the input of the first
three-state buffer and the first terminal of the second transistor
of the first flip-flop circuit, and wherein the first terminal of
the capacitor of the first flip-flop circuit is electrically
connected to the input of the first three-state buffer and the
first terminal of the second transistor of the second flip-flop
circuit.
6. The semiconductor device according to claim 5, wherein the
register is configured to hold first data, wherein the first
flip-flop circuit is configured to hold second data output from the
register, wherein the second flip-flop circuit is configured to
hold third data output from the first flip-flop circuit, wherein
the register is configured to output the first data to the first
flip-flop circuit in a first period, wherein the first flip-flop
circuit is configured to store the first data and output the second
data to the second flip-flop circuit in the first period, and
wherein the second flip-flop circuit is configured to store the
second data in the first period.
7. The semiconductor device according to claim 6, wherein the
second flip-flop circuit is configured to output the second data to
the first flip-flop circuit in a second period after the first
period, wherein the first flip-flop circuit is configured to store
the second data and output the first data to the register in the
second period, and wherein the register is configured to store the
first data in the second period.
8. A semiconductor device comprising: a register; a
first-in-last-out register comprising a first flip-flop circuit and
a second flip-flop circuit; and an external memory device, wherein
the register is electrically connected to the first flip-flop
circuit, wherein the first flip-flop circuit is electrically
connected to the second flip-flop circuit, wherein the second
flip-flop circuit is electrically connected to the external memory
device, wherein each of the first flip-flop circuit and the second
flip-flop circuit comprises a first transistor and a capacitor,
wherein the first transistor comprises a channel formation region
comprising an oxide semiconductor, and wherein a first terminal of
the first transistor is electrically connected to a first terminal
of the capacitor.
9. The semiconductor device according to claim 8, wherein each of
the first flip-flop circuit and the second flip-flop circuit is a
nonvolatile flip-flop circuit.
10. The semiconductor device according to claim 9, wherein each of
the first flip-flop circuit and the second flip-flop circuit
comprises a first three-state buffer, and wherein an output of the
first three-state buffer is electrically connected to a second
terminal of the first transistor.
11. The semiconductor device according to claim 10, wherein each of
the first flip-flop circuit and the second flip-flop circuit
comprises a second transistor and a second three-state buffer,
wherein the second transistor comprises a channel formation region
comprising an oxide semiconductor, wherein a first terminal of the
second transistor is electrically connected to an input of the
first three-state buffer, wherein a second terminal of the second
transistor is electrically connected to an output of the second
three-state buffer, and wherein an input of the second three-state
buffer is electrically connected to the first terminal of the
capacitor.
12. The semiconductor device according to claim 11, wherein the
register is electrically connected to the input of the first
three-state buffer and the first terminal of the second transistor
of the first flip-flop circuit, wherein the first terminal of the
capacitor of the first flip-flop circuit is electrically connected
to the input of the first three-state buffer and the first terminal
of the second transistor of the second flip-flop circuit, and
wherein the first terminal of the capacitor of the second flip-flop
circuit is electrically connected to the external memory
device.
13. The semiconductor device according to claim 12, wherein the
register is configured to hold first data, wherein the first
flip-flop circuit is configured to hold second data output from the
register, wherein the second flip-flop circuit is configured to
hold third data output from the first flip-flop circuit, wherein
the register is configured to output the first data to the first
flip-flop circuit in a first period, wherein the first flip-flop
circuit is configured to store the first data and output the second
data to the second flip-flop circuit in the first period, and
wherein the second flip-flop circuit is configured to store the
second data and output the third data to the external memory device
in the first period.
14. The semiconductor device according to claim 13, wherein the
second flip-flop circuit is configured to output the second data to
the first flip-flop circuit in a second period after the first
period, wherein the first flip-flop circuit is configured to store
the second data and output the first data to the register in the
second period, and wherein the register is configured to store the
first data in the second period.
15. A semiconductor device comprising: a register; a
first-in-last-out register comprising a first flip-flop circuit and
a second flip-flop circuit; and a memory access determination
circuit, wherein the register is electrically connected to the
first flip-flop circuit, wherein the first flip-flop circuit is
electrically connected to the second flip-flop circuit, wherein
each of the first flip-flop circuit and the second flip-flop
circuit comprises a first transistor, a capacitor, and a first
three-state buffer, wherein the first transistor comprises a
channel formation region comprising an oxide semiconductor, wherein
a first terminal of the first transistor is electrically connected
to a first terminal of the capacitor, wherein an output of the
first three-state buffer is electrically connected to a second
terminal of the first transistor, and wherein the memory access
determination circuit is configured to monitor data written to the
first-in-last-out register from the register, and output a wait
signal before the data is written to the first-in-last-out register
when the volume of the data exceeds the capacity of the
first-in-last-out register.
16. The semiconductor device according to claim 15, wherein each of
the first flip-flop circuit and the second flip-flop circuit is a
nonvolatile flip-flop circuit.
17. The semiconductor device according to claim 16, wherein each of
the first flip-flop circuit and the second flip-flop circuit
comprises a second transistor and a second three-state buffer,
wherein the second transistor comprises a channel formation region
comprising an oxide semiconductor, wherein a first terminal of the
second transistor is electrically connected to an input of the
first three-state buffer, wherein a second terminal of the second
transistor is electrically connected to an output of the second
three-state buffer, and wherein an input of the second three-state
buffer is electrically connected to the first terminal of the
capacitor.
18. The semiconductor device according to claim 17, wherein the
register is electrically connected to the input of the first
three-state buffer and the first terminal of the second transistor
of the first flip-flop circuit, and wherein the first terminal of
the capacitor of the first flip-flop circuit is electrically
connected to the input of the first three-state buffer and the
first terminal of the second transistor of the second flip-flop
circuit.
19. The semiconductor device according to claim 18, wherein the
register is configured to hold first data, wherein the first
flip-flop circuit is configured to hold second data output from the
register, wherein the second flip-flop circuit is configured to
hold third data output from the first flip-flop circuit, wherein
the register is configured to output the first data to the first
flip-flop circuit in a first period, wherein the first flip-flop
circuit is configured to store the first data and output the second
data to the second flip-flop circuit in the first period, and
wherein the second flip-flop circuit is configured to store the
second data in the first period.
20. The semiconductor device according to claim 19, wherein the
second flip-flop circuit is configured to output the second data to
the first flip-flop circuit in a second period after the first
period, wherein the first flip-flop circuit is configured to store
the second data and output the first data to the register in the
second period, and wherein the register is configured to store the
first data in the second period.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an object, a method, or a
manufacturing method. Further, the present invention relates to a
process, a machine, manufacture, or a composition of matter. In
particular, the present invention relates to, for example, a
semiconductor device, a display device, a light-emitting device, a
power storage device, a driving method thereof, or a manufacturing
method thereof. In particular, the present invention relates to a
semiconductor device including a register and a processing unit
including the semiconductor device.
[0003] 2. Description of the Related Art
[0004] The processing speed of a processing unit is significantly
affected by the speed at which an arithmetic portion accesses data
(the speed of reading operation and writing operation). For that
reason, the processing unit is provided with a memory circuit
called a register, which operates at high speed.
[0005] The arithmetic portion needs to execute an interrupt
instruction in some cases. When the arithmetic portion executes an
interrupt instruction, data in the register is temporarily stored
in another memory circuit so that another data can be written to
the register before the interrupt instruction is executed. After
the interrupt instruction is executed, the stored data is restored
to the register. The memory circuit in which data in the register
can be temporarily stored is called a stack register, and is
provided in the processing unit.
[0006] Note that the processing unit includes not only the
arithmetic portion and the memory portion but also a control
portion, a transmission path (also referred to as a bus), and the
like. The control portion controls components of the processing
unit, and the transmission path is a common signal line connecting
the components. The transmission path is used when data is
transferred between the register and the stack register, for
example.
[0007] A semiconductor device that can hold stored data even
without power supply and has an unlimited number of write cycles
has been known (Patent Document 1).
REFERENCE
Patent Document
[0008] [Patent Document 1] Japanese Published Patent Application
No. 2011-151377
SUMMARY OF THE INVENTION
[0009] With an enriched infrastructure of the information
communication means, an improvement in the information-processing
capability and an increase in the continuous operation time of a
portable information terminal have been strongly requested. Also in
terms of energy problems, a reduction in the power consumption of a
processing unit has been requested.
[0010] In order to improve the processing speed of a processing
unit, a memory circuit needs to be provided such that access to
data in an arithmetic portion is easy. For example, the number of
registers (in other words, the memory capacity of the memory
circuit) is increased.
[0011] However, it has been difficult to increase the memory
capacity of the register while power consumption is reduced because
most memory circuits operating at high speed are volatile and thus
consume power constantly for storing data.
[0012] One embodiment of the present invention has been made in
view of the foregoing technical background. Therefore, an object is
to provide a semiconductor device in which the power consumption of
a register is low. Another object is to provide a processing unit
whose operation speed is high and whose power consumption is
low.
[0013] Note that the descriptions of these objects do not preclude
the existence of other objects. Note that one embodiment of the
present invention does not necessarily achieve all the objects
listed above. Other objects will be apparent from and can be
derived from the description of the specification, the drawings,
the claims, and the like.
[0014] In order to solve the above problem, one embodiment of the
present invention has been made with a focus on the structure of a
semiconductor device including a register. The present inventors
conceived a semiconductor device which includes a register
operating at high speed and a nonvolatile first-in-last-out (FILO)
register that can read and write data to/from the register. Note
that in this specification, the term "nonvolatile" means a property
of maintaining stored data even when power supply is stopped, and
the term "volatile" means a property of erasing stored data
instantly when power supply is stopped.
[0015] One embodiment of the present invention is a semiconductor
device including a register to which data can be written through a
first transmission path and from which the data can be read out to
the first transmission path or a second transmission path; a
reading/writing circuit which writes data read out from the second
transmission path to the first transmission path; and a nonvolatile
FILO register. The nonvolatile FILO register operates in a first
mode in which data is written through the second transmission path
to the nonvolatile FILO register and a second mode in which data
stored in the nonvolatile FILO register is read out to the second
transmission path.
[0016] Note that in this specification, an FILO register and a
first-in-first-out (FIFO) register each mean a register that can
store a plurality of pieces of data sequentially. The FILO register
can read out a plurality of pieces of data in the order which is
the reverse of the order of storing them; specifically, four pieces
of data, A, B, C, and D, which are stored in this order can be read
out in the order of D, C, B, and A. On the other hand, the FIFO
register can read out a plurality of pieces of data in the order of
storing them; specifically, four pieces of data, A, B, C, and D,
which are stored in this order can be read out in the order of A,
B, C, and D.
[0017] That is, one embodiment of the present invention is a
semiconductor device including: a register electrically connected
to a first transmission path and a second transmission path; a
reading/writing circuit electrically connected to the first
transmission path and the second transmission path; a nonvolatile
FILO register electrically connected to the second transmission
path; a control circuit configured to control the nonvolatile FILO
register; and a control signal line electrically connecting the
nonvolatile FILO register and the control circuit.
[0018] Data is written to the register through the first
transmission path, and data stored in the register is read out to
the first transmission path or the second transmission path.
[0019] The reading/writing circuit is configured to write data read
from the second transmission path to the first transmission
path.
[0020] The nonvolatile FILO register operates in a first mode in
which data is written through the second transmission path to the
nonvolatile FILO register and a second mode in which data stored in
the nonvolatile FILO register is read out to the second
transmission path.
[0021] The control circuit outputs a mode control signal through
the control signal line to switch the first mode and the second
mode of the nonvolatile FILO register.
[0022] With such a structure, data written to the register can be
stored in the nonvolatile FILO register. Since the power
consumption of the nonvolatile FILO register in a standby state is
low, the memory capacity of the nonvolatile FILO register can be
increased while the power consumption of the semiconductor device
is reduced. Note that data can be transferred between the register
and the nonvolatile FILO register through the second transmission
path even when the first transmission path transfers another data.
As a result, the semiconductor device including the register whose
power consumption is low and from which data can be stored at high
speed can be provided.
[0023] Another embodiment of the present invention is a
semiconductor device having the above structure. The nonvolatile
FILO register includes a plurality of nonvolatile flip-flop
circuits. Each of the plurality of nonvolatile flip-flop circuits
includes: a first terminal; a second terminal; a first control
terminal electrically connected to a first control signal line
functioning as the control signal line; and a second control
terminal electrically connected to a second control signal line
functioning as the control signal line. The first terminal
functions as an input terminal and the second terminal functions as
an output terminal in response to a first mode control signal input
to the first control terminal, and the first terminal functions as
the output terminal and the second terminal functions as the input
terminal in response to a second mode control signal. Stored first
data is output to the output terminal and second data is input from
the input terminal in response to a clock signal input to the
second control terminal in a state where power is supplied. Stored
data is held in a state where power is not supplied.
[0024] The semiconductor device of one embodiment of the present
invention includes a plurality of nonvolatile flip-flop circuits in
which the first control terminals are connected in parallel with
the first control signal line and the second control terminals are
connected in parallel with the second control signal line. In each
of the flip-flop circuits, the input terminal and the output
terminal are interchanged with each other in response to the mode
control signal input from the control circuit through the first
control signal line. The nonvolatile flip-flop circuits are
connected in series with respect to the second transmission path.
The nonvolatile FILO register is formed in this manner.
[0025] Accordingly, by a reduction in the number of kinds of
control signals, the structure of the control circuit can be
simplified, and an increase in the number of the control signal
lines and an increase in the area occupied by the control circuit
or wirings including the control signal lines can be prevented. As
a result, the manufacturing process can be simplified, the capacity
of the nonvolatile FILO register can be increased, or a signal
delay due to an increase in the wiring capacitance can be
prevented. Further, a semiconductor device including the register
whose power consumption is low and from which data can be stored at
high speed can be provided.
[0026] Another embodiment of the present invention is a
semiconductor device having the above structure. The nonvolatile
FILO register includes a nonvolatile flip-flop circuit. The
nonvolatile flip-flop circuit includes: a first component circuit,
a second component circuit, a third component circuit, and a fourth
component circuit each including an A terminal, a B terminal, a C
terminal, a D terminal, and an E terminal. The A terminal and the B
terminal are in a high impedance state when a low potential is
input to the D terminal and a high potential is input to the E
terminal A signal is output to the B terminal in accordance with a
signal input from the A terminal when the high potential is input
to the C terminal and the D terminal and the low potential is input
to the E terminal.
[0027] The nonvolatile flip-flop circuit further includes: a first
capacitor one terminal of which is connected to the B terminal of
the first component circuit, the A terminal of the second component
circuit, the B terminal of the third component circuit, and the A
terminal of the fourth component circuit, and the other terminal of
which is grounded; and a second capacitor one terminal of which is
connected to the B terminal of the second component circuit and the
A terminal of the third component circuit, and the other terminal
of which is grounded.
[0028] The nonvolatile flip-flop circuit further includes: a first
control terminal connected to the D terminal of the first component
circuit, the D terminal of the second component circuit, the E
terminal of the third component circuit, and the E terminal of the
fourth component circuit; and a second control circuit connected to
the C terminal of the first component circuit and the C terminal of
the third component circuit.
[0029] The nonvolatile flip-flop circuit further includes: a first
inverter circuit an input terminal of which is connected to the
first control terminal; and a second inverter circuit an input
terminal of which is connected to the second control terminal.
[0030] The nonvolatile flip-flop circuit further includes: a first
terminal connected to the A terminal of the first component circuit
and the B terminal of the fourth component circuit; and a second
terminal connected to the B terminal of the second component
circuit and the A terminal of the third component circuit.
[0031] The E terminal of the first component circuit, the E
terminal of the second component circuit, the D terminal of the
third component circuit, and the D terminal of the fourth component
circuit are connected to an output terminal of the first inverter
circuit. The C terminal of the second component circuit and the C
terminal of the fourth component circuit are connected to an output
terminal of the second inverter circuit.
[0032] Another embodiment of the present invention is a
semiconductor device having the above structure. Each of the
component circuits in nonvolatile flip-flop circuit in the
nonvolatile FILO register includes: a three-state buffer; a
switching transistor a first electrode of which is connected to an
output terminal of the three-state buffer; an A terminal connected
to an input terminal of the three-state buffer; a B terminal
connected to a second electrode of the switching transistor; a C
terminal connected to a gate electrode of the switching transistor;
a D terminal connected to a mode control signal terminal of the
three-state buffer; and an E terminal connected to an inverted mode
control signal terminal of the three-state buffer.
[0033] A channel formation region of the switching transistor
includes a semiconductor having a wider band gap and low intrinsic
carrier density than silicon.
[0034] The nonvolatile flip-flop circuit included in the
nonvolatile FILO register in the semiconductor device of one
embodiment of the present invention includes a storage node
connected to the first capacitor. The nonvolatile flip-flop circuit
stores data input to the input terminal and outputs data stored in
the nonvolatile flip-flop circuit in response to the clock signal
input to the second control terminal. The input terminal and the
output terminal are interchanged in response to the mode control
signal input to the first control terminal. The inverter circuit
connected to each control terminal generates an inverted signal
inside the inverter circuit.
[0035] From the above, by providing a plurality of flip-flop
circuits connected to the two control signal lines, the capacity of
the nonvolatile FILO register can be increased. As a result, a
semiconductor device in which an increase in the area occupied by a
control circuit or wirings is suppressed, in which a signal delay
due to an increase in wiring capacitance, and which can be
manufactured easily can be provided. The semiconductor device
includes a register whose power consumption is low and from which
data can be stored at high speed.
[0036] The storage node is connected to the second electrode of the
switching transistor whose leakage current in an off state is
extremely small and the high impedance input terminal of the
three-state buffer.
[0037] Consequently, the leakage current of the switching
transistor in an off state can be extremely small, and data in the
storage node can be held for a long time even when power supply is
stopped (in other words, power gating is performed). Further,
driving voltage can be reduced and an increase in power consumption
can be suppressed in comparison with a structure where electric
charge is held in a storage node with the use of a transistor
having a floating gate, for example.
[0038] Another embodiment of the present invention is a
semiconductor device having the above structure. The semiconductor
device further includes a memory access determination circuit. The
memory access determination circuit outputs a wait signal in a
period during which data is written to the nonvolatile FILO
register.
[0039] Since the semiconductor device of one embodiment of the
present invention includes the memory access determination circuit,
a failure in which, before writing data read from the register to
the nonvolatile FILO register is finished, another data is written
to the register can be prevented. As a result, a semiconductor
device with less malfunction, high reliability, and low power
consumption, which includes a register from which data can be
stored at high speed, can be provided.
[0040] Another embodiment of the present invention is a
semiconductor device having the above structure. The nonvolatile
FILO register includes: a nonvolatile external memory device; and a
nonvolatile FIFO register including a first input/output terminal
electrically connected to the second transmission path and a second
input/output terminal connected to the external memory device.
[0041] The nonvolatile FIFO register operates in a first mode and a
second mode. In the first mode, data is written to the nonvolatile
FIFO register from the first input/output terminal and the oldest
data input from the first input/output terminal is read out to the
second input/output terminal.
[0042] Data read from the second input/output terminal of the
nonvolatile FIFO register is written to the external memory
device.
[0043] In the second mode, the latest data input to the nonvolatile
FIFO register from the first input/output terminal is read out to
the first input/output terminal and data is written to the
nonvolatile FIFO from the second input/output terminal.
[0044] Data read by the external memory device is input from the
second input/output terminal of the nonvolatile FIFO register.
[0045] Since the nonvolatile FILO register in the semiconductor
device of one embodiment of the present invention includes the
nonvolatile external memory device and the nonvolatile FIFO
register electrically connected to the external memory device, the
capacity of the nonvolatile FILO register can be made significantly
large. As a result, there is no possibility of an overflow of the
FILO register; thus, a semiconductor device with high reliability
and low power consumption, which includes the register from which
data can be stored at high speed, can be provided.
[0046] According to one embodiment of the present invention, a
semiconductor device including a register whose power consumption
is low can be provided. Further, a processing unit whose operation
speed is high and whose power consumption is low can be
provided.
BRIEF DESCRIPTION OF THE DRAWINGS
[0047] FIGS. 1A to 1C are block diagrams each illustrating the
structure of a semiconductor device of an embodiment.
[0048] FIG. 2 is a block diagram illustrating the structure of a
semiconductor device of an embodiment.
[0049] FIGS. 3A and 3B are block diagrams illustrating the
structure of a semiconductor device of an embodiment.
[0050] FIGS. 4A to 4C are block diagrams illustrating the structure
of a nonvolatile flip-flop applicable to a semiconductor device of
an embodiment.
[0051] FIG. 5 is a circuit diagram illustrating the structure of a
nonvolatile flip-flop applicable to a semiconductor device of an
embodiment.
[0052] FIGS. 6A and 6B are block diagrams illustrating the
structure of a semiconductor device of an embodiment.
[0053] FIG. 7 is a timing chart showing the operations of a
nonvolatile flip-flop applicable to a semiconductor device of an
embodiment.
[0054] FIG. 8 illustrates the structure of a semiconductor device
of an embodiment.
[0055] FIGS. 9A and 9B each illustrate the structure of a
nonvolatile FIFO circuit of an embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0056] Embodiments will be described in detail with reference to
the accompanying drawings. Note that the present invention is not
limited to the following description, and it will be easily
understood by those skilled in the art that various changes and
modifications can be made without departing from the spirit and
scope of the present invention. Therefore, the present invention
should not be construed as being limited to the description in the
following embodiments. In the structures described below, the same
portions or portions having similar functions are denoted by the
same reference numerals in different drawings, and explanation
thereof will not be repeated.
Embodiment 1
[0057] In this embodiment, the structure of a semiconductor device
of one embodiment of the present invention will be described with
reference to FIGS. 1A to 1C. FIG. 1A is a block diagram
illustrating the structure of a semiconductor device of one
embodiment of the present invention, FIG. 1B is a block diagram
illustrating the structure of a semiconductor device of another
embodiment of the present invention, and FIG. 1C is a block diagram
illustrating the structure of a semiconductor device of yet another
embodiment of the present invention.
[0058] The semiconductor device illustrated in FIG. 1A includes a
register 210 electrically connected to a first transmission path
150 and a second transmission path 160, a reading/writing circuit
120 electrically connected to the first transmission path 150 and
the second transmission path 160, a nonvolatile FILO register 220
electrically connected to the second transmission path 160, a
control circuit 110 controlling the nonvolatile FILO register 220,
and a control signal line 111 electrically connecting the
nonvolatile FILO register 220 and the control circuit 110.
[0059] To the register 210, data can be written through the first
transmission path 150. Further, data stored in the register 210 can
be read out to the first transmission path 150 or the second
transmission path 160.
[0060] By the reading/writing circuit 120, data read out from the
second transmission path 160 can be written to the first
transmission path 150.
[0061] The nonvolatile FILO register 220 operates in a first mode
in which data is written to the nonvolatile FILO register 220
through the second transmission path 160 and a second mode in which
data stored in the nonvolatile FILO register 220 is read out to the
second transmission path 160.
[0062] The control circuit 110 outputs a mode control signal
through the control signal line 111 to switch the first mode and
the second mode of the nonvolatile FILO register 220.
[0063] In the semiconductor device 100 described in this
embodiment, data written to the register 210 can be stored in the
nonvolatile FILO register 220. Since the power consumption of the
nonvolatile FILO register 220 in a standby state is low, the memory
capacity of the nonvolatile FILO register 220 can be increased
while the power consumption of the semiconductor device 100 is
reduced. Note that data can be transferred between the register 210
and the nonvolatile FILO register 220 through the second
transmission path 160 even when the first transmission path 150
transfers another data. As a result, the semiconductor device 100
including the register 210 whose power consumption is low and from
which data can be stored at high speed can be provided.
[0064] The following describes individual components included in
the semiconductor device of one embodiment of the present
invention.
<<Register>>
[0065] The operation speed of the register 210 is preferably
higher; for example, the operation speed of the register 210 is
preferably higher than that of the nonvolatile FILO register 220.
The higher the operation speed of the register 210 is, the higher
the operation speed of the semiconductor device becomes.
[0066] In the case where the register 210 is formed using a
transistor, a variety of semiconductors can be used for a channel
formation region. For example, a semiconductor containing an
element belonging to Group 14 of the periodic table (e.g., Si, Ge,
or SiC), a compound semiconductor (e.g., GaAs or GaP), a
semiconductor having a wider band gap than silicon (e.g., an oxide
semiconductor), or the like can be used. In particular, a
semiconductor having crystallinity is preferable because it has
high mobility and enables the operation speed of the transistor to
be high.
[0067] The register 210 may be a volatile memory circuit which
consumes power in holding data.
[0068] Note that data in the register 210 can be stored in the
nonvolatile FILO register 220. After data in the register 210 is
stored in the nonvolatile FILO register 220, power supply to the
register 210 is stopped so that power consumption can be reduced.
After power supply to the register 210 is restarted, data stored in
the nonvolatile FILO register 220 is restored to the register 210
through the second transmission path 160, the reading/writing
circuit 120, and the first transmission path 150. By such a series
of operations, the state of the register 210 can be returned in an
extremely short time to a state which is the same as that just
before power supply is stopped. As a result, power consumption can
be reduced without a significant reduction in operation speed.
<<Reading/Writing Circuit>>
[0069] The reading/writing circuit 120 writes data read out from
the second transmission path 160 to the first transmission path
150.
<<Nonvolatile FILO Register>>
[0070] The nonvolatile FILO register 220 stores data in the second
transmission path 160 and the stored data is read out to the second
transmission path 160.
[0071] An example of the structure of the nonvolatile FILO register
220 will be described in detail in Embodiment 2.
<<Control Circuit>>
[0072] The control circuit 110 outputs a mode control signal to the
nonvolatile FILO register 220 through the control signal line 111
to control the operation of the nonvolatile FILO register 220.
Specifically, an operation in which data is read out from the
nonvolatile FILO register 220 and an operation in which data is
written to the nonvolatile FILO register 220 are switched.
Modification Example 1
[0073] A modification example of the semiconductor device described
in this embodiment of the present invention will be described with
reference to FIG. 1B.
[0074] A semiconductor device 100B illustrated in FIG. 1B includes
a first memory access determination circuit 214 which outputs a
wait signal in a period during which data is written to the
nonvolatile FILO register 220.
[0075] Since the semiconductor device 100B includes the first
memory access determination circuit 214, a failure in which, before
writing data read from the register 210 to the nonvolatile FILO
register 220 is finished, another data is written to the register
210 can be prevented. As a result, a semiconductor device with less
malfunction, high reliability, and low power consumption, which
includes a register from which data can be stored at high speed,
can be provided.
[0076] A memory access determination circuit that can be used in
the modification example of this embodiment will be described
below.
<<Memory Access Determination Circuit>>
[0077] The first memory access determination circuit 214 outputs a
wait signal to a terminal 215 so that an access request for the
register 210 is not made while data read from the register 210 is
written to the nonvolatile FILO register 220. Another circuit
monitors the terminal 215, whereby data can be prevented from being
written to the register 210 at an inappropriate timing.
Modification Example 2
[0078] Another modification example of the semiconductor device
described in this embodiment of the present invention will be
described with reference to FIG. 1C.
[0079] A semiconductor device 100D illustrated in FIG. 1C includes
a second memory access determination circuit 216 which outputs a
wait signal in a period during which data is written to the
nonvolatile FILO register 220.
[0080] Since the semiconductor device 100D includes the second
memory access determination circuit 216, data which is read from
the register 210 and then written to the nonvolatile FILO register
220 is monitored so that a flood of data can be prevented. As a
result, a semiconductor device with less malfunction, high
reliability, and low power consumption, which includes a register
from which data can be stored at high speed, can be provided.
[0081] The second memory access determination circuit 216 that can
be used in the modification example of this embodiment will be
described below.
<<Second Memory Access Determination Circuit>>
[0082] The second memory access determination circuit 216 monitors
data written to the nonvolatile FILO register 220 from the register
210, and outputs a wait signal to a terminal 217 just before the
data is newly written when the volume of the data exceeds the
capacity of the nonvolatile FILO register 220. Another circuit
monitors a wait signal output to the terminal 217, whereby data can
be prevented from being written to the nonvolatile FILO register
220 and can be written to another memory circuit (e.g., a stack
register or an external memory device). As a result, data can be
prevented from being written when the volume of the data exceeds
the capacity of the nonvolatile FILO register 220, and data in the
nonvolatile FILO register 220 can be prevented from being lost.
Further, data writing at an inappropriate timing can be
prevented.
[0083] This embodiment can be implemented in combination with any
of the other embodiments in this specification as appropriate.
Embodiment 2
[0084] In this embodiment, the structure of a nonvolatile FILO
register applicable to a semiconductor device of one embodiment of
the present invention will be described with reference to FIG. 2
and FIGS. 6A and 6B. FIG. 2 is a block diagram illustrating the
structure of a semiconductor device handling 1-bit data in one
embodiment of the present invention, and FIGS. 6A and 6B are block
diagrams illustrating the structure of a nonvolatile FILO register
220E applicable to a semiconductor device handling k-bit (k is a
natural number of 2 or more) data in one embodiment of the present
invention.
[0085] The nonvolatile FILO register 220 described in this
embodiment is a shift register in which the shift direction is
inverted depending on a mode control signal input through a first
control signal line 111_1. The nonvolatile FILO register 220 is
formed of a nonvolatile flip-flop circuit, and can hold data even
without power supply. Thus, the memory capacity of the register can
be increased while an increase in power consumption is
suppressed.
<Structure of Nonvolatile FILO Register>
[0086] The nonvolatile FILO register 220 includes n (n is a natural
number of 2 or more) nonvolatile flip-flop circuits. In FIG. 2, a
first nonvolatile flip-flop circuit 224a, a second nonvolatile
flip-flop circuit 224b, a third nonvolatile flip-flop circuit 224c,
and an n-th nonvolatile flip-flop circuit 224n are illustrated.
[0087] Each of the nonvolatile flip-flop circuits includes a first
terminal, a second terminal, a first control terminal, and a second
control terminal.
[0088] For example, the first nonvolatile flip-flop circuit 224a
includes a first terminal 271a, a second terminal 272a, a first
control terminal 261a, and a second control terminal 262a. The
second nonvolatile flip-flop circuit 224b includes a first terminal
271b and a second terminal 272b.
[0089] These nonvolatile flip-flop circuits hold stored data even
without power supply. One of the first terminal and the second
terminal functions as an input terminal and the other thereof
functions as an output terminal in response to a mode control
signal input to the first control terminal in the state where power
is supplied, and the nonvolatile flip-flop circuit outputs stored
first data to the output terminal and stores second data input from
the input terminal in response to a clock signal input to the
second control terminal.
[0090] For example, in the first flip-flop circuit, the first
terminal 271a functions as an input terminal and the second
terminal 272a functions as an output terminal in response to a
first mode control signal input to the first control terminal 261a.
Further, in response to a clock signal input to the second control
terminal 262a, stored first data is output to the second terminal
272a, and second data is input from the first terminal 271a to be
stored. The second terminal 272a functions as an input terminal and
the first terminal 271a functions as an output terminal in response
to a second mode control signal input to the first control terminal
261a. Further, in response to a clock signal input to the second
control terminal 262a, stored third data is output to the first
terminal 271a, and fourth data is input from the second terminal
272a to be stored.
[0091] The first control terminal of each of the nonvolatile
flip-flop circuits is electrically connected to the first control
signal line 111_1, and the second control terminal thereof is
electrically connected to a second control signal line 111_2.
[0092] The first terminal 271a of the first nonvolatile flip-flop
circuit 224a is electrically connected to the second transmission
path 160, and the second terminal 272a thereof is electrically
connected to the first terminal 271b of the second nonvolatile
flip-flop circuit 224b. The second terminal 272b of the second
nonvolatile flip-flop circuit 224b is electrically connected to a
first terminal 271c of the third nonvolatile flip-flop circuit
224c.
<Operation of Nonvolatile FILO Register>
[0093] The operation of the nonvolatile FILO register 220 in this
embodiment will be described.
[0094] When the first mode control signal is input to the
nonvolatile FILO register 220 through the first control signal line
111_1, the first terminal of the nonvolatile flip-flop circuit
functions as an input terminal and the second terminal thereof
functions as an output terminal.
[0095] In other words, the second terminal functioning as an output
terminal of the m-th (m is a natural number greater than or equal
to 1 and less than or equal to (n-1)) nonvolatile flip-flop circuit
is connected to the first terminal functioning as an input terminal
of the (m+1)-th nonvolatile flip-flop circuit. The plurality of
nonvolatile flip-flop circuits connected in series with respect to
the second transmission path 160 functions as a shift register in
which data is shifted from the m-th nonvolatile flip-flop circuit
to the (m+1)-th nonvolatile flip-flop circuit in response to a
clock signal input to the second control signal line 111_2.
[0096] When the second mode control signal is input to the
nonvolatile FILO register 220 through the first control signal line
111_2, the first terminal of the nonvolatile flip-flop circuit
functions as an output terminal and the second terminal thereof
functions as an input terminal.
[0097] In other words, the first terminal functioning as an output
terminal of the (m+1)-th nonvolatile flip-flop circuit is connected
to the second terminal functioning as an input terminal of the m-th
nonvolatile flip-flop circuit. The plurality of nonvolatile
flip-flop circuits connected in series with respect to the second
transmission path 160 functions as a shift register in which data
is shifted from the (m+1)-th nonvolatile flip-flop circuit to the
m-th nonvolatile flip-flop circuit in response to a clock signal
input to the second control signal line 111_2.
[0098] The semiconductor device described in this embodiment
includes a plurality of nonvolatile flip-flop circuits in which the
first control terminals are connected in parallel with the first
control signal line 111_1 and the second control terminals are
connected in parallel with the second control signal line 111_2. In
each of the nonvolatile flip-flop circuits, the input terminal and
the output terminal are interchanged with each other in response to
the mode control signal input from the control circuit 110 through
the first control signal line 111_1. The nonvolatile flip-flop
circuits are connected in series with respect to the second
transmission path 160. The nonvolatile FILO register is formed in
this manner.
[0099] Accordingly, by a reduction in the number of kinds of
control signals, the structure of the control circuit 110 can be
simplified, and an increase in the number of the control signal
lines 111 and an increase in the area occupied by the control
circuit 110 or wirings including the control signal lines 111 can
be prevented. As a result, the manufacturing process can be
simplified, the capacity of the nonvolatile FILO register 220 can
be increased, or a signal delay due to an increase in the wiring
capacitance can be prevented.
[0100] With the use of the nonvolatile FILO register 220 including
the plurality of nonvolatile flip-flop circuits and the register
210, the semiconductor device 100 including the register 210 whose
power consumption is reduced and from which data can be stored at
high speed can be provided.
[0101] Individual components of the nonvolatile FILO register
applicable to the semiconductor device of one embodiment of the
present invention will be described below.
<<Nonvolatile Flip-Flop Circuit>>
[0102] The nonvolatile flip-flop circuits can be formed using a
variety of rewritable nonvolatile memory circuits.
[0103] A rewritable nonvolatile memory circuit can be formed using,
for example, a transistor whose leakage current in an off state is
extremely small described in Embodiment 4 as well as a rewritable
nonvolatile memory element such as a magnetoresistive random access
memory, a ferroelectric memory, a flash memory, a phase change
memory, or a resistive random access memory.
<<Control Circuit>>
[0104] The control circuit 110 outputs a mode control signal to
switch the writing operation and the reading operation of the
nonvolatile FILO register. Since the plurality of nonvolatile
flip-flop circuits is connected to the first control signal line
111_1 in parallel with the control circuit 110, the operation of
the nonvolatile FILO register can be controlled with a smaller
number of control signals and a smaller number of control signal
lines.
[0105] Accordingly, the structure of the control circuit 110 can be
simplified, and an increase in the number of the control signal
lines 111 and an increase in the area occupied by the control
circuit 110 or wirings including the control signal lines 111 can
be prevented. As a result, the manufacturing process can be
simplified, the capacity of the nonvolatile FILO register 220 can
be increased, or a signal delay due to an increase in the wiring
capacitance can be prevented.
[0106] A method in which data written to a register is stored in a
stack memory has been conventionally known. In this method, in the
case where an address space in part of an external memory circuit
such as a cache memory is used for a stack memory, a decoder
specifying an address is needed in addition to a writing circuit
and a reading circuit. An address line, an enable signal line, and
the like are further needed in addition to a clock signal line
providing an instruction for reading or writing.
[0107] For example, a 1 MB (2.sup.23-bit) stack memory needs as
many as 23 address lines.
[0108] On the other hand, in the semiconductor device 100 in this
embodiment, the nonvolatile FILO register 220 is provided together
with the register 210; thus, only the first control signal line
111_1 transmitting a mode control signal and the second control
signal line 111_2 transmitting a clock signal for an instruction
for reading or writing are needed. There is no particular
limitation on the control circuit 110 as long as it supplies a mode
control signal and a clock signal to the nonvolatile FILO register
220 in accordance with a reading/writing signal; thus, the
structure of the control circuit 110 can be made simple in
comparison with a conventional control circuit controlling a stack
memory.
Modification Example
[0109] A semiconductor device 100E described in this embodiment of
the present invention will be described with reference to FIGS. 6A
and 6B. Specifically, the semiconductor device 100E in FIG. 6A can
handle k-bit (k is a natural number of 2 or more) data, which is
different from the semiconductor device 100 in FIG. 2 handling
1-bit data. Note that the semiconductor device 100E can handle, in
addition to data, part of data, large-scale information such as a
program, and part of a program.
[0110] The semiconductor device 100E illustrated in FIG. 6A is a
modification example of the semiconductor device 100 illustrated in
FIG. 2, and their structures have a lot in common. Therefore, the
description of the semiconductor device 100 is referred to for
common portions, and different portions are mainly described
below.
[0111] A transmission path 160E in the semiconductor device 100E
includes k transmission lines; thus, k-bit data can be transmitted,
which is different from the 1-bit semiconductor device 100.
Further, the nonvolatile FILO register 220E in the semiconductor
device 100E can store k-bit data.
[0112] An example of the structure of the nonvolatile FILO register
220E is illustrated in FIG. 6B.
<<Structure of Nonvolatile FILO Register Capable of Storing
k-bit Data>>
[0113] The nonvolatile FILO register 220E includes N (N is a
natural number of 2 or more) nonvolatile memory circuits. In FIG.
6B, a first nonvolatile memory circuit 224A, a second nonvolatile
memory circuit 224B, and an N-th nonvolatile memory circuit 224N
are illustrated.
[0114] Each of the nonvolatile memory circuits includes k
nonvolatile flip-flop circuits. For example, k nonvolatile
flip-flop circuits (224A_1 to 224A_k) are provided in the first
nonvolatile memory circuit 224A, k nonvolatile flip-flop circuits
(224B_1 to 224B_k) are provided in the second nonvolatile memory
circuit 224B, and k nonvolatile flip-flop circuits (224N_1 to
224N_k) are provided in the N-th nonvolatile memory circuit
224N.
[0115] A first terminal of the j-th (j is a natural number greater
than or equal to 1 and less than or equal to k) nonvolatile
flip-flop circuit in the first nonvolatile memory circuit 224A is
electrically connected to the j-th transmission line 160E_j in the
transmission path 160E. A second terminal of the j-th nonvolatile
flip-flop circuit in the M-th (M is a natural number greater than
or equal to 1 and less than or equal to (N-1)) nonvolatile memory
circuit is electrically connected to a first terminal of the j-th
nonvolatile flip-flop circuit in the (M+1)-th nonvolatile memory
circuit. In other words, N nonvolatile flip-flop circuits connected
in series with respect to the j-th transmission line 160E_j form a
shift register.
[0116] The k transmission lines in the transmission path 160E are
each provided with a shift register, and the nonvolatile FILO
register 220E includes k shift registers.
[0117] Accordingly, the semiconductor device 100E can handle k-bit
data. By a reduction in the number of kinds of control signals, the
structure of the control circuit 110 can be simplified, and an
increase in the number of the control signal lines 111 and an
increase in the area occupied by the control circuit 110 or wirings
including the control signal lines 111 can be prevented. As a
result, the manufacturing process can be simplified, the capacity
of the k-bit nonvolatile FILO register 220E can be increased, or a
signal delay due to an increase in the wiring capacitance can be
prevented.
[0118] This embodiment can be implemented in combination with any
of the other embodiments in this specification as appropriate.
Embodiment 3
[0119] In this embodiment, the structure of a semiconductor device
of one embodiment of the present invention will be described with
reference to FIGS. 3A and 3B. FIG. 3A is a block diagram
illustrating the structure of the semiconductor device of one
embodiment of the present invention, and FIG. 3B is a block diagram
illustrating the structure of an FIFO register that can be used in
the semiconductor device.
[0120] In a semiconductor device 100C illustrated in FIG. 3A, a
nonvolatile FILO register includes a nonvolatile external memory
device 290 and a nonvolatile FIFO register 280 including a first
input/output terminal 281 electrically connected to the second
transmission path 160 and a second input/output terminal 282
connected to the external memory device 290.
[0121] The nonvolatile FIFO register 280 operates in a first mode
and a second mode.
[0122] To the nonvolatile FIFO register 280, data can be written
from the first input/output terminal 281 in the first mode.
Further, the oldest data input from the first input/output terminal
281 can be transmitted to the second input/output terminal 282.
Data read from the second input/output terminal 282 of the
nonvolatile FIFO register 280 is written to the external memory
device 290.
[0123] In the nonvolatile FIFO register 280, in the second mode,
the latest data input from the first input/output terminal 281 is
read out to the first input/output terminal 281 and data is written
from the second input/output terminal 282. Data read by the
external memory device 290 is input to the second input/output
terminal 282 of the nonvolatile FIFO register 280.
[0124] Since the nonvolatile FILO register in the semiconductor
device 100C includes the nonvolatile external memory device 290 and
the nonvolatile FIFO register 280 electrically connected to the
external memory device 290, the capacity of the nonvolatile FILO
register can be made significantly large. As a result, there is no
possibility of an overflow of the FILO register; thus, a
semiconductor device with high reliability and low power
consumption, which includes the register from which data can be
stored at high speed, can be provided.
[0125] The following describes individual components included in
the semiconductor device of one embodiment of the present
invention.
<<Nonvolatile FIFO Register>>
[0126] The nonvolatile FIFO register 280 described in this
embodiment is a shift register in which the shift direction is
inverted depending on a mode control signal input through the first
control signal line 111_1. The nonvolatile FIFO register 280 is
formed of a nonvolatile flip-flop circuit, and can hold data even
without power supply. Thus, the memory capacity of the register can
be increased while an increase in power consumption is
suppressed.
[0127] The nonvolatile FIFO register 280 is a modification example
of the nonvolatile FILO register 220 described in Embodiment 2, and
their structures have a lot in common. Therefore, the description
in Embodiment 2 is referred to for common portions, and different
portions are mainly described in this embodiment.
[0128] Specifically, the nonvolatile FIFO register 280 includes n
(n is a natural number of 2 or more) nonvolatile flip-flop circuits
similarly to the nonvolatile FILO register 220 described in
Embodiment 2. The nonvolatile FIFO register 280 has the same
structure as the nonvolatile FILO register 220 except that a second
terminal 272n of the n-th nonvolatile flip-flop circuit is
electrically connected to the nonvolatile external memory device
290.
<<Operation of Nonvolatile FIFO Register>>
[0129] The operation of the nonvolatile FIFO register 280 in this
embodiment is described in comparison with the operation of the
nonvolatile FILO register 220.
[0130] When a first mode control signal is input to the nonvolatile
FIFO register 280 through the first control signal line 111_1, the
first terminal of the nonvolatile flip-flop circuit functions as an
input terminal and the second terminal thereof functions as an
output terminal.
[0131] The nonvolatile FIFO register 280 operates in the same
manner as the nonvolatile FILO register 220 until the first
nonvolatile flip-flop circuit 224a sequentially stores n pieces of
data from the second transmission path 160.
[0132] The nonvolatile FILO register 220 can store n pieces of data
at most. When the first nonvolatile flip-flop circuit 224a stores
(n+1)-th data, data second from the oldest (second data) is written
to the n-th flip-flop circuit 224n, and the oldest data (first
data) is lost.
[0133] On the other hand, the nonvolatile FIFO register 280 also
can store n pieces of data at most. When the first nonvolatile
flip-flop circuit 224a stores the (n+1)-th data, the n-th flip-flop
circuit 224n outputs the oldest data (first data) to the second
terminal 272n, and the data second from the oldest (second data) is
written to the n-th flip-flop circuit 224n.
[0134] Note that the oldest data (first data) read by the second
terminal 272n is written to the external memory device 290.
[0135] When the second mode control signal is input to the
nonvolatile FILO register 220 or the nonvolatile FIFO register 280
through the first control signal line 111_1, the first terminal of
the nonvolatile flip-flop circuit functions as an output terminal
and the second terminal thereof functions as an input terminal.
[0136] In the nonvolatile FILO register 220, when one piece of data
is read from the first nonvolatile flip-flop circuit 224a, null
data is written to the n-th flip-flop circuit 224n.
[0137] On the other hand, in the nonvolatile FIFO register 280,
when one piece of data is read from the first nonvolatile flip-flop
circuit 224a, the latest data written to the external memory device
290 is written to the n-th flip-flop circuit 224n.
[0138] Note that as the nonvolatile FIFO register 280, for example,
such a high-density nonvolatile FIFO circuit in which a plurality
of latch circuits 284 is connected in series as is illustrated in
FIG. 9A can also be used.
[0139] The nonvolatile FIFO circuit in FIG. 9A shows an example in
which the number of pieces of input data is three, and each of d1,
d2, and d3 corresponds to the second transmission path 160 in FIGS.
3A and 3B. The control circuit 110 can output a plurality of mode
control signals, and ST can be connected to the first control
signal line 111_1 from which a second mode control signal is
output.
[0140] In the case where a third control signal line that is
different from the first control signal line 111_1 and can output a
mode control signal is provided as one of signal lines connected to
the control circuit 110, ST may be connected to the third control
signal line. To the second control signal line 111_2, .phi.1 is
connected.
[0141] Note that in the case where a fourth control signal line
that is different from the second control signal line 111_2 and
outputs a clock signal is provided as one of the signal lines
connected to the control circuit 110, .phi.1 may be connected to
the second control signal line 111_2 and .phi.2 may be connected to
the fourth control signal line as illustrated in FIG. 9B.
[0142] Note that there is no particular limitation on the structure
of a circuit 283 as long as it is a D-FF circuit and is a D-type
flip-flop circuit.
[0143] The nonvolatile FIFO circuit includes a transistor whose
leakage current in an off state is extremely small described in
Embodiment 4. Therefore, by stacking such a transistor and a
transistor which includes silicon or the like (a transistor forming
a buffer, an inverter 285, or the like) and is a component element
of the nonvolatile FIFO circuit, the area occupied by the
nonvolatile FIFO circuit can be reduced.
[0144] Further, a structure in which the nonvolatile FIFO circuit
is added to the semiconductor device of one embodiment of the
present invention may also be employed. For example, by using the
nonvolatile FIFO circuit for a nonvolatile memory device, the
operation condition (the state) of the semiconductor device before
and after power gating can be saved. Further, the operation history
or the like of the semiconductor device, which is needed for
analysis of the cause of breakdown of the semiconductor device, can
be sequentially saved.
<<Nonvolatile External Memory Device>>
[0145] There is no particular limitation on the external memory
device 290 as long as it is rewritable and nonvolatile. A
rewritable nonvolatile memory circuit can be formed using, for
example, a DRAM including a transistor whose leakage current in an
off state is extremely small described in Embodiment 4, a NAND
memory circuit, or a NOR memory circuit as well as a rewritable
nonvolatile memory element such as a magnetoresistive random access
memory, a ferroelectric memory, a flash memory, a phase change
memory, or a resistive random access memory.
[0146] This embodiment can be implemented in combination with any
of the other embodiments in this specification as appropriate.
Embodiment 4
[0147] In this embodiment, the structure of a nonvolatile flip-flop
circuit applicable to an FILO register in a semiconductor device of
one embodiment of the present invention will be described with
reference to FIGS. 4A to 4C. FIG. 4A is a circuit diagram
illustrating the structure of the nonvolatile flip-flop circuit
applicable to a semiconductor device of one embodiment of the
present invention, FIG. 4B illustrates the arrangement of terminals
in a component circuit in FIG. 4A, and FIG. 4C illustrates an
example of the component circuit.
[0148] The nonvolatile flip-flop circuit in this embodiment
includes four component circuits (component circuits 250a to 250d)
(see FIG. 4A).
[0149] Each of the component circuits includes an A terminal, a B
terminal, a C terminal, a D terminal, and an E terminal. The A
terminal and the B terminal are in a high impedance state when a
low potential is input to the D terminal and a high potential is
input to the E terminal A signal is output to the B terminal in
accordance with a signal input from the A terminal when the high
potential is input to the C terminal and the D terminal and the low
potential is input to the E terminal (see FIG. 4B).
[0150] One terminal of a first capacitor 253a is connected to a B
terminal of the first component circuit 250a, an A terminal of the
second component circuit 250b, a B terminal of the third component
circuit 250c, and an A terminal of the fourth component circuit
250d, and the other terminal thereof is grounded.
[0151] One terminal of a second capacitor 253b is connected to a B
terminal of the second component circuit 250b and an A terminal of
the third component circuit 250c, and the other terminal thereof is
grounded.
[0152] A first control terminal 261 is connected to a D terminal of
the first component circuit 250a, a D terminal of the second
component circuit 250b, an E terminal of the third component
circuit 250c, and an E terminal of the fourth component circuit
250d.
[0153] A second control terminal 262 is connected to a C terminal
of the first component circuit 250a and a C terminal of the third
component circuit 250c.
[0154] An input terminal of a first inverter circuit 255a is
connected to the first control terminal 261, and an input terminal
of a second inverter circuit 255b is connected to the second
control terminal 262.
[0155] A first terminal 271 is connected to an A terminal of the
first component circuit 250a and a B terminal of the fourth
component circuit 250d, and a second terminal 272 is connected to
the B terminal of the second component circuit 250b and the A
terminal of the third component circuit 250c.
[0156] An output terminal of the first inverter circuit 255a is
connected to an E terminal of the first component circuit 250a, an
E terminal of the second component circuit 250b, a D terminal of
the third component circuit 250c, and a D terminal of the fourth
component circuit 250d. An output terminal of the second inverter
circuit 255b is connected to a C terminal of the second component
circuit 250b and a C terminal of the fourth component circuit
250d.
[0157] The nonvolatile flip-flop circuit 224 that can be used in
the nonvolatile FILO register in the semiconductor device of one
embodiment of the present invention includes a storage node
connected to the first capacitor 253a. The nonvolatile flip-flop
circuit 224 stores data input to the input terminal and outputs
data stored in the nonvolatile flip-flop circuit 224 in response to
a clock signal input to the second control terminal 262. The input
terminal and the output terminal are interchanged in response to a
mode control signal input to the first control terminal 261. The
inverter circuit connected to each control terminal generates an
inverted signal inside the inverter circuit.
[0158] Accordingly, by providing the plurality of flip-flop
circuits, the capacity of the nonvolatile FILO register can be
increased while the number of the control signal lines does not
need to be three or more. As a result, a semiconductor device in
which an increase in the area occupied by a control circuit or a
wiring can be suppressed, in which a delay in signal due to an
increase in wiring capacitance can be suppressed, and which can be
manufactured easily can be provided, or a semiconductor device
including a register from which data can be stored at high speed
and whose power consumption is reduced can be provided.
[0159] The following describes individual components included in
the semiconductor device of one embodiment of the present
invention.
<<Component Circuit>>
[0160] The component circuit is also referred to as a latch
circuit. In the component circuit, the A terminal and the B
terminal are in a high impedance state when the low-potential is
input to the D terminal and the high-potential is input to the E
terminal, and a signal is output to the B terminal in accordance
with a signal input from the A terminal when the high-potential is
input to each of the C terminal and the D terminal and the
low-potential is input to the E terminal (see FIG. 4B).
[0161] The first component circuit 250a will be described as an
example of the configuration of a component circuit that can be
used in this embodiment with reference to FIG. 4C.
[0162] The first component circuit 250a includes a first
three-state buffer 252a and a first switching transistor 251a whose
first electrode is connected to an output terminal of the first
three-state buffer 252a.
[0163] The A terminal of the first component circuit 250a is
connected to an input terminal of the first three-state buffer
252a, the B terminal thereof is connected to a second electrode of
the first switching transistor 251a, and the C terminal thereof is
connected to a gate electrode of the first switching transistor
251a. Further, the D terminal of the first component circuit 250a
is connected to a mode control signal terminal of the first
three-state buffer 252a, and the E terminal thereof is connected to
an inverted mode control signal terminal of the first three-state
buffer 252a.
<<Switching Transistor>>
[0164] The first switching transistor 251a is a transistor whose
leakage current in an off state is extremely small. The transistor
that can be used as the first switching transistor 251a includes,
for example, a semiconductor having wider band gap and lower
intrinsic carrier density than silicon.
[0165] A semiconductor having wider band gap and lower intrinsic
carrier density than silicon, which can be used for a region where
a channel is formed in the first switching transistor 251a, will be
described in detail in Embodiment 5.
<<Three-State Buffer>>
[0166] The first three-state buffer 252a outputs a signal to the
output terminal in accordance with a signal input to the input
terminal through the A terminal of the component circuit when the
high-level potential is input through the D terminal of the
component circuit and the low-level potential is input through the
E terminal of the component circuit. Specifically, a logical value
input to the input terminal through the A terminal is inverted, and
the inverted logical value is output to the output terminal.
[0167] The input terminal and the output terminal of the first
three-state buffer 252a are in a high impedance state when the
low-level potential is input through the D terminal of the first
component circuit 250a and the high-level potential is input
through the E terminal of the first component circuit 250a.
[0168] In the first three-state buffer 252a, current does not leak
through the high impedance input terminal. For example, a gate
electrode of a transistor is used as the input terminal.
[0169] The second electrode of the first switching transistor 251a
is electrically connected to the first capacitor 253a through the B
terminal of the first component circuit 250a, at which the storage
node is formed.
[0170] In addition to the B terminal of the first component circuit
250a, the B terminal of the third component circuit 250c, the A
terminal of the second component circuit 250b, and the A terminal
of the fourth component circuit 250d are connected to the storage
node.
[0171] As a result, the storage node is connected to the second
electrode of the switching transistor whose leakage current in an
off state is extremely small and to the high impedance input
terminal of the three-state buffer; thus, data can be held for a
long time even after power supply is stopped.
[0172] With the use of a switching transistor whose leakage current
in an off state is extremely small, power consumed at the time of
data writing can be reduced and thus an increase in power
consumption can be suppressed in comparison with a ferroelectric
memory or a flash memory.
[0173] FIG. 5 is a circuit diagram of the nonvolatile flip-flop
circuit 224 to which the component circuits illustrated in FIG. 4C
are applied to the structure illustrated in FIG. 4A.
[0174] The flip-flop circuit 224 includes the first three-state
buffer 252a, the first switching transistor 251a, a second
three-state buffer 252b, a second switching transistor 251b, a
third three-state buffer 252c, a third switching transistor 251c, a
fourth three-state buffer 252d, and a fourth switching transistor
251d.
[0175] Note that a node where the second electrode of the first
switching transistor 251a, the one terminal of the first capacitor
253a, an input terminal of the second three-state buffer 252b, a
second terminal of the third switching transistor 251c, and an
input terminal of the fourth three-state buffer 252d are connected
to one another is referred to as NODE_A.
[0176] Further, a node where a second electrode of the second
switching transistor 251b, the one terminal of the second capacitor
253b, and an input terminal of the third three-state buffer 252c
are connected to one another is referred to as NODE_B. Note that
NODE_B is connected to the second terminal 272 of the flip-flop
circuit 224.
[0177] An example of the operation of the nonvolatile flip-flop
circuit 224 will be described with reference to a timing chart
shown in FIG. 7.
<Operation Method of Nonvolatile Flip-Flop Circuit>
[0178] In a first operation period T1, a first mode control signal
(a high potential) is input to the first control terminal 261. The
first three-state buffer 252a and the second three-state buffer
252b are on, and the third three-state buffer 252c and the fourth
three-state buffer 252d are off. As a result, the first terminal
271 of the nonvolatile flip-flop circuit 224 functions as an input
terminal, and the second terminal 272 thereof functions as an
output terminal.
[0179] In a period T1_1 in the first operation period T1, a low
potential is input to the first terminal 271 of the nonvolatile
flip-flop circuit 224. The first three-state buffer 252a in an on
state inverts the low potential input to the input terminal, and
outputs the high potential to the first terminal of the first
switching transistor 251a connected to the output terminal.
[0180] In the period T1_1, a clock signal having the high potential
is input to the gate electrode of the first switching transistor
251a from the second control terminal 262. The first switching
transistor 251a is on, and the potential of NODE_A depends on a
potential input to the first terminal of the first switching
transistor 251a (here, high potential).
[0181] Next, in a period T1_2 in the first operation period T1, a
clock signal having the low potential is input to the gate
electrode of the first switching transistor 251a from the second
control terminal 262. The first switching transistor 251a is off,
and the high potential is stored in NODE_A.
[0182] The second three-state buffer 252b in an on state inverts
the potential of NODE_A (high potential), and outputs the low
potential to the first terminal of the second switching transistor
251a connected to the output terminal.
[0183] The second inverter circuit 255b inverts a clock signal
input to the second control terminal 262.
[0184] In the period T1_2, a clock signal which is the inverted
signal of the clock signal having the low potential (that is, a
clock signal having the high potential) is input to a gate
electrode of the second switching transistor 251b. The second
switching transistor 251b is on, and the potential of NODE_B
depends on a potential input to the first terminal of the second
switching transistor 251b (here, low potential).
[0185] As a result, the nonvolatile flip-flop circuit 224 outputs
the low potential to the second terminal 272 connected to
NODE_B.
[0186] From the above, it is clear that the low potential input to
the first terminal 271 of the nonvolatile flip-flop circuit 224 is
stored in the second terminal 272 in a period from the period T1_1
through the period T1_2 of the first operation period T1.
[0187] Then, in a period T1_3 and a period T1_4 in the first
operation period T1, the high potential is input to the first
terminal 271 of the nonvolatile flip-flop circuit 224. The
nonvolatile flip-flop circuit 224 operates in accordance with the
timing chart show in FIG. 7. As a result, the high potential input
to the first terminal 271 of the nonvolatile flip-flop circuit 224
is stored in the second terminal 272 in a period from the period
T1_3 through the period T1_4 of the first operation period T1.
[0188] In a second operation period T2, power supply is stopped. In
other words, power gating is performed in the nonvolatile flip-flop
circuit 224.
[0189] NODE_A and NODE_B are each connected to the second electrode
of the switching transistor whose leakage current in an off state
is extremely small and the high impedance input terminal. As a
result, the potentials stored in NODE_A and NODE_B are held for a
long time without being lost in comparison with the case of a
structure using a transistor in which silicon is used for a
semiconductor layer as a switching transistor.
[0190] In a third period T3, power supply is restarted. A second
mode control signal (low potential) is input to the first control
terminal 261. The first three-state buffer 252a and the second
three-state buffer 252b are off, and the third three-state buffer
252c and the fourth three-state buffer 252d are on. As a result,
the first terminal 271 of the nonvolatile flip-flop circuit 224
functions as an output terminal, and the second terminal 272
thereof functions as an input terminal.
[0191] In a period T3_1 in the third operation period T3, the low
potential or the high potential is input to the second terminal 272
of the nonvolatile flip-flop circuit 224. The third three-state
buffer 252c in an on state inverts the potential input to the input
terminal, and outputs the inverted potential to the first terminal
of the third switching transistor 251c connected to an output
terminal.
[0192] In the period T3_1, a clock signal having the high potential
is input to a gate electrode of the third switching transistor 251c
from the second control terminal 262. The third switching
transistor 251c is on, and the potential of NODE_A depends on a
potential input to the first terminal of the third switching
transistor 251c (here, inverted potential).
[0193] Next, in a period T3_2 in the third operation period T3, a
clock signal having the low potential is input to the gate
electrode of the third switching transistor 251c from the second
control terminal 262. The third switching transistor 251c is off,
and the inverted potential is stored in NODE_A.
[0194] The fourth three-state buffer 252b in an on state inverts
the potential of NODE_A input to the input terminal (inverted
potential), and outputs one of the low potential and the high
potential to a first terminal of the fourth switching transistor
251d connected to the output terminal.
[0195] The second inverter circuit 255b inverts a clock signal
input to the second control terminal 262.
[0196] In the period T3_2, a clock signal which is the inverted
signal of the clock signal having the low potential (that is, a
clock signal having the high potential) is input to a gate
electrode of the fourth switching transistor 251d. The fourth
switching transistor 251d is on, and outputs one of the low
potential and the high potential to the first terminal 271.
[0197] From the above, it is clear that one of the high potential
and the low potential input to the second terminal 272 of the
nonvolatile flip-flop circuit 224 is stored in the first terminal
271 in a period from the period T3_1 through the period T3_2 of the
third operation period T3.
[0198] Then, in a period T3_3 and a period T3_4 in the third
operation period T3, the low potential or the high potential is
input to the second terminal 272 of the nonvolatile flip-flop
circuit 224. The nonvolatile flip-flop circuit 224 operates in
accordance with the timing chart show in FIG. 7. As a result, one
of the high potential and the low potential input to the second
terminal 272 of the nonvolatile flip-flop circuit 224 is stored in
the first terminal 271 in a period from the period T3_3 through the
period T3_4 of the third operation period T3.
[0199] In this manner, in the nonvolatile flip-flop circuit 224, a
potential input to one of the first terminal 271 and the second
terminal 272 later is output to the other thereof.
[0200] This embodiment can be implemented in combination with any
of the other embodiments in this specification as appropriate.
Embodiment 5
[0201] In this embodiment, a semiconductor that can be applied to a
semiconductor device of one embodiment of the present invention and
can be used in a channel formation region of a transistor whose
leakage current in an off state is extremely small will be
described.
[0202] Specifically, the transistor whose channel formation region
includes an oxide semiconductor and whose leakage current in an off
state is extremely small, which is described in this embodiment,
can be used as a switching transistor that will be described in
Embodiment 6.
[0203] An oxide semiconductor has a wide energy gap of 3.0 eV or
more. A transistor including an oxide semiconductor layer obtained
by processing of an oxide semiconductor in an appropriate condition
and a sufficient reduction in carrier density of the oxide
semiconductor can have much smaller leakage current between a
source and a drain in an off state (off-state current) than a
conventional transistor including silicon.
<Oxide Semiconductor>
[0204] An oxide semiconductor to be used preferably contains at
least indium (In) or zinc (Zn). In particular, In and Zn are
preferably contained. As a stabilizer for reducing changes in
electric characteristics of a transistor including the oxide
semiconductor, gallium (Ga) is preferably additionally contained.
Tin (Sn) is preferably contained as a stabilizer. In addition, as a
stabilizer, one or more selected from hafnium (Hf), zirconium (Zr),
titanium (Ti), scandium (Sc), yttrium (Y), and a lanthanoid element
(such as cerium (Ce), neodymium (Nd), or gadolinium (Gd), for
example) is preferably contained.
[0205] As the oxide semiconductor, for example, any of the
following can be used: indium oxide, tin oxide, zinc oxide, an
In--Zn-based oxide, a Sn--Zn-based oxide, an Al--Zn-based oxide, a
Zn--Mg-based oxide, a Sn--Mg-based oxide, an In--Mg-based oxide, an
In--Ga-based oxide, an In--Ga--Zn-based oxide (also referred to as
IGZO), an In--Al--Zn-based oxide, an In--Sn--Zn-based oxide, a
Sn--Ga--Zn-based oxide, an Al--Ga--Zn-based oxide, a
Sn--Al--Zn-based oxide, an In--Hf--Zn-based oxide, an
In--Zr--Zn-based oxide, an In--Ti--Zn-based oxide, an
In--Sc--Zn-based oxide, an In--Y--Zn-based oxide, an
In--La--Zn-based oxide, an In--Ce--Zn-based oxide, an
In--Pr--Zn-based oxide, an In--Nd--Zn-based oxide, an
In--Sm--Zn-based oxide, an In--Eu--Zn-based oxide, an
In--Gd--Zn-based oxide, an In--Tb--Zn-based oxide, an
In--Dy--Zn-based oxide, an In--Ho--Zn-based oxide, an
In--Er--Zn-based oxide, an In--Tm--Zn-based oxide, an
In--Yb--Zn-based oxide, an In--Lu--Zn-based oxide, an
In--Sn--Ga--Zn-based oxide, an In--Hf--Ga--Zn-based oxide, an
In--Al--Ga--Zn-based oxide, an In--Sn--Al--Zn-based oxide, an
In--Sn--Hf--Zn-based oxide, and an In--Hf--Al--Zn-based oxide.
[0206] Here, an In--Ga--Zn-based oxide refers to an oxide mainly
containing In, Ga, and Zn and there is no particular limitation on
the ratio of In:Ga:Zn. The In--Ga--Zn-based oxide may contain a
metal element other than In, Ga, and Zn.
[0207] Alternatively, a material represented by
InMO.sub.3(ZnO).sub.m, (m>0, m is not an integer) may be used as
an oxide semiconductor. Note that M represents one or more metal
elements selected from Ga, Fe, Mn, and Co, or the above-described
element as a stabilizer. Alternatively, as the oxide semiconductor,
a material represented by In.sub.2SnO.sub.5(ZnO).sub.n (n>0, n
is an integer) may be used.
[0208] For example, an In--Ga--Zn-based oxide with an atomic ratio
of In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In:Ga:Zn=2:1:3, or any of
oxides whose composition is in the neighborhood of the above
compositions can be used.
[0209] An oxide semiconductor film may be either single crystal or
non-single-crystal.
<CAAC-OS Film>
[0210] The oxide semiconductor film is preferably a c-axis aligned
crystalline oxide semiconductor (CAAC-OS) film.
[0211] With the use of the CAAC-OS film in a transistor, a change
in electric characteristics of the transistor due to irradiation
with visible light or ultraviolet light is small.
[0212] The CAAC-OS film is described below.
[0213] In an image obtained with a transmission electron microscope
(TEM), for example, crystal parts can be found in the CAAC-OS in
some cases. In most cases, in an image obtained with a TEM, crystal
parts in the CAAC-OS each fit inside a cube whose one side is less
than 100 nm, for example. In an image obtained with a TEM, a
boundary between the crystal parts in the CAAC-OS is not clearly
observed in some cases. Further, in an image obtained with a TEM, a
grain boundary in the CAAC-OS is not clearly observed in some
cases. In the CAAC-OS, since a clear grain boundary does not exist,
for example, segregation of an impurity is unlikely to occur. In
the CAAC-OS, since a clear boundary does not exist, for example,
high density of defect states is unlikely to occur. In the CAAC-OS,
since a clear grain boundary does not exist, for example, a
reduction in electron mobility is unlikely to occur.
[0214] In each of the crystal parts included in the CAAC-OS film,
for example, a c-axis is aligned in a direction parallel to a
normal vector of a surface where the CAAC-OS film is formed or a
normal vector of a surface of the CAAC-OS film. Further, in each of
the crystal parts, metal atoms are arranged in a triangular or
hexagonal configuration when seen from the direction perpendicular
to the a-b plane, and metal atoms are arranged in a layered manner
or metal atoms and oxygen atoms are arranged in a layered manner
when seen from the direction perpendicular to the c-axis. Note
that, among crystal parts, the directions of the a-axis and the
b-axis of one crystal part may be different from those of another
crystal part. In this specification, a term "perpendicular"
includes a range from 80.degree. to 100.degree., preferably from
85.degree. to 95.degree.. In addition, a term "parallel" includes a
range from -10.degree. to 10.degree., preferably from -5.degree. to
5.degree..
[0215] In the CAAC-OS film, distribution of crystal parts is not
necessarily uniform. For example, in the formation process of the
CAAC-OS film, in the case where crystal growth occurs from a
surface side of the oxide semiconductor film, the proportion of
crystal parts in the vicinity of the surface of the oxide
semiconductor film is higher than that in the vicinity of the
surface where the oxide semiconductor film is formed in some
cases.
[0216] Since the c-axes of the crystal parts included in the
CAAC-OS film are aligned in the direction parallel to a normal
vector of a surface where the CAAC-OS film is formed or a normal
vector of a surface of the CAAC-OS film, the directions of the
c-axes may be different from each other depending on the shape of
the CAAC-OS film (the cross-sectional shape of the surface where
the CAAC-OS film is formed or the cross-sectional shape of the
surface of the CAAC-OS film). Note that the direction of c-axis of
the crystal part is the direction parallel to a normal vector of
the surface where the CAAC-OS film is formed or a normal vector of
the surface of the CAAC-OS film. The crystal portion is formed by
deposition or by performing treatment for crystallization such as
heat treatment after deposition.
<Method for Forming CAAC-OS Film>
[0217] There are three methods for forming a CAAC-OS film when the
CAAC-OS film is used as the oxide semiconductor film.
[0218] The first method is to form an oxide semiconductor film at a
temperature higher than or equal to 200.degree. C. and lower than
or equal to 450.degree. C., whereby crystal parts in which the
c-axes are aligned in the direction parallel to a normal vector of
a surface where the oxide semiconductor film is formed or a normal
vector of a surface of the oxide semiconductor film are formed in
the oxide semiconductor film.
[0219] The second method is to form an oxide semiconductor film
with a small thickness and then heat it at a temperature higher
than or equal to 200.degree. C. and lower than or equal to
700.degree. C., whereby crystal parts in which the c-axes are
aligned in the direction parallel to a normal vector of a surface
where the oxide semiconductor film is formed or a normal vector of
a surface of the oxide semiconductor film are formed in the oxide
semiconductor film.
[0220] The third method is to form a first oxide semiconductor film
with a small thickness, then heat it at a temperature higher than
or equal to 200.degree. C. and lower than or equal to 700.degree.
C., and form a second oxide semiconductor film, whereby crystal
parts in which the c-axes are aligned in the direction parallel to
a normal vector of a surface where the oxide semiconductor film is
formed or a normal vector of a surface of the oxide semiconductor
film are formed in the oxide semiconductor film.
[0221] For example, the CAAC-OS film is formed by a sputtering
method using a polycrystalline oxide semiconductor sputtering
target. When ions collide with the sputtering target, a crystal
region included in the sputtering target may be separated from the
target along an a-b plane; in other words, a sputtered particle
having a plane parallel to an a-b plane (flat-plate-like sputtered
particle or pellet-like sputtered particle) may flake off from the
sputtering target. In that case, the flat-plate-like sputtered
particle reaches a substrate while maintaining their crystal state,
whereby the CAAC-OS film can be formed.
[0222] For the deposition of the CAAC-OS film, the following
conditions are preferably used.
[0223] By reducing the amount of impurities entering the CAAC-OS
film during the deposition, the crystal state can be prevented from
being broken by the impurities. For example, the concentration of
impurities (e.g., hydrogen, water, carbon dioxide, or nitrogen)
which exist in a deposition chamber may be reduced. Furthermore,
the concentration of impurities in a deposition gas may be reduced.
Specifically, a deposition gas whose dew point is -80.degree. C. or
lower, preferably -100.degree. C. or lower is used.
[0224] By increasing the substrate heating temperature during the
deposition, migration of a sputtered particle is likely to occur
after the sputtered particle reaches a substrate surface.
Specifically, the substrate heating temperature during the
deposition is higher than or equal to 100.degree. C. and lower than
or equal to 740.degree. C., preferably higher than or equal to
200.degree. C. and lower than or equal to 500.degree. C. By
increasing the substrate heating temperature during the deposition,
when the flat-plate-like sputtered particle reaches the substrate,
migration occurs on the substrate surface, so that a flat plane of
the flat-plate-like sputtered particle is attached to the
substrate.
[0225] Furthermore, it is preferable that the proportion of oxygen
in the deposition gas be increased and the power be optimized in
order to reduce plasma damage at the deposition. The proportion of
oxygen in the deposition gas is 30 vol % or higher, preferably 100
vol %.
[0226] As an example of the sputtering target, an In--Ga--Zn--O
compound target is described below.
[0227] The In--Ga--Zn--O compound target, which is polycrystalline,
is made by mixing InO.sub.X powder, GaO.sub.Y powder, and ZnO.sub.Z
powder in a predetermined molar ratio, applying pressure, and
performing heat treatment at a temperature higher than or equal to
1000.degree. C. and lower than or equal to 1500.degree. C. Note
that X, Y and Z are given positive numbers. Here, the predetermined
molar ratio of InO.sub.X powder to GaO.sub.Y powder and ZnO.sub.Z
powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or
3:1:2. The kinds of powder and the molar ratio for mixing powder
may be determined as appropriate depending on the desired
sputtering target.
[0228] The above is the description of the CAAC-OS film.
<Dehydration Treatment (Dehydrogenation Treatment), Oxygen
Adding Treatment (Treatment for Making Oxygen-Excess State)>
[0229] After formation of the oxide semiconductor film, it is
preferable that dehydration treatment (dehydrogenation treatment)
be performed to remove hydrogen or moisture from the oxide
semiconductor film so that the oxide semiconductor film is highly
purified to contain impurities as little as possible, and that
oxygen be added to the oxide semiconductor film to fill oxygen
vacancies increased by the dehydration treatment (dehydrogenation
treatment). In this specification and the like, supplying oxygen to
an oxide semiconductor film may be expressed as oxygen adding
treatment or treatment for making the oxygen content of an oxide
semiconductor film be in excess of that of the stoichiometric
composition may be expressed as treatment for making an
oxygen-excess state.
[0230] In this manner, hydrogen or moisture is removed from the
oxide semiconductor film by the dehydration treatment
(dehydrogenation treatment) and oxygen vacancies therein are filled
by the oxygen adding treatment, whereby the oxide semiconductor
film can be turned into an i-type (intrinsic) or substantially
i-type oxide semiconductor film. The oxide semiconductor film
formed in such a manner contains extremely few (close to zero)
carriers derived from a donor, and the carrier concentration
therein is lower than 1.times.10.sup.14/cm.sup.3, preferably lower
than 1.times.10.sup.12/cm.sup.3, further preferably lower than
1.times.10.sup.11/cm.sup.3, still further preferably lower than
1.45.times.10.sup.10/cm.sup.3.
[0231] The transistor including the oxide semiconductor layer which
is highly purified by sufficiently reducing the hydrogen
concentration, and in which defect levels in the energy gap due to
oxygen vacancies are reduced by sufficiently supplying oxygen can
achieve extremely excellent off-state current characteristics. For
example, the off-state current (per unit channel width (1 .mu.m)
here) at room temperature (25.degree. C.) is 100 zA (1 zA
(zeptoampere) is 1.times.10.sup.-21 A) or less, preferably 10 zA or
less. The off-state current at 85.degree. C. is 100 zA
(1.times.10.sup.-19 A) or less, preferably 10 zA
(1.times.10.sup.-20 A) or less. In this manner, the transistor
which has extremely favorable off-state current characteristics can
be obtained with the use of an i-type (intrinsic) or substantially
i-type oxide semiconductor layer.
Embodiment 6
[0232] In this embodiment, a structure applicable to a
semiconductor device of one embodiment of the present invention
will be described with reference to FIG. 8. FIG. 8 is a
cross-sectional view illustrating the structure of a semiconductor
device of one embodiment of the present invention. Specifically, in
FIG. 8, a unit memory circuit including a transistor whose leakage
current in an off state is extremely small and a capacitor is
provided over another circuit that is formed through a CMOS
process.
[0233] Note that the transistor whose leakage current in an off
state is extremely small includes the semiconductor described in
Embodiment 5 in a region where a channel is formed.
[0234] In the semiconductor device illustrated in FIG. 8, the unit
memory circuit including a transistor 303 whose leakage current in
an off state is extremely small and a capacitor 302 is provided
over a register including a transistor 301 that is formed through a
CMOS process. Specifically, the transistor 301 including a
semiconductor layer containing a semiconductor belonging to Group
14 of the periodic table (e.g., silicon), the transistor 303
including an oxide semiconductor layer in which a channel is
formed, and the capacitor 302 are provided. Further, a
semiconductor layer 311, an insulating layer 314, a conductive
layer 315, an insulating layer 316, an insulating layer 317, a
connection layer 318, a conductive layer 319a, a conductive layer
319b, a conductive layer 319c, an insulating layer 320, a
connection layer 321, a semiconductor layer 331, an insulating
layer 333, a conductive layer 334, a conductive layer 336a, a
conductive layer 336b, a conductive layer 338, an insulating layer
339, a connection layer 341, and a conductive layer 342 are
provided.
[0235] Note that the structure of the unit memory circuit can be
applied to the nonvolatile flip-flop circuit described in
Embodiment 4. Specifically, the transistor 303 whose leakage
current in an off state is extremely small can be used as the
switching transistor in the component circuit provided in the
nonvolatile flip-flop circuit, and the capacitor 302 can be used as
the capacitor connected to the B terminal of the component circuit
provided in the nonvolatile flip-flop circuit.
[0236] With such a structure, even when power supply to the
flip-flop circuit is stopped or interrupted, data stored in the
flip-flop circuit is not lost. That is, the flip-flop circuit can
function as a nonvolatile circuit. Further, since the transistor
303 and the capacitor 302 can be formed so as to overlap with
another circuit (for example, the register, a first transmission
path, a second transmission path, a reading/writing circuit, a
control circuit, a control signal line, or the like), the area
occupied by the semiconductor device can be reduced even when two
or more unit memory circuits are provided.
[0237] Further, driving voltage can be reduced and an increase in
power consumption can be suppressed in comparison with a structure
where electric charge is held in a storage node with the use of a
transistor having a floating gate.
[0238] The following describes individual components included in
the semiconductor device of one embodiment of the present
invention.
<<Layer Including Transistor Formed through CMOS
Process>>
[0239] The semiconductor layer 311 includes a region 313a and a
region 313b. In addition, adjacent transistors are electrically
isolated by insulating layers 312 in some regions of the
semiconductor layer 311.
[0240] For example, a semiconductor substrate can be used as the
semiconductor layer 311. Alternatively, a semiconductor layer over
a different substrate can be used as the semiconductor layer
311.
[0241] The region 313a and the region 313b are spaced apart from
each other, and a dopant imparting n-type or p-type conductivity is
added to the region 313a and the region 313b. The region 313a and
the region 313b function as a source region and a drain region of
an n-channel or p-channel transistor. For example, the region 313a
and the region 313b are electrically connected to the conductive
layer 319a and the conductive layer 319b, respectively, through the
connection layers 318.
[0242] In the case where the transistor 301 is an n-channel
transistor, an element imparting n-type conductivity is used as the
dopant. In contrast, in the case where the transistor 301 is a
p-channel transistor, an element imparting p-type conductivity is
used as the dopant.
[0243] Note that low-concentration regions may be in parts of the
region 313a and the region 313b. In that case, the
low-concentration regions may be shallower than the rest of the
region 313a and the region 313b; however, this embodiment is not
limited thereto.
[0244] The insulating layer 314 is provided over a region of the
semiconductor layer 311 that is between the insulating layers 312.
The insulating layer 314 functions as a gate insulating layer of
the transistor 301.
[0245] A layer of a material such as silicon oxide, silicon
nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide,
aluminum nitride, aluminum oxynitride, aluminum nitride oxide,
hafnium oxide, or an organic insulating material (e.g., polyimide
or acrylic) can be used as the insulating layer 314, for example.
The insulating layer 314 may be formed by stacking materials that
can be used for the insulating layer 314.
[0246] The conductive layer 315 overlaps with the semiconductor
layer 311 with the insulating layer 314 provided therebetween. A
region of the semiconductor layer 311 that overlaps with the
conductive layer 315 is a channel formation region of the
transistor 301. The conductive layer 315 functions as a gate of the
transistor 301.
[0247] A layer of a metal material such as molybdenum, magnesium,
titanium, chromium, tantalum, tungsten, aluminum, copper,
neodymium, or scandium or an alloy material containing the metal
material as a main component can be used as the conductive layer
315, for example. The conductive layer 315 may be formed by
stacking materials that can be used for the conductive layer
315.
[0248] The insulating layers 316 are provided over the insulating
layer 314 and in contact with a pair of side surfaces of the
conductive layer 315 that face each other.
[0249] The insulating layer 317 is provided over the conductive
layer 315 and the insulating layers 316.
[0250] Each of the insulating layers 316 and 317 can be formed
using any of the materials that can be used for the insulating
layer 314, which may be the same as or different from the material
used for the insulating layer 314. Alternatively, the insulating
layers 316 or the insulating layer 317 can be formed by stacking
materials that can be used for the insulating layers 316 and
317.
[0251] The connection layers 318 are provided to fill openings in
the insulating layer 317 and are electrically connected to the
region 313a and the region 313b.
[0252] The conductive layer 319a, the conductive layer 319b, and
the conductive layer 319c are provided over the insulating layer
317. The conductive layer 319a is electrically connected to the
region 313a through the connection layer 318. The conductive layer
319b is electrically connected to the region 313b through the
connection layer 318. The conductive layer 319c is electrically
connected to the conductive layer 315 through the connection layer
318 (not illustrated).
[0253] Each of the connection layer 318, the conductive layer 319a,
the conductive layer 319b, and the conductive layer 319c can be
formed using any of the materials that can be used for the
conductive layer 315, which may be the same as or different from
the material used for the conductive layer 315. Alternatively, each
of the connection layer 318, the conductive layer 319a, the
conductive layer 319b, and the conductive layer 319c can be formed
by stacking materials that can be used for the connection layer
318, the conductive layer 319a, the conductive layer 319b, and the
conductive layer 319c.
[0254] The insulating layer 320 is provided over the insulating
layer 317, the conductive layer 319a, the conductive layer 319b,
and the conductive layer 319c. The structure of the insulating
layer 320 can be similar to that of the insulating layer 317.
[0255] The connection layer 321 is provided to fill an opening in
the insulating layer 320 and is electrically connected to the
conductive layer 319c. The structure of the connection layer 321
can be similar to that of the connection layer 318.
<<Layer Including Transistor Whose Leakage Current in Off
State is Extremely Small and Capacitor>>
[0256] The semiconductor layer 331 is provided over the insulating
layer 320. For the semiconductor layer 331, the semiconductor
described in Embodiment 5 can be used.
[0257] A region to which a dopant is added may be provided for
regions of the semiconductor layer 331 which overlap with the
conductive layer 336a and the conductive layer 336b. One or more
selected from the following can be used as the dopant: Group 15
elements (typical examples thereof are nitrogen (N), phosphorus
(P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al),
argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F),
chlorine (Cl), titanium (Ti), and zinc (Zn). Note that such a
region is not necessarily provided.
[0258] The conductive layer 336a and the conductive layer 336b are
spaced apart from each other and electrically connected to each
other while being in contact with the semiconductor layer 331. The
conductive layer 336a and the conductive layer 336b function as a
source electrode and a drain electrode of a transistor. The
conductive layer 336b is electrically connected to the connection
layer 321. The conductive layer 336a also functions as one of
electrodes of the capacitor 302.
[0259] The conductive layers 336a and 336b can be formed using a
metal selected from aluminum (Al), chromium (Cr), copper (Cu),
tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W),
neodymium (Nd), scandium (Sc), and the like; an alloy containing
the above metal element; an alloy containing the above metal
elements in combination; a nitride of the above metal element; or
the like. Further, one or more metal elements selected from
manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and
the like may be used.
[0260] The insulating layer 333 is provided over the semiconductor
layer 331, the conductive layer 336a, and the conductive layer
336b. The insulating layer 333 functions as a gate insulating layer
of the transistor. The insulating layer 333 also functions as a
dielectric layer of the capacitor 302.
[0261] The insulating layer 333 can be formed using, for example, a
single layer or a stacked layer using a material selected from
aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum
oxynitride, silicon nitride, silicon oxide, silicon nitride oxide,
silicon oxynitride, tantalum oxide, and lanthanum oxide.
[0262] When a high-k material such as hafnium silicate
(HfSiO.sub.x), hafnium silicate to which nitrogen is added
(HfSi.sub.xO.sub.yN.sub.z), hafnium aluminate to which nitrogen is
added (HfAl.sub.xO.sub.yN.sub.z), hafnium oxide, or yttrium oxide
is used as the insulating layer 333, gate leakage can be reduced by
increasing the physical thickness of a gate insulating film without
changing the substantial thickness (e.g., equivalent silicon oxide
thickness) of the gate insulating film. Further, a stacked
structure can be used in which a high-k material and one or more of
silicon oxide, silicon nitride, silicon oxynitride, silicon nitride
oxide, aluminum oxide, aluminum oxynitride, and gallium oxide are
stacked.
[0263] The conductive layer 334 overlaps with the semiconductor
layer 331 with the insulating layer 333 provided therebetween. The
conductive layer 334 functions as a gate of the transistor.
Further, it is preferable that the conductive layer 334 be provided
so as to partially overlap with the conductive layers 336a and
336b.
[0264] The conductive layer 334 can be formed using a metal
selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum
(Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd),
and scandium (Sc); an alloy containing the above metal element; an
alloy containing the above metal elements in combination; a nitride
of the above metal element; or the like. Further, one or more metal
elements selected from manganese (Mn), magnesium (Mg), zirconium
(Zr), beryllium (Be), and the like may be used.
[0265] In addition, the conductive layer 334 may have a
single-layer structure or a stacked structure of two or more
layers. For example, a single-layer structure of aluminum
containing silicon, a two-layer structure in which titanium is
stacked over aluminum, a two-layer structure in which titanium is
stacked over titanium nitride, a two-layer structure in which
tungsten is stacked over titanium nitride, a two-layer structure in
which tungsten is stacked over tantalum nitride, a two-layer
structure in which Cu is stacked over a Cu--Mg--Al alloy, a
three-layer structure in which titanium, aluminum, and titanium are
stacked in this order, and the like can be given.
[0266] Alternatively, for the conductive layer 334, a
light-transmitting conductive material such as indium tin oxide,
indium oxide containing tungsten oxide, indium zinc oxide
containing tungsten oxide, indium oxide containing titanium oxide,
indium tin oxide containing titanium oxide, indium zinc oxide, or
indium tin oxide to which silicon oxide is added can be used. It is
also possible to employ a stacked structure including the
light-transmitting conductive material and the metal element.
[0267] Gallium oxide, indium gallium zinc oxide containing
nitrogen, indium tin oxide containing nitrogen, indium gallium
oxide containing nitrogen, indium zinc oxide containing nitrogen,
tin oxide containing nitrogen, indium oxide containing nitrogen, or
a metal nitride (e.g., InN or ZnN) may overlap with the conductive
layer 334 and the semiconductor layer 331 and be in contact with
the conductive layer 334 and the insulating layer 333.
[0268] These materials each have a work function of 5 eV or higher,
preferably 5.5 eV or higher. When a layer formed using any of these
materials is provided so as to overlap with the semiconductor layer
331 with the insulating layer 333 provided therebetween, the
threshold voltage of the transistor can be positive. Accordingly, a
so-called normally-off switching element can be obtained. For
example, in the case where In--Ga--Zn--O containing nitrogen is
used, In--Ga--Zn--O having higher nitrogen concentration than at
least the semiconductor layer 331, specifically, In--Ga--Zn--O
having a nitrogen concentration of 7 atomic percent or higher is
used.
[0269] The conductive layer 338 is provided over the conductive
layer 336a with the insulating layer 333 provided therebetween.
[0270] Here, the capacitor 302 is formed using the conductive layer
336a, the insulating layer 333, and the conductive layer 338.
[0271] The insulating layer 339 is provided over the insulating
layer 333 and the conductive layers 334 and 338.
[0272] A material that is similar to the material of the insulating
layer 317 can be used for the insulating layer 339.
[0273] The connection layer 341 is provided to fill an opening in
the insulating layer 339 and is electrically connected to the
conductive layer 338.
[0274] The structure of the connection layer 341 can be similar to
that of the connection layer 318.
[0275] The conductive layer 342 is provided over the insulating
layer 339. The conductive layer 342 is electrically connected to
the conductive layer 338 through the connection layer 341.
[0276] The structure of the conductive layer 342 can be similar to
those of the conductive layer 319a, the conductive layer 319b, and
the conductive layer 319c.
[0277] This embodiment can be implemented in combination with any
of the other embodiments in this specification as appropriate.
[0278] This application is based on Japanese Patent Application
serial no. 2012-125993 filed with Japan Patent Office on Jun. 1,
2012, and Japanese Patent Application serial no. 2013-010751 filed
with Japan Patent Office on Jan. 24, 2013, the entire contents of
which are hereby incorporated by reference.
* * * * *