U.S. patent application number 13/486185 was filed with the patent office on 2013-12-05 for semiconductor device having non-orthogonal element.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC"). The applicant listed for this patent is Kuei-Shun Chen, Chia-Chu Liu, Hong-Jang Wu, Shiao-Chian Yeh. Invention is credited to Kuei-Shun Chen, Chia-Chu Liu, Hong-Jang Wu, Shiao-Chian Yeh.
Application Number | 20130320451 13/486185 |
Document ID | / |
Family ID | 49669186 |
Filed Date | 2013-12-05 |
United States Patent
Application |
20130320451 |
Kind Code |
A1 |
Liu; Chia-Chu ; et
al. |
December 5, 2013 |
SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT
Abstract
The present disclosure provides a device includes a first gate
structure segment and a collinear second gate structure segment, as
well as a third gate structure segment and a collinear fourth gate
structure segment. An interconnection extends from the first gate
structure segment to the fourth gate structure segment. The
interconnection is disposed above the first gate structure segment
and the fourth gate structure segment. The interconnection may be
formed on or co-planar with a contact layer of the semiconductor
device.
Inventors: |
Liu; Chia-Chu; (Shin-Chu
City, TW) ; Yeh; Shiao-Chian; (Kaohsiung City,
TW) ; Wu; Hong-Jang; (Linbian Township, TW) ;
Chen; Kuei-Shun; (Hsin-Chu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Liu; Chia-Chu
Yeh; Shiao-Chian
Wu; Hong-Jang
Chen; Kuei-Shun |
Shin-Chu City
Kaohsiung City
Linbian Township
Hsin-Chu |
|
TW
TW
TW
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd., ("TSMC")
Hsin-Chu
TW
|
Family ID: |
49669186 |
Appl. No.: |
13/486185 |
Filed: |
June 1, 2012 |
Current U.S.
Class: |
257/368 ;
257/E21.409; 257/E27.06; 438/586 |
Current CPC
Class: |
H01L 23/522 20130101;
H01L 21/76895 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; H01L 27/0207 20130101; H01L 29/66545 20130101; H01L
2924/00 20130101; H01L 29/4238 20130101 |
Class at
Publication: |
257/368 ;
438/586; 257/E27.06; 257/E21.409 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 21/336 20060101 H01L021/336 |
Claims
1. A semiconductor device, comprising: a first gate structure
segment and a collinear second gate structure segment; a third gate
structure segment and a collinear fourth gate structure segment;
and an interconnection structure extending from the first gate
structure segment to the fourth gate structure segment, wherein the
interconnection structure is disposed above the first gate
structure segment and the fourth gate structure segment, and
wherein the interconnect structure has a planar bottom surface, the
planar bottom surface extending from on the first gate structure to
on the fourth gate structure.
2. The device of claim 1, wherein the interconnection structure
includes: a first portion disposed on the first gate structure
segment; a second portion disposed on the fourth gate structure
segment, wherein the first and second portions are substantially
parallel; and a third portion connecting the first and second
portions, wherein the third portion is substantially perpendicular
to the first and second portions, wherein each of the first, second
and third portions are co-planar.
3. The device of claim 1, further comprising: a contact plug
co-planar with the interconnection structure.
4. The device of claim 1, further comprising: spacer elements
formed on sidewalls of the first and fourth gate structure
segments, wherein the interconnection structure is disposed on a
top surface of the spacer elements.
5. The device of claim 1, wherein the interconnection structure
includes tungsten.
6. The device of claim 1, wherein the first gate structure segment
is non-orthogonal with respect to a third gate structure segment
such that an imaginary line drawn from a first end of the first
gate structure segment to a first end of the third gate structure
segment is non-orthogonal with respect to a sidewall of the first
gate structure segment.
7. A semiconductor device, comprising: a substrate; a first gate
structure disposed on the substrate; a second gate structure
disposed on the substrate adjacent and parallel to the first gate
structure, wherein the first gate structure is non-orthogonally
disposed with respect to the second gate structure; a third gate
structure aligned with and spaced a first distance from the first
gate structure, wherein the third gate structure is parallel to the
second gate structure; and an interconnection structure extending
between the second gate structure and the third gate structure,
wherein the interconnection structure includes a conductive
material disposed in a single layer extending from the second gate
structure to the third gate structure; and a contact element
connected to one of the first, second and third gate structures,
wherein the conductive material is co-planar with the contact
element.
8. The semiconductor device of claim 7, wherein the first gate
structure is non-orthogonal with respect to the second gate
structure such that an imaginary line drawn from a first end of the
first gate structure to a first end of the second gate structure is
non-orthogonal with respect to a sidewall of at least one of the
first and second gate structures.
9. The semiconductor device of claim 8, wherein the first end of
the first gate structure and the first end of the second gate
structure are disposed on an isolation region.
10. The semiconductor device of claim 7, wherein a first end of the
first gate structure is non-orthogonal with respect to a sidewall
of the first gate structure.
11. The semiconductor device of claim 7, further comprising: a
fourth gate structure aligned with the second gate structure and
spaced a second distance from the second gate structure.
12. The semiconductor device of claim 7, wherein the
interconnection is not co-planar with a plane extending through the
second gate structure and the third gate structure.
13. (canceled)
14. The semiconductor device of claim 11, wherein the first
distance and the second distance are substantially equal, and
wherein the space between the third gate structure and the first
gate structure is offset from the space between the fourth gate
structure and the second gate structure in a direction parallel to
the length of the first gate structure.
15.-20. (canceled)
21. A semiconductor device, comprising: a gate layer formed on a
substrate, the gate layer including: a first gate structure and a
collinear second gate structure; a third gate structure and a
collinear fourth gate structure; and a contact layer disposed above
the gate layer, the contact layer including: an interconnection
structure extending from the first gate structure to the fourth
gate structure; and a contact plug connected one of the first,
second, third and fourth gate structure.
22. The semiconductor device of claim 21, wherein the contact plug
is disposed in a dielectric layer of the contact layer.
23. The semiconductor device of claim 21, wherein the
interconnection structure extending from the first gate structure
to the fourth gate structure includes tungsten.
24. The semiconductor device of claim 21, wherein the
interconnection structure directly interfaces with the first gate
structure and the second gate structure.
25. The device of claim 1, wherein the bottom surface of the
interconnect structure includes tungsten.
Description
BACKGROUND
[0001] The semiconductor integrated circuit (IC) industry has
experienced exponential growth. Technological advances in IC
materials and design have produced generations of ICs where each
generation has smaller and more complex circuits than the previous
generation. In the course of IC evolution, functional density
(i.e., the number of interconnected devices per chip area) has
generally increased while geometry size (i.e., the smallest
component (or line) that can be created using a fabrication
process) has decreased. This scaling down process generally
provides benefits by increasing production efficiency and lowering
associated costs. Such scaling down has also increased the
complexity of processing and manufacturing ICs and, for these
advances to be realized, similar developments in IC processing and
manufacturing are needed.
[0002] One challenge with the decreasing geometry of semiconductor
ICs is the formation of interconnections between elements of a
semiconductor device. These interconnections can take up valuable
area of the layout of a semiconductor device. Thus, what is desired
is a device and method that may reduce the layout area and provide
flexible patterning of interconnections between elements of a
semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is emphasized that, in accordance with the standard
practice in the industry, various features are not drawn to scale.
In fact, the dimensions of the various features may be arbitrarily
increased or reduced for clarity of discussion.
[0004] FIG. 1 is a flow chart of an embodiment of a method of
fabricating a semiconductor device according to one or more aspects
of the present disclosure.
[0005] FIGS. 2-12 illustrate an embodiment of a semiconductor
device according to one or more steps of the method of FIG. 1.
[0006] FIGS. 13-14 illustrate another embodiment of a semiconductor
device according to one or more steps of the method of FIG. 1.
DETAILED DESCRIPTION
[0007] It is to be understood that the following disclosure
provides many different embodiments, or examples, for implementing
different features of the invention. Specific examples of
components and arrangements are described below to simplify the
present disclosure. These are, of course, merely examples and are
not intended to be limiting. Moreover, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed interposing the first and second
features, such that the first and second features may not be in
direct contact. Various features may be arbitrarily drawn in
different scales for simplicity and clarity.
[0008] Illustrated in FIG. 1 is a method 100 of fabricating a
semiconductor device. The method 100 may be useful for fabricating
a semiconductor device having at least one non-orthogonal element.
In an embodiment, the non-orthogonal element is an interconnect,
for example, connecting gate structures. In an embodiment, the
method 100 including a non-orthogonal cut of a plurality of gate
structure elements (e.g., lines or strips). The term non-orthogonal
as used herein may be used to describe any element or method that
includes an inclined or slanted feature (e.g., not at a
substantially right angle or perpendicular to a referenced
feature). The non-orthogonal cut may provide for a non-orthogonal
end of a gate structure. The non-orthogonal cut across adjacent
gate structure elements (strips) may provide a configuration of the
elements such that the ends are not collinear with respect to a
line drawn perpendicular to the length of the gate structures.
FIGS. 2-14 are cross-sectional and top-views of a semiconductor
device 200 fabricated according to embodiments of the method 100 of
FIG. 1.
[0009] It is understood that parts of the method 100 and/or device
200 are provided by complementary metal-oxide-semiconductor (CMOS)
technology process flow, and thus some processes are only briefly
described herein. Further, the semiconductor device 200 may include
various other devices and features, such as additional transistors,
bipolar junction transistors, resistors, capacitors, diodes, fuses,
etc., but is simplified for a better understanding of the inventive
concepts of the present disclosure. The semiconductor device 200
includes a plurality of semiconductor devices (e.g., transistors),
which may be interconnected.
[0010] The method 100 begins at block 102 where a substrate is
provided. The semiconductor substrate may typically be a silicon
substrate. The substrate may include various doping configurations
depending on design requirements as is known in the art. The
substrate may also include other elementary semiconductors such as
germanium and diamond. Alternatively, the substrate may include a
compound semiconductor and/or an alloy semiconductor. Further, the
substrate may optionally include an epitaxial layer (epi layer),
may be strained for performance enhancement, may include a
silicon-on-insulator (SOI) structure, and/or have other suitable
enhancement features. The substrate may include active regions on
which MOS devices can be formed. The active regions may be doped
with suitable n-type or p-type dopants (impurities) to form well
regions. The boundaries of the active regions may be defined by
isolation structures such as shallow trench isolation (STI)
features. In other embodiments, other types of isolation structures
are possible. The substrate may include isolation features such as
a shallow trench isolation (STI), field oxide, a local-oxidation of
silicon (LOCOS) feature, and/or other suitable isolation features.
The isolation structure may be formed of silicon oxide, silicon
nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a
low-k dielectric, combinations thereof, and/or other suitable
material.
[0011] Referring to the examples of FIGS. 2 and 3, a top view of a
semiconductor device 200 having a substrate 202 is provided in FIG.
2. A cross-sectional view of a portion of the semiconductor device
200 is provided in FIG. 3. The substrate 202 includes a plurality
of active regions 204. Isolation features 206 interpose the active
regions 204. As illustrated, the isolation features 206 include STI
features.
[0012] The method 100 then proceeds to block 104 where a plurality
of gate structure elements is formed on the substrate. In an
embodiment, the gate structure elements may be formed a "strips"
extending substantially parallel to one another. The gate structure
elements may include a gate dielectric and/or a gate electrode
layer. In an embodiment, one or more of the layers of the gate
structure elements are sacrificial (e.g., dummy) layers.
[0013] In an embodiment, the gate structure element includes a gate
dielectric layer. In an embodiment, the gate dielectric layer
includes a dielectric material such as silicon oxide, for example,
formed by thermal oxidation or suitable deposition methods. In an
embodiment, the gate dielectric layer includes a high-k dielectric
layer, for example, formed by atomic layer deposition (ALD) or
other suitable technique. The high-k dielectric layer may include
hafnium oxide (HfO.sub.2). Alternatively, the high-k dielectric
layer may include other high-k dielectrics, such as TiO.sub.2,
HfZrO, Ta.sub.2O.sub.3, HfSiO.sub.4, ZrO.sub.2, ZrSiO.sub.2,
combinations thereof, and/or other suitable material. Further, the
gate dielectric layer may include a multiple layer
configuration.
[0014] The gate structure element may further include a gate
electrode. The gate electrode may be sacrificial, for example, such
as formed in a replacement gate process. In an embodiment, the gate
electrode layer includes polysilicon. However, other embodiments
are possible. The polysilicon layer may be formed by suitable
deposition processes such as, for example, low-pressure chemical
vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD).
[0015] Referring to the example of FIGS. 2 and 3, a plurality of
gate structure elements 208 are disposed on the substrate 202. As
illustrated, the gate structure elements 208 are patterned such
that they form strips. The gate structure elements 208 may be
formed by depositing one or more layers of the gate structure
elements. The layers may be patterned using suitable
photolithography processes such as, for example, forming a
photoresist layer, exposing the photoresist layer to a pattern,
baking and developing the photoresist to form masking elements. The
masking elements may then be used to etch a pattern (e.g., strips)
into the layers of the gate structure element (e.g., the
polysilicon). The plurality of gate structure elements 208 are
substantially parallel to each other and extend from one active
region 204 to another. While the illustrated embodiment shows the
gate structure elements 208 being of substantially equal width and
pitch, other embodiments are possible.
[0016] The method 100 then proceeds to block 106 where the gate
structure elements are patterned again. The patterning includes an
inclined or non-orthogonal cut of at least one gate structure such
that it is sectioned. For example, a gate structure element is cut
such that it is provided in two sections, with an space interposing
the sections. The two sections of the gate structure may be
collinear. In an embodiment, a plane extending from the face of the
end of a segment of a gate structure element is not substantially
perpendicular to or orthogonal to a plane extending along a center
line of the length of the gate structure element (i.e., it is at a
slant or incline with respect to the length of the gate structure
element or a plane perpendicular to the length of the gate
structure). In other words, the face of the end of the gate
structure element may be non-orthogonal to one or more of the
sidewalls of the gate structure.
[0017] In an embodiment, two (e.g., adjacent) gate structure
elements are cut and the cut extends across the gate structures in
a non-orthogonal manner. For example, the cut may extend across the
gate structures at an angle other than 90 degrees, for example
approximately 45 degrees from a centerline drawn along the length
of the gate structure element(s). In an embodiment, adjacent gate
structures are cut such that an imaginary line drawn from the ends
of the gate structure elements is non-orthogonal (or inclined) with
respect to a line parallel to a centerline drawn along the length
of the gate structure(s).
[0018] As discussed above, one or more gate structure elements
(e.g., strips) may be cut or etched such that a portion of the gate
structure element is removed from the substrate. In an embodiment,
a photoresist layer is deposited on the gate structure element
(e.g., strip); the photoresist layer then is exposed to an inclined
pattern formed on a suitable photomask, developed thereby forming a
masking element on the gate structure element(s). The masking
elements may be used to protect regions of the gate elements while
portions are etched. Other methods of patterning such as e-beam
lithography are possible. The patterning of block 106 may be
separate and distinct from the patterning of block 104, where the
gate structure elements (e.g., strips) are formed.
[0019] Referring to the example of FIGS. 4 and 5, a first and
second gate structure element 208 are cut non-orthogonally or at an
incline. The region removed from the gate structures is denoted
402. The region 402 may be defined by photolithography methods. The
cut is a non-orthogonal or inclined cut as illustrated by line
404.
[0020] FIG. 6 illustrates further details of an embodiment of cut
gate structure elements 208. The end of the gate structure 208 is
illustrated as 602. Surface 602 is inclined or non-orthogonally,
for example, compared to a centerline extending along the gate
structure element, denoted as line 604. The center line 604 may
extend in the direction substantially parallel the gate structure
elements. In other embodiments, a single end 602 (e.g., lateral
face) of a cut gate structure may be substantially perpendicular to
the respective center line 604.
[0021] FIGS. 4, 5, and 6 also illustrate a non-orthogonal cut
across a plurality of gate structure elements. The non-orthogonal
cut provides adjacent gate structure elements 208 disposed
non-orthogonally to one another, or in other words, at an angle 606
with respect to the center line 604. The angle 606 may be less than
approximately 90 degrees. In an embodiment, the angle 606 is
approximately 45 degrees. In another embodiment, the angle 606 is
between approximately 75 degrees and approximately 20 degrees. The
non-orthogonal cut provides a second set of adjacent gate structure
elements 208 disposed non-orthogonally to one another, or in other
words, at an angle 608 with respect to the center line 604. The
angle 608 may be less than approximately 90 degrees. In an
embodiment, the angle 608 is approximately 45 degrees. In another
embodiment, the angle 608 is between approximately 75 degrees and
approximately 20 degrees. While the non-orthogonal cut is
illustrated as segmenting two adjacent gate structure elements, any
number of gate structure elements may be segment and thus, be
disposed non-orthogonally form one another. The gate structure
elements 208 may be sectioned using a single photolithography
and/or etching process, where those processes provide a
non-orthogonal sectioning of the gate structure elements.
[0022] The method 100 then proceeds to block 108 where spacer
elements are formed on sidewalls of the gate structure elements. In
embodiments, spacer elements may be formed abutting the sidewalls
of the gate structures prior to or after the formation of an
associated source/drain regions (or portions thereof). The spacer
elements may be formed by depositing a dielectric material followed
by an isotropic etching process, however other embodiments are
possible. In an embodiment, the spacer elements include silicon
oxide, silicon nitride, and/or other suitable dielectrics. The
spacer elements may include a plurality of layers. For example, in
an embodiment, the spacer elements include seal liners, main spacer
wall layers, spacers defining low-dose drain (LDD) regions, and/or
other suitable spacers. Referring to the example of FIGS. 7 and 8,
spacer elements 702 are formed abutting the sidewalls of the gate
structures 208. The spacer elements 702 may also be referred to as
main spacer walls.
[0023] The method 100 then proceeds to block 110 where a transistor
element is formed. In an embodiment, source/drain regions are
formed in the active regions of the substrate associated with a
gate structure element. The source/drain regions may include the
introduction of suitable dopant types: n-type or p-type dopants.
The source/drain regions may include halo or low-dose drain (LDD)
implantation, source/drain implantation, source/drain activation
(e.g., anneal), and/or other suitable processes. In other
embodiments, the source/drain regions may include raised
source/drain regions, strained regions, epitaxially-grown regions,
and/or other suitable techniques. In an embodiment, the method 100
includes the silicidation of doped source/drain regions. The
silicide materials may include nickel silicide (NiSi),
nickel-platinum silicide (NiPtSi), nickel-platinum-germanium
silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium
silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi),
erbium silicide (ErSi), cobalt silicide (CoSi), other suitable
conductive materials, and/or combinations thereof. The silicide
features can be formed by a process that includes depositing a
metal layer, annealing the metal layer such that the metal layer is
able to react with silicon to form silicide, and then removing the
non-reacted metal layer.
[0024] The method 100 then proceeds to block 112 where a metal gate
structure is formed using a replacement gate methodology. In
alternative embodiments, the method 100 may include a gate-first
process or other technology such that the non-orthogonal cut
described above with reference to block 106 is provided on a metal
gate structure or a polysilicon gate structure that remains on the
substrate in the final device.
[0025] In an embodiment, the method 100 includes a replacement gate
process. For example, a contact etch stop layer (CESL) and/or
intermediate dielectric layer (ILD) are formed on and/or
interposing the plurality of gate structures. Examples of materials
that may be used to form CESL include silicon nitride, silicon
oxide, silicon oxynitride, and/or other materials known in the art.
The CESL may be formed by PECVD process and/or other suitable
deposition or oxidation processes. The dielectric layer may include
materials such as, tetraethylorthosilicate (TEOS) oxide, un-doped
silicate glass, or doped silicon oxide such as borophosphosilicate
glass (BPSG), fused silica glass (FSG), phosphosilicate glass
(PSG), boron doped silicon glass (BSG), and/or other suitable
dielectric materials. The dielectric layer may be deposited by a
PECVD process or other suitable deposition technique. A
planarization process is then performed to expose a top surface of
a gate structure. The planarization process may include a chemical
mechanical planarization (CMP). A sacrificial layer of the gate
structures described above, for example, polysilicon, may then be
removed to form a trench in which a metal gate structure may be
formed. A metal gate is then formed in the trench(es). The metal
gate may include gate dielectric layer(s), work function layer(s),
capping layer(s), fill layer(s), and/or other suitable layers. A
work function metal layer included in the metal gate may be an
n-type or p-type work function layer. Exemplary p-type work
function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi.sub.2,
MoSi.sub.2, TaSi.sub.2, NiSi.sub.2, WN, other suitable p-type work
function materials, or combinations thereof. Exemplary n-type work
function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN,
TaSiN, Mn, Zr, other suitable n-type work function materials, or
combinations thereof. The work function layer may include a
plurality of layers. The work function layer(s) may be deposited by
CVD, PVD, and/or other suitable process. A dielectric layer of the
metal gate structure may include a high-k dielectric layer such as
hafnium oxide (HfO.sub.2). Alternatively, the high-k dielectric
layer may optionally include other high-k dielectrics, such as
TiO.sub.2, HfZrO, Ta.sub.2O.sub.3, HfSiO.sub.4, ZrO.sub.2,
ZrSiO.sub.2, combinations thereof, or other suitable material. The
dielectric layer may be formed by ALD and/or other suitable
methods.
[0026] A fill layer of the metal gate structure may include Al, W,
or Cu and/or other suitable materials. The fill metal may be formed
by CVD, PVD, plating, and/or other suitable processes. The fill
metal may be deposited over a work function metal layer(s), and
thereby filling in the remaining portion of the trenches or
openings.
[0027] Referring to the example of FIGS. 9 and 10, the gate
structure 208 has been replaced (in whole or in part) by a metal
gate structure 902. The metal gate structure 902 includes the same
dimensions as the gate structure 208 (e.g., having been formed in a
trench created by its removal). Thus, the metal gate structure 902
includes the non-orthogonal features discussed above with reference
to FIG. 6. In other words, the metal gate structures 902 have
non-orthogonal or inclined segments.
[0028] The method 100 then proceeds to block 114 where a contact
layer including a plurality of contact elements is formed on the
substrate. The contact layer includes an interconnect structure
connecting two gate structures (e.g., gate structure segments
having been provided by the orthogonal or inclined cut described
above with reference to block 106).
[0029] In an embodiment, an inter-layer dielectric (ILD) layer is
first formed on the substrate on and/or above the metal gate
structure. The ILD layer may include dielectric materials such as,
tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or
doped silicon oxide such as borophosphosilicate glass (BPSG), fused
silica glass (FSG), phosphosilicate glass (PSG), boron doped
silicon glass (BSG), and/or other suitable dielectric materials.
The ILD layer may be deposited by a PECVD process or other suitable
deposition technique. The ILD layer may be the same as or
differently composed as the dielectric layer described above with
reference to block 112.
[0030] Contact elements are then formed to one or more of the
features on the substrate. The contact element may also provide
interconnection to one or more of the interconnect layers of a
multilayer interconnect (MLI), described below, and a transistor
feature. The contact elements may include tungsten or other
suitable conductive element. The contact elements may be formed by
etching trenches or openings in the ILD layer and filling the
trenches with a conductive material to form vias or plugs. The vias
or plugs may contact features such as source/drain regions and/or
the gate structure (e.g., metal gate structure). The contact
elements may be provided to a silicided region of the source/drain
or other feature. Such contact elements may be referred to as
contact plugs, or simply plugs.
[0031] In an embodiment, the contact layer of the device of the
method 100 includes contact elements and an interconnection
structure between segments of the non-orthogonally cut gate
structure elements. Thus, the interconnection between the segments
of the gate structure elements is provided on a contact layer (or
level) of the semiconductor device. In other words, the
interconnection is co-planar with a contact, for example, a contact
to a gate structure element. The interconnection in the contact
layer may be non-orthogonal or not a straight, linear connection.
In an embodiment, the interconnection may be a slanted or traverse
interconnection connecting adjacent gate structures. In an
embodiment, the interconnection may connect adjacent gate
structures using a plurality of line segments including those
parallel and traverse to the gate structure lengths. The
interconnection may be formed on portions of the gate structures,
such as a top surface. For example, the interconnection may be
formed on a top surface of the gate electrode, on a top surface of
the spacer elements, on a top surface of a metal layer in the gate
structure, and/or other suitable layers as illustrated in the
embodiments of FIGS. 11-14, described below.
[0032] Referring to the example of FIGS. 11 and 12, a contact-level
interconnection 1102 is illustrated connecting gate structures 902a
and 902b. The contact-level interconnection 1102 provides physical
and electrical connection between gate structures 902a and 902b.
The contact-level interconnection 1102 includes two segments 1104
extending on and parallel with the length of the gate structure
elements 902 and further includes a lateral segment 1106 extending
substantially transverse or perpendicular to the length of the gate
structure elements 902.
[0033] The contact-level interconnection 1102 is co-planar with a
contact element (or plug) 1108 provided to the gate structure
element 902. The contact-level interconnection 1102 is co-planar
with a contact element (or plug) 1110 provided to the substrate 202
(e.g., a source/drain region).
[0034] Referring to the example of FIGS. 13 and 14, a contact-level
interconnection 1302 is illustrated connecting gate structures 902a
and 902b. The contact-level interconnection 1302 provides physical
and electrical connection between gate structures 902a and 902b.
The contact-level interconnection 1302 extends substantially
transverse to the length of the gate structure elements 902.
[0035] The contact-level interconnection 1302 is co-planar with the
contact element (or plug) 1108 provided to the gate structure
element 902. The contact-level interconnection 1302 is co-planar
with a contact element (or plug) 1110 provided to the substrate 202
(e.g., a source/drain region).
[0036] The method 100 then proceeds to block 116 where a multiple
layer interconnect (MLI) structure is formed on the substrate. The
MLI structure includes a plurality of conductive (metal) lines
stacked laterally with vias interposing and connecting the layers.
The conductive lines are typically referred to as metal 1, metal 2,
etc. The MLI structure may include a plurality of ILD layers
interposing the conductive layers.
[0037] In summary, the methods and devices disclosed herein provide
for a semiconductor device and method of fabricating thereof, that
provides for a non-orthogonal element. In doing so, embodiments of
the present disclosure offer several advantages over prior art
devices. Advantages of aspects of the present disclosure include
horizontal interconnection between adjacent gate structures in a
manner that is efficient and effective with respect to layout
space. For example, horizontal patterning of the gate structure
itself (e.g., connecting 908a and 908b at the gate-level) may be
difficult to achieve in shrinking geometries. For example, the
spacer process may be unable to sustain a horizontal
interconnection. Thus, the disclosure provides a device and method
having a layout that provides a horizontal connection without or
with minimal impact to the spacer process. Another example of an
advantage of some embodiments is that as the distance between
active regions (e.g., distance between 204) of a substrate decrease
with decreasing technology nodes one slanted cut (e.g., etch
process/mask) can be performed as opposed to etching each gate
structure separately. See FIG. 4 allowing for a single but of a
plurality of gate structures 208. This single cut may save process
time and/or device area.
[0038] It is understood that different embodiments disclosed herein
offer different disclosure, and that they may make various changes,
substitutions and alterations herein without departing from the
spirit and scope of the present disclosure. As but one example,
though the present disclosure and the embodiment of method 100
include a replacement gate metal gate process, the present
disclosure may be applicable to other methods and device types
including those with a polysilicon gate structure.
[0039] Thus, provided in an embodiment is a semiconductor device.
The semiconductor device includes a first gate structure segment
and a collinear second gate structure segment, as well as a third
gate structure segment and a collinear fourth gate structure
segment. An interconnection structure extends from the first gate
structure segment to the fourth gate structure segment. The
interconnection structure is disposed above the first gate
structure segment and the fourth gate structure segment.
[0040] In a further embodiment, the interconnection structure
includes a first portion disposed on the first gate structure
segment and a second portion disposed on the fourth gate structure
segment. The first and second portions may be substantially
parallel. A third portion of the interconnect structure connects
the first and second portions and is substantially perpendicular to
the first and second portions. A contact plug may be co-planar with
the interconnection structure, the interconnection structure, for
example, being formed on the same "layer" of the semiconductor
device as the contact elements (e.g., underlying metal 1). Like a
contact plug, the interconnection structure may include tungsten,
or other conductive material.
[0041] The semiconductor device, in embodiments, includes spacer
elements formed on sidewalls of the gate structure segments; the
interconnection structure may be disposed on a top surface of the
spacer elements.
[0042] In embodiments of the semiconductor device, the first gate
structure segment is non-orthogonal with respect to a third gate
structure segment such that an imaginary line drawn from a first
end of the first gate structure segment to a first end of the third
gate structure segment is non-orthogonal with respect to a sidewall
of the first gate structure segment. See FIG. 6.
[0043] In another embodiment described herein, a semiconductor
device includes a first gate structure, a second adjacent gate
structure, and a third gate structure disposed on a substrate. An
interconnection structure is between the second gate structure and
the third gate structure. A third gate structure may be aligned
with and spaced a first distance from the first gate structure, and
the third gate structure may be parallel to the second gate
structure. The first gate structure may be non-orthogonally
disposed with respect to the second gate structure. For example,
the first gate structure may be non-orthogonally with respect to
the second gate structure such that an imaginary line drawn from a
first end of the first gate structure to a first end of the second
gate structure is non-orthogonal with respect to a sidewall of at
least one of the first and second gate structures. The respective
first ends of the gate structures may be disposed on an isolation
region (e.g., STI). In an embodiment, an end of the first gate
structure is non-orthogonal with respect to a sidewall of the first
gate structure.
[0044] As discussed above, in a further embodiment of the device,
the interconnection may not be co-planar with a plane extending
through the second gate structure and the third gate structure
(e.g., a lateral plane). The interconnection structure may be
co-planar with a contact connected to the first gate structure. In
embodiments, a fourth gate structure collinear with the second gate
structure and spaced a second distance from the second gate
structure is provided in the device. The first distance and the
second distance may be substantially equal, although the associated
space between the third gate structure and the first gate structure
and the associated space between the fourth gate structure and the
second gate structure may be offset from one another in a direction
parallel to the length of the first gate structure.
[0045] In another embodiment, a method of semiconductor fabrication
includes forming a first gate structure and a second gate structure
on a semiconductor substrate and cutting the first gate structure
and the second gate structure concurrently. (The cutting may be
defined by a photolithography process and etching of the gate
structures.) The first gate structure is cut to form a first gate
segment and a second gate segment, and the second gate structure is
cut to form a third segment and a fourth segment. The cutting
includes performing an inclined cut (e.g., 45 degrees with respect
to a length of the first gate structure) of the first gate
structure and the second gate structure.
[0046] In a further embodiment, the gate structure may be formed by
forming a dielectric layer; forming a polysilicon layer on the
dielectric layer; and patterning the dielectric layer and the
polysilicon layer to provide the first gate structure and the
second gate structure.
[0047] In embodiments, the method continues to include forming an
interconnect structure connecting a segment of the first gate
structure and a segment of the second gate structure by forming a
conductive material on the second segment and on the third segment.
The segments of the first and second gate structure are formed by
the cutting process. The interconnect structure may be formed
concurrently with a contact plug coupled to the first gate
structure. The interconnect structure may be formed on the segments
of the first and second gate structures, for example, on a top
surface of the gate electrode, on a top surface of the spacer
elements, on a top surface of a metal layer in the gate structure,
and/or other suitable layers.
* * * * *