U.S. patent application number 13/953321 was filed with the patent office on 2013-11-28 for constant voltage circuit.
This patent application is currently assigned to ROHM CO., LTD.. The applicant listed for this patent is ROHM CO., LTD.. Invention is credited to Manabu OYAMA.
Application Number | 20130314127 13/953321 |
Document ID | / |
Family ID | 44655676 |
Filed Date | 2013-11-28 |
United States Patent
Application |
20130314127 |
Kind Code |
A1 |
OYAMA; Manabu |
November 28, 2013 |
CONSTANT VOLTAGE CIRCUIT
Abstract
A current source generates a reference current. A first
transistor is a depletion-type MOSFET arranged such that one
terminal thereof is connected to the current source and its gate is
connected to its source. A second transistor is an enhancement-type
MOSFET arranged such that one terminal thereof is connected to the
other terminal of the first transistor, the other terminal thereof
is connected to a fixed voltage terminal, and its gate and drain
are connected. A third MOSFET is an enhancement-type P-channel
MOSFET arranged such that one terminal thereof is connected to the
current source, the other terminal thereof is connected to the
fixed voltage terminal, and its gate is connected to a connection
node connecting the first and second transistors. A constant
voltage circuit outputs at least a voltage that corresponds to the
gate voltage of the third transistor or a voltage that corresponds
to the gate voltage thereof.
Inventors: |
OYAMA; Manabu; (Kyoto,
JP) |
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Applicant: |
Name |
City |
State |
Country |
Type |
ROHM CO., LTD. |
Kyoto |
|
JP |
|
|
Assignee: |
ROHM CO., LTD.
Kyoto
JP
|
Family ID: |
44655676 |
Appl. No.: |
13/953321 |
Filed: |
July 29, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13070036 |
Mar 23, 2011 |
8519782 |
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13953321 |
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Current U.S.
Class: |
327/88 |
Current CPC
Class: |
G05F 3/242 20130101;
H03K 5/2481 20130101 |
Class at
Publication: |
327/88 |
International
Class: |
H03K 5/24 20060101
H03K005/24 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 26, 2010 |
JP |
2010-073217 |
Claims
1.-6. (canceled)
7. A comparator configured to make a comparison between a first
voltage and a second voltage, and to generate an output voltage
which represents the comparison result, the comparator comprising:
a differential pair configured to receive, as input signals, the
first voltage and the second voltage; a tail current source
configured to supply a tail current to the differential pair; a
load circuit connected to the differential pair; a source follower
comprising a current source and an output transistor arranged on a
path of the current source, and configured such that the turn-on
degree of the output transistor changes according to a current that
flows through a transistor that is one component of the
differential pair; and a constant voltage element arranged between
the transistor that is one component of the differential pair and
the control terminal of the output transistor.
8. A comparator according to claim 7, wherein the constant voltage
element comprises a MOSFET arranged such that the gate thereof is
connected to the drain thereof.
9. A comparator according to claim 7, wherein the constant voltage
element comprises a diode.
10. (canceled)
11. A voltage monitoring circuit configured to compare a voltage to
be monitored with a predetermined reference voltage, the voltage
monitoring circuit comprising: a constant voltage circuit
configured to generate the reference voltage; and a comparator
according to claim 7, configured to compare the voltage to be
monitored with the reference voltage.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor integrated
circuit employing a MOSFET (Metal Oxide Semiconductor Field Effect
Transistor).
[0003] 2. Description of the Related Art
[0004] In a semiconductor integrated circuit, a constant voltage
circuit (reference voltage circuit) is employed in order to
generate a constant voltage that does not fluctuate with
fluctuation in the power supply voltage or fluctuation in the
temperature. Patent documents 1 and 2 each disclose a constant
voltage circuit employing MOSFETs. FIG. 1 is a circuit diagram
which shows a configuration of a constant voltage circuit 200
according to a comparison technique. The constant voltage circuit
200 includes a first transistor M11 and a second transistor M12
sequentially stacked between the power supply terminal and the
ground terminal. The first transistor M11 is configured as a
depletion-type N-channel MOSFET, and is arranged such that the gate
thereof is connected to the source thereof. The second transistor
M12 is configured as an enhancement-type N-channel MOSFET, and is
arranged such that the gate thereof is connected to the drain
thereof. A comparatively stable reference voltage Vref is generated
at a connection node N1 that connects the first transistor M11 and
the second transistor M12.
RELATED ART DOCUMENTS
Patent Documents
[0005] [patent document 1] [0006] Japanese Patent Application Laid
Open No. H06-067744 [patent document 2] [0007] Japanese Patent
Application Laid Open No. 2002-140124 [patent document 3] [0008]
Japanese Patent Application Laid Open No. H07-092203
[0009] However, the constant voltage circuit 200 shown in FIG. 1
has a problem in that the reference voltage Vref fluctuates due to
fluctuation in the power supply voltage. In other words, such an
arrangement has a problem of a low PSRR (power supply rejection
ratio).
SUMMARY OF THE INVENTION
[0010] The present invention has been made in order to solve such a
problem. Accordingly, it is a general purpose of an embodiment of
the present invention to provide a constant voltage circuit having
a high PSRR.
[0011] An embodiment of the present invention relates to a constant
voltage circuit. The constant voltage circuit comprises: a current
source configured to generate a reference current; a depletion-type
first MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
arranged such that one terminal thereof is connected to the current
source, and the gate thereof is connected to the source thereof; an
enhancement-type second MOSFET arranged such that one terminal
thereof is connected to the other terminal of the first MOSFET, the
other terminal thereof is connected to a fixed voltage terminal,
and the gate thereof is connected to the drain thereof; and an
enhancement-type P-channel third MOSFET arranged such that one
terminal thereof is connected to the current source, the other
terminal thereof is connected to the fixed voltage terminal, and
the gate thereof is connected to a connection node that connects
the first MOSFET and the second MOSFET. The constant voltage
circuit outputs at least one of a voltage that corresponds to the
gate voltage of the third MOSFET and a voltage that corresponds to
the source voltage of the third MOSFET.
[0012] Such an embodiment is capable of generating a stable
reference voltage independent of fluctuation in the power supply
voltage.
[0013] Another embodiment of the present invention relates to a
comparator configured to make a comparison between a first voltage
and a second voltage, and to generate an output voltage which
represents the comparison result. The comparator comprises: a
differential pair configured to receive, as input signals, the
first voltage and the second voltage; a tail current source
configured to supply a tail current to the differential pair; a
load circuit connected to the differential pair; a source follower
comprising a constant current source and an output transistor
arranged on a path of the constant current source, and configured
such that the turn-on degree of the output transistor changes
according to a current that flows through a transistor that is one
component of the differential pair; and a constant voltage element
arranged between the transistor that is one component of the
differential pair and the control terminal of the output
transistor.
[0014] With such an embodiment, the constant voltage element
provides a reduction in the extent of change in the gate voltage of
the output transistor. Thus, such an arrangement provides an
improved response speed.
[0015] Yet another embodiment of the present invention relates to a
voltage monitoring circuit configured to compare a voltage to be
monitored with a predetermined reference voltage. The voltage
monitoring circuit comprises: the aforementioned constant voltage
circuit configured to generate the reference voltage; and the
aforementioned comparator configured to compare the voltage to be
monitored with the reference voltage.
[0016] It is to be noted that any arbitrary combination or
rearrangement of the above-described structural components and so
forth is effective as and encompassed by the present
embodiments.
[0017] Moreover, this summary of the invention does not necessarily
describe all necessary features so that the invention may also be a
sub-combination of these described features.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Embodiments will now be described, by way of example only,
with reference to the accompanying drawings which are meant to be
exemplary, not limiting, and wherein like elements are numbered
alike in several Figures, in which:
[0019] FIG. 1 is a circuit diagram which shows a configuration of a
constant voltage circuit according to a comparison technique;
[0020] FIGS. 2A and 2B are circuit diagrams each showing a
configuration of a constant voltage circuit according to a first
embodiment;
[0021] FIGS. 3A through 3C are circuit diagrams each showing a
modification of the constant voltage circuit;
[0022] FIG. 4 is a circuit diagram which shows a configuration of a
comparator according to a comparison technique;
[0023] FIG. 5 is a circuit diagram which shows a configuration of a
comparator according to a second embodiment;
[0024] FIG. 6 is a time chart which shows the operation of the
comparator shown in FIG. 5; and
[0025] FIG. 7 is a circuit diagram which shows a configuration of a
power supply circuit including a constant voltage circuit and a
comparator.
DETAILED DESCRIPTION OF THE INVENTION
[0026] The invention will now be described based on preferred
embodiments which do not intend to limit the scope of the present
invention but exemplify the invention. All of the features and the
combinations thereof described in the embodiment are not
necessarily essential to the invention.
[0027] In the present specification, the state represented by the
phrase "the member A is connected to the member B" includes a state
in which the member A is indirectly connected to the member B via
another member that does not substantially affect the electric
connection therebetween, or that does not damage the functions or
effects of the connection therebetween, in addition to a state in
which the member A is physically and directly connected to the
member B. Similarly, the state represented by the phrase "the
member C is provided between the member A and the member B"
includes a state in which the member A is indirectly connected to
the member C, or the member B is indirectly connected to the member
C via another member that does not substantially affect the
electric connection therebetween, or that does not damage the
functions or effects of the connection therebetween, in addition to
a state in which the member A is directly connected to the member
C, or the member B is directly connected to the member C.
First Embodiment
[0028] FIGS. 2A and 2B are circuit diagrams each showing a
configuration of a constant voltage circuit 100 according to a
first embodiment. The constant voltage circuit 100 includes a
current source 10, a first transistor M1, a second transistor M2,
and a third transistor M3.
[0029] The current source 10 generates a reference current Iref.
The only difference between FIG. 2A and FIG. 2B is in the
configuration of the current source 10. The configuration of the
current source 10 will be described later.
[0030] The first transistor M1 is configured as a depletion-type
P-channel MOSFET (Metal Oxide Semiconductor Field Effect
Transistor), and is arranged such that one terminal (source)
thereof is connected to the current source 10 and the gate thereof
is connected to the source thereof.
[0031] The second transistor M2 is configured as an
enhancement-type P-channel MOSFET, and is arranged such that one
terminal (source) is connected to the other terminal (drain) of the
first transistor M1, and the other terminal (drain) thereof is
connected to a fixed voltage terminal (ground terminal).
Furthermore, the second transistor M2 is arranged such that the
gate thereof is connected to the drain thereof.
[0032] The third transistor M3 is configured as an enhancement-type
P-channel MOSFET, and is arranged such that one terminal (source)
thereof is connected to the current source 10, and the other
terminal (drain) thereof is connected to the fixed voltage terminal
(ground terminal). The gate of the third transistor M3 is connected
to a connection node N1 that connects the first transistor M1 and
the second transistor M2.
[0033] The constant voltage circuit 100 outputs, as the reference
voltage Vref, at least one of the voltages that occurs at a node N1
and a node N2.
[0034] (1) Voltage Vref1 that occurs at the gate of the third
transistor M3 (connection node that connects the first transistor
M1 and the second transistor M2).
[0035] (2) Voltage Vref2 that occurs at the source N2 of the third
transistor M3 (connection node that connects the first transistor
M1 and the current source 10).
[0036] The above is the basic configuration of the constant voltage
circuit 100.
[0037] Next, description will be made regarding the current source
10.
[0038] The current source 10 shown in FIG. 2A includes a fourth
transistor M4, a seventh transistor M7, and a constant current
source 12. The fourth transistor M4 and the seventh transistor M7
are each configured as a P-channel MOSFET, and form a current
mirror circuit. The fourth transistor M4 duplicates the reference
current Iref' generated by the constant current source 12, thereby
generating the reference current Iref.
[0039] The current source 10 shown in FIG. 2B includes a fifth
transistor M5 and a sixth transistor M6. The fifth transistor M5 is
configured as a depletion-type P-channel MOSFET, which is the same
conduction type as that of the first transistor M1. The sixth
transistor M6 is configured as a depletion-type P-channel MOSFET,
which is the same conduction type as that of the third transistor
M3. The gates and the sources of the fifth transistor M5 and the
sixth transistor M6 are each connected to the power supply terminal
(Vdd).
[0040] The drains of the fifth transistor M5 and the sixth
transistor M6 are connected together so as to form a common drain
terminal, and the reference current Iref is output via this common
drain terminal. A part of the reference current Iref, i.e.,
I.sub.M1, flows through the first transistor M1, and the remainder,
i.e., I.sub.M3, flows through the third transistor M3. The
transistor size (gate width W/gate length L) of the fifth
transistor M5 is adjusted by design so as to provide the flow of
the current I.sub.M1. The transistor size of the sixth transistor
M6 is adjusted by design so as to provide the flow of the current
I.sub.M3.
[0041] The current source 10 shown in FIG. 2B has a simple
configuration, and has an advantage of requiring a small number of
circuit elements. It should be noted that the configuration of the
current source 10 is not restricted to such arrangements shown in
FIGS. 2A and 2B.
[0042] The above is the configuration of the constant voltage
circuit 100. Next, description will be made regarding the operation
thereof.
[0043] The current I.sub.M1, which is a part of the reference
current Iref, flows through a path including the first transistor
M1 and the second transistor M2. As a result, the electric
potential Vref1 at the connection node N1 is stabilized to
Vref=Vth.sub.M2 . . . (1).
[0044] Here, Vth.sub.M2 represents the gate-source threshold
voltage of the second transistor M2.
[0045] Furthermore, the current I.sub.M3, which is a part of the
reference current Iref, flows through the third transistor M3.
Thus, the electric potential Vref2 at the connection node N2 is
stabilized to Vref2=Vref1+Vth.sub.M3=Vth.sub.M2+Vth.sub.M3 . . .
(2). Here, Vth.sub.M3 represents the gate-source threshold voltage
of the third transistor M3.
[0046] With the constant voltage circuits 100 shown in FIGS. 2A and
2B, by maintaining the reference current Iref1 at a constant value,
such an arrangement is capable of stably maintaining the reference
voltages Vref1 and Vref2, respectively represented by Expressions
(1) and (2).
[0047] The advantages of the constant voltage circuits 100 shown in
FIGS. 2A and 2B can be clearly understood in comparison with the
constant voltage circuit 200 shown in FIG. 1. With the constant
voltage circuit 200 shown in FIG. 1, if the power supply voltage
Vdd fluctuates, the drain voltage of the first transistor M11 also
fluctuates. Accordingly, the operating points of the first
transistor M1 and the second transistor M2 each fluctuate according
to the fluctuation in the power supply voltage Vdd. As a result,
the reference voltage Vref fluctuates due to the effects of the
power supply voltage Vdd.
[0048] In contrast, with the constant voltage circuits 100 shown in
FIGS. 2A and 2B, the third transistor M3 functions as a clamping
element configured to stabilize the electric potential at the
second node N2, i.e., the source voltage of the first transistor
M1. Thus, even if the power supply voltage Vdd fluctuates, the
operating points of the first transistor M1 and the second
transistor M2 do not fluctuate. Thus, such an arrangement is
capable of preventing the reference voltages Vref2 and Vref1 from
fluctuating. That is to say, the constant voltage circuit 100
provides a higher PSRR than that of the constant voltage circuit
200 shown in FIG. 1.
[0049] It should be noted that the transistor size of the third
transistor M3 is preferably designed to be greater than the sizes
of the first transistor M1 and the second transistor M2. Due to the
large transistor size of the third transistor M3, the drain-source
voltage VdsM3 of the third transistor M3 becomes smaller. As a
result, even in a state in which the power supply voltage Vdd is
low, such an arrangement ensures that the source voltage of the
first transistor M1 is a sufficiently high voltage.
[0050] Conversely, in a case in which a sufficiently large voltage
can be employed as the power supply voltage Vdd, the transistor
size of the third transistor M3, i.e., the gate-source threshold
voltage Vth.sub.M3 of the third transistor M3, should be designed
giving consideration to the value of the desired reference voltage
Vref2.
[0051] Furthermore, the constant voltage circuit 100 has a
configuration in which all the transistors are configured as
P-channel MOSFETs. With a circuit in which P-channel MOSFETs and
N-channel MOSFETs are mixed, because of process irregularities,
there are irregularities from differences in the characteristics of
the P-channel MOSFETs and the N-channel MOSFETs. This leads to a
problem of irregularities in the operating point of the circuit. In
contrast, the constant voltage circuits 100 shown in FIGS. 2A and
2B each have an advantage of a stable operating point of the
circuit that is resistant to process irregularities.
[0052] Furthermore, by configuring the pair composed of the fifth
transistor M5 and the first transistor M1 as the same
conduction-type transistors, and by configuring the pair composed
of the sixth transistor M6 and the third transistor M3 as the same
conduction-type transistors, such an arrangement provides further
improvement to the stability of the reference voltages Vref1 and
Vref2 with respect to the effects of fluctuation in the power
supply voltage and fluctuation in the temperature.
[0053] FIGS. 3A through 3C are circuit diagrams each showing a
modification of the constant voltage circuit 100. The constant
voltage circuit 100a shown in FIG. 3A has the same configuration as
that of the constant voltage circuit 100 shown in FIG. 2, except
that the first transistor M1 and the second transistor M2 are each
configured as an N-channel MOSFET.
[0054] The constant voltage circuit 100b shown in FIG. 3B has the
same configuration as that of the constant voltage circuit 100
shown in FIG. 2, except that the second transistor M2 is configured
as an N-channel MOSFET.
[0055] The constant voltage circuit 100c shown in FIG. 3C has the
same configuration as that of the constant voltage circuits 100
shown in FIGS. 2A and 2B, except that the first transistor M1 is
configured as an N-channel MOSFET.
[0056] The constant voltage circuits 100a through 100c shown in
FIGS. 3A through 3C are each capable of generating the stable
reference voltages Vref1 and Vref2 which are resistant to the
effects of irregularities in the power supply voltage Vdd and
irregularities in the temperature, in the same way as with the
constant voltage circuits 100 shown in FIGS. 2A and 2B. The
constant voltage circuits 100a through 100c shown in FIGS. 3A
through 3C each have a configuration including a mixture of
P-channel MOSFETs and N-channel MOSFETS. Accordingly, such
arrangements are effectively employed in a case in which a
semiconductor process having small process irregularities can be
employed.
Second Embodiment
[0057] Next, description will be made regarding a comparator
according to a second embodiment.
[0058] In a semiconductor integrated circuit, a comparator is used
in order to compare the magnitudes of two voltages.
[0059] FIG. 4 is a circuit diagram which shows a configuration of a
comparator 400 according to a comparison technique. The comparator
400 includes a differential amplifier 402 and a source follower
404. The differential amplifier 402 includes a differential pair
406 (M21, M22), a current mirror load 408 (M23, M24), and a tail
current source 20.
[0060] The source follower 404 includes a constant current source
22 and an output transistor M25. The drain voltage of the
transistor M22 is input to the gate of the output transistor
M25.
[0061] The comparator 400 shown in FIG. 4 has a problem in that the
response speed is reduced due to the gate capacitance of the output
transistor M25. That is to say, the gate voltage Vg of the output
transistor M25 is controlled according to the magnitude relation
between two input voltages INA and INB. In FIG. 4, the maximum
value of the gate voltage Vg is the difference between the power
supply voltage Vdd and the drain-source voltage Vds.sub.M24 of the
transistor M24 (Vdd-Vds.sub.M24). The minimum value of the gate
voltage Vg is the sum of the voltage Vbias that occurs between both
terminals of the tail current source 20 and the drain-source
voltage Vds.sub.M22 of the transistor M22, i.e.,
(Vbias+Vds.sub.M22).
[0062] Accordingly, with the comparator 400 shown in FIG. 4, there
is a need to change the gate voltage Vg of the output transistor
M25 in a range between (Vbias+Vds.sub.M22) and (Vdd-Vds.sub.M24).
With a larger gate capacitance of the output transistor M25, the
period of time required to switch the gate voltage Vg between
(Vbias+Vds.sub.M22) and (Vdd-Vds.sub.M24) becomes longer. This
leads to poor responsiveness of the comparator 400.
[0063] A second embodiment is made in view of such a situation.
Accordingly, it is an exemplary purpose thereof to provide a
comparator having an improved response speed.
[0064] FIG. 5 is a circuit diagram which shows a configuration of a
comparator 300 according to the second embodiment. The comparator
300 is configured to make a comparison between a first voltage INA
and a second voltage INB, and to generate an output voltage OUT
which represents the comparison result.
[0065] The comparator 300 includes a differential amplifier 302 and
a source follower 304. The differential amplifier 302 includes a
differential pair 306 (M21, M22) respectively configured to receive
the first voltage INA and the second voltage INB as input signals,
a tail current source 20 configured to supply a tail current to the
differential pair 306, a load circuit 308 connected to the
differential pair 306, and a constant voltage element 24. The load
circuit 308 is configured as a current mirror circuit including
transistors M23 and M24.
[0066] The source follower 304 includes a constant current source
22 and an output transistor M25 arranged on a path of the constant
current source 22. The gate of the output transistor M25 is
connected to the drain of the transistor M24, which is one
component of the load circuit 308. The turn-on degree of the output
transistor M25 changes according to the current that flows through
the transistor M22, which is one component of the differential pair
306.
[0067] As can be understood in comparison with the comparator 400
shown in FIG. 4, the comparator 300 shown in FIG. 5 includes the
constant voltage element 24. The constant voltage element 24 is
arranged between the drain of the transistor M22, which is one
component of the differential pair 306, and the control terminal
(gate) of the output transistor M25.ds
[0068] In FIG. 4, the constant voltage element 24 is configured as
a P-channel MOSFET arranged such that the gate thereof is connected
to the drain thereof. The voltage that occurs between both
terminals of the constant voltage element 24 is clamped to be equal
to or greater than the gate-source threshold voltage of the MOSFET.
As the constant voltage element 24, a diode may be employed instead
of such a P-channel MOSFET. Also, other kinds of constant voltage
elements may be employed. Also, the constant voltage element 24 may
include a MOSFET and a diode connected in series.
[0069] The above is the configuration of the comparator 300. Next,
description will be made regarding the operation thereof. FIG. 6 is
a time chart which shows the operation of the comparator 300 shown
in FIG. 5. FIG. 6 also shows the operation of the comparator 400
shown in FIG. 4, which is indicated by the lines of dashes and
dots. The upper graph in the time chart shows the gate voltage Vg
of the output transistor M25, and the lower graph shows the output
voltage OUT.
[0070] In order to clarify the advantage of the comparator 300
according to the embodiment, first, description will be made
regarding the operation of the comparator 400 indicated by the
lines of dashes and dots shown in FIG. 4.
[0071] In the initial state (t<t0), the relation INA<INB is
taken to hold true. In this state, current flows through the
transistor M22 side, and accordingly, the gate-source voltage Vgs
of the output transistor M25 is set to its lower limit level VL',
which is approximately equal to Vbias+Vds.sub.M22. The gate-source
voltage Vgs of the output transistor M25 is greater than its
threshold voltage Vthp. Accordingly, in this state, the output
transistor M25 is on, and the output voltage OUT is set to high
level (Vdd).
[0072] When INA becomes greater than INB at the time point t0,
current flows through the transistor M21 side, and accordingly, the
current that flows through the transistor M22 side is reduced. In
this state, the gate voltage Vg rises over time. When the
gate-source voltage Vgs of the output transistor M25 becomes
smaller than the threshold voltage Vthp at the time point t2, the
output transistor M25 is turned off, whereupon the output voltage
OUT transits to the low level (Vgnd).
[0073] That is to say, with the comparator 400 shown in FIG. 4, the
level of the output voltage OUT transits after a delay time .tau.2
elapses after the relation between the input voltages INA and INB
changes.
[0074] Next, description will be made regarding the operation of
the comparator 300 shown in FIG. 5 with reference to the solid
lines.
[0075] In the initial state, the relation INA<INB is taken to
hold true. In this state, current flows through the transistor M22
side, and accordingly, the gate-source voltage Vgs of the output
transistor M25 is set to its lower limit level VL, which is
approximately equal to Vbias+Vds.sub.M22+Vth. That is to say, in
the state in which INA<INB, the gate voltage Vg of the output
transistor M25 is maintained at a level that is higher than that of
the comparator 400 shown in FIG. 4 by the voltage Vth that occurs
between both terminals of the constant voltage element 24.
[0076] When the relation between INA and INB changes to INA>INB
at the time point t0, the gate voltage Vg of the output transistor
M25 starts to rise. After the delay time .tau.1 elapses, at the
time point t1, the gate-source voltage Vgs of the output transistor
M25 becomes smaller than the threshold voltage Vthp, and
accordingly, the output transistor M25 is turned off. As a result,
the output voltage OUT transits from high level to low level.
[0077] With the comparator 400 shown in FIG. 4, in order to switch
the transistor M25 from the off state to the on state, there is a
need to change the gate voltage Vg by an amount of change
.DELTA.Vg'. In contrast, with the comparator 300 shown in FIG. 5,
the amount of change .DELTA.Vg in the gate voltage Vg required to
switch the transistor is smaller than that required by the
comparator 400 shown in FIG. 4. As a result, such an arrangement
provides a reduction in the delay time before the output voltage
OUT switches after the magnitude relation between the input
voltages INA and INB changes. Thus, such an arrangement provides a
comparator 300 having an improved response speed.
[0078] It should be noted that description has been made in the
embodiment regarding an arrangement in which the differential pair
306 comprises N-channel MOSFETs. Also, the present invention may be
applied to a comparator including a differential pair 306
comprising P-channel MOSFETs.
[0079] Lastly, description will be made regarding a suitable
application of the constant voltage circuit 100 according to the
first embodiment and the comparator 300 according to the second
embodiment.
[0080] FIG. 7 is a circuit diagram which shows a configuration of a
power supply circuit 500 including the constant voltage circuit 100
and the comparator 300. The power supply circuit 500 includes a
switching regulator. The power supply circuit 500 includes a
switching regulator 502 and a overcurrent protection circuit (OCP)
504. The switching regulator 502 includes a control unit 506,
transistors M31 and M32, an inductor L1, and a capacitor C1. The
switching regulator 502 has a typical configuration, and
accordingly, description thereof will be omitted. The control unit
506 controls the duty ratio of the switching operation of the
transistors M31 and M32 by means of pulse width modulation or pulse
frequency modulation such that the output voltage Vout is
maintained at a constant level.
[0081] The overcurrent protection circuit 504 is configured as a
voltage monitoring circuit configured to compare a voltage V.sub.L1
that corresponds to a current I.sub.L1 that flows through the
inductor L1 with a predetermined threshold voltage Vref, and to
generate a signal OCP which indicates whether or not an overcurrent
state occurs. When the signal OCP indicates an overcurrent state,
the control unit 506 stops the switching of the transistor M31 and
M32. The overcurrent protection circuit 504 includes the constant
voltage circuit 100 according to the first embodiment and the
comparator 300 according to the second embodiment.
[0082] With such a configuration, the constant voltage circuit 100
is capable of generating a stable reference voltage Vref. Thus,
such an arrangement provides accurate overcurrent protection.
Furthermore, such an arrangement employs a comparator 300 having a
high response speed, thereby providing a rapid overcurrent
protection operation.
[0083] While the preferred embodiments of the present invention
have been described using specific terms, such description is for
illustrative purposes only, and it is to be understood that changes
and variations may be made without departing from the spirit or
scope of the appended claims.
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