U.S. patent application number 13/947576 was filed with the patent office on 2013-11-21 for conductive chip disposed on lead semiconductor package and methods of making the same.
This patent application is currently assigned to Fairchild Semiconductor Corporation. The applicant listed for this patent is Fairchild Semiconductor Corporation. Invention is credited to David CHONG, Jatinder KUMAR.
Application Number | 20130307134 13/947576 |
Document ID | / |
Family ID | 47438163 |
Filed Date | 2013-11-21 |
United States Patent
Application |
20130307134 |
Kind Code |
A1 |
KUMAR; Jatinder ; et
al. |
November 21, 2013 |
CONDUCTIVE CHIP DISPOSED ON LEAD SEMICONDUCTOR PACKAGE AND METHODS
OF MAKING THE SAME
Abstract
In one implementation, a method of forming a conductive device
can include depositing a non-conductive epoxy on a first portion of
a lower surface of a semiconductor die, and can include depositing
a conductive epoxy on a second portion of the lower surface of the
semiconductor die.
Inventors: |
KUMAR; Jatinder; (Jalandhar
City, IN) ; CHONG; David; (Penang, MY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Fairchild Semiconductor Corporation |
San Jose |
CA |
US |
|
|
Assignee: |
Fairchild Semiconductor
Corporation
San Jose
CA
|
Family ID: |
47438163 |
Appl. No.: |
13/947576 |
Filed: |
July 22, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13177060 |
Jul 6, 2011 |
8525321 |
|
|
13947576 |
|
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Current U.S.
Class: |
257/690 ;
257/734; 438/127 |
Current CPC
Class: |
H01L 23/4951 20130101;
H01L 2924/10253 20130101; H01L 2224/48091 20130101; H01L 23/3107
20130101; H01L 2224/48091 20130101; H01L 2224/48465 20130101; H01L
2924/13091 20130101; H01L 23/49517 20130101; H01L 2224/48247
20130101; H01L 2224/48465 20130101; H01L 23/49548 20130101; H01L
2924/10253 20130101; H01L 21/565 20130101; H01L 23/28 20130101;
H01L 2924/3025 20130101; H01L 2224/48465 20130101; H01L 2924/13091
20130101; H01L 2924/3025 20130101; H01L 2924/00 20130101; H01L
2924/00014 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2924/00 20130101; H01L 2224/48091 20130101; H01L 2224/48247
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/690 ;
257/734; 438/127 |
International
Class: |
H01L 23/28 20060101
H01L023/28; H01L 21/56 20060101 H01L021/56 |
Claims
1.-13. (canceled)
14. A method of forming a conductive device, comprising: depositing
a non-conductive epoxy on a first portion of a lower surface of a
semiconductor die; and depositing a conductive epoxy on a second
portion of the lower surface of the semiconductor die.
15. The method of claim 14, further comprising: disposing at least
a portion of a lead within a portion of the non-conductive epoxy
after the deposing of the non-conductive epoxy.
16. The method of claim 14, further comprising: melting a portion
of the non-conductive epoxy; and disposing at least a portion of a
lead within the portion of the non-conductive epoxy.
17. The method of claim 14, wherein the depositing a non-conductive
epoxy on a first portion of a lower surface of a semiconductor die
includes placing a stencil proximate the lower surface of the
semiconductor die.
18. The method of claim 14, wherein the depositing a non-conductive
epoxy on a first portion of a lower surface of a semiconductor die
includes placing a first stencil proximate the lower surface of the
semiconductor die, the depositing a conductive epoxy on a second
portion of the lower surface of the semiconductor die includes
placing a second stencil proximate the lower surface of the
semiconductor die.
19. The method of claim 14, further comprising: disposing a molding
material about at least a portion of the semiconductor die.
20. The method of claim 14, further comprising: disposing a molding
material about at least a portion of the semiconductor die such
that the conductive epoxy is disposed outside of the molding.
21. A method, comprising: forming a semiconductor die having an
upper surface and a lower surface opposite the upper surface;
forming a lead electrically coupled to the upper surface of the
semiconductor die; depositing a non-conductive material on a first
portion of the lower surface of the semiconductor die; and
depositing a conductive material on a second portion of the lower
surface of the semiconductor die.
22. The method of claim 21, wherein a wire of conductive material
extends from the lead to the upper surface of the semiconductor die
to electrically couple the lead to the upper surface of the
semiconductor die.
23. The method of claim 21, wherein the semiconductor die is a
vertical transistor.
24. The method of claim 21, wherein the semiconductor die includes
an epitaxial layer, a vertical axis disposed perpendicular to the
epitaxial layer extends though a portion of the epitaxial layer, a
portion of the semiconductor die, a portion of the non-conductive
material, and a portion of the lead.
25. The method of claim 21, wherein the lead includes an upper
surface, a portion of the non-conductive material being disposed
between the upper surface of the lead and the lower surface of the
semiconductor die.
26. The method of claim 21, wherein the lead is a first lead and is
electrically coupled to the semiconductor die adjacent a first side
of the semiconductor die, the method further comprising: forming a
second lead electrically coupled to the upper surface of the
semiconductor die adjacent a second side of the semiconductor die,
the second side of the semiconductor die being opposite the first
side of the semiconductor die, a distance between the first side of
the semiconductor die and the second side of the semiconductor die
being greater than a distance between the first lead and the second
lead.
27. The method of claim 21, further comprising: forming a housing
containing at least a portion of the semiconductor die, the
conductive material extending from the lower surface to a location
outside of the housing.
28. The method of claim 21, wherein a horizontal axis extends
substantially parallel to the lower surface of the semiconductor
die, the horizontal axis extends through a portion of the
non-conductive material and through a portion of the conductive
material.
29. The method of claim 21, wherein the semiconductor die includes
a drain contact disposed proximate the lower surface of the
semiconductor die.
30. A method, comprising: forming a semiconductor die including a
vertical transistor device having an upper surface and a lower
surface opposite the upper surface; forming a lead having an upper
surface being electrically coupled to the upper surface of the
semiconductor die; and forming a non-conductive material on a
portion of the lower surface of the semiconductor die.
31. The method of claim 30, wherein at least a portion of the
non-conductive material is disposed between the lower surface of
the semiconductor die and the upper surface of the lead.
32. The method of claim 30, further comprising: forming a
conductive material disposed on a portion of the lower surface of
the semiconductor die.
33. The method of claim 30, wherein a wire of conductive material
extends from the upper surface of the lead to the upper surface of
the semiconductor die to electrically couple the upper surface of
the lead to the upper surface of the semiconductor die.
34. The method of claim 30, further comprising: forming an
epitaxial layer, a vertical axis disposed perpendicular to the
epitaxial layer extends though a portion of the epitaxial layer, a
portion of the semiconductor die, a portion of the non-conductive
material, and a portion of the lead.
35. The method of claim 30, wherein the lead is a first lead and is
electrically coupled to the semiconductor die adjacent a first side
of the semiconductor die, the method further comprising: forming a
second lead electrically coupled to the upper surface of the
semiconductor die adjacent a second side of the semiconductor die,
the second side of the semiconductor die being opposite the first
side of the semiconductor die, a distance between the first side of
the semiconductor die and the second side of the semiconductor die
being greater than a distance between the first lead and the second
lead.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation application of U.S.
application Ser. No. 13/177,060, filed Jul. 6, 2011, which is
incorporated herein by reference in its entirety.
TECHNICAL FIELD
[0002] This description relates to a semiconductor die disposed
adjacent to and/or operatively coupled to a semiconductor lead
package.
BACKGROUND
[0003] Conductive device assemblies typically include a
semiconductor die, such as a conductive chip, and a set of leads,
such as a lead package. The semiconductor die and leads may be
disposed within a packaging or molding and used within an
electronic device. The semiconductor die and the leads may be
disposed within the packaging such that current may be passed
through the semiconductor die via the leads.
[0004] Known non-conductive assemblies can have some drawbacks.
First, some known non-conductive assemblies can suffer from cooling
issues (i.e., the non-conductive assemblies can overheat or have
poor thermal performance). Additionally, some known conductive
assemblies can be undesirably large. As some electronic devices,
such as mobile phones and other consumer electronics, become more
complex in their functions and become smaller in size, the size of
known conductive assemblies can be a drawback.
[0005] Accordingly, there is a need for a conductive assembly that
provides for better thermal performance. Additionally, there is a
need for a conductive assembly having a reduced size.
SUMMARY
[0006] In one implementation, an apparatus includes a semiconductor
die, a lead, a non-conductive epoxy, and a conductive epoxy. The
semiconductor die includes an upper surface and a lower surface
opposite the upper surface. The lead is electrically coupled to the
upper surface of the semiconductor die. The non-conductive epoxy is
disposed on a first portion of the lower surface of the
semiconductor die. The conductive epoxy is disposed on a second
portion of the lower surface of the semiconductor die. In some
implementations, a conductive wire extends from the lead to the
upper surface of the semiconductor die to electrically couple the
lead to the upper surface of the semiconductor die.
[0007] In another implementation, an apparatus, includes a
semiconductor die, a lead, and a non-conductive epoxy. The
semiconductor die includes a vertical transistor device having an
upper surface and a lower surface opposite the upper surface. The
lead has an upper surface that is electrically coupled to the upper
surface of the semiconductor die. The non-conductive epoxy is
disposed on a portion of the lower surface of the semiconductor
die.
[0008] In another implementation, a method of forming a conductive
assembly includes depositing a non-conductive epoxy on a first
portion of a lower surface of a semiconductor die and depositing a
conductive epoxy on a second portion of the lower surface of the
semiconductor die. In some implementations, the method includes
electrically coupling a lead to an upper surface of the
semiconductor die.
[0009] The details of one or more implementations are set forth in
the accompanying drawings and the description below. Other features
will be apparent from the description and drawings, and from the
claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a schematic illustration of a conductive assembly
according to an embodiment.
[0011] FIG. 2 is a perspective view of a conductive assembly
according to an embodiment.
[0012] FIG. 3 is a perspective view of a portion of the conductive
assembly of FIG. 2.
[0013] FIG. 4 is a bottom view of the conductive assembly of FIG.
2.
[0014] FIG. 5 is a cross-sectional view of the conductive assembly
of FIG. 2 taken along line 5-5 of FIG. 4.
[0015] FIGS. 6A-6H schematically illustrate a process for forming a
conductive assembly according to an embodiment.
[0016] FIGS. 7A-7C schematically illustrate a process for forming a
conductive assembly according to an embodiment.
[0017] FIG. 8 is a flow chart illustrating a process of forming a
conductive assembly.
DETAILED DESCRIPTION
[0018] FIG. 1 is a schematic illustration of a conductive assembly
100 according to an embodiment. The conductive assembly 100
includes a semiconductor die 110 disposed within a housing 150. The
conductive assembly 100 also includes a lead package 120. In some
embodiments, at least a portion of the lead package 120 is also
disposed within the housing 150.
[0019] The conductive assembly 100 is configured to selectively
conduct current such that the conductive assembly 100 may be used
in an electronic device, such as a computer type device, a power
regulation device, an electronic measurement device, a cellular or
mobile phone, a laptop or tablet type computer, or other type of
electronic device. Specifically, the conductive assembly 100 may be
configured to conduct current such that the electronic device may
perform the functions specific to the particular electronic
device.
[0020] In some embodiments, the semiconductor die 110 may be formed
of a conductive material (e.g., silicon, germanium, gallium
arsenide). For example, in some embodiments, the semiconductor die
110 is a wafer formed of silicon. In some embodiments, the
semiconductor die 110 is a conductive chip or includes a
semiconductor device. For example, in some embodiments, the
semiconductor die is or includes a vertical transistor (e.g., a
vertically-oriented transistor such as a power metal-oxide
semiconductor field effect transistor (MOSFET) that may include a
shield electrode).
[0021] In the illustrated embodiment, the lead package 120 is
electrically or operatively coupled to the semiconductor die 110.
In some embodiments, the lead package 120 includes a plurality of
leads that are each individually electrically or operatively
coupled to the semiconductor die 110. For example, in some
embodiments, a first lead and a second lead are each electrically
or operatively coupled to the semiconductor die and are
electrically isolated or spaced from each other.
[0022] In some embodiments, the leads are formed of a conductive
material. For example, in such embodiments, the leads may be formed
of an electrically conductive metal. In some embodiments, a wire or
line of electrically conductive material extends between each of
the leads to electrically couple the leads to the semiconductor die
110.
[0023] The housing 150 may be formed of a non-conductive material
such as a polymer or a plastic material. The housing 150 may be
coupled to or formed around the semiconductor die and the lead
package 120 via a molding process.
[0024] FIGS. 2 through 5 illustrate a conductive assembly 200
according to an embodiment. FIG. 2 is a perspective view of the
conductive assembly 200. FIG. 3 is a perspective view of a portion
of the conductive assembly 200. FIG. 4 is a bottom view of the
conductive assembly 200. FIG. 5 is a cross-sectional view of the
conductive assembly 200 taken along line 5-5 of FIG. 4.
[0025] The conductive assembly 200 includes a device or a
semiconductor die 210 and a lead package 220. The components of the
conductive assembly 200 are disposed within a molding (e.g., a
molding compound) (also can be referred as a molding material), a
packaging, or a housing 250. In some embodiments, portions of the
lead package 220 (such as individual leads) extend from or are
disposed outside of the housing 250.
[0026] The device or semiconductor die 210 can be any type of
conductive material, such as a semi-conductor device. For example,
in some embodiments, the semiconductor die includes a substrate,
such as a silicon (Si) wafer, and an integrated circuit. In some
embodiments, at least a portion of the integrated circuit is formed
within an epitaxial layer 280 associated with (e.g., disposed upon)
a surface of the substrate. In some embodiments, the semiconductor
die 210 is or includes a vertical transistor.
[0027] The semiconductor die 210 includes an upper surface 212 and
a lower surface 214. The upper surface 212 is disposed opposite the
lower surface 214 of the semiconductor die 210. In some
embodiments, the upper surface 212 of the semiconductor die 210
includes an integrated circuit.
[0028] The semiconductor die 210 also includes side portions or
side edges 215, 216, 217, and 218. Side portion 215 is opposite
side portion 217. Similarly, side portion 216 is opposite side
portion 218.
[0029] As best illustrated in FIG. 4, the semiconductor die 210 has
a length L. The length L of the semiconductor die 210 extends from
one side portion to an opposite side portion. Specifically, the
length L extends from or is the distance between side portion or
edge 216 of the semiconductor die 210 and side portion or edge 218
of the semiconductor die 210. In some embodiments, the length L is
between a few micrometers and several centimeters. In other
embodiments, the length L is less than a few micrometers or greater
than several centimeters.
[0030] In some embodiments, the semiconductor die 210 has a height.
The height of the semiconductor die 210 extends from one side
portion to an opposite side portion. Specifically, the height
extends between side portion or edge 215 of the semiconductor die
210 and side portion or edge 217 of the semiconductor die 210.
[0031] In the illustrated embodiment, the semiconductor die 210,
when viewed from the bottom (such as in FIG. 4), generally forms a
square shape. In other embodiments, the semiconductor die 210, when
viewed from the bottom, forms a rectangle or another shape. In some
embodiments, the semiconductor die 210 can be formed from several
separately produced and coupled semiconductor die.
[0032] The lower surface 214 of the semiconductor die 210 includes
a first portion 211 and a second portion 213. The first portion 211
of the lower surface 214 is different than the second portion 213
of the lower surface 214. As best illustrated in FIG. 4, the second
portion 213 of the lower surface 214 is located proximate the side
portions or edges 215, 216, 217, and 218 of the semiconductor die
210. In other words, the second portion 213 extends along the
perimeter of the lower surface 214 of the semiconductor die 210.
The second portion 213 of the lower surface 214 surrounds the first
portion 211 of the lower surface 214. In other words, the first
portion 211 is located within the area surrounded by the second
portion 213.
[0033] A conductive material 242 is disposed on or coupled to the
first portion 211 of the lower surface 214 of the semiconductor die
210. In some embodiments, the conductive material 242 is an
electrically conductive material. In some embodiments, the
conductive material 242 is an adhesive, such as a conductive epoxy.
In some embodiments, the conductive material 242 can be a wafer
back-coated epoxy, a dispense epoxy, and so forth that includes a
conductive material (e.g., metallic material) in the epoxy. In
other embodiments, the conductive material 242 is another type of
conductive material.
[0034] As best illustrated in FIG. 5, the conductive material 242
is directly coupled to the first portion 211 of the lower surface
214. Specifically, the conductive material 242 is in direct contact
with the first portion 211 of the lower surface 214 of the
semiconductor die 210. In other words, there is no intermediate
layer or material between the first portion 211 of the lower
surface 214 and the conductive material 242.
[0035] The first portion 211 of the lower surface 214 may include
drain contact 205. Thus, the first portion 211 of the lower surface
214 may align with drain or drain contact 205 of an integrated
circuit of the semiconductor die 210. As the conductive material
242 is coupled directly to the first portion 211 of the lower
surface 214, current may flow or drain from the semiconductor
device 210 through the first portion 211 of the lower surface 214
(and through the conductive material). As illustrated in FIG. 5,
the conductive material extends from a surface of the housing 250
to the lower surface 214 of the semiconductor die 210. Thus, the
first portion 211 of the lower surface 214 may be placed in
electrical communication or contact from a location outside of the
housing 250 (though the conductive material 242).
[0036] A non-conductive material 244 is disposed on or coupled to
the second portion 213 of the lower surface 214 of the
semiconductor die 210. In some embodiments, the non-conductive
material 244 is an electrically non-conductive material such as a
wafer back-coated epoxy, a dispense epoxy, and so forth that does
not include a conductive material in the epoxy or includes an
insulator in the epoxy. In some embodiments, the non-conductive
material 244 is an adhesive, such as a non-conductive epoxy. In
other embodiments, the conductive material 244 is another type of
non-conductive material.
[0037] As best illustrated in FIG. 5, the non-conductive material
244 is directly coupled to the second portion 213 of the lower
surface 214. Specifically, the non-conductive material 244 is in
direct contact with the second portion 213 of the lower surface 214
of the semiconductor die 210. In other words, there is no
intermediate layer or material between the second portion 213 of
the lower surface 214 and the non-conductive material 244.
[0038] The lead package 220 includes several leads. In the
illustrated embodiment, the lead package 220 includes leads 222,
224, 226, 228, 230, and 232. The leads 222, 224, 226, 228, 230, and
232 and are configured to facilitate the connection of the
semiconductor die 210 and an integrated circuit of the
semiconductor die 210 within an electronic device.
[0039] Leads 222, 224, and 226 are disposed proximate side portion
216 of the semiconductor die 210. Similarly, leads 228, 230, and
232 are disposed proximate side portion 218 of the semiconductor
die 210.
[0040] In the illustrated embodiment, the lead package 220 includes
six leads (222, 224, 226, 228, 230, and 232). In other embodiments,
the lead package 210 can include any number of leads. For example,
in some embodiments, the lead package includes more than six leads.
In yet other embodiments, the lead package includes less than six
leads. Additionally, in the illustrated embodiment, the leads 222,
224, 226, 228, 230, and 232 of the lead package 220 are disposed
adjacent or proximate side portions 216 and 218 of the
semiconductor die 210, in other embodiments, leads of the lead
package are disposed adjacent all side portions of the
semiconductor die 210.
[0041] In some embodiments, the leads 222, 224, 226, 228, 230, and
232 are formed of a conductive material. For example, in some
embodiments, the leads 222, 224, 226, 228, 230, and 232 are formed
of a metal material that is electrically conductive.
[0042] Each of the leads 222, 224, 226, 228, 230, and 232 is
electrically or operatively coupled to the semiconductor die 210.
Specifically, in some embodiments, the leads 222, 224, 226, 228,
230, and 232 are electrically coupled to an integrated circuit of
the semiconductor die 210. In the illustrated embodiment, the leads
222, 224, 226, 228, 230, and 232 are operatively coupled to the
upper surface 212 of the semiconductor die 210. In the illustrated
embedment, a wire formed of a conductive material extends from each
of the leads 222, 224, 226, 228, 230, and 232 to the upper surface
212 of the semiconductor die 210. Specifically, in the illustrated
embodiment, wire 235 couples the lead 222 to the upper surface 212,
wire 236 couples the lead 224 to the upper surface 212, wire 237
couples the lead 226 to the upper surface 212, wire 238 couples the
lead 228 to the upper surface 212, wire 239 couples the lead 230 to
the upper surface 212, and wire 240 couples the lead 232 to the
upper surface 212.
[0043] In other embodiments, other methods or materials are used to
electrically or operatively couple the leads 222, 224, 226, 228,
230, and 232 to the upper surface 212 of the semiconductor die 210.
For example, in some embodiments, more than one wire (not shown)
may be used to couple one or more of the leads 222, 224, 226, 228,
230, and 232 to the semiconductor die 210. In some embodiments, a
conductive clip (not shown) may be used to couple one or more of
the leads 222, 224, 226, 228, 230, and 232 to the semiconductor die
210.
[0044] A portion of each of the leads 222, 224, 226, 228, 230, and
232 is disposed within the non-conductive material 244.
Specifically, the leads 222, 224, 226, 228, 203, and 232 are
disposed within the non-conductive material 244 such that the leads
are electrically isolated from the lower surface 214 of the
semiconductor die 210. Additionally, the leads are disposed within
the non-conductive material 244 such that a portion of each of the
leads is disposed outside of the non-conductive material 244. In
other words, in the illustrated embodiment, the leads, in there
entireties are not disposed within the non-conductive material
244.
[0045] As illustrated in FIG. 5, a portion of each of the lead 222
and the lead 228 are disposed within the non-conductive material
244. The lead 222 and the lead 228 are disposed within the
non-conductive material such that a portion non-conductive material
244 is disposed between a surface of the lead and the lower surface
214 of the semiconductor die 210. In other words, the leads 222 and
228 are also disposed within the non-conductive material such that
a portion of the non-conductive material is disposed between a
surface 208 and 209 of the leads 222 and 228 and the lower layer
214 of the semiconductor die 210 and the leads 222 and 228 are
electrically isolated from the lower surface 214 of the
semiconductor die 210. Additionally, a portion of the each of the
leads 222 and 228 are disposed outside of the non-conductive
material 244.
[0046] As best illustrated in FIGS. 4 and 5, a portion of each of
the leads is disposed underneath the semiconductor die 210. For
example, a portion 248 of the lead 228 and a portion 249 of the
lead 222 are disposed underneath or below the semiconductor die
210. The portion 248 of the lead 228 is disposed a distance D from
the portion 249 of the lead 222. As the portions are disposed below
or under the lower surface of the semiconductor die 210, the
distance D is less than the length L of the semiconductor die
210.
[0047] In the illustrated embodiment (as best illustrated in FIG.
5), the upper surface 212 of the semiconductor die 210 includes the
epitaxial layer 280. A vertical axis VA which is disposed
perpendicular to the epitaxial layer 280 and the upper surface 212
of the semiconductor die 210 extends through a portion of the
epitaxial layer 280, a portion of the semiconductor die 210, a
portion of the non-conductive material 244, and the lead 222.
Additionally, as best illustrated in FIG. 5, a horizontal axis HA,
which extends parallel to the upper surface 212 or epitaxial layer
280, extends though a portion of the non-conductive material 244
and through a portion of the conductive material 242.
[0048] FIGS. 6A-6H illustrate a process for forming a conductive
assembly 300 according to an embodiment. As illustrated in FIGS.
6A-6C, a semiconductor die 310, such as a silicon wafer, undergoes
two wafer back coating ("WBC") processes. A WBC process is used to
deposit or couple a non-conductive material 344, such as a
non-conductive epoxy, on a backside or lower surface of the
semiconductor die 310. The non-conductive material 344 is deposited
on a first portion or area of the lower surface of the
semiconductor die 310. In some embodiments, a stencil is used to
facilitate the WBC process. In such embodiments, the non-conductive
material 344 is disposed on or coupled to the portion of the lower
surface of the semiconductor die 310 that is not covered or
shielded by the stencil.
[0049] Another WBC process is used to deposit or couple a
conductive material 342, such as a conductive epoxy, on the
backside or lower surface of the semiconductor die 310. The
conductive material 342 is deposited on a second portion or area of
the lower surface of the semiconductor die 310. The second portion
or area of the lower surface of the semiconductor die 310 is
different than the first portion or area of the lower surface of
the semiconductor die 310. In some embodiments, a stencil may be
used during the second WBC process. For example, the stencil may be
configured to cover or shield the first portion of the
semiconductor die 310 (the portion that received the non-conductive
material).
[0050] FIGS. 6D-FH are cross-sectional views of the device taken
along line 6D of FIG. 6C at various times during the process. FIG.
6D illustrates the device after the two WBC processes.
[0051] As illustrated in FIG. 6E, a lead package or lead frame 320
is then coupled to the device. Specifically, the individual leads
(leads 322 and 328 are illustrated in FIG. 6E) are at least
partially disposed within the non-conductive material 344.
Specifically, the leads are disposed within the non-conductive
material 344 such that a portion of the non-conductive material 344
is disposed between the leads and the lower surface of the
semiconductor die 310 to electrically isolate the leads from the
lower surface of the semiconductor die 310.
[0052] In some embodiments, the non-conductive material 344 is
heated or otherwise melted or softened. The leads of the lead
package may then be inserted into the softened non-conductive
material. In some embodiments, the leads of the lead package may
then be inserted into the softened non-conductive material after a
die attach process has been performed.
[0053] In some embodiments, the leads are coupled to or within the
non-conductive material 344 before the non-conductive material 344
dries or hardens. In some embodiments, heat is applied to the
non-conductive material 344 to facilitate the drying or hardening
of the non-conductive material 344.
[0054] Also as illustrated in FIG. 6E, a layer of tape 360 is also
applied to the lower surface of the device. Specifically, the tape
is placed to cover the lower surfaces of the leads, the
non-conductive material 344, and the conductive material 342.
[0055] The leads of the lead package may then be electrically
coupled to the upper surface 312 of the semiconductor die 310. In
the illustrated embodiment, electrically conductive wires are
coupled to leads and to an upper surface of the semiconductor die
310 to operatively couple the leads 322 and 328 to the
semiconductor die 310.
[0056] The components of the device are then placed in a molding
(e.g., molding compound) or packaging 350 (as best illustrated in
FIG. 6G). As illustrated in FIG. 6H, after the molding process to
place the components within a housing, the tape 360 may be removed.
According, the lower surface of the conductive material, the lower
surface of the non-conductive material, and the lower surface of
the leads 222 and 228 are exposed. In other words, the lower
surface of the conductive material, the lower surface of the
non-conductive material, and the lower surface of the leads 222 and
228 are disposed on the outer surface of the assembly and are
exposed or disposed outside of the housing 250.
[0057] FIGS. 7A-7C are cross-sectional views during a process for
forming a conductive assembly according to another embodiment. In
this embodiment, more than one conductive assembly may be processed
or formed at the same time. Specifically, more than one
semiconductor die may be processed together. In the illustrated
embodiment, two semiconductor dies are illustrated as being
processed at the same time, however, any number of semiconductor
dies (using various shapes and types of stencils) may be processed
at the same time.
[0058] As illustrated in FIG. 7A, semiconductor die 410 is disposed
adjacent to semiconductor die 510. During the first WBC process, a
stencil 495 is disposed over or on top of the semiconductor dies
410 and 510. The stencil 495 includes or defines several openings
496, 497, and 498 and spans or extends over both semiconductor dies
410 and 510. The openings 496, 497, and 498 allow the
non-conductive material 444 to be applied or disposed on the
appropriate portions of the semiconductor dies 410 and 510 during
the WBC process. In other words, the stencil 495 is configured to
block or shield the portion of the semiconductor dies 410 and 510
that are configured to receive or be coated with the conductive
material 442.
[0059] As illustrated in FIG. 7B, after the non-conductive material
444 is applied to the semiconductor dies 410 and 510, a second
stencil 595 may be disposed over or on top of the semiconductor
dies 410 and 510 and the non-conductive material 444. The stencil
595 includes or defines several openings 596 and 597 and spans or
extends over both semiconductor dies 410 and 510. The openings 596
and 597 allow the conductive material 442 to be applied or disposed
on the appropriate portions of the semiconductor dies 410 and 510
during the WBC process. In other words, the stencil 595 is
configured to block or shield the portion of the semiconductor dies
410 and 510 that are coated with the non-conductive material
444.
[0060] As illustrated in FIG. 7C, after the two WBC processes, the
semiconductor dies 410 and 510 are each coated with or coupled to a
non-conductive material 444 at first locations on the upper
surfaces of the semiconductor dies 410 and 510 and a conductive
material 442 at second locations on the upper surfaces of the
semiconductor dies 410 and 510.
[0061] In the illustrated embodiments, the non-conductive material
and the conductive material are disposed on the semiconductor die
such that they form squares or rectangles (and the stencils used
define square or rectangular openings). In other embodiments,
however, the non-conductive material and the conductive material
can form other shapes (and the stencils can define openings of
other shapes).
[0062] In some embodiments, the layer of non-conductive material is
between about 1 micron to several millimeters thick and the layer
of conductive material is between about 1 micron to several
millimeters thick. In some embodiments, the thickness of the
non-conductive material is greater than the thickness of the
conductive material. In some embodiments, the thickness of the
non-conductive material is less than or equal to the thickness of
the conductive material
[0063] FIG. 8 is a flow chart of a process 800 for forming a
conductive assembly according to an embodiment. At 810, a
non-conductive material is disposed or deposited on a first portion
of a lower surface of a semiconductor die. The non-conductive
material may be any type of non-conductive material. In some
embodiments, it is an adhesive, such as a non-conductive epoxy. In
some embodiments, a WBC process is used to apply the non-conductive
material to the semiconductor die. For example, in some
embodiments, the non-conductive material is applied to the lower
surface of the semiconductor die is in a slightly melted or
flowable state and is allowed to cool or dry.
[0064] In some embodiments, the non-conductive material is
deposited directly onto the surface of the semiconductor die. In
other words, there is no intermediate layer or structure between
the non-conductive material and the lower surface of the
semiconductor die. In some embodiments, a stencil is used during
the process to apply the non-conductive material to the
semiconductor die.
[0065] At 820, a conductive material is disposed or deposited on a
second portion of a lower surface of a semiconductor die. The
conductive material may be any type of conductive material. In some
embodiments, it is an adhesive, such as a conductive epoxy. In some
embodiments, a WBC process is used to apply the conductive material
to the semiconductor die. For example, in some embodiments, the
conductive material is applied to the lower surface of the
semiconductor die is in a slightly melted, wet, or flowable state
and is allowed to cool or dry.
[0066] In some embodiments, the conductive material is deposited
directly onto the surface of the semiconductor die. In other words,
there is no intermediate layer or structure between the conductive
material and the lower surface of the semiconductor die. In some
embodiments, a stencil is used during the process to apply the
conductive material to the semiconductor die.
[0067] At 830, a lead is deposited within the non-conductive
material. In some embodiments, the non-conductive material is
heated or warmed to melt or soften the non-conductive material to
allow the lead to be inserted into the non-conductive material. In
some embodiments, the lead is formed of an electrically conductive
material. In some embodiments, the lead is disposed within the
non-conductive material such that only a portion of the lead is
disposed within the non-conductive material. In some embodiments,
the lead is disposed within the non-conductive material such that a
layer or a portion of the non-conductive material is disposed
between the semiconductor die and the lead to electrically isolate
the lead from the lower surface of the semiconductor die.
[0068] At 840, the lead is coupled to the upper surface of the
semiconductor die. In some embodiments, the semiconductor die
includes an integrated circuit and the lead is electrically coupled
to the integrated circuit. In some embodiments, an electrically
conductive wire is coupled to the lead and to the upper surface of
the semiconductor die to electrically couple the lead to the upper
surface of the semiconductor die. In some embodiments, more than
one lead is disposed within the non-conductive layer or
material.
[0069] At 850, a molding material is disposed about or around at
least a portion of the semiconductor die. For example, in some
embodiments, the semiconductor die is placed into a molding
material and a material, such as a plastic or a polymer material,
is molded around or about at least a portion of the device,
including the semiconductor die.
[0070] In some embodiments, the molding material is disposed about
or around at least a portion of the conductive device or
semiconductor die such that at least a portion of the conductive
material is disposed outside of the housing or molding material. In
some embodiments, at least a portion of the conductive material, at
least a portion of the non-conductive material, and at least a
portion of the lead are disposed outside of the housing or molding
material.
[0071] Although the above-described processes illustrate the
non-conductive material being applied to the semiconductor dies
before the conductive material is applied to the semiconductor
dies, in other embodiments, the conductive material is applied to
the semiconductor dies before the non-conductive material is
applied to the semiconductor dies.
[0072] Also, while the various embodiments described above can be
implemented in silicon, these embodiments can also be implemented
in silicon carbide, gallium arsenide, gallium nitride, diamond,
and/or so forth. Some examples of substrates that can be used
include, but are not limited to, silicon wafers, epitaxial Si
layers, bonded wafers such as used in silicon-on-insulator (SOI)
technologies, and/or amorphous silicon layers, all of which may be
doped or undoped. Further, the cross-sectional views of the
different embodiments may not be to scale, and as such are not
intended to limit the possible variations in the layout design of
the corresponding structures
[0073] While certain features of the described implementations have
been illustrated as described herein, many modifications,
substitutions, changes and equivalents will now occur to those
skilled in the art. It is, therefore, to be understood that the
appended claims are intended to cover all such modifications and
changes as fall within the scope of the embodiments. It should be
understood that they have been presented by way of example only,
not limitation, and various changes in form and details may be
made. Any portion of the apparatus and/or methods described herein
may be combined in any combination, except mutually exclusive
combinations. The embodiments described herein can include various
combinations and/or sub-combinations of the functions, components
and/or features of the different embodiments described.
* * * * *