U.S. patent application number 13/861564 was filed with the patent office on 2013-11-14 for hybrid optical modulator.
This patent application is currently assigned to Skorpios Technologies, Inc.. The applicant listed for this patent is Skorpios Technologies, Inc.. Invention is credited to Timothy Creazzo, Stephen B. Krasulick, Elton Marchena, Amit Mizrahi, John Y. Spann, Robert J. Stone, Derek Van Orden.
Application Number | 20130301975 13/861564 |
Document ID | / |
Family ID | 49328188 |
Filed Date | 2013-11-14 |
United States Patent
Application |
20130301975 |
Kind Code |
A1 |
Spann; John Y. ; et
al. |
November 14, 2013 |
HYBRID OPTICAL MODULATOR
Abstract
An optical modulator includes an input port, a first waveguide
region comprising silicon and optically coupled to the input port,
and a waveguide splitter optically coupled to the first waveguide
region and having a first output and a second output. The optical
modulator also includes a first phase adjustment section optically
coupled to the first output and comprising a first III-V diode and
a second phase adjustment section optically coupled to the second
output and comprising a second III-V diode. The optical modulator
further includes a waveguide coupler optically coupled to the first
phase adjustment section and the second phase adjustment section, a
second waveguide region comprising silicon and optically coupled to
the waveguide coupler, and an output port optically coupled to the
second waveguide region.
Inventors: |
Spann; John Y.;
(Albuquerque, NM) ; Van Orden; Derek;
(Albuquerque, NM) ; Mizrahi; Amit; (Albuquerque,
NM) ; Creazzo; Timothy; (Albuquerque, NM) ;
Marchena; Elton; (Albuquerque, NM) ; Stone; Robert
J.; (Berkeley, CA) ; Krasulick; Stephen B.;
(Albuquerque, NM) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Skorpios Technologies, Inc.; |
|
|
US |
|
|
Assignee: |
Skorpios Technologies, Inc.
Albuquerque
NM
|
Family ID: |
49328188 |
Appl. No.: |
13/861564 |
Filed: |
April 12, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61624099 |
Apr 13, 2012 |
|
|
|
Current U.S.
Class: |
385/3 ; 257/506;
438/118 |
Current CPC
Class: |
G02F 2202/105 20130101;
H01L 21/02538 20130101; G02F 2202/102 20130101; H01L 29/20
20130101; G02F 1/2257 20130101; G02F 1/025 20130101 |
Class at
Publication: |
385/3 ; 257/506;
438/118 |
International
Class: |
G02F 1/025 20060101
G02F001/025; H01L 21/02 20060101 H01L021/02; H01L 29/20 20060101
H01L029/20 |
Claims
1. A hybrid diode structure comprising: a substrate comprising
silicon material; an insulating layer coupled to the substrate; a
III-V diode coupled to the insulating layer and having an n-type
region and a p-type region; a first electrical contact electrically
coupled to the n-type region; a second insulating layer overlying
the III-V diode material; and a second electrical contact
electrically coupled to the p-type region.
2. The hybrid diode structure of claim 1 further comprising a III-V
conductive element passing through the second insulating layer and
electrically coupled to the p-type region.
3. The hybrid diode structure of claim 1 wherein the first
electrical contact passes through the second insulating layer.
4. The hybrid diode structure of claim 1 wherein the insulating
layer comprises a central portion having a first thickness and a
lateral portion having a second thickness less than the first
thickness;
5. The hybrid diode structure of claim 1 wherein the III-V diode
material comprises a propagation region adjacent the central
portion of the insulating layer and a bias region adjacent the
lateral portion of the insulating layer
6. The hybrid diode structure of claim 1 wherein the substrate
comprises silicon waveguide sections optically coupled to the III-V
diode.
7. The hybrid diode structure of claim 1 wherein the bottom contact
region comprises a P+ contact.
8. The hybrid diode structure of claim 1 further comprising an N+
contact electrically coupled to the bias region of the III-V diode
material.
9. The hybrid diode structure of claim 1 wherein the bonding region
comprises at least one of Ti, Pt, or In.
10. The hybrid diode structure of claim 1 wherein a cathode of the
III-V diode is disposed between the p-type region and the
substrate.
11. An optical modulator comprising: an input port; a first
waveguide region comprising silicon and optically coupled to the
input port; a waveguide splitter optically coupled to the first
waveguide region and having a first output and a second output; a
first phase adjustment section optically coupled to the first
output and comprising a first III-V diode; a second phase
adjustment section optically coupled to the second output and
comprising a second III-V diode; a waveguide coupler optically
coupled to the first phase adjustment section and the second phase
adjustment section; a second waveguide region comprising silicon
and optically coupled to the waveguide coupler; and an output port
optically coupled to the second waveguide region.
12. The optical modulator of claim 11 wherein the first waveguide
region and the second waveguide region comprise silicon waveguides
having oxide cladding.
13. The optical modulator of claim 11 wherein the first III-V diode
and the second III-V diode comprise InGaAsP diodes.
14. The optical modulator of claim 11 wherein the waveguide
splitter comprises at least one of a multi-mode interference
device, a directional coupler, or a Y-junction coupler.
15. The optical modulator of claim 11 wherein at least one of the
waveguide splitter or the waveguide coupler comprises a 3 dB
directional coupler.
16. The optical modulator of claim 11 wherein the waveguide coupler
comprises at least one of a multi-mode interference device, a
directional coupler, or a Y-junction coupler.
17. A method of fabricating a hybrid diode structure, the method
comprising: providing a substrate having a silicon substrate, an
insulating layer coupled to the silicon substrate, and a silicon
waveguide disposed in the insulating layer; bonding a III-V diode
to the insulating layer, wherein the III-V diode comprises an
n-type region and a p-type region; forming a second insulating
layer coupled to the III-V diode and the insulating layer; forming
an electrical contact to the n-type region; and forming an
electrical contact to the p-type region.
18. The method of claim 17 further comprising: removing a portion
of the insulating layer; and forming one or more bonding regions
coupled to a remaining portion of the insulating layer, wherein
bonding the III-V diode to the insulating layer comprises bonding
the III-V diode to the one or more bonding regions.
19. The method of claim 17 further comprising removing a portion of
the III-V diode to form a remaining portion; forming a first
electrical contact to the remaining portion of the III-V diode;
forming a second insulating layer coupled to the III-diode; and
forming a second electrical contact to the III-V diode.
20. The method of claim 17 wherein the substrate comprises an SOI
substrate.
21. The method of claim 17 wherein the III-V diode comprises
InGaAsP.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Patent
Application No. 61/624,099, filed on Apr. 13, 2012, entitled
"Hybrid Optical Modulator," the disclosure of which is hereby
incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
[0002] High speed modulators are utilized in communications systems
to modulate signals, for example, digital signals. High speed
modulators using, for example, Mach Zehnder interferometer designs,
have been implemented in lithium niobate and InP as discrete
components that are utilized in conjunction with discrete optical
elements.
[0003] Current high speed modulators suffer from a variety of
performance limitations. These include the need for a high drive
voltage, which, in turn, results in high power consumption.
Additionally, conventional high speed modulators occupy a large
footprint, reducing device yield and increasing device cost.
Moreover, integration with other optical systems can result in high
insertion loss, which adversely impacts system performance.
[0004] Thus, there is a need in the art for improved methods and
systems related to high speed modulators.
SUMMARY OF THE INVENTION
[0005] Embodiments of the present invention relate to optical
systems. More particularly, embodiments of the present invention
relate to the fabrication of a hybrid optical modulator, for
example, using a template assisted bonding process. In a particular
embodiment, a hybrid optical modulator utilizes silicon waveguide
sections integrated with III-V diodes operable to introduce phase
delay in the arms of a Mach Zehnder interferometer.
[0006] According to an embodiment of the present invention, a
hybrid diode structure is provided. The hybrid diode structure
includes a substrate comprising silicon material and an insulating
layer coupled to the substrate. The hybrid diode structure also
includes a III-V diode coupled to the insulating layer and having
an n-type region and a p-type region and a first electrical contact
electrically coupled to the n-type region. The hybrid diode
structure further includes a second insulating layer overlying the
III-V diode material and a second electrical contact electrically
coupled to the p-type region.
[0007] According to another embodiment of the present invention, an
optical modulator is provided. The optical modulator includes an
input port, a first waveguide region comprising silicon and
optically coupled to the input port, and a waveguide splitter
optically coupled to the first waveguide region and having a first
output and a second output. The optical modulator also includes a
first phase adjustment section optically coupled to the first
output and comprising a first III-V diode and a second phase
adjustment section optically coupled to the second output and
comprising a second III-V diode. The optical modulator further
includes a waveguide coupler optically coupled to the first phase
adjustment section and the second phase adjustment section, a
second waveguide region comprising silicon and optically coupled to
the waveguide coupler, and an output port optically coupled to the
second waveguide region.
[0008] According to a specific embodiment of the present invention,
a method of fabricating a hybrid diode structure is provided. The
method includes providing a substrate having a silicon substrate,
an insulating layer coupled to the silicon substrate, and a silicon
waveguide disposed in the insulating layer. The method also
includes bonding a III-V diode to the insulating layer. The III-V
diode includes an n-type region and a p-type region. The method
further includes forming a second insulating layer coupled to the
III-V diode and the insulating layer, forming an electrical contact
to the n-type region, and forming an electrical contact to the
p-type region.
[0009] According to a particular embodiment of the present
invention, a hybrid diode structure is provided. The hybrid diode
structure includes a substrate comprising silicon material and an
insulating layer coupled to the substrate. The insulating layer
comprises a central portion having a first thickness and a lateral
portion having a second thickness less than the first thickness.
The hybrid diode structure also includes a bonding region (e.g.,
including Ti, Pt, or In) coupled to the lateral portion of the
insulating layer, a bottom contact region coupled to the lateral
portion of the insulating layer, and a III-V diode material (e.g.,
InGaAsP) coupled to the insulating layer. The III-V diode material
comprises a propagation region adjacent the central portion of the
insulating layer and a bias region adjacent to the lateral portion
of the insulating layer. The hybrid diode structure further
includes a second insulating layer overlying the III-V diode
material, a III-V conductive element passing through the second
insulating layer, and an electrical contact electrically coupled to
the III-V conductive element.
[0010] In an implementation, the bottom contact region can include
a P+ contact and the hybrid diode structure can also include an N+
contact electrically coupled to the bias region of the III-V diode
material.
[0011] According to another particular embodiment of the present
invention, an optical modulator is provided. The optical modulator
includes an input port, a first waveguide region optically coupled
to the input port, and a waveguide splitter (e.g., a multi-mode
interference device, a directional coupler, or a Y-junction
coupler) optically coupled to the first waveguide region and having
a first output and a second output. The waveguide splitter can be a
3 dB directional coupler. The optical modulator also includes a
first phase adjustment section optically coupled to the first
output and comprising a first hybrid diode and a second phase
adjustment section optically coupled to the second output and
comprising a second hybrid diode. The optical modulator further
includes a waveguide coupler (e.g., a multi-mode interference
device, a directional coupler, or a Y-junction coupler) optically
coupled to the first phase adjustment section and the second phase
adjustment section, a second waveguide region optically coupled to
the waveguide coupler, and an output input port optically coupled
to the second waveguide region. The waveguide coupler can be a 3 dB
directional coupler.
[0012] According to yet another particular embodiment of the
present invention, a method of fabricating a diode is provided. The
method includes providing a substrate having a silicon-containing
layer and an insulating layer coupled to the silicon-containing
layer, removing a portion of the insulating layer, and forming one
or more bonding regions (e.g., Ti/Pt/In) coupled to a remaining
portion of the insulating layer. The method also includes bonding
III-V diode material to the one or more bonding regions, removing a
portion of the III-V diode material, and forming a first electrical
contact (e.g., an n-type contact) to a remaining portion of the
III-V diode material. The method further includes forming a second
insulating layer coupled to the III-V diode material and forming a
second electrical contact (e.g., a p-type contact) to the III-V
diode material. The second insulating layer can be a CVD dielectric
or a spin on glass (SOG).
[0013] The substrate can be an SOI substrate and the III-V diode
materials can be InGaAsP-based. In an embodiment, the portion of
the III-V diode material comprises lateral portions and the portion
of the III-V diode material comprises a portion of a p-type
material.
[0014] In an embodiment, a hybrid diode structure includes a
substrate comprising silicon material and an insulating layer
coupled to the substrate. The insulating layer comprises a central
portion having a first thickness and a lateral portion having a
second thickness less than the first thickness and a bonding region
coupled to the lateral portion of the insulating layer. The hybrid
diode structures also includes a bottom contact region coupled to
the lateral portion of the insulating layer and a III-V diode
material coupled to the insulating layer. The III-V diode material
comprises a propagation region adjacent the central portion of the
insulating layer and a bias region adjacent the lateral portion of
the insulating layer. The hybrid diode structure further includes a
second insulating layer overlying the III-V diode material, a III-V
conductive element passing through the second insulating layer, and
an electrical contact electrically coupled to the III-V conductive
element.
[0015] Numerous benefits are achieved by way of the present
invention over conventional techniques. For example, embodiments of
the present invention provide a high performance, low drive
voltage, low insertion loss, as well as compatibility with high
volume production in a CMOS fabrication facility. These and other
embodiments of the invention along with many of its advantages and
features are described in more detail in conjunction with the text
below and attached figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1A is schematic diagram illustrating a hybrid optical
modulator according to an embodiment of the present invention;
[0017] FIG. 1B is a schematic diagram illustrating a cross-section
of a silicon waveguide according to an embodiment of the present
invention;
[0018] FIG. 2A is a schematic diagram illustrating a cross-section
of a III-V diode structure of a hybrid optical modulator according
to an embodiment of the present invention;
[0019] FIG. 2B is a schematic diagram illustrating a cross-section
of a III-V diode structure of a hybrid optical modulator according
to another embodiment of the present invention;
[0020] FIG. 2C is a schematic diagram illustrating an InGaAsP diode
structure according to an alternative embodiment of the present
invention;
[0021] FIGS. 3A and 3B are schematic diagrams illustrating bonding
configurations according to embodiments of the present
invention;
[0022] FIG. 4 is a plot illustrating modal properties of the III-V
diode structure according to an embodiment of the present
invention;
[0023] FIG. 5 is a plot illustrating transmission and phase as a
function of voltage for the III-V diode structure according to an
embodiment of the present invention; and
[0024] FIG. 6 is a simplified flowchart illustrating a method of
fabricating a hybrid optical modulator according to an embodiment
of the present invention.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
[0025] The inventors have determined that pure silicon modulators
suffer from bandwidth limitations, large size, high drive power,
and high insertion loss. On the contrary, III-V modulators exhibit
higher bandwidth and higher performance than silicon modulators.
Although embodiments of the present invention are discussed in
terms of Mach-Zehnder modulator (either phase or amplitude
modulation) applications, the hybrid diode structure described
herein is not limited to these applications, but can also be
utilized in other applications including ring modulators, disk
modulators, tuning elements based on phase shift, phase bias
elements, or other types of phase shifting devices.
[0026] Embodiments of the present invention provide a
high-performance hybrid Si/III-V modulator based on a template
assisted bonding (TAB) process. The III-V materials are disposed on
a low index material, as well as surrounded by low index materials
in some implementations.
[0027] High-performance is facilitated by the strong mode
confinement provided by the low index materials utilized in the
design. This gives a performance that is even higher than pure
(i.e., monolithically integrated) III-V modulators. Additionally,
as described below, a top hat design (pedestal for the metal
contact) is used in some implementations, which keeps the contact
from interfering with the optical mode, and thus reduces the
modulator insertion loss. In addition, bonding is performed at a
significant distance from the optical mode to reduce or minimize
optical losses. Utilizing the TAB process, it is possible to
fabricate a hybrid modulator that is compatible with high volume
CMOS fabrication processes, opening up opportunities for device
integration and leveraging existing CMOS designs and processes. In
a particular embodiment, the III-V diodes bonded using the TAB
process are utilized in a Mach-Zehnder configuration.
[0028] FIG. 1A is schematic diagram illustrating a hybrid optical
modulator according to an embodiment of the present invention. As
illustrated in FIG. 1A, the hybrid optical modulator 100 receives
input light at silicon waveguide 110 and utilizes waveguide
splitters to direct light from the optical input through a set of
III-V (e.g., InGaAsP) diodes 120 and 122. After transmission
through the set of III-V diodes, the light is recombined by a
waveguide coupler to provide an optical output through silicon
waveguide 130.
[0029] The embodiment illustrated in FIG. 1A utilizes the
performance characteristics provided by silicon waveguides in
combination with those of III-V diodes in an integrated hybrid
configuration, enabling a high efficiency modulator on a silicon
platform. The III-V diode enjoys the high performance properties
associated with III-V materials, including high mobility, and the
like, providing fast and responsive devices. At the same time, the
silicon waveguides are characterized by low optical losses (i.e.,
low total losses). In monolithic III-V designs in which the
waveguides utilize III-V materials, the active regions of the
waveguide are also present in the waveguide sections, resulting in
high optical losses in the waveguide sections. By separating the
waveguiding and phase adjustment functions into optimized
materials, embodiments of the present invention provide benefits
not available using monolithic (i.e., monolithically integrated)
designs.
[0030] FIG. 1B is a simplified cross-sectional view of a silicon
waveguide suitable for use as waveguides 110 and 130 shown in FIG.
1A. A silicon-on-insulator (SOI) structure is used as the substrate
material and includes silicon substrate 112, which can be a single
crystal substrate. The buried oxide layer 114 of the SOI substrate
is present below the silicon waveguide 116, which is fabricated
from the single crystal layer of the SOI substrate. After
definition of the waveguide, additional insulating material (e.g.,
SiO.sub.2) is deposited to cover the sides and the top of the
waveguide. In an embodiment, the lateral width of the silicon
waveguide 116 is 400 nm and the vertical height is 220 nm although
other dimensions can be utilized. As will be evident to one of
skill in the art, the dimensions of the silicon waveguide structure
can be modified to provide for low optical loss as the optical mode
couples from the silicon waveguide to the III-V diode.
[0031] Although coupling between the silicon waveguide and the
waveguide region of the III-V diode is accomplished in some
embodiments by positioning the silicon waveguide and the III-V
diode waveguides at the same height with respect to the SOI layers
(e.g., the SOI substrate), this is not required by the present
invention and other coupling methods can be utilized. In some
embodiments, the optical coupling between the silicon waveguide and
the core of the III-V diode can be implemented while the silicon
waveguide and the core of the III-V diode are at different heights,
with tapered optical couplers transferring the optical signal
vertically to provide for high coupling efficiency for cores
present at different heights. Additional description related to
integrated waveguide couplers is provided in commonly assigned U.S.
patent application Ser. No. 13/597,117, entitled "Integrated
Waveguide Coupler," and filed on Aug. 28, 2012, the disclosure of
which is hereby incorporated by reference in its entirety for all
purposes. One of ordinary skill in the art would recognize many
variations, modifications, and alternatives.
[0032] FIG. 2A is a schematic diagram illustrating a III-V diode
structure of a hybrid optical modulator according to an embodiment
of the present invention. The structure illustrated in FIG. 2A
represents one of the III-V (e.g., InGaAsP) diodes 120/122
illustrated in FIG. 1. The optical mode propagates into the plane
of FIG. 2A.
[0033] Referring to FIG. 2A, a silicon substrate 210 is provided.
In some implementations, the silicon substrate is a support
substrate of a silicon-on-insulator (SOI) structure in which the
single crystal silicon layer above the buried oxide has been
removed. A buried oxide layer 212 (which may be the insulator layer
of the SOI structure) is coupled to the silicon substrate. The
buried oxide layer is patterned and etched (or other suitable
removal process) to form an extension region 213 that is adjacent
to recessed areas 220, which can also be referred to as bonding
regions. Utilizing a bonding process, for example, a Template
Assisted Bonding (TAB) process, metallization (e.g.,
In.sub.0.7Pd.sub.0.3) is formed in recessed areas 220 to connect to
the p-type layer at the bottom of the InGaAsP diode and bottom P+
contacts 221 are deposited on the buried oxide layer 212 so that
they are coupled to the buried oxide layer. Electrical contact to
the bottom P+ contacts and the N+ contacts is provided through
electrical connections (not shown), for example, vias passing
through the insulating layer 222. Electrical contact and bonding of
III-V materials to the layers of the SOI substrate can be performed
independent of the TAB process.
[0034] In order to provide bonding regions for the III-V diode
material, bonding regions are formed, for example, by depositing
and/or patterning a metal stack (e.g., Ti/Pt/In). Although this
particular bonding material is illustrated, embodiments of the
present invention are not limited to this example and other
materials suitable for forming bonding contacts can be utilized.
Additional description related to the TAB process is provided in
co-pending and commonly assigned U.S. patent application Ser. No.
13/112,142, filed on May 20, 2011, the disclosure of which is
hereby incorporated by reference in its entirety for all purposes.
Typically, the III-V diode bottom p-type layer contacts the oxide
layer, but is not necessarily bonded to the oxide layer, with
bonding accomplished through the metallization formed in the
recessed areas 220. In other embodiments, direct bonding of the
III-V diode to the insulating layer (i.e., oxide 212) is performed.
It should be noted that contacts to both p-type materials and
n-type materials can be provided through vias (not shown) passing
through the insulating layer 222 and/or located to the sides of the
portions of the III-V diode illustrated in FIG. 2A, obviating the
need for the InGaAsP or InP fin 224 discussed below.
[0035] As illustrated in FIG. 2A, the pedestal 213 formed by the
buried oxide near the center of the diode enables lateral spatial
separation between the optical mode and the bonding regions and
bottom P+ contacts, reducing optical losses. Embodiments of the
present invention provide benefits not available using monolithic
III-V designs since the InGaAsP diode 215 is coupled to the buried
oxide layer 212 of the SOI substrate, providing an index difference
between the core and cladding materials not available using only
III-V materials. As will be evident to one of skill in the art, for
monolithic designs, the refractive index of InP used as the
cladding material is on the order of.about.3.17, providing only a
small index difference between the cladding and the InGaAsP core
(refractive index of.about.3.3). In contrast, utilizing embodiments
of the present invention, the index difference is much greater
since the cladding includes the buried oxide with a refractive
index of.about.1.46. The large index contrast resulting from the
hybrid integration enables the diodes in the modulator to be much
more efficient (e.g., higher phase shift per voltage) than can be
achieved using conventional monolithically integrated III-V
designs.
[0036] The hybrid optical modulator also includes a III-V diode
material with a bandgap (e.g., 1.0 eV) larger than the wavelength
of light propagating through the modulator (e.g., 0.8 eV). In the
example illustrated in FIG. 2A, the III-V diode material is InGaAsP
with a bandgap of approximately 1.0 eV, but other III-V materials
are suitable for use depending on the particular applications, for
example, InP, InGaAs, or the like. One of ordinary skill in the art
would recognize many variations, modifications, and
alternatives.
[0037] Additionally, the III-V diode material provides larger index
of refraction changes near the wavelengths of interest than silicon
diodes. As discussed above, use of metal bonding techniques or
direct bonding techniques, which may include use of the TAB process
in some embodiments, enables the use of a high index III-V material
in conjunction with the low index insulating layer (e.g., the
buried oxide), providing a high level of optical mode
confinement.
[0038] As illustrated in FIG. 2A, portions of the III-V diode
material is removed (e.g., the lateral edges) to pattern the diode
material as appropriate to the particular applications. In the
illustrated example, the upper portions of the InGaAsP material are
p-doped, the middle portions are n-doped, and the lower portions
are p-doped. Thus, to access the n-type material for the N+
contact, upper portions of the InGaAsP material are removed on the
lateral edges to expose the n-type material and facilitate
electrical contact.
[0039] N+ contacts (e.g., aluminum) are formed in electrical
communication with the n-type layers in the III-V diode material,
enabling the injection of current into the InGaAsP material in
response to application of a voltage bias between the N+ and P+
contacts. Accordingly, depletion (or injection) of carriers in the
diode junction is provided in response to bias. As the carrier
concentrations in the diode structure are modified, phase
modulation is provided as appropriate for a modulator.
[0040] An insulating layer 222 (e.g., oxide) is formed above the
III-V diode 215, providing electrical and optical isolation.
Additionally, a top hat design (pedestal for the top P+ metal
contact 230) is used in some implementations, which reduces the
impact of the electrical contact on the optical mode. As
illustrated in FIG. 2A, an InGaAsP or InP rod or fin 224 extends
vertically from the diode region to the top metal contact 23 and is
fabricated as part of the original InGaAsP structure that is bonded
to the substrate using the TAB process in some embodiments. In some
embodiments, the fin 224 extends into the plane of the image and
has a length along the propagation direction substantially equal to
the length of the diode. Although a rod or fin shape extending into
the plane of the figure is illustrated, other suitable shapes are
included within the scope of the present invention. Additionally,
other materials can be utilized such as InP materials. Thus, some
embodiments of the present invention utilize a monolithic InGaAsP
or InP pedestal (e.g., fin 224) that serves to separate the top P+
metal contact 230 from the optical mode, thereby reducing optical
losses. Below fin 224, the InGaAsP diode 215 includes a ridge guide
as well as active regions as described more fully below.
[0041] The fabrication of the InGaAsP diode 215 can include
epitaxial growth of the various layers, including the layers
adjacent oxide 212, etching or use of another removal process to
define the fin 224 and the ridge guide, as well as removal of
portions of the p-type layers to access the n-type layers for N+
contacts 226. After the N+ contacts are formed, the oxide 222 is
blanket deposited. The oxide pedestal 213 between metal contacts in
the recessed areas 220 is typically a small fraction of the width
of the III-V diode , for example, 10 .mu.m in width for a III-V
diode with a width of 100-300 .mu.m. It should be noted that
typically, the actual diode is small, but the piece of bonded
epitaxial material is much larger. The oxide pedestal provides a
cladding for the optical mode in the diode waveguide with the
majority of the bond interface being with the metal materials,
reducing the impact of differing lattice mismatch, differing
coefficients of thermal expansion, and the like.
[0042] In some embodiments, rather than using an oxide pedestal, an
oxide stripe can be deposited and patterned on the III-V material
of the diode after epitaxial growth. Referring to
[0043] FIG. 3A, a bonding metal 312 is formed on the surface of the
silicon substrate 310. The oxide (e.g., silicon dioxide) layer 314
is deposited on the III-V diode 316 before bonding. Subsequently,
the oxide stripe 314 is then bonded to the bonding metal layer 312.
In these embodiments, the metal contacts are thus formed between
the silicon substrate 310 and the deposited oxide stripe 314.
Typically, contacts are formed as illustrated in relation to FIG.
2B.
[0044] In the embodiment illustrated in FIG. 3B, an oxide stripe
322 is embedded in bonding metal 320, with the bond interface
between the III-V diode 316 including both regions bonded to the
bonding metal 320 as well as regions bonded to the oxide stripe
322. The oxide stripe 322 can be deposited as a layer on the bottom
of the III-V diode and then patterned to provide the optical
cladding for the III-V diode waveguide. In some embodiments, the
interface between the oxide stripe 322 is not a chemical bond, but
merely physical contact. Blanket oxide 318 is illustrated in both
figures.
[0045] In the InGaAsP diode illustrated in FIG. 2A, a P-i-N-i-P
diode structure is utilized, but this is not required by the
present invention. FIG. 2B illustrates a P-N diode structure that
can be utilized in other embodiments, which is bonded to the SOI
substrate, for example, the buried oxide layer of the SOI
substrate. The InGaAsP diode 250 includes a plurality of epitaxial
layers including an 80 nm thick n-InGaAsP layer 252 doped at
1.times.10.sup.18 cm.sup.-3 that serves as a heavily doped n-type
contact layer to the anode 266. The diode also includes a 30 nm
thick n-InGaAsP layer 254 doped at 1.times.10.sup.17 cm.sup.-3 and
a 30 nm thick p-InGaAsP layer 256 doped at 1.times.10.sup.17
cm.sup.-3. The diode further includes a 20 nm thick p-InGaAsP layer
260 doped at 1.times.10.sup.18 cm.sup.-3 and a 60 nm thick
n-InGaAsP pedestal 261 doped at 1.times.10.sup.18 cm.sup.-3. In an
embodiment, the lateral width of the pedestal is 560 nm. In order
to spatially separate the P-N junction from the cathode 264, a
vertical extension fin 262 of p-InP doped at 1.5.times.10.sup.18
cm.sup.-3 450 nm thick (measured vertically) and 150 nm in lateral
width is provided. The InP/InGaAsP structure is typically grown in
a single growth run and then patterned as illustrated after bonding
to the SOI substrate including the silicon waveguides. Typical
lateral spacing between the anodes and cathode is on the order of
microns, for example, a lateral spacing of 1.5 .mu.m between the
cathode and the anodes. Although the configuration illustrated in
FIG. 2B, and other figures illustrated herein, is p-up, this is not
required by embodiments of the present invention and bonding could
be performed in a p-down configuration as well. One of ordinary
skill in the art would recognize many variations, modifications,
and alternatives.
[0046] FIG. 2C is a simplified schematic diagram illustrating an
InGaAsP diode structure according to an alternative embodiment of
the present invention. Although InGaAsP layers are illustrated in
FIG. 2C, the invention is not limited to these particular
quaternary materials and other III-V structures are included within
the scope of the present invention. The III-V diode material can
thus include layers of InGaAsP in which the mole fractions of at
least In, Ga, As, or P range from zero to one. In the embodiment
illustrated in FIG. 2C the InGaAsP diode 280 includes a 2.0 .mu.m
thick p-InP layer 284 doped at 1.5.times.10.sup.18 cm.sup.-3 that
serves as a contact layer to the cathode 28. The first P-N junction
is formed by a 275 nm thick p-InGaAsP layer 286 doped at
7.5.times.10.sup.17 cm.sup.-3 and a 280 nm thick n-InGaAsP layer
288 doped at 1.5.times.10.sup.18 cm.sup.-3. The anodes 296 are
electrically connected to the n-InGaAsP layer 288. Another P-N
junction is formed between n-InGaAsP layer 288 and a p-InGaAsP
structure including a 110 nm thick layer 289 and a 385 nm thick
pedestal 290. The contact element includes a p-InP element 292
doped at 1.5.times.10.sup.18 cm.sup.-3, 650 nm thick and 1.4 .mu.m
in width. Although contact element 292 is illustrated as the same
width as the ridge portion 290 of p-InGaAsP structure, this is not
required by the present invention and the contact element can be
thinner as discussed in relation to fin 224 in FIG. 2A.
[0047] In the illustrated embodiment, the lateral spacing between
the anodes 296 and cathode 294 is on the order of microns (e.g., 2
.mu.m) although other dimensions can be utilized.
[0048] As illustrated in FIG. 2C, this diode structure does not
include a bottom oxide layer and is thicker than the diode
structure illustrated in FIG. 2B. Additionally, the P-N-P diode
design utilizes both bottom and top cathodes. The diode could also
utilize a P-i-N-i-P structure. Due to the thicker design, the SOI
substrate to which the diode structure is bonded is modified in a
corresponding manner, with a 1.5 .mu.m thick silicon waveguide
structure buried in oxide with a lateral width of 2.0 .mu.m.
Additionally, an MMI coupler is utilized rather than Y-junctions in
the Mach-Zehnder modulator structure. One of ordinary skill in the
art would recognize many variations, modifications, and
alternatives.
[0049] As shown in FIGS. 2A-2C, versions of a 1.0 eV InGaAsP
depletion mode modulator are illustrated, and can be modeled by
computing the changes in refractive index and absorption loss as a
function of voltage bias. As an example, modeling parameters used
in relation to a specific device were a waveguide width of 560 nm
and a waveguide height of 210 nm. The pedestal formed by the buried
oxide layer had a width of 100 nm and a height of 300 nm. Other
device dimensions are included within the scope of the present
invention and these values are used merely by way of example.
[0050] For the device and model illustrated in FIGS. 2A and 4, a
voltage of Vpp-1.2 V and a reverse bias of 0.9.+-.0.6 V were
utilized. For a diode length of 180 .mu.m, insertion loss was 1.8
dB and the index of refraction was n=2.577323. Switching between
bias points was achieved with .DELTA.n=0.00435, .DELTA.loss=0.16
dB.
[0051] FIG. 4 is a plot illustrating modal properties of the III-V
diode structure according to an embodiment of the present
invention. As illustrated in FIG. 4, the effective mode index was
2.577+j 2.258.times.10.sup.-4 with substantial mode confinement.
The optical mode is confined by a ridge guide (e.g., ridge 261
illustrated in FIG. 2B). Optical coupling of the mode to the
silicon waveguides is discussed herein and can be accomplished by
utilizing epitaxial layers that will vertically align the mode in
the III-V diode with the mode in the silicon waveguide. Referring
to FIGS. 1B and 2A, silicon layer 112 corresponds to silicon
substrate 210, both layers being the silicon substrate of the SOI
structure. As discussed herein, the optical losses of the silicon
waveguide are reduced in comparison to what the optical losses
would be if the P-N junction materials of the III-V diode were
present in a monolithically integrated waveguide fabricated from
the same III-V diode materials. One of ordinary skill in the art
would recognize many variations, modifications, and
alternatives.
[0052] FIG. 5 is a plot illustrating transmission (parabolic curve)
and phase (stair step) as a function of voltage for the III-V diode
MZI structure driven differentially according to an embodiment of
the present invention. The transmission drops from about 0.65 to
about zero as the applied voltage decreases from about -0.6 V to
zero volts. Increasing the voltage to 0.6 V returns the
transmission to about 0.65. The phase is substantially constant as
the voltage is ramped from -0.6 V to zero and then from zero to 0.6
V (with a it phase shift over the whole voltage swing). The MZI
structure can be driven in multiple ways to achieve the desired
modulation, for example, amplitude or phase modulation.
[0053] FIG. 6 is a simplified flowchart illustrating a method of
fabricating a diode according to an embodiment of the present
invention. The method includes providing a substrate having a
silicon-containing layer and an insulating layer coupled to the
silicon-containing layer. In an embodiment, the substrate is part
of an SOI wafer with one of the silicon layers removed. The method
may include removing a portion of the insulating layer and forming
one or more bonding regions (e.g., Ti/Pt/In) coupled to a remaining
portion of the insulating layer.
[0054] The method also includes bonding III-V diode material (e.g.,
InGaAsP) to the one or more bonding regions, removing a portion of
the III-V diode material, and forming a first electrical contact
(e.g., an N+ contact) to a remaining portion of the III-V diode
material. In an embodiment, the lateral portions of the upper
epitaxial layers (e.g., p-type layers) of III-V diode material are
removed to expose n-type layers of the III-V diode material.
Additionally, the method includes forming a second insulating layer
coupled to the III-V diode material and forming a second electrical
contact (e.g., a P+ contact) to the III-V diode material. The
second insulating layer can be a CVD dielectric, an SOG,
combinations thereof, or the like.
[0055] In some embodiments, the portion of the III-V diode material
comprises a portion of a p-type material, the first electrical
contact comprises an n-type contact, the second insulating layer
comprises at least one of a CVD dielectric or SOG, or the second
electrical contact comprises a p-type contact. The bonding regions
can utilize Ti/Pt/In or other suitable metals or alloys. The
portion of the III-V diode material can include lateral
portions.
[0056] According to another embodiment of the present invention, a
method of fabricating a hybrid diode structure includes providing a
substrate having a silicon substrate, an insulating layer coupled
to the silicon substrate, and a silicon waveguide disposed in the
insulating layer. The method also includes bonding a III-V diode to
the insulating layer. The III-V die includes an n-type region and a
p-type region. The method further includes forming a second
insulating layer coupled to the III-V diode and the insulating
layer, forming an electrical contact to the n-type region, and
forming an electrical contact to the p-type region.
[0057] It should be appreciated that the specific steps illustrated
in FIG. 6 provide a particular method of fabricating a diode
according to an embodiment of the present invention. Other
sequences of steps may also be performed according to alternative
embodiments. For example, alternative embodiments of the present
invention may perform the steps outlined above in a different
order. Moreover, the individual steps illustrated in FIG. 6 may
include multiple sub-steps that may be performed in various
sequences as appropriate to the individual step. Furthermore,
additional steps may be added or removed depending on the
particular applications. One of ordinary skill in the art would
recognize many variations, modifications, and alternatives.
[0058] It is also understood that the examples and embodiments
described herein are for illustrative purposes only and that
various modifications or changes in light thereof will be suggested
to persons skilled in the art and are to be included within the
spirit and purview of this application and scope of the appended
claims.
* * * * *