U.S. patent application number 13/665451 was filed with the patent office on 2013-10-31 for memory card and sd card.
The applicant listed for this patent is Takashi OKADA, Atsuko SEKI. Invention is credited to Takashi OKADA, Atsuko SEKI.
Application Number | 20130286603 13/665451 |
Document ID | / |
Family ID | 49477097 |
Filed Date | 2013-10-31 |
United States Patent
Application |
20130286603 |
Kind Code |
A1 |
OKADA; Takashi ; et
al. |
October 31, 2013 |
MEMORY CARD AND SD CARD
Abstract
According to one embodiment, there are provided a memory which
is provided on a circuit board, a controller which is provided on
the circuit board and controls the memory, and a signal line which
is formed on the circuit board and configured to perform data
transmission between the controller and the memory, in which a
width of the signal line in the place where the signal line is led
out from the memory is large compared with a place disposed under
the memory.
Inventors: |
OKADA; Takashi; (Kanagawa,
JP) ; SEKI; Atsuko; (Kanagawa, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
OKADA; Takashi
SEKI; Atsuko |
Kanagawa
Kanagawa |
|
JP
JP |
|
|
Family ID: |
49477097 |
Appl. No.: |
13/665451 |
Filed: |
October 31, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61640491 |
Apr 30, 2012 |
|
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|
Current U.S.
Class: |
361/746 ;
361/728; 361/748; 361/752; 361/774 |
Current CPC
Class: |
G11C 5/02 20130101; H05K
7/02 20130101; G06K 19/07732 20130101; H05K 7/14 20130101; G11C
5/063 20130101; H01L 2224/49171 20130101 |
Class at
Publication: |
361/746 ;
361/748; 361/728; 361/752; 361/774 |
International
Class: |
H05K 7/02 20060101
H05K007/02; H05K 7/14 20060101 H05K007/14 |
Claims
1. A memory card comprising: a circuit board; a memory which is
provided on the circuit board; a controller which is provided on
the circuit board and controls the memory; and a signal line which
is formed on the circuit board and configured to perform data
transmission between the controller and the memory, wherein a width
of the signal line in the place where the signal line is led out
from the memory is large compared with a place disposed under the
memory.
2. The memory card according to claim 1, wherein the memory is
provided with a memory package on which a memory chip is mounted,
and wherein a width of the signal line in a place of a boundary
portion of the memory package is large by 2 or more times compared
with the place disposed under the memory.
3. The memory card according to claim 1, wherein a width of the
signal line in a place where the signal line is led out from the
controller is large by 2 or more times compared with the place
disposed under the controller.
4. The memory card according to claim 1, wherein the controller
includes a controller chip which is COB-mounted on the circuit
board, and a sealing resin which seals the controller chip on the
circuit board, and wherein a width of the signal line in a place of
a boundary portion of the sealing resin is large by 2 or more times
compared with the place disposed under the memory.
5. The memory card according to claim 1, further comprising a case
which is bent and accommodates the circuit board, wherein a width
of the signal line in a bent portion of the circuit board is large
by 2 or more times compared with an unbent portion of the circuit
board.
6. A memory card comprising: a circuit board; a memory which is
provided on the circuit board; a controller which is provided on
the circuit board and controls the memory; a signal line which is
formed on the circuit board and configured to perform data
transmission between the controller and the memory; and a land
electrode which is provided on an end portion of the signal line
and electrically connects the memory to the signal line, wherein
the signal line includes a first sub-line which is led out from the
land electrode, and a second sub-line which is connected to the
land electrode through the first sub-line, and wherein a width of
the first sub-line is large compared with that of the second
sub-line.
7. A memory card comprising: a circuit board; a memory which is
provided on the circuit board; a controller which is provided on
the circuit board and controls the memory; a signal line which is
formed on the circuit board and configured to perform data
transmission between the controller and the memory; and a power
line which is disposed on the circuit board along with the signal
line so as to be adjacent to the signal line.
8. The memory card according to claim 7, wherein the power line
includes a first power line which is disposed on the circuit board
along with the signal line, a second power line which is disposed
on the rear surface of the circuit board so as to intersect the
signal line, and a through hole line which connects the first power
line and the second power line.
9. The memory card according to claim 8, further comprising a
ground pattern which is disposed on the rear surface of the circuit
board so as to overlap the first power line.
10. The memory card according to claim 9, wherein the first power
line is connected through a fuse.
11. An SD card comprising: a circuit board; a memory which is
provided on the circuit board; a controller which is provided on
the circuit board and controls the memory; and a signal line which
is formed on the circuit board and configured to perform data
transmission between the controller and the memory, wherein a width
of the signal line in a place where the signal line is led out from
the memory is large compared with a place disposed under the
memory.
12. The SD card according to claim 11, wherein the memory includes
a memory package on which a memory chip is mounted, and wherein a
width of the signal line in a place of a boundary portion of the
memory package is large by 2 or more times compared with the place
disposed under the memory.
13. The SD card according to claim 11, wherein a width of the
signal line in a place where the signal line is led out from the
controller is large by 2 or more times compared with the place
disposed under the controller.
14. The SD card according to claim 11, wherein the controller
includes a controller chip which is COB-mounted on the circuit
board, and a sealing resin which seals the controller chip on the
circuit board, and wherein a width of the signal line in a place of
a boundary portion of the sealing resin is large by 2 or more times
compared with the place disposed under the memory.
15. The SD card according to claim 11, further comprising a case
which is bent and accommodates the circuit board, wherein a width
of the signal line in a bent portion of the circuit board is large
by 2 or more times compared with an unbent portion of the circuit
board.
16. An SD card comprising: a circuit board; a memory which is
provided on the circuit board; a controller which is provided on
the circuit board and controls the memory; a signal line which is
formed in the circuit board and configured to perform data
transmission between the controller and the memory; and a land
electrode which is provided on an end portion of the signal line
and electrically connects the memory to the signal line, wherein
the signal line includes a first sub-line which is led out from the
land electrode, and a second sub-line which is connected to the
land electrode through the first sub-line, and wherein a width of
the first sub-line is large compared with that of the second
sub-line.
17. An SD card comprising: a circuit board; a memory which is
provided on the circuit board; a controller which is provided on
the circuit board and controls the memory; a signal line which is
formed on the circuit board and configured to perform data
transmission between the controller and the memory; and a power
line which is disposed on the circuit board along with the signal
line so as to be adjacent to the signal line.
18. The SD card according to claim 17, wherein the power line
includes a first power line which is disposed on the circuit board
along with the signal line, a second power line which is disposed
on the rear surface of the circuit board so as to intersect the
signal line, and a through hole line which connects the first power
line and the second power line.
19. The SD card according to claim 18, further comprising a ground
pattern which is disposed on the rear surface of the circuit board
so as to overlap the first power line.
20. The SD card according to claim 19, wherein the first power line
is connected through a fuse.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from Provisional Patent Application No. 61/640491, filed
on Apr. 30, 2012; the entire contents of which are incorporated
herein by reference.
FIELD
[0002] Embodiments disclosed herein relate generally to a memory
card and an SD (secure digital) card.
BACKGROUND
[0003] An example of a typical memory card includes an SD card. The
SD card includes a controller and a memory package which are
mounted on a circuit board. Further, examples of methods of
mounting the controller on the circuit board include a method of
mounting a controller chip on the circuit board using a COB (Chip
On Board) technology and a method of mounting a controller package
on the circuit board. The circuit board is provided with signal
lines through which data transmission is performed between the
controller and a memory.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a cross-sectional view illustrating a schematic
configuration of a memory card according to a first embodiment;
[0005] FIG. 2 is a cross-sectional view illustrating a schematic
configuration of a circuit board of the memory card of FIG. 1;
[0006] FIG. 3 is a plane view illustrating a schematic
configuration of the memory card according to the first
embodiment;
[0007] FIG. 4A is a plane view illustrating a schematic
configuration of a controller chip on a mounting surface side in
the circuit board of FIG. 1;
[0008] FIG. 4B is a plane view illustrating the vicinity of a
sealing area of FIG. 4A on a magnified scale;
[0009] FIG. 5 is a plane view illustrating a schematic
configuration of a memory card according to a second
embodiment;
[0010] FIG. 6A is a plane view illustrating a schematic
configuration of a controller package on a mounting surface side in
a circuit board of FIG. 5;
[0011] FIG. 6B is a plane view illustrating the vicinity of a
package area of FIG. 6A on a magnified scale;
[0012] FIG. 7 is a plane view illustrating a schematic
configuration of a controller chip on a mounting surface side in a
circuit board which is applied to a memory card according to a
third embodiment; and
[0013] FIG. 8 is a plane view illustrating a schematic
configuration of the controller chip on a non-mounting surface side
in the circuit board of FIG. 7.
DETAILED DESCRIPTION
[0014] In general, according to one embodiment, a memory card is
provided with a circuit board, a memory, a controller, and signal
lines. The memory is provided on the circuit board. The controller
is provided on the circuit board, and controls the memory. The
signal lines are formed in the circuit board, and data transmission
is performed through the signal lines between the controller and
the memory. Herein, the width of the signal line in the place where
the signal line is led out from the memory is formed to be large
compared with the place disposed under the memory.
[0015] Referring to the accompanying drawings hereinbelow, the
memory card and the SD card according to the embodiments will be
described in detail. Further, the invention is not limited to these
embodiments.
First Embodiment
[0016] FIG. 1 is a cross-sectional view illustrating a schematic
configuration of a memory card according to a first embodiment.
[0017] In FIG. 1, the memory card is provided with a circuit board
3, and a memory M and a controller N are provided on the circuit
board 3. Further, as the circuit board 3, a double-sided board may
be used or a multilayer board may be used. In addition, as the
memory M, a nonvolatile semiconductor memory device such as a NAND
flash memory or a resistance variable memory may be used. The
controller N can perform a drive control on the memory M. Further,
as a drive control performed on the memory M, a read-write control,
a block selection, an error correction, and a wear leveling can be
performed on the memory M, for example.
[0018] The memory M is provided with a memory chip 8, and the
memory chip 8 is sealed with a memory package 5 in a state of being
mounted on a lead frame 7. Further, a material of the memory
package 5 may be made of a sealing resin such as an epoxy resin or
a silicon resin. An example of the memory package 5 includes a TSOP
(Thin Small Outline L-Leaded Package).
[0019] The controller N is provided with a controller chip 6, and
the controller chip 6 is COB-mounted on the circuit board 3.
Further, a board for the memory chip 8 and the controller chip 6
may be made of a semiconductor. Examples of the semiconductor
include Si, Ge, SiGe, GaAs, InP, GaP, InGaAs, GaN, SiC, and the
like. Then, the controller chip 6 is sealed with the sealing resin
4 on the circuit board 3. Further, the material of the sealing
resin 4 may include the epoxy resin, the silicon resin, or the
like.
[0020] Further, the circuit board 3 on which the memory M and the
controller N are provided is accommodated to a space between a
lower case 1 and an upper case 2. Herein, an external terminal 9 is
formed on the rear surface of the circuit board 3, and the external
terminal 9 is exposed from the lower case 1.
[0021] Herein, in the standards of the SD card, the total thickness
T2 of the lower case 1 and the upper case 2 is set to, for example,
2.1 mm, and a distance T3 from the uppermost surface of the upper
case 2 to the surface of the external terminal 9 is set to, for
example, 1.4 mm. At this time, in a case where the thickness T1 of
the memory package 5 is large, in order to put the memory package 5
between the lower case 1 and the upper case 2, the memory package 5
is disposed on a deeper position of the lower case 1. At this time,
the thickness of the lower case 1 under the memory package 5, for
example, may be set from 0.3 to 0.4 mm. In addition, in a case
where the distance T3 is set to 1.4 mm, the surface of the external
terminal 9 is necessarily disposed on a higher position by 0.7 mm
from the bottom surface of the lower case 1. For this reason, the
circuit board 3 is bent such that the external terminal 9 is lifted
up from the bottom surface of the lower case 1. At this time, the
circuit board 3 may be provided with bent portions B1 and B2. The
bent portion B1 may be provided between the sealing resin 4 and the
external terminal 9, and the bent portion B2 may be provided
between the sealing resin 4 and the memory package 5.
[0022] FIG. 2 is a cross-sectional view illustrating a schematic
configuration of the circuit board of the memory card of FIG. 1.
Further, FIG. 2 gives an example in which the double-sided board is
used as the circuit board.
[0023] In FIG. 2, the circuit board 3 is provided with an
insulating board 11. Further, the insulating board, for example,
may include a resin board which is configured of a glass epoxy
resin or the like, or may include a sheet board which is configured
of polyimide, polyester, or the like. Then, the surface of the
insulating board 11 is formed with a conductor pattern 13A, and the
rear surface of the insulating board 11 is formed with a conductor
pattern 13B. In addition, the insulating board 11 is formed with
through holes 12A and 12B, and the through holes 12A and 12B are
formed with a through hole line 13C. Herein, the conductor patterns
13A and 13B may be connected to each other through the through hole
line 13C. Further, the materials of the conductor patterns 13A and
13B and the through hole line 13C may include metal such as Cu or
Al.
[0024] In addition, the surface of the insulating board 11 is
formed with a solder resist film 14A to cover the conductor pattern
13A, and the rear surface of the insulating board 11 is formed with
a solder resist film 14B to cover the conductor pattern 13B.
Herein, a part of the conductor pattern 13A is exposed from the
solder resist film 14A, and a part of the conductor pattern 13B is
exposed from the solder resist film 14B. Then, the exposed surfaces
of the conductor patterns 13A and 13B are formed with a plating
layer 15. Further, the material of the plating layer 15 may include
Au, Ni, or the like.
[0025] FIG. 3 is a plane view illustrating a schematic
configuration of the memory card according to the first
embodiment.
[0026] In FIG. 3, the circuit board 3 is provided with land
electrodes 21 to 24 and 29. Further, the land electrodes 21 to 24
and 29 may be configured using a part of the conductor pattern 13A
of FIG. 2. The controller chip 6 is provided with a pad electrode
25. Further, the material of the pad electrode 25 may include metal
such as Cu or Al. Then, the pad electrode 25 is connected to the
land electrode 23 through a bonding wire 26. The bonding wire 26 is
sealed with the sealing resin 4 on the circuit board 3 together
with the controller chip 6. In addition, on the circuit board 3,
the memory package 5 is mounted through the land electrode 22. In
addition, on the circuit board 3, a fuse 27 is mounted through the
land electrode 24, and a capacitor 30 is mounted through the land
electrode 29. Further, the land electrode 21 may be used for
exchanging signals between the controller chip 6 and an external
device of the circuit board 3.
[0027] FIG. 4A is a plane view illustrating a schematic
configuration of the controller chip on a mounting surface side in
the circuit board of FIG. 1, and FIG. 4B is a plane view
illustrating the vicinity of a sealing area of FIG. 4A on a
magnitude scale.
[0028] In FIGS. 4A and 4B, a signal line S1, a power line D1, and a
ground pattern G1 are provided on the circuit board 3. Further, the
signal line S1, the power line D1, and the ground pattern G1 may be
configured using a part of the conductor pattern 13A of FIG. 2.
Power can be supplied to the memory chip 8 and the controller chip
6 through the power line D1. Data transmission can be performed
between the controller N and the memory M through the signal line
S1.
[0029] In addition, the sealing area E1 is provided on the circuit
board 3. The sealing resin 4 is disposed on the sealing area E1. In
addition, the circuit board 3 is formed with a through hole 28.
[0030] Herein, the width of the signal line S1 in the place where
the signal line is led out from the memory M may be large compared
with the place disposed under the memory M. Herein, the place where
the signal line is led out from the memory M, for example, may be
set as the boundary portion of the memory package 5. Alternatively,
the width of the signal line S1 in the place where the signal line
is led out from the controller N may be formed to be large compared
with the place disposed under the controller N. Herein, the place
where the signal line is led out from the controller N, for
example, may be set as the boundary portion of the sealing area E1.
Alternatively, the width of the signal line S1 in the bent portion
B2 of the circuit board 3 may be formed to be large compared with
an unbent portion of the circuit board 3.
[0031] Herein, in order to make the signal line S1 have a different
width, the signal line S1 may be provided with sub-lines S1a and
S1b. At this time, the width of the sub-line line S1b may be formed
to be large compared with the width of the sub-line S1a. At this
time, it is preferable that the width of the sub-line S1b be formed
to be large by 2 or more times compared with the width of the
sub-line S1a. For example, the width of the sub-line S1a may be 70
.mu., and the width of the sub-line S1b may be 200 .mu.m or more.
Herein, the sub-line S1b may be disposed on the boundary portion of
the memory package 5, the boundary portion of the sealing area El,
or the bent portion B2. In other words, the layout position of the
sub-line S1b may be set to be disposed on a place where stress or
load is heavy compared with the layout position of the sub-line
S1a. Alternatively, the layout position of the sub-line S1b may be
set to be disposed on a place where the stress or the load is
fluctuated violently compared with the layout position of the
sub-line S1a.
[0032] Therefore, it is possible to enhancing the strength of the
place where the signal line S1 is likely to be broken. Even in a
case where the memory card is used under an environment highly
vibrating such as in automobile use or portable use, the
disconnection of the signal line S1 can be prevented, so that a
lifespan of the memory card can be enhanced. In addition, in order
to make the signal line S1 highly strengthened, compared with the
case where the width of the signal line S1 is made to be uniformly
large, the layout area of the signal line S1 can be reduced, and
the miniaturization of the memory card can be achieved.
Second Embodiment
[0033] FIG. 5 is a plane view illustrating a schematic
configuration of a memory card according to a second
embodiment.
[0034] In FIG. 5, a circuit board 31 is provided with land
electrodes 32 to 35. Further, the land electrodes 32 to 35 may be
configured using a part of the conductor pattern 13A of FIG. 2. A
controller package 37 is sealed with a controller chip. Further,
the controller package 37, for example, may include a BGA (Ball
Grid Array). The controller package 37 is mounted with the circuit
board 31 by bonding a solder ball to the land electrode 35.
[0035] In addition, a memory package 36 is mounted on the circuit
board 31 through the land electrode 32. The memory package 36 is
sealed with the memory chip. Further, the memory package 36, for
example, may include a TSOP.
[0036] In addition, the capacitor 38 is mounted on the circuit
board 31 through the land electrode 33. Further, the land electrode
34 may be used for exchanging signals between the controller chip
and an external device of the circuit board 31.
[0037] In FIG. 6A is a plane view illustrating a schematic
configuration of the controller package on the mounting surface
side in the circuit board of FIG. 5, and FIG. 6B is a plane view
illustrating the vicinity of the package area of FIG. 6A on a
magnified scale.
[0038] In FIGS. 6A and 6B, a signal line S2, a power line D2, and a
ground pattern G2 are provided on the circuit board 31. Further,
the signal line S2, the power line D2, and the ground pattern G2
may be configured using a part of the conductor pattern 13A of FIG.
2. Power can be supplied to the memory chip and the controller chip
through the power line D2. Data transmission can be performed
between the controller and the memory through the signal line S2.
In addition, the package area E2 is provided on the circuit board
31. The controller package 37 is disposed on the package area E2.
In addition, a through hole 39 is formed in the circuit board
31.
[0039] Herein, the end portion of the signal line S2 is connected
to the land electrode 35 in the package area E2. The width of the
signal line S2 can be formed to be large in the place near the land
electrode 35 compared with the place away from the land electrode
35.
[0040] Herein, in order to make the signal line S2 have a different
width, the signal line S2 may be provided with sub-lines S2a and
S2b. At this time, the width of the sub-line S2b may be formed to
be large compared with the width of the sub-line S2a. At this time,
it is preferable that the width of the sub-line S2b be formed to be
large by 2 or more times compared with the width of the sub-line
S2a. For example, the width of the sub-line S2a may be 70 .mu.m,
and the width of the sub-line S2b may be 200 .mu.m or more. Then,
the end portion of the sub-line S2b is connected to the land
electrode 35. The sub-line S2a is connected to the land electrode
35 through the sub-line S2b.
[0041] Therefore, even in a case where a load applied to the signal
line S2 in the vicinity of the land electrode 35 increases, the
disconnection of the signal line S2 can be prevented, so that a
lifespan of the memory card can be enhanced. In addition, in order
to make the signal line S2 highly strengthened, compared with the
case where the width of the signal line S2 is formed to be
uniformly large, the layout area of the signal line S2 can be
reduced, and the miniaturization of the memory card can be
achieved.
Third Embodiment
[0042] FIG. 7 is a plane view illustrating a schematic
configuration of the controller chip on the mounting surface side
in a circuit board which is applied to a memory card according to a
third embodiment, and FIG. 8 is a plane view illustrating a
schematic configuration of the controller chip on a non-mounting
surface side in the circuit board of FIG. 7.
[0043] In FIGS. 7 and 8, a signal line SA, a power line DA, and a
ground pattern GA are provided on the insulating board 11. A signal
line SB, a power line DB, a ground pattern GB, and the external
terminal 9 are provided on the rear surface of the insulating board
11. Further, the signal line SA, the power line DA, and the ground
pattern GA may be configured using a part of the conductor pattern
13A of FIG. 2. The signal line SB, the power line DB, and the
ground pattern GB may be configured using a part of the conductor
pattern 13B of FIG. 2. In addition, the through hole 28 is formed
in the insulating board 11. Herein, a through hole line DC is
formed in the through hole 28. Herein, the power lines DA and DB
are connected to each other through the through hole line DC.
Further, the configuration of the circuit board on the surface side
may be the same as that of FIG. 4A. In addition, as illustrated in
FIG. 1, the memory M and the controller N can be provided on the
circuit board.
[0044] Power can be supplied to the memory chip 8 and the
controller chip 6 through the power lines DA and DB. Data
transmission can be performed through the signal lines SA and SB
between the controller N and the memory M. Further, a data
transmission rate between the controller N and the memory M can be
set about 100 to 200 Mbit/sec per bus wiring for data transmission
at maximum.
[0045] Herein, the power line DA may be disposed on the circuit
board along with the signal line SA so as to be adjacent to the
signal line SA. For example, in a case where a plurality of the
signal lines SA are disposed in parallel, the power lines DA and
the signal lines SA can be alternatively disposed. Further, the
width of the power line DA can be formed to be larger than that of
the signal line SA. Further, the power lines DA are not necessarily
disposed along with the entire signal lines SA, and in particular
the power lines may be disposed along with signal lines SA which
are required to be operated at a high data transmission rate. In
addition, the signal line SA to be operated at a high data
transmission rate may be formed such that the width of the power
line DA adjacent to the signal line SA becomes large compared with
the signal line SA to be operated at a row data transmission
rate.
[0046] In addition, the power line DB is disposed to intersect the
signal line SA on the rear surface side of the circuit board, and
the power line DA can be connected to the power line DB through the
through hole line DC. With this configuration, the power lines DA
which are separated from each other on the surface side of the
circuit board can be connected to each other through the power line
DB, so that the conductivity of the power lines DA can be
enhanced.
[0047] In addition, the fuse 27 is mounted on the circuit board
through the land electrode 24, and the power line DA is connected
to an external device of the circuit board through the fuse 27.
With this configuration, it is possible to prevent a large amount
of current flowing to the power lines DA and DB, so that the power
lines DA and DB can be protected.
[0048] In addition, the ground pattern GB can be disposed so as to
face the power line DA through the insulating board 11. Herein, the
ground pattern GB may be formed in a solid pattern so as to make
the ground pattern GB face the power line DA.
[0049] When an input/output buffer of the controller N or an
input/output buffer of the memory M performs a switching operation,
switching noises may occur in the signal line SA. At this time,
current flows to the power line DA and the ground pattern GB so as
to cancel the switching noises occurred in the signal line SA.
Then, a return path of the current is formed by the power line DA
and the ground pattern GB, so that an inductance of the signal line
SA is reduced and the switching noises occurred in the signal line
SA is reduced.
[0050] Therefore, the high data transmission rate of the memory
card can be achieved, and the data transmission rate can be secured
about 100 to 200 Mbit/sec per bus wiring at maximum.
[0051] Further, the above-described memory card may be applied to
the SD card, or may be applied to other memory cards such as SM
(Smart Media) cards, compact flash memories, or USB memories.
[0052] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions.
* * * * *