U.S. patent application number 13/850124 was filed with the patent office on 2013-10-17 for semiconductor device.
The applicant listed for this patent is KABUSHIKI KAISHA TOSHIBA. Invention is credited to Kanako KOMATSU, Jun Morioka, Mariko Shimizu, Koji Shirai, Keita Takahashi, Tsubasa Yamada.
Application Number | 20130270637 13/850124 |
Document ID | / |
Family ID | 46859376 |
Filed Date | 2013-10-17 |
United States Patent
Application |
20130270637 |
Kind Code |
A1 |
KOMATSU; Kanako ; et
al. |
October 17, 2013 |
SEMICONDUCTOR DEVICE
Abstract
A first semiconductor layer extends from the element region to
the element-termination region, and functions as a drain of the MOS
transistor. A second semiconductor layer extends, below the first
semiconductor layer, from the element region to the
element-termination region. A third semiconductor layer extends
from the element region to the element-termination region, and is
in contact with the second semiconductor layer to function as a
drift layer of the MOS transistor. A distance between a boundary
between the first semiconductor layer and the field oxide film, and
the end portion of the third semiconductor layer on the fifth
semiconductor layer side in the element region is smaller than that
between a boundary between the first semiconductor layer and the
field oxide layer and an end portion of the third semiconductor
layer on the fifth semiconductor layer side in the
element-termination region.
Inventors: |
KOMATSU; Kanako; (Kanagawa,
JP) ; Morioka; Jun; (Kanagawa, JP) ; Shirai;
Koji; (Kanagawa, JP) ; Takahashi; Keita;
(Kanagawa, JP) ; Yamada; Tsubasa; (Kanagawa,
JP) ; Shimizu; Mariko; (Kanagawa, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
KABUSHIKI KAISHA TOSHIBA |
Tokyo |
|
JP |
|
|
Family ID: |
46859376 |
Appl. No.: |
13/850124 |
Filed: |
March 25, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13241107 |
Sep 22, 2011 |
8421153 |
|
|
13850124 |
|
|
|
|
Current U.S.
Class: |
257/339 |
Current CPC
Class: |
H01L 29/0847 20130101;
H01L 29/0696 20130101; H01L 29/7816 20130101; H01L 29/7823
20130101; H01L 29/4238 20130101; H01L 29/1045 20130101; H01L
29/0886 20130101; H01L 29/0692 20130101; H01L 29/0653 20130101;
H01L 29/7835 20130101 |
Class at
Publication: |
257/339 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 23, 2011 |
JP |
2011-63875 |
Claims
1.-20. (canceled)
21. A semiconductor device, comprising: a semiconductor substrate;
a source layer formed on the semiconductor substrate; and a drain
layer formed on the semiconductor substrate, the drain layer being
formed to face the source layer in a first direction with a channel
region and a drift layer therebetween, and the drain layer being
formed to extend in a second direction orthogonal to the first
direction; wherein a distance along the first direction from the
drain layer to an edge of the drift layer on a side of the source
layer is larger in an end portion of the drain layer than in a
center of the drain layer in the second direction.
22. The semiconductor device according to claim 21, wherein the
drift layer is formed to surround the drain layer, and includes a
first part in a vicinity of the center of the drain layer and a
second part in a vicinity of the end portion of the drain
layer.
23. The semiconductor device according to claim 22, wherein the
first part has a first width along the first direction, and the the
second part has a second width larger than the first width along
the first direction.
24. The semiconductor device according to claim 22, wherein the
second part has a polygon shape.
25. The semiconductor device according to claim 22, wherein the
first part is formed in an element region including an MOS
transistor formed thereon, and the second part is formed in an
element termination region formed at an end region of the element
region.
26. The semiconductor device according to claim 22, further
comprising a field oxide film formed on a surface of the drift
layer.
27. The semiconductor device according to claim 21, wherein the
source layer, the drain layer and the drift layer have a first
conductivity type, and the impurity concentration of the drift
layer is lower than that of the drain layer.
28. The semiconductor device according to claim 21, further
comprising a gate electrode formed on the channel region via an
insulating film to surround the drain layer, wherein a distance
along the first direction from the drain layer to an edge of the
gate electrode is larger in an end portion of the drain layer than
in a center of the drain layer in the second direction.
29. A semiconductor device, comprising: a semiconductor substrate;
a source layer formed on the semiconductor substrate; and a drain
layer formed on the semiconductor substrate, the drain layer being
formed to face the source layer in a first direction with a channel
region therebetween, and the drain layer being formed to extend in
a second direction orthogonal to the first direction; and a gate
electrode formed on the channel region via an insulating film to
surround the drain layer, wherein a distance along the first
direction from the drain layer to an edge of the gate electrode is
larger in an end portion of the drain layer than in a center of the
drain layer in the second direction.
30. The semiconductor device according to claim 29, wherein the
gate electrode is formed to surround the drain layer, and includes
a first part in a vicinity of the center of the drain layer and a
second part in a vicinity of the end portion of the drain
layer.
31. The semiconductor device according to claim 30, wherein the
first part has a first width along the first direction, and the the
second part has a second width larger than the first width along
the first direction.
32. A semiconductor device, comprising: a semiconductor substrate;
a source layer formed on the semiconductor substrate; and a drain
layer formed on the semiconductor substrate, the drain layer being
formed to face the source layer in a first direction with a channel
region and a drift layer therebetween, and the drain layer being
formed to extend in a second direction orthogonal to the first
direction, wherein the drift layer is formed to surround the drain
layer, and includes a first part in the vicinity of the center of
the drain layer and a second part in the vicinity of the end
portion of the drain layer, the second part being enlarged compared
to the first part.
33. The semiconductor device according to claim 32, wherein the
first part has a first width along the first direction, and the the
second part having a second width larger than the first width along
the first direction.
34. The semiconductor device according to claim 32, wherein the
second part has a polygon shape.
35. The semiconductor device according to claim 32, wherein the
first part is formed in an element region including an MOS
transistor formed thereon, and the second part is formed in an
element termination region formed at an end region of the element
region.
36. The semiconductor device according to claim 32, further
comprising a field oxide film formed on a surface of the drift
layer.
37. The semiconductor device according to claim 32, wherein the
source layer, the drain layer and the drift layer have a first
conductivity type, the impurity concentration of the drift layer is
lower than that of the drain layer.
38. The semiconductor device according to claim 32, further
comprising a gate electrode formed on the channel region via an
insulating film to surround the drain layer, wherein the gate
electrode includes a third part in the vicinity of the center of
the drain layer and a fourth part in the vicinity of the end
portion of the drain layer, an area surrounded by the fourth part
is larger than that surrounded by the third part.
39. A semiconductor device, comprising: a semiconductor substrate;
a source layer formed on the semiconductor substrate; and a drain
layer formed on the semiconductor substrate, the drain layer being
formed to face the source layer in a first direction with a channel
region therebetween, and the drain layer being formed to extend in
a second direction orthogonal to the first direction; and a gate
electrode formed on the channel region via an insulating film to
surround the drain layer, wherein the gate electrode is formed to
surround the drain layer, and includes a first part in the vicinity
of the center of the drain layer and a second part in the vicinity
of the end portion of the drain layer, an area surrounded by the
second part is larger than that surrounded by the first part.
40. The semiconductor device according to claim 39, wherein an area
surrounded by the first part has a first width along the first
direction, and an area surrounded by the second part has a second
width larger than the first width along the first direction.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is based on and claims the benefit of
priority from prior Japanese Patent Application No. 2011-63875,
filed on Mar. 23, 2011, the entire contents of which are
incorporated herein by reference.
FIELD
[0002] Embodiments described herein relate to a semiconductor
device.
BACKGROUND
[0003] A DMOS transistor is known as one of power semiconductor
devices.
[0004] The DMOS transistor comprises a drift region adjacent to a
drain diffusion layer having a high impurity concentration. The
drift region has the same conductivity type as that of the drain
diffusion layer, and has a lower impurity concentration than the
drain diffusion layer. The DMOS transistor is characterized in that
its switching speed is fast in a relatively-low voltage region, and
its conversion efficiency is high. The DMOS transistor may perform
an operation with a high breakdown voltage and a low ON resistance
may be achieved at the same time. However, in such a DMOS
transistor, an element termination region is formed at an end
region of an element region where a DMOS transistor itself is
formed. In some cases, an element termination region does not have
a predetermined breakdown voltage even when an element region has
such a predetermined breakdown voltage.
[0005] In this case, the breakdown voltage of the whole element is
determined by the breakdown voltage of the element termination
region. With the conventional DMOS transistor, concentration of an
electric field occurs in such an element termination region, and
impact-ion due to this may easily be generated. As a result, a
breakdown voltage of the whole semiconductor device becomes lower.
Therefore, a semiconductor device having an element termination
region with a high breakdown voltage is required. On the other
hand, it is highly requested that a circuit area of the whole
semiconductor device is decreased.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a plan view showing a structure of the
semiconductor device according to the embodiment.
[0007] FIG. 2 is a plan view showing a structure of the semi
conductor device according to the embodiment.
[0008] FIG. 3 is a plan view showing a structure of the
semiconductor device according to the embodiment.
[0009] FIG. 4 is A-A' B-B' and C-C' sectional views of FIG. 1-FIG.
3.
[0010] FIG. 5 is a plan view showing a structure of a comparative
example.
DETAILED DESCRIPTION
[0011] A semiconductor device according to embodiments described
hereinbelow includes an element region formed on a semiconductor
substrate and including an MOS transistor formed thereon, and an
element termination region formed on the semiconductor substrate
and formed at an end region of the element region. A first
semiconductor layer of a first conductivity type is formed to
extend in a first direction as its lengthwise direction from the
element region to the element termination region. The first
semiconductor layer has a first impurity concentration, and
functions as a drain region of the MOS transistor in the element
region. A second semiconductor layer of a first conductivity type
is formed to extend in a first direction as its lengthwise
direction from the element region to the element termination
region. The second semiconductor layer is formed in a layer below
the first semiconductor layer, and has a second impurity
concentration that is smaller than the first impurity
concentration. A third semiconductor layer of the first
conductivity type is formed to extend in a first direction as its
lengthwise direction from the element region to the element
termination region. The third semiconductor layer has a third
impurity concentration that is smaller than the second impurity
concentration. The third semiconductor layer is arranged in contact
with the second semiconductor layer and functions as a drift layer
of the MOS transistor. A field oxide film is formed on a surface of
the third semiconductor layer and in contact with the first
semicondutor layer. A fourth semiconductor layer of the second
conductivity type is formed on the semiconductor layer to extend in
a first direction as its lengthwise direction from the element
region to the element termination region. The fourth semiconductor
layer functions as a channel region of the MOS transistor in the
element region. A fifth semiconductor layer of the first
conductivity type is formed on a surface of the fourth
semiconductor layer and functions as a source region of the MOS
transistor. A gate electrode is formed on a surface of the
semiconductor substrate between the third semiconductor layer and
the fourth semiconductor layer, via a gate insulating film. A
distance between a boundary between the first semiconductor layer
and the field oxide film, and the end portion of the third
semiconductor layer on the side of the fifth semiconductor layer in
the element region is smaller than a distance between a boundary
between the first semiconductor layer and the field oxide layer and
an end portion of the third semiconductor layer on the side of the
fifth semiconductor layer in the element termination region.
[0012] The semiconductor device according to the embodiment is
described hereinbelow with reference to the drawings. Referring now
to FIGS. 1-4, a laminated structure of the semiconductor device
according to the embodiment is described. This semiconductor device
relates to a p-channel type DMOS transistor.
[0013] It is possible that conductivity types of all of the
semiconductor layers in FIGS. 1-4 are reversed, thereby forming a
an n-channel type DMOS transistor formed on a P.sup.- type
substrate or p.sup.- type semiconductor layer.
[0014] FIG. 1 to FIG. 3 illustrate plan views of the semiconductor
device according to the embodiment. FIG. 1 to FIG. 3 each
illustrates some of the components in a selective manner to show
positional relationship among overlapping components. Also, FIG. 4
shows A-A', B-B', and C-C sectional views of FIG. 1, FIG. 2, and
FIG. 3. Note that in the following discussion "p.sup.- type"
designates a semiconductor whose impurity concentration is smaller
than "P type".
[0015] Also, "n.sup.- type" designates a semiconductor whose
impurity concentration is smaller than "N type".
[0016] As shown in FIG. 1, one semiconductor device of the present
embodiment is formed, for example, on an N type semiconductor
substrate 11. The semiconductor substrate 11 includes an element
region R1 and an element termination region R2. The element region
R1 is a region for forming a p channel type DMOS transistor. The
element termination region R2 is formed at the end region of the
element region R1 in a first direction. Note that the semiconductor
substrate 11 may be replaced by a p-type substrate.
[0017] As shown in FIG. 1, in the semiconductor device according to
the embodiment, the element region R1 and element termination
region R2 are divided into a plurality of rectangular areas CP. The
rectangular areas CP1, CP2, CP3 . . . are arranged to be aligned
along the X-direction. In addition, each of the rectangular areas
CP1, CP2, CP3 . . . has the same width Wcp in the X-direction.
[0018] The width of each of the rectangular areas CP in the element
region R1 and the width of each rectangular area CP in the element
termination region R2 are both Wcp.
[0019] The semiconductor device of the present embodiment relates
to an improvement in the shape of various components in such a
rectangular area CP. This improvement can supppress increase in
circuit area. Also, a semiconductor device with a high breakdown
voltage can be provided.
[0020] Also, as shown in FIG. 1, a gate electrode 18 is formed on
the semiconductor substrate 11 through a gate insulating film 18a
(not illustrated in FIG. 1). As an example, the gate electrode 18
is extended not only in the element region R1 but also up to the
element termination region R2. The gate electrode 18 is connected
to a contact CSg in this element termination region R2, and is
supplied with a necessary voltage. The gate electrode has a gate
electrode length Lg1 in the element region R1, and has a gate
electrode length Lg2 (.noteq.Lg1) in the element termination region
R2. The gate electrode 18 is located such that it is sandwiched by
a P+ type drain region 12 functioning as a drain of the p-channel
type DMOS transistor and a P+ type source region 15 functioning as
a source of the p-channel type DMOS transistor, along the gate
length direction. There is formed a P type diffusion region 13 in a
layer below the drain region 12.
[0021] Also, an N type diffusion region 16 is formed in a layer
below the source region 15 and a back gate diffusion region 19, as
shown in FIG. 3.
[0022] FIG. 4 shows A-A', B-B', and C-C' sectional views of FIG.
1.
[0023] The A-A' section is a section along the drain region 12 and
the source region 15 of the above-mentioned p channel type MOS
transistor. The B-B' section is a section along the drain region 12
and the back gate diffusion region 19 of the p channel MOS
transistor. The C-C' section is a section of the element
termination region R2 including the vicinity of the end portion of
the drain region 12.
[0024] First, the structure of the p channel type MOS transistor
along the A-A' section is described with reference to FIG. 4. As
shown in the A-A' section of FIG. 4, the p channel type MOS
transistor includes the P+ type drain region 12. As shown in FIGS.
1-3, the P+ type drain region 12 is formed to have a rectangular
shape with the Y-direction (the first direction) as its lengthwise
direction. The drain region 12 is arranged in the vicinity of the
center of the rectangular area CP along the X-direction. The drain
region 12 extends from the element region R1 to the element
termination region R2. The P+ type drain region 12 is injected with
P type impurities such as boron (B), and has an impurity
concentration of 1e20 [cm.sup.-3], for example.
[0025] The P type diffusion region 13 is formed in a layer below
the drain region 12. The P type diffusion region 13 forms a a part
of a drain of the p-channel type MOS transistor. The P-type
diffusion region 13 is formed to extend from the element region R1
to the element termination region R2 in a Y-direction as its
lengthwise direction.
[0026] The P type diffusion region 13 has an impurity concentration
of about 1e18 [cm.sup.-3] that is smaller than an impurity
concentration of the drain region 12. The P type diffusion region
13 has a width W1 in the element region R1 (see A-A' sectional view
of FIG. 4), whereas it has a width W2 in an area in the vicinity of
the end portion of the drain region 12 in the element termination
region R2 (see the C-C' section of FIG. 4). In addition, a distance
a1 from the end of the drain region 12 to the end of the P type
diffusion region 13 in the A-A' section is made smaller than a
distance a2 from the end of drain region 12 to the end of the P
type diffusion region 13 in the C-C' section. As an example, the
distance a1 is around 0.1 .mu.m, and the distance a2 is around 0.3
.mu.m.
[0027] The p-type drift region 14 is formed at a position beneath
the gate electrode 18 such that it contacts the P type diffusion
region 13.
[0028] The p-type drift region 14 has an impurity concentration
lower than an impurity concentration of the P type diffusion region
13, e.g., an impurity concentration of about 1e17 [cm.sup.-3]. The
drift region 14 is formed to extend in the Y-direction as its
lengthwise direction up to the element termination region R2, like
the drain region 12. However, a width b1 of the drift region 14
from the junction of the P type diffusion region 13 in the A-A'
section is made smaller than a width b2 thereof in the C-C'
section. In addition,
[0029] Also, a distance (a1+b1) from an end portion of the drift
region 14 on the source region 15 side to an end portion of the
drain region 12 (a border between the field oxide film 17 and the
drain region 12) in the A-A' section is smaller than a distance
(a2+b2) from an end portion of the drift region 14 on the source
region 15 side to an end portion of the drain region 12 (a border
between the field oxide film 17 and the drain region 12) in the
C-C' section. Accordingly, when a reverse bias is applied to the p
channel MOS transistor, a depletion layer easily spreads in the
element termination region R2.
[0030] A field oxide film 17 composed of a silicon oxide film
(e.g., SiO2 film) is formed on a surface of the P.sup.- type drift
region 14. The field oxide film 17 extends in the Y-direction as
its lengthwise direction, and the width c1 thereof in the A-A'
section is made smaller than the width c2 thereof in the C-C'
section. Note that the field oxide film 17 may be omitted,
depending on a required breakdown voltage of the MOS
transistor.
[0031] Also, an N type diffusion region 16 is formed at a position
isolated from the drift region 14 on the semiconductor substrate
11. The N type diffusion region 16 and the semiconductor substrate
11 between the N type diffusion region 16 and the drift region 14
function as a channel region of this p channel type MOS transistor.
The above-mentioned source region 15 is formed on the surface of
this N type diffusion region 16. The source region 15 is connected
to a source electrode which is not illustrated through a contact
plug CSs.
[0032] The N type diffusion region 16 is formed to extend in the
Y-direction as its lengthwise direction, like the gate electrode 18
and the like (see FIG. 3). The widths d1, d1' of this N type
diffusion region 16 in the element region R1 are made smaller than
the width d2, d2' thereof in the element termination region R2.
[0033] Like the gate electrode 18, the sourice region 15 is formed
to extend in the Y-direction as its lengthwise direction. The
source region 15 is located at the end portion in the X-direction
of the rectangular area CP. Note that the source region 15 is
divided at certain positions in the Y-direction, and the back gate
diffusion region 19 is formed in the divided position (B-B'
section), as shown in FIG. 2. The gate electrode 18 is formed on
the semiconductor substrate 11 through the gate insulating film 18a
to extend over the drift region 14, the N type diffusion region 16,
and the source region 15.
[0034] Sizes, impurity concentrations and the like of the drain
region 12, the P type diffusion region 13, the drift region 14, and
the source region 15 may be set such that required characteristics
such as an ON resistance, a breakdown voltage of the p channel MOS
transistor in the element region are satisfied.
[0035] The shape of the p channel type MOS transistor in the B-B'
section is approximately similar to that in the A-A' section.
However, it is different from that in the A-A' section in that the
source region 15 does not exist in the B-B' section, and, instead,
the P+ type back gate diffusion region 19 is formed with a larger
width.
[0036] As described above, the drain region 12, P type diffusion
region 13, the drift region 14 and the N type diffusion region 16
are formed to extend in the Y-direction from the element region R1
to the element termination region R2 (see the C-C' section of FIG.
4). However, the width W2 of the p type diffusion region 13 along
the C-C' section is made larger than the width W1 thereof in the
element region R1 including the A-A' section. Thus, as shown in a
plan view of FIG. 1, the P type diffusion region 13 has an expanded
tip portion with a polygon shape, like a matchstick shape. Having
such a shape, this embodiment may relax concentration of an
electric field around the region R3 shown in FIG. 1, and suprres
the generation of impact ions, thereby raising a breakdown voltage
of the MOS transistor. In addition, in the element termination
region R2, the width b2 of the drift region 14 along the C-C'
section is made larger than the width b1 thereof in the element
region R1 including the A-A' section. Due to this, in the element
termination region R2, a depletion layer tends to spread more
easily than in the element region R1, thereby improving a breakdown
voltage in the element termination region R2.
[0037] On the other hand, the width d2 of the N type diffusion
region 16 along the C-C' section is made smaller than the width d1
thereof in the element region R1 including the A-A' section.
Decreasing the width of the N type diffusion region 16 in the
element termination region R2 does not lower the breakdown voltage
of the MOS transistor.
[0038] In this way, in the semiconductor device according to the
present embodiment, while the width W2 of the P type diffusion
region 13 in the C-C' section (in the element termination region
R2) and the width b2 of the drift region 14 in the C-C' section are
made larger than those in the element region R1. On the other hand,
the width d2of the N type diffusion region 16 is made smaller. An
element width in the element termination region R2 can be the same
as that in the element region R1. Accordingly, various components
can be acccomodated in the rectangular region CP, as a whole.
[0039] The above-mentioned widths W2, b2, and d2 may be determined
irresppsctive of the widths W1, b1, d1 in the element region R1,
and based on a breakdown voltage required in the element
termination region 16. Even when the widths W2 and b2 are
determined to have larger values than those of the widths W1 and
b1, respectively, the width d2 may be determined to be smaler than
the width d1. Accordingly, the width of the element termination
region R2 along the X-direction need not be larger than the width
of the element region R1 along the X-direction.
[0040] In this way, according to the present embodiment, while the
element region R1 may be designed to obtain a P channel MOS
transistor therein with an optimized ON resistance or the like, the
element termination region R2 may be designed to obtain a required
breakdown voltage.
[0041] In above-mentioned embodiment, an example has been explained
in which the width b2 is made larger than the width b1, and the
width W2 is made larger than the width W1. However, it is possible
that only the width b2 is made larger than the width b1, and the
width W2 is made substantially equal to the width W1. This also
allows the breakdown voltage of the element termination region R2
to be raised.
[0042] However, enlarging the width W2 may contribute for
preventing electric field concentration in the end portion of the P
type diffusion region 13, thereby raising the breakdown voltage of
the element. Accordingly, in addition to enlargement of the width
b2, enlargement of the width W2 may serve to raise the breakdown
voltage of the element termination region even more.
[0043] FIG. 5 shows the planar shape of the element termination
region in a comparative example of the present embodiment. In this
comparative example, the width of the P type diffusion region 13 in
the element region R1 is the same as that of the element
termination region R2. This structure cannnot prevent electric
field concentration in the vicinity of the region R3 shown in FIG.
5. This causes the breakdown voltage in the element termination
region to lower, thereby lowering the breakdown voltage of the
semiconductor element as a whole. In this embodiment, because the
width W2 of the P type diffusion region 13 in the element
termination region R2 is expanded compared to the element region
R1, the breakdown voltage of the semiconductor device may be
raised.
[0044] While certain embodiments of the inventions have been
described, these embodiments have been presented by way of example
only, and are not intended to limit the scope of the inventions.
Indeed, the novel methods and systems described herein may be
embodied in a variety of other forms; furthermore, various
omissions, substitutions and changes in the form of the methods and
systems described herein may be made without departing from the
spirit of the inventions. The accompanying claims and their
equivalents are intended to cover such forms or modifications as
would fail within the scope and spirit of the inventions.
* * * * *