U.S. patent application number 13/907980 was filed with the patent office on 2013-10-10 for semiconductor device with stress-providing structure.
The applicant listed for this patent is UNITED MICROELECTRONICS CORPORATION. Invention is credited to Shu-Yen CHAN, Chin-Cheng CHIEN, Ching-Hong JIANG, Ching-I LI, Chin-I LIAO.
Application Number | 20130264585 13/907980 |
Document ID | / |
Family ID | 47174282 |
Filed Date | 2013-10-10 |
United States Patent
Application |
20130264585 |
Kind Code |
A1 |
LIAO; Chin-I ; et
al. |
October 10, 2013 |
SEMICONDUCTOR DEVICE WITH STRESS-PROVIDING STRUCTURE
Abstract
A semiconductor device is provided. The semiconductor device
includes a substrate, a recess and a stress-providing structure. A
channel structure is formed in the substrate. The recess is formed
in the substrate and arranged beside the channel structure. The
recess has a round inner surface. The stress-providing structure is
formed within the recess. Corresponding to the profile of the round
inner surface of the recess, the stress-providing structure has a
round outer surface.
Inventors: |
LIAO; Chin-I; (Tainan City,
TW) ; JIANG; Ching-Hong; (Taipei County, TW) ;
LI; Ching-I; (Tainan County, TW) ; CHAN; Shu-Yen;
(Changhua County, TW) ; CHIEN; Chin-Cheng; (Tainan
County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORPORATION |
HSINCHU |
|
TW |
|
|
Family ID: |
47174282 |
Appl. No.: |
13/907980 |
Filed: |
June 3, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13110294 |
May 18, 2011 |
8481391 |
|
|
13907980 |
|
|
|
|
Current U.S.
Class: |
257/77 |
Current CPC
Class: |
H01L 29/66636 20130101;
H01L 21/3247 20130101; H01L 29/7848 20130101; H01L 29/7842
20130101 |
Class at
Publication: |
257/77 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Claims
1. A semiconductor device, comprising: a substrate with a channel
structure; and a stress-providing structure formed within a recess,
wherein the recess was formed in the substrate and arranged beside
the channel structure, wherein the recess has a round inner
surface, the stress-providing structure is filling the recess and
has a round outer surface corresponding to the round inner surface
of the recess.
2. The semiconductor device according to claim 1, wherein the
semiconductor device further comprises a gate structure, which is
formed over the channel structure.
3. The semiconductor device according to claim 1, wherein the
recess has a depth from 600 angstroms to 650 angstroms.
4. The semiconductor device according to claim 1, wherein the
substrate is a silicon substrate.
5. The semiconductor device according to claim 1, wherein the
channel structure is a p-type channel structure, and the
stress-providing structure is made of silicon germanium (SiGe) or
germanium.
6. The semiconductor device according to claim 1, wherein the
channel structure is an n-type channel structure, and the
stress-providing structure is made of silicon carbide (SiC).
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application is a divisional application claiming
benefit from a parent U.S. patent application bearing a Ser. No.
13/110,294 and filed May 18, 2011, entire contents of which are
incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to a semiconductor device, and
more particularly to a semiconductor device with a stress-providing
structure.
BACKGROUND OF THE INVENTION
[0003] Generally, in the fabrication of a complementary
metal-oxide-semiconductor (CMOS) transistor, a selective area
epitaxial (SAE) (growth) process is widely used to form
source/drain regions. By using the selective area epitaxial process
to provide stress, the channel mobility of the transistor is
improved and the performance of the transistor is enhanced.
[0004] However, the efficacy of using the conventional selective
area epitaxial process to increase the performance of the
transistor is still unsatisfactory.
SUMMARY OF THE INVENTION
[0005] Therefore, the object of the present invention is to provide
a semiconductor device. The semiconductor device includes a
substrate, a recess and a stress-providing structure. A channel
structure is formed in the substrate. The recess is formed in the
substrate and arranged beside the channel structure. The recess has
a round inner surface. The stress-providing structure is formed
within the recess. Corresponding to the round inner surface, the
stress-providing structure has a round outer surface.
[0006] In an embodiment, the semiconductor device further includes
a gate structure, which is formed over the channel structure.
[0007] In an embodiment, the recess has a depth from 550 to 700
angstroms, and preferably from 600 to 650 angstroms.
[0008] In an embodiment, the substrate is a silicon substrate.
[0009] In an embodiment, the channel structure is a p-type channel
structure, and the stress-providing structure is made of silicon
germanium (SiGe) or germanium.
[0010] In an embodiment, the channel structure is an n-type channel
structure, and the stress-providing structure is made of silicon
carbide (SiC).
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The above objects and advantages of the present invention
will become more readily apparent to those ordinarily skilled in
the art after reviewing the following detailed description and
accompanying drawings, in which:
[0012] FIGS. 1A.about.1E schematically illustrate a process for
fabricating a stress-providing structure according to an embodiment
of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0013] The present invention will now be described more
specifically with reference to the following embodiments. It is to
be noted that the following descriptions of preferred embodiments
of this invention are presented herein for purpose of illustration
and description only. It is not intended to be exhaustive or to be
limited to the precise form disclosed.
[0014] FIGS. 1A.about.1E schematically illustrate a process for
fabricating a stress-providing structure according to an embodiment
of the present invention. The process for fabricating the
stress-providing structure may be applied to the fabrication of a
semiconductor device such as a complementary
metal-oxide-semiconductor (CMOS) transistor.
[0015] Firstly, as shown in FIG. 1A, a substrate 1 is provided. An
example of the substrate 1 includes but is not limited to a silicon
substrate. In addition, a channel structure 10 is formed in the
substrate 1, and a gate structure 11 is formed over the channel
structure 10. In this embodiment, the gate structure 11 comprises a
gate insulator layer 110 and a gate conductor layer 111.
[0016] Then, as shown in FIG. 1B, a silicon nitride layer 12 is
formed over the substrate 20 by chemical vapor deposition under a
halogen-containing environment. In one embodiment, the chemical
vapor deposition is performed under a chlorine-containing
environment. The chlorine-containing environment includes a
chlorine-containing species such as hexachlorodisilane
(Si.sub.2Cl.sub.6, also referred as HCD) or dichlorosilane
(SiH.sub.2Cl.sub.2, also referred as DCS). In such one embodiment,
the silicon nitride layer 12 is chlorine-rich.
[0017] Then, as shown in FIG. 1C, a series of photolithography and
etching processes are performed to partially remove the silicon
nitride layer 12 so as to partially expose the surface of the
substrate 1 beside the channel structure 10. Then, an etching
process is performed to remove the exposed surface of the substrate
1 to produce a recess 13. The depth of the recess 13 is from 550
angstroms to 700 angstroms, and preferably from 600 angstroms to
650 angstroms. As shown in FIG. 1C, the recess has a sigma-shaped
inner surface 130. The profile of the sigma-shaped inner surface
130 is similar to the profile of the sidewall of the conventional
embedded source/drain structure. By utilizing the lattice property
of the silicon substrate and performing dry/wet etching processes,
the sigma-shaped inner surface 130 will be produced.
[0018] Then, the substrate 1 with the recess 13 is subjected to a
thermal treatment process. For example, the thermal treatment
process is performed by baking the substrate 1 under a hydrogen gas
atmosphere at a temperature between 750.degree. C. and 820.degree.
C. for a time period from 10 seconds to 10000 seconds. Prior to the
thermal treatment process, the halogen-rich atoms (e.g.
chlorine-rich atoms) of the silicon nitride layer 12 are released
to the inner surface of the recess 13, and the halogen-rich atoms
and the silicon atoms interact with each other at the inner surface
of the recess 13. Moreover, during the thermal treatment process is
performed, the elevated temperature of between 750.degree. C. and
820.degree. C. causes migration and recombination of the silicon
atoms at the inner wall of the recess 13. Consequently, a recess 20
with a round inner surface is produced (see FIG. 1D). The depth of
the recess 20 is from 550 angstroms to 700 angstroms, and
preferably from 600 angstroms to 650angstroms.
[0019] Then, a stress-providing material is filled into the recess
20 to form a stress-providing structure 21 within the recess 20.
Corresponding to the round inner surface of the recess 20, the
stress-providing structure 21 has a round outer surface. In a case
that the channel structure 10 is a p-type channel structure, the
stress-providing material is silicon germanium (SiGe) or germanium
(Ge). Whereas, in a case that the channel structure 10 is an n-type
channel structure, the stress-providing material is silicon carbide
(SiC).
[0020] From the above description, the process for manufacturing a
stress-providing structure according to the present invention may
be applied to the fabrication of a semiconductor device. The inner
surface of the recess 20 has enhanced cleanliness, and is
chlorine-free. Moreover, the round inner surface of the recess 20
is beneficial for providing increased channel stress. Experiments
demonstrate that under side-by-side comparison by maintaining the
stress-providing material to be unchanged or constant, the round
inner surface of the recess produced by embodiment of present
invention may provide better channel mobility than the conventional
sigma-shaped inner surface.
[0021] While the invention has been described in terms of what is
presently considered to be the most practical and preferred
embodiments, it is to be understood that the invention needs not be
limited to the disclosed embodiment. On the contrary, it is
intended to cover various modifications and similar arrangements
included within the spirit and scope of the appended claims which
are to be accorded with the broadest interpretation so as to
encompass all such modifications and similar structures.
* * * * *